WO2017206806A1 - 移位寄存器电路及其驱动方法、栅线驱动电路和阵列基板 - Google Patents

移位寄存器电路及其驱动方法、栅线驱动电路和阵列基板 Download PDF

Info

Publication number
WO2017206806A1
WO2017206806A1 PCT/CN2017/086071 CN2017086071W WO2017206806A1 WO 2017206806 A1 WO2017206806 A1 WO 2017206806A1 CN 2017086071 W CN2017086071 W CN 2017086071W WO 2017206806 A1 WO2017206806 A1 WO 2017206806A1
Authority
WO
WIPO (PCT)
Prior art keywords
pull
node
circuit
pole
shift register
Prior art date
Application number
PCT/CN2017/086071
Other languages
English (en)
French (fr)
Inventor
张小祥
刘正
郭会斌
刘明悬
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/742,723 priority Critical patent/US20180211606A1/en
Publication of WO2017206806A1 publication Critical patent/WO2017206806A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a shift register unit and a driving method thereof, a gate line driving circuit including the shift register unit, and an array substrate including the gate line driving circuit.
  • a pixel array such as a liquid crystal display generally includes staggered multi-row gate lines and multi-column data lines.
  • the driving of the gate line can be realized by the attached integrated driving circuit.
  • the gate line driving circuit can be integrated on the thin film transistor array substrate to form a GOA (Gate driver On Array) to drive the gate line.
  • a switching signal can be provided by each row of gate lines constituting the GOA as a pixel array by a multi-stage shift register unit, thereby controlling the plurality of rows of gate lines to be sequentially turned on, and inputting the display data signals from the data lines to the pixels of the corresponding rows in the pixel array.
  • a gray voltage required for each gray scale of the displayed image thereby displaying each frame of image.
  • the off phase of the gate line that is, the low level sustaining phase
  • the coupling capacitance Cp of the output TFT in the corresponding shift register unit in the shift register unit
  • the potential of the pull-up node PU and the output terminal is easily affected by the high-level signal of the clock signal connected to the output TFT, especially under high-temperature operating conditions, the threshold voltage Vth of the output TFT drifts, resulting in the pull-up node PU and the output terminal.
  • the influence is more serious, so that the corresponding gate line has an abnormal signal during the off phase, so that the working state of the pixel unit connected to the gate line may be abnormal, resulting in a decrease in display quality of the display panel.
  • the present disclosure proposes a shift register unit and a driving method thereof, a gate line driving circuit, and an array substrate, which can utilize a first pull-down period in a low-level sustaining phase during a shift register unit driving process.
  • the circuit pulls down the pull-up node PU and the output terminal OUT, eliminating noise caused by the presence of the coupling capacitor.
  • a shift register unit including: a charging sub-circuit, Connected to the input signal terminal and the pull-up node, and charge the pull-up node under the control of the signal input from the input signal terminal; the output sub-circuit is connected with the pull-up node, the first clock signal end and the output end, and is connected to the pull-up node Under the control of the level, the clock signal provided by the first clock signal end is outputted as a driving signal through the output terminal; the first pull-down sub-circuit is connected with the pull-up node, the output end and the first pull-down node, at the first Under the level control of the pull node, the pull-up node and the output end are pulled down; the reset sub-circuit is connected with the pull-up node, the output end and the reset signal end, and is pulled up under the control of the reset signal input by the reset signal terminal.
  • the node and the output are reset; and the first control sub-circuit is connected to the pull-up node, the first clock signal end, and the first pull-down node, and is configured to control the level of the pull-up node and the first clock signal end Next, the level of the first pulldown node is controlled.
  • a gate line driving circuit including a plurality of stages of the aforementioned shift register unit.
  • an array substrate including the aforementioned gate line driving circuit is provided.
  • a driving method applied to the aforementioned shift register unit comprising: inputting an active level to an input signal terminal, charging a pull-up node to a first high level, and turning on an output sub- a circuit; outputting a high-level first clock signal to the gate line as a driving signal via the output sub-circuit; inputting an effective reset level to the reset signal terminal, discharging the pull-up node and the output terminal to a low level, and turning off the output sub-output a circuit; and inputting a first clock signal of a high level, turning on the first pull-down sub-circuit, keeping the pull-up node and the output low until the input signal terminal inputs the next active level.
  • Figure 1 illustrates a circuit structure of a known shift register unit
  • Figure 2 illustrates related signal timings available for the known shift register unit
  • FIG. 3 is a block diagram of a shift register unit in accordance with an embodiment of the present disclosure.
  • FIG. 4 illustrates a circuit configuration of a shift register unit according to an embodiment of the present disclosure
  • Figure 5 illustrates related signal timings that may be used with the shift register unit shown in Figure 4;
  • FIG. 6 is a block diagram of a shift register unit in accordance with another embodiment of the present disclosure.
  • FIG. 7 is a circuit configuration of a shift register unit according to another embodiment of the present disclosure.
  • Figure 8 illustrates related signal timings that may be used with the shift register unit shown in Figure 7;
  • FIG. 9 is a schematic diagram of a connection structure of a gate line driving device according to an embodiment of the present disclosure.
  • FIG. 10 is a flowchart of a driving method applied to a shift register unit, according to an embodiment of the present disclosure.
  • Figure 1 illustrates the circuit structure of a known shift register unit.
  • the shift register unit includes: an input transistor M1 whose gate and drain are connected together, and is connected to an input terminal of a shift register unit, a source thereof is connected to the pull-up node PU; an output transistor M3, whose gate is connected to the pull-up node PU, the drain is connected to the first clock signal terminal CLK, the source is connected to the output terminal of the shift register unit, and the capacitor C1 is connected in parallel between the gate and the source of the output transistor M3.
  • the pull-up node resets the transistor M2, its gate is connected to the reset terminal of the shift register unit, the drain is connected to the pull-up node, the source is connected to the low-level input terminal VSS, and the output reset transistor M14 is connected to the gate thereof.
  • the reset terminal of the shift register unit has a drain connected to the output terminal of the shift register unit, a source connected to the low level input terminal VSS, a pull-up node level control transistor M10, a gate connected to the pull-down node PD, and a drain
  • the pole is connected to the pull-up node PU, the source is connected to the low-level input terminal VSS;
  • the output terminal controls the transistors M11 and M12, wherein the gate of M11 is connected to the pull-down node PD, and the drain is connected to the shift register unit
  • the output terminal is connected to the low level input terminal VSS;
  • the gate of the M12 is connected to the second clock signal terminal CLKB, the drain is connected to the output terminal of the shift register unit, and the source is connected to the low level input terminal VSS;
  • the transistor M13 has a gate connected to the second clock signal terminal, a drain connected to the input end of the shift register unit, a source connected to the pull-up node, and a pull-down
  • the gate and drain of M9 are connected to the second clock signal terminal, the source is connected to the pull-down control node PD_CN; the gate of M5 is connected to the pull-down control node PD_CN, and the drain of M5 is connected to the second clock signal terminal, the source Connected to the pull-down node PD; the drain of M8 is connected to the pull-down control node PD_CN, M8
  • the gate is connected to the pull-up node PU, the source of M8 is connected to the low-level input terminal VSS;
  • the gate of M6 is connected to the pull-up node PU, the drain is connected to the pull-down node PD, and the source is connected to the low-level input End VSS.
  • the operation of the shift register unit illustrated in FIG. 1 will be described below with reference to the signal timing shown in FIG. 2, which is shifted in the five stages shown by a, b, c, d, and e shown in FIG. 2.
  • the register unit performs the following operations:
  • the clock signal CLK input to the first clock signal terminal is at a low level
  • the second clock signal terminal input clock signal CLKB is at a high level
  • the input signal input to the input terminal INPUT is at a high level
  • the node PU performs charging; since the second clock signal CLKB is at a high level, the transistor M13 is turned on to accelerate the charging process of the pull-up node PU; thereby, the pull-up node PU is charged to the first high level, and the output transistor M3 is turned on.
  • the transistor M9 is turned on to charge the pull-down control node PD_CN, however, since the pull-up node PU is at the first high level, the transistors M6 and M8 are turned on; in the design of the transistor, The size ratio of the transistors M8 and M9 is configured such that when both M9 and M8 are turned on, the level of the pull-down control node PD_CN is pulled down to a low level, in which case PD_CN is low level, and the transistor M5 remains off; by When the transistor M6 is turned on, the level of the pull-down node PD is pulled down to a low level, so that the transistors M10 and M11 are in an off state at this stage; since CLKB is at a high level, the transistor M12 is turned on, and the shift register unit can be ensured.
  • the output is pulled low to low VSS;
  • the clock signal CLK input to the first clock signal terminal is at a high level
  • the clock signal CLKB input to the second clock signal terminal is at a low level
  • the signal input to the input terminal INPUT is at a low level
  • the transistor M1 M13, M9, M5 and M12 are turned off
  • the output transistor M3 is turned on
  • the high-level clock signal CLK is output as the gate line driving signal; due to the bootstrap effect of the storage capacitor C1, the level of the pull-up node PU is further increased.
  • the clock signal CLK input to the first clock signal terminal is at a low level
  • the clock signal CLKB input to the second clock signal terminal is at a high level
  • the input terminal INPUT continues to be connected to a low level
  • the transistors M2 and M14 are turned on, respectively
  • the output terminals of the pull-up node PU and the shift register unit are pulled down to a low level VSS; while the transistor M1 is turned off, the transistor M13 is turned on, and the low level is connected to the pull-up node PU, and the pull-up node PU is discharged;
  • the node PU is discharged to a low level, so that the transistor M3 is turned off; since the second clock signal CLKB is at a high level, the transistor M12 is turned on, pulling the output terminal of the shift register unit to the low level VSS; the transistor M9 is turned on.
  • the clock signal CLK input to the first clock signal terminal is at a high level
  • the clock signal CLKB input to the second clock signal terminal is at a low level
  • the input terminal INPUT continues to be connected to a low level
  • the reset terminal is connected.
  • transistors M1, M13, M2, M14, M9 and M12 are turned off; since the pull-up node PU is held low, transistors M6 and M8 continue to turn off; since transistors M8 and M9 are both turned off, the pull-down control node
  • the discharge path of PD_CN is turned off, and the pull-down control node PD_CN maintains the previous high level, so that the transistor M5 remains on, and since the second clock signal CLKB is at a low level, the pull-down node PD is discharged.
  • the transistors M10 and M11 are turned off, respectively closing the discharge path of the pull-up node and the discharge path of the output terminal of the shift register unit, thereby causing the pull-up node PU and the output terminal to be in a floating state.
  • the shift register unit is in the non-output stage at this stage, the pull-up node PU and the output should maintain the previous low state, however, since the first clock signal CLK is high, and as shown in the figure As shown in FIG.
  • the clock signal CLK input to the first clock signal terminal is at a low level
  • the clock signal CLKB input to the second clock signal terminal is at a high level
  • the input terminal INPUT continues to be connected to a low level
  • the reset terminal is connected.
  • the transistors M1, M2, M14 are turned off; the transistor M13 is turned on, the low level is connected to the pull-up node PU, and the pull-up node PU is discharged to ensure that the transistor M3 is turned off; CLKB is high level, the transistor M12 is turned on, the output terminal of the shift register unit is pulled low to VSS, and the noise of the output terminal of the shift register unit is eliminated; the transistor M9 is turned on, and the pull-down control node PD_CN is charged, so that the turn-on of the transistor M5 is more sufficient, and The pull-down node PD is charged, so that the pull-down node PD becomes a high level; Since the pull-up node PU is discharged, the transistors M6 and M8 are turned off; the high level of the pull-down node PD causes the transistors M10 and M11 to be turned on, respectively pulling the output terminals of the pull-up node PU and the shift register unit to the low level VSS, The noise
  • the shift register unit repeats the operations of stages d and e until the next valid input signal arrives.
  • the shift register unit includes: a charging sub-circuit 110 connected between the input signal terminal INPUT and the pull-up node PU, configured to be a pull-up node under the control of a signal input at the input signal terminal.
  • the PU is charged;
  • the output sub-circuit 120 is connected between the pull-up node PU, the first clock signal terminal CLK and the output terminal OUT, and is configured to output the first clock via the output terminal under the control of the level of the pull-up node PU.
  • the clock signal provided by the signal terminal is used as a driving signal;
  • the first pull-down sub-circuit 130 is connected to the pull-up node PU, the output terminal OUT and the first pull-down node PD1, and is configured to be level-controlled at the first pull-down node PD1.
  • the pull-up node PU and the output terminal OUT are pulled down;
  • the reset sub-circuit 140 is connected to the pull-up node PU, the output terminal OUT, and the reset signal terminal RESET, and is configured to be under the control of the reset signal input by the reset signal terminal. , reset the pull-up node PU and the output terminal OUT.
  • the first pull-down sub-circuit 130 since the first pull-down sub-circuit 130 is configured, it is possible to perform a low-level sustaining phase in the shift register unit driving process according to the level of the first pull-down node PD1
  • the pull-up node PU and the output terminal OUT are pulled down, eliminating the noise caused by the existence of the coupling capacitor, thereby ensuring that the correct driving signal is output to the gate line connected to the shift register unit, and finally ensuring the quality of the pixel display.
  • the shift register unit further includes: a first control sub-circuit 150 connected to the pull-up node PU, the first clock signal terminal CLK, and the first pull-down node PD1, configured to be configured as In
  • the level of the first pull-down node PD1 is controlled under the control of the level of the pull-up node PU and the first clock signal terminal CLK.
  • the level of the first pull-down node PD1 can be controlled by the first clock signal CLK, so that the level of the first pull-down node PD1 is pulled when the CLK outputs a high level and the pull-up node PU is at a low level. High to turn on the first pull-down sub-circuit, thereby eliminating noise generated by the coupling capacitors of the pull-up node PU and the output.
  • the shift register unit further includes: a second pull-down sub-circuit 160 connected to the pull-up node PU, the output terminal OUT, and the second pull-down node PD2, configured to be in the second pull-down Under the level control of the node PD2, the pull-up node PU and the output terminal OUT are pulled down.
  • a second pull-down sub-circuit 160 connected to the pull-up node PU, the output terminal OUT, and the second pull-down node PD2, configured to be in the second pull-down Under the level control of the node PD2, the pull-up node PU and the output terminal OUT are pulled down.
  • the pull-down node PU and the output terminal OUT can be pulled down by the second pull-down sub-circuit under the control of the second pull-down node, so that the shift register unit is after the output phase, when the first clock signal is low , to ensure that the pull-up node and the output are in a low state.
  • the shift register unit further includes: a second control sub-circuit 170 connected to the second clock signal terminal CLKB and the second pull-down node PD2, configured to be at the second clock signal end
  • the level of the second pull-down node PD2 is controlled under the control of the second clock signal provided by CLKB.
  • the level of the second pull-down node PD2 can be controlled by the second clock signal CLKB such that the level of the second pull-down node PD2 is pulled high when the CLKB outputs a high level and the pull-up node PU is at a low level.
  • CLKB the second clock signal
  • the pull-up node and the output terminal can be maintained in the low state by the operation of the first pull-down sub-circuit and the second pull-down sub-circuit in the low-level sustain phase of the shift register unit.
  • the shift register unit further includes: an output pull-down sub-circuit 180 connected to the second clock signal terminal CLKB and the output terminal OUT, configured to be under the control of the second clock signal terminal , pull down the output OUT.
  • the output pull-down sub-circuit can be used to pull down the output of the shift register unit under the control of the second clock signal, so that the output of the shift register unit outputs a low level in the non-output stage.
  • the reliability and redundancy of the system can be increased, and the size of other transistors for pulling down the output of the shift register unit can be reduced, reducing the cost.
  • the charging sub-circuit 110 includes a first thin film transistor (TFT) M1 having a first pole and a second pole connected to the input signal terminal INPUT and a third pole connected to the pull-up node PU.
  • TFT thin film transistor
  • the output sub-circuit 120 includes: a second TFT M13 having a first pole connected to the pull-up node, a second pole connected to the first clock signal terminal CLK, and a third pole connected to the output terminal OUT; and capacitor C1, connected between the pull-up node and the output.
  • the first pull-down sub-circuit 130 includes: a third TFT M4 having a first pole connected to the first pull-down node PD1, a second pole connected to the pull-up node, and a third pole connected To the low-level signal terminal VSS; and the fourth TFT M11, the first electrode thereof is connected to the first pull-down node PD1, the second electrode is connected to the output terminal OUT, and the third electrode is connected to the low-level signal terminal VSS.
  • the reset sub-circuit 140 includes: a fifth TFT M2 having a first pole connected to the reset signal terminal RESET, a second pole connected to the pull-up node, and a third pole connected to the low-level signal The terminal VSS; and the sixth TFT M15 have a first electrode connected to the reset signal terminal, a second terminal connected to the output terminal, and a third electrode connected to the low level signal terminal VSS.
  • the first control sub-circuit 150 includes: a seventh TFT M9 having a first pole connected to the pull-up node PU, a second pole connected to the first pull-down node PD1, and a third pole connected To the low-level signal terminal VSS; and the eighth TFT M12, the first and second electrodes thereof are connected to the first clock signal terminal CLK, and the third electrode is connected to the first pull-down node PD1.
  • the output pull-down sub-circuit 180 includes: a ninth TFT M10 having a first pole connected to the second clock signal terminal CLKB, a second pole connected to the output terminal OUT, and a third pole connected to the low terminal Level signal terminal VSS.
  • the second pull-down sub-circuit 160 includes: a tenth TFT M3 having a first pole connected to the second pull-down node PD2, a second pole connected to the pull-up node, and a third pole connected to the low The level signal terminal VSS; and the eleventh TFT M14 have a first electrode connected to the second pull-down node PD2, a second electrode connected to the output terminal OUT, and a third electrode connected to the low-level signal terminal VSS.
  • the second control sub-circuit 170 includes: a twelfth TFT M5, a thirteenth TFT M7, a fourteenth TFT M6, and a fifteenth TFT M8; wherein, the twelfth TFT M5
  • the first pole and the second pole are connected to the second clock signal terminal CLKB
  • the third pole is connected to the first pole of the thirteenth TFT M7
  • the second pole of the thirteenth TFT M7 is connected to the second clock signal terminal, the third pole Connected to the second pull-down node
  • the first pole of the fourteenth TFT M6 is connected to the pull-up node
  • the second pole is connected to the thirteenth TFT M7
  • the first pole, the third pole is connected to the low-level signal terminal
  • the first pole of the fifteenth TFT M8 is connected to the pull-up node, the second pole is connected to the second pull-down node, and the third pole is connected to the low level Signal terminal VSS.
  • the first pole of the TFT is a gate
  • the second pole is a drain
  • the third pole is a source
  • the source and drain of the TFT transistor used herein are symmetrical, the source and the drain are interchangeable.
  • one of the poles is referred to as a source and the other pole is referred to as a drain. If the source is selected as the signal input, the drain acts as the signal output and vice versa.
  • the low level signal terminals are shown as being both connected to the low level VSS.
  • the low level signal terminals can be connected to different low levels, such as low levels VSS and VGL having different voltage values.
  • a low level connected to a transistor for pulling down the output of the shift register unit can be connected to a low level VGL
  • a low level connected to a transistor for pulling up the pull-up node of the shift register unit can be connected low.
  • Level VSS where the level of VGL is lower than the level of VSS.
  • the gate-source potential of the output transistor of the shift register unit can be reversed when both the pull-up node and the output terminal are pulled low, and the output can be guaranteed even when the output transistor uses a depletion transistor.
  • the transistor is completely turned off.
  • the first clock signal of the shift register unit is terminated with a first clock signal CLK
  • the second clock signal is terminated with a second clock signal CLKB
  • the input terminal is connected to the STV signal; optionally, the shift register unit is used as In the first stage, STV represents a frame start signal, and when the shift register unit is used as another stage, STV represents an output signal from a previous stage shift register unit in series with the shift register unit.
  • the shift register unit performs the following operations:
  • the clock signal CLK input to the first clock signal terminal is at a low level
  • the clock signal CLKB input to the second clock signal terminal is at a high level
  • the STV input to the input signal terminal INPUT is at a high level
  • the transistor M1 is turned on, so that the input of the high level is made.
  • the signal charges the pull-up node PU to reach the first high level; since the clock signal CLKB is high level, the transistor M5 is turned on to charge the pull-down control node PD_CN, but since the pull-up node PU is at the first high level, the transistor M6 and M8 are turned on; in the design of the transistor, the size ratio of the transistors M5 and M6 can be configured such that when both M5 and M6 are turned on, the level of the pull-down control node PD_CN is pulled down to a low level, and therefore, the transistor M7 is not Turn on; since the transistor M8 is turned on and M7 is turned off, the second pull-down node PD2 is pulled down to a low level, thereby ensuring that the transistors M3 and M14 are in an off state at this stage; in addition, since the first clock signal CLK is low Ping, M12 is turned off, and the pull-up node PU is high, M9 is turned on, so the first pull-down node PD1 is
  • the clock signal CLK input to the first clock signal terminal is at a high level
  • the clock signal CLKB input to the second clock signal terminal is at a low level
  • the STV input to the input terminal INPUT is at a low level
  • M1, M5 and M10 are turned off
  • the output transistor M13 is kept turned on, and the first clock signal of the high level is output to the output terminal
  • the potential of the pull-up node PU is further raised to the second high voltage due to the bootstrap action of the storage capacitor C1.
  • Leveling makes the conduction of the output transistor M13 more sufficient; since the potential of the pull-up node PU is further increased, the conduction of the transistors M6 and M8 is more sufficient, and since the transistor M5 is turned off, the level of the pull-down control node PD_CN is The pull is lower; the transistor M7 remains turned off, the level of the second pull-down node PD2 is also pulled lower, and the transistors M3 and M14 remain turned off, so that the shift register unit does not normally output the shift signal; Since the first clock signal CLK is high, the transistor M12 is turned on, however, since the pull-up node PU is at the second high level, the turn-on of the transistor M9 is more sufficient, and in design, the transistor M9 can be The size ratio of M12 is configured such that when both M9 and M12 are turned on, the first pull-down node PD1 is pulled down to a low level; in this case, the level of the first pull-down node PD1 is pulled down lower, the transistor M
  • the clock signal CLK input to the first clock signal terminal is at a low level
  • the clock signal CLKB input to the second clock signal terminal is at a high level
  • the STV input to the input terminal INPUT is at a low level
  • the transistor M1 continues to be turned off, transistor M10 is turned on under the control of CLKB of high level, so that the output terminal of the shift register unit is pulled down to VSS; since reset signal terminal RESET is high level, transistors M2 and M15 are turned on, respectively The pull-up node PU and the output are pulled low; since the pull-up node PU is pulled down to VSS, transistors M6, M8 and M13 are turned off, capacitor C1 is discharged; since CLKB is high, transistor M5 is turned on, pull-down control node PD_CN is charged, whereby pull-down control node PD_CN is charged to a high level, thereby turning on Transistor M7, and via the turned-on transistor M7, the second pull-down node PD
  • the clock signal CLK input to the first clock signal terminal is at a high level
  • the clock signal CLKB input to the second clock signal terminal is at a low level
  • the STV input to the input terminal INPUT is at a low level
  • the signal terminal RESET is low
  • the transistor M1 continues to be turned off, the transistors M5, M10 are turned off; since the pull-up node PU is kept low, the transistors M6, M8, M9 and M13 remain off; since the transistors M5 and M6 are both Shutdown, the discharge path of the pull-down control node PD_CN is turned off, the pull-down control node PD_CN remains at the previous high level, and the transistor M7 remains on, thereby connecting the low level CLKB to the second pull-down node PD2 via the turned-on transistor M7; CLK is high, transistor M12 is on, pull-up node PU is low, transistor M9 is turned off, so the first pull-down node PD1 is charged to the
  • the transistors M4 and M11 are turned on, thereby ensuring that the pull-up node PU and the output are respectively pulled low. . It can be seen that, compared with the previous stage, the transistor M4 pulls down the pull-up node instead of M3, and the transistor M11 pulls down the output terminal instead of M14.
  • the high-level clock signal CLK turns on the transistor M12, and charges the first pull-down node PD1 to A high level turns on transistors M4 and M11 to pull the pull-up node PU and output, respectively, to eliminate possible noise.
  • the clock signal CLK input to the first clock signal terminal is at a low level
  • the clock signal CLKB input to the second clock signal terminal is at a high level
  • the STV input to the input terminal INPUT is at a low level, resetting
  • the signal terminal is connected to the low level; since the STV is low, the transistor M1 continues to be turned off; since CLKB is high, the transistors M5 and M10 are turned on; since the pull-up node PU is kept low, the transistors M6, M8, M9 and M13 remain off; via the turned-on transistor M5, the pull-down control node PD_CN is connected to the high level.
  • the clock signal CLKB can maintain the previous high level; the transistor M7 continues to be turned on, and the high level CLKB is connected to the second pull-down node PD2, so that the second pull-down node PD2 becomes a high level; since CLK is low, The transistor M12 is turned off, the pull-up node PU is at a low level, the transistor M9 is kept off, the discharge path of the first pull-down node PD1 is turned off, and the first pull-down node PD1 maintains the previous high level; in this case Since the first pull-down node PD1 is kept at a high level, the transistors M4 and M11 remain turned on, respectively pulling the pull-up node PU and the output terminal; in addition, since the second pull-down node PD2 is also at a high level, the transistors M3 and M14 It is also turned on to ensure that the pull-up node PU and output are pulled low, respectively.
  • Subsequent phases will repeat the operations of the fourth and fifth phases until the next high level of the STV signal.
  • the shift register unit illustrated in FIG. 3 can also be simplified.
  • the shift register unit includes: a charging sub-circuit 110 connected between the input signal terminal INPUT and the pull-up node PU, configured to be a pull-up node under the control of a signal input at the input signal terminal.
  • the PU is charged;
  • the output sub-circuit 120 is connected between the pull-up node PU, the first clock signal terminal CLK and the output terminal OUT, and is configured to output the first clock via the output terminal under the control of the level of the pull-up node PU.
  • the clock signal provided by the signal terminal is used as a driving signal;
  • the first pull-down sub-circuit 130 is connected to the pull-up node PU, the output terminal OUT and the first pull-down node PD1, and is configured to be level-controlled at the first pull-down node PD1.
  • the pull-up node PU and the output terminal OUT are pulled down;
  • the reset sub-circuit 140 is connected to the pull-up node PU, the output terminal OUT, and the reset signal terminal RESET, and is configured to be under the control of the reset signal input by the reset signal terminal. , reset the pull-up node PU and the output terminal OUT.
  • the shift register unit further includes: a first control sub-circuit 150 connected to the pull-up node PU, the first clock signal terminal CLK, and the first pull-down node PD1, configured to The level of the first pull-down node PD1 is controlled under the control of the level of the pull-up node PU and the first clock signal terminal CLK.
  • the shift register unit further includes: an output pull-down sub-circuit 180 connected to the second clock signal terminal CLKB and the output terminal OUT, configured to be under the control of the second clock signal terminal , pull down the output OUT.
  • the difference from the shift register unit shown in FIG. 3 is mainly that the second pull-down sub-circuit and the second control sub-circuit may not be included in the shift register unit.
  • the pull-up node PU and the output terminal OUT can be pulled down according to the level of the first pull-down node PD1 during the low-level sustaining phase of the shift register unit driving process, thereby eliminating noise caused by the existence of the coupling capacitor Therefore, it is ensured that the correct driving signal is output to the gate line connected to the shift register unit, and finally the quality of the pixel display is ensured.
  • the level of the first pull-down node PD1 can be controlled by the first clock signal CLK, so that when the CLK outputs a high level and the pull-up node PU is at a low level, The level of a pull-down node PD1 is pulled high to turn on the first pull-down sub-circuit, thereby eliminating noise generated by the pull-up node PU and the output due to the coupling capacitance.
  • the pull-up node and the output terminal can be maintained in the low state by the operation of the first pull-down sub-circuit in the low-level sustain phase of the shift register unit.
  • the output pull-down sub-circuit can be used to pull down the output of the shift register unit under the control of the second clock signal, so that the output of the shift register unit outputs low power at this stage. level.
  • FIG. 7 illustrates a schematic circuit structure of a shift register unit according to another embodiment of the present disclosure.
  • the circuit configuration of the shift register unit will be described in detail below with reference to FIGS. 6 and 7.
  • the charging sub-circuit 110 includes a first thin film transistor (TFT) M1 having a first pole and a second pole connected to the input signal terminal INPUT and a third pole connected to the pull-up node PU.
  • TFT thin film transistor
  • the output sub-circuit 120 includes: a second TFT M13 having a first pole connected to the pull-up node, a second pole connected to the first clock signal terminal CLK, and a third pole connected to the output terminal OUT; and capacitor C1, connected between the pull-up node and the output.
  • the first pull-down sub-circuit 130 includes: a third TFT M4 having a first pole connected to the first pull-down node PD1, a second pole connected to the pull-up node, and a third pole connected To the low-level signal terminal VSS; and the fourth TFT M11, the first electrode thereof is connected to the first pull-down node PD1, the second electrode is connected to the output terminal OUT, and the third electrode is connected to the low-level signal terminal VSS.
  • the reset sub-circuit 140 includes: a fifth TFT M2 having a first pole connected to the reset signal terminal RESET, a second pole connected to the pull-up node, and a third pole connected to the low-level signal The terminal VSS; and the sixth TFT M15 have a first electrode connected to the reset signal terminal, a second terminal connected to the output terminal, and a third electrode connected to the low level signal terminal VSS.
  • the first control sub-circuit 150 includes: a seventh TFT M9 having a first pole connected to the pull-up node PU, a second pole connected to the first pull-down node PD1, and a third pole connected To low electricity The flat signal terminal VSS; and the eighth TFT M12 have a first pole and a second pole connected to the first clock signal terminal CLK, and a third pole connected to the first pull-down node PD1.
  • the output pull-down sub-circuit 180 includes: a ninth TFT M10 having a first pole connected to the second clock signal terminal CLKB, a second pole connected to the output terminal OUT, and a third pole connected to the low terminal Level signal terminal VSS.
  • the shift register unit circuit illustrated in FIG. 7 removes the second pull-down sub-circuit and the second control sub-circuit as compared with the shift register unit circuit illustrated in FIG. 4, simplifying the circuit configuration.
  • the first pole of the TFT is a gate
  • the second pole is a drain
  • the third pole is a source
  • the source and drain of the TFT transistor used herein are symmetrical, the source and the drain are interchangeable.
  • one of the poles is referred to as a source and the other pole is referred to as a drain. If the source is selected as the signal input, the drain acts as the signal output and vice versa.
  • the low level signal terminals are shown as being both connected to the low level VSS.
  • the low level signal terminals can be connected to different low levels, such as low levels VSS and VGL having different voltage values.
  • a low level connected to a transistor for pulling down the output of the shift register unit can be connected to a low level VGL
  • a low level to a pull-up node for a pull-down shift register unit can be connected to a low level VSS.
  • the level of VGL is lower than the level of VSS.
  • the gate-source potential of the output transistor of the shift register unit can be reversed when both the pull-up node and the output terminal are pulled low, and the output can be guaranteed even when the output transistor uses a depletion transistor.
  • the transistor is completely turned off.
  • the first clock signal of the shift register unit is terminated with a first clock signal CLK
  • the second clock signal is terminated with a second clock signal CLKB
  • the input terminal is connected to the STV signal; optionally, the shift register unit is used as In the first stage, STV represents the frame start signal, and when the shift register unit is used as other stages, STV represents the shift from the previous stage in series with the shift register unit.
  • the output signal of the register unit In the five stages shown by a, b, c, d, and e shown in FIG. 8, the shift register unit performs the following operations:
  • the clock signal CLK input to the first clock signal terminal is at a low level
  • the clock signal CLKB input to the second clock signal terminal is at a high level
  • the STV input to the input signal terminal INPUT is at a high level
  • the transistor M1 is turned on, so that the input signal of the high level charges the pull-up node PU to reach the first high level
  • the first clock signal CLK is low level
  • M12 Shutdown while the pull-up node PU is high, M9 is on, so the first pull-down node PD1 is pulled down to low level
  • transistors M4 and M11 are turned off
  • the pull-up node PU is high, it is the storage capacitor C1 Charging, causing the output transistor M13 to be turned on, outputting a low-level clock signal CLK to the output terminal; further, since the second clock signal CLKB is at a high level, the transistor M10 is turned on, thereby
  • the clock signal CLK input to the first clock signal terminal is at a high level
  • the clock signal CLKB input to the second clock signal terminal is at a low level
  • the STV input to the input terminal INPUT is at a low level
  • M1 and M10 are turned off
  • the output transistor M13 is kept turned on, and the first clock signal of the high level is output to the output terminal
  • the potential of the pull-up node PU is further raised to the second high level due to the bootstrap action of the storage capacitor C1.
  • the transistor M9 makes the conduction of the output transistor M13 more sufficient, ensuring charging of the pixels connected by the gate line; since the first clock signal CLK is high, the transistor M12 is turned on, however, since the pull-up node PU is further prompted to the second high level, the transistor
  • the conduction of M9 is more sufficient, and in design, the size ratio of the transistors M9 and M12 can be configured such that when both M9 and M12 are turned on, the first pull-down node PD1 is pulled down to a low level; in this case, The level of the first pull-down node PD1 is pulled down lower, and the transistors M4 and M11 remain turned off so as not to affect the normal output shift signal of the shift register unit.
  • the clock signal CLK input to the first clock signal terminal is at a low level
  • the clock signal CLKB input to the second clock signal terminal is at a high level
  • the STV input to the input terminal INPUT is at a low level
  • the transistor M1 continues to be turned off
  • transistor M10 is turned on under the control of CLKB of high level, so that the output terminal of the shift register unit is pulled down to VSS; since reset signal terminal RESET is high level, transistors M2 and M15 are turned on, respectively
  • the pull-up node PU and the output are pulled low; since the pull-up node PU is pulled low to VSS, the capacitor C1 is discharged; since the pull-up node PU is pulled low, the transistor M9 is turned off, and since CLK is low, the transistor M12 Also turned off, the level of the first pull-down node PD1 remains low despite a slight increase; although the transistors M4 and M11 remain off due to the first pull-down node PD1 being low, due to reset
  • the clock signal CLK input to the first clock signal terminal is at a high level
  • the clock signal CLKB input to the second clock signal terminal is at a low level
  • the STV input to the input terminal INPUT is at a low level
  • RESET is low
  • the transistor M1 continues to be turned off
  • the transistor M10 is turned off; since the pull-up node PU is kept low, M13 remains off; since CLK is high, the transistor M12 is turned on, and the pull-up node PU is low level, transistor M9 is turned off, so the first pull-down node PD1 is charged to the high level via the turned-on transistor M12; since the first pull-down node PD1 is high level, the transistors M4 and M11 It is turned on to ensure that the pull-up node PU and output are pulled low, respectively.
  • the high-level clock signal CLK turns on the transistor M12, and charges the first pull-down node PD1 to A high level turns on transistors M4 and M11 to pull the pull-up node PU and output, respectively, to eliminate possible noise.
  • the clock signal CLK input to the first clock signal terminal is at a low level
  • the clock signal CLKB input to the second clock signal terminal is at a high level
  • the STV input to the input terminal INPUT is at a low level, resetting
  • the signal terminal is connected to the low level; since the STV is low, the transistor M1 continues to be turned off; since CLKB is high, the transistor M10 is turned on; since the pull-up node PU is kept low, the transistor M13 remains off; CLK is low, transistor M12 is turned off, and pull-up node PU is low, transistor M9 is kept off, the discharge path of the first pull-down node PD1 is turned off, and the first pull-down node PD1 maintains the previous high power. In this case, since the first pull-down node PD1 is kept at a high level, the transistors M4 and M11 remain turned on, pulling the pull-up node PU and the output terminal, respectively.
  • Subsequent phases will repeat the operations of the fourth and fifth phases until the next high level of the STV signal.
  • a grid line driving device is also provided. As shown in FIG. 9, the gate line driving device includes a plurality of stages of the aforementioned shift register unit.
  • each stage shift register unit is connected to a gate line; the odd-level shift register unit is connected to the first and third clock signals, and the even-stage shift register unit is connected to the second and fourth clocks. a signal; an odd-order shift register unit is connected in series with each other, and an even-numbered shift register unit is connected in series with each other; in a two-stage shift register unit connected in series, the first clock signal terminal The clock signal input by the second clock signal terminal is interchanged, and the output end of the shift stage register unit of the previous stage is connected to the input signal end of the shift register unit of the latter stage, and the reset signal end of the shift register unit of the previous stage is connected to The output of the latter stage shift register unit. As shown in FIG.
  • the output terminal OUTPUT is connected to the Nth gate line G(n) and the input signal terminal INPUT of the (N+2)th stage shift register unit. Its input terminal is connected to the output terminal OUT of the (n-2)th stage shift register unit, and its reset signal terminal RESET is connected to the output terminal of the (N+2)th stage shift register unit.
  • the method mainly includes the steps of: S1010, inputting an effective level to an input signal terminal, charging the pull-up node to a first high level, and turning on an output sub-circuit; and S1020 outputting to the gate line via the output sub-circuit
  • the first clock signal of the high level is used as the driving signal; in S1030, the effective reset level is input to the reset signal terminal, the discharge of the pull-up node and the output terminal is pulled low to the low level, and the output sub-circuit is turned off; S1040, the input high level
  • the first clock signal turns on the first pull-down sub-circuit, keeping the pull-up node and the output low until the input signal terminal inputs the next active level.
  • step S1010 a second clock signal of a high level is input to pull down the output terminal.
  • step S1040 the first control sub-circuit is turned on by the input first high-level clock signal to charge the first pull-down node to turn on the first pull-down sub-circuit.
  • the first control sub-circuit in the low-level sustaining phase of the shift register unit, is turned on by the first clock signal to charge the first pull-down node, thereby turning on The first pull-down sub-circuit pulls the pull-up node and the output low to eliminate the noise caused by the coupling capacitor, improve the signal waveform outputted to the gate line, and improve the display quality of the pixel.

Abstract

公开了一种移位寄存器电路及其驱动方法、栅线驱动电路，以及阵列基板，其中该移位寄存器电路包括：充电子电路（110），在输入信号端（ INPUT）输入的信号的控制下，为上拉节点（PU）充电；输出子电路（120），在上拉节点（PU）的电平的控制下，通过输出端（OUT）输出第一时钟信号端（CLK）提供的时钟信号作为驱动信号；第一下拉子电路（130），在第一下拉节点（PDI）的电平控制下，对上拉节点（PU）和输出端（OUT）进行下拉；以及复位子电路（140），在复位信号端（RESET）输入的复位信号的控制下，对上拉节点（PU）和输出端（OUT）进行复位。由此，可以在移位寄存器电路驱动过程中的低电平维持阶段，利用第一下拉子电路对上拉节点（PU）和输出端（OUT）进行下拉，消除由于藕合电容引起的噪声。

Description

移位寄存器电路及其驱动方法、栅线驱动电路和阵列基板 技术领域
本公开涉及显示技术领域，具体涉及一种移位寄存器单元及其驱动方法、包括该移位寄存器单元的栅线驱动电路，以及包括该栅线驱动电路的阵列基板。
背景技术
在显示技术领域，诸如液晶显示的像素阵列通常包括交错的多行栅线和多列数据线。其中，对栅线的驱动可以通过贴附的集成驱动电路实现。近几年随着非晶硅薄膜工艺的不断提高，也可以将栅线驱动电路集成在薄膜晶体管阵列基板上构成GOA(Gate driver On Array)来对栅线进行驱动。
通常，可以采用由多级移位寄存器单元构成GOA为像素阵列的各行栅线提供开关信号，从而控制多行栅线依序打开，并由数据线向像素阵列中对应行的像素输入显示数据信号，以形成显示图像的各灰阶所需要的灰度电压，进而显示每一帧图像。
在利用GOA对栅线进行驱动的过程中，在栅线的关闭阶段，也就是低电平维持阶段，由于对应的移位寄存器单元中输出TFT的耦合电容Cp的存在，移位寄存器单元中的上拉节点PU和输出端的电位易于受到输出TFT所连接的时钟信号的高电平信号的影响，特别是在高温工作条件下，输出TFT的阈值电压Vth产生漂移，导致上拉节点PU和输出端受到的影响更严重，使得对应的栅线在关闭阶段出现不正常的信号，从而有可能使得与该栅线连接的像素单元的工作状态不正常，导致显示面板的显示质量的降低。
发明内容
针对以上问题，本公开提出了一种移位寄存器单元及其驱动方法、栅线驱动电路，以及阵列基板，可以在移位寄存器单元驱动过程中的低电平维持阶段，利用第一下拉子电路对上拉节点PU和输出端OUT进行下拉，消除了由于耦合电容的存在所引起的噪声。
根据本公开的一方面，提供了一种移位寄存器单元，包括：充电子电路， 与输入信号端和上拉节点连接，在输入信号端输入的信号的控制下，为上拉节点充电；输出子电路，与上拉节点、第一时钟信号端和输出端连接，在上拉节点的电平的控制下，通过输出端输出第一时钟信号端提供的时钟信号作为驱动信号；第一下拉子电路，与上拉节点、输出端和第一下拉节点连接，在第一下拉节点的电平控制下，对上拉节点和输出端进行下拉；复位子电路，与上拉节点、输出端和复位信号端连接，在复位信号端输入的复位信号的控制下，对上拉节点和输出端进行复位；以及，第一控制子电路，与上拉节点、第一时钟信号端和第一下拉节点连接，被配置为在上拉节点和第一时钟信号端的电平的控制下，控制第一下拉节点的电平。
根据本公开的另一方面，还提供了一种栅线驱动电路，包括多级前述的移位寄存器单元。
根据本公开的又一方面，提供了一种阵列基板，包括前述的栅线驱动电路。
根据本公开的另一方面，提供了一种应用于前述的移位寄存器单元的驱动方法，包括：向输入信号端输入有效电平，将上拉节点充电到第一高电平，开启输出子电路；经由输出子电路向栅线输出高电平的第一时钟信号作为驱动信号；向复位信号端输入有效复位电平，将上拉节点和输出端放电拉低到低电平，关闭输出子电路；以及输入高电平的第一时钟信号，开启第一下拉子电路，保持上拉节点和输出端为低电平直至输入信号端输入下一个有效电平。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1图示了一种已知的移位寄存器单元的电路结构；
图2图示了可用于该已知的移位寄存器单元的有关信号时序；
图3是根据本公开一实施例的移位寄存器单元的框图；
图4图示了根据本公开一实施例的移位寄存器单元的电路结构；
图5图示了可用于图4所示的移位寄存器单元的有关信号时序；
图6是根据本公开另一实施例的移位寄存器单元的框图；
图7是根据本公开另一实施例的移位寄存器单元的电路结构；
图8图示了可用于图7所示的移位寄存器单元的有关信号时序；
图9是根据本公开一实施例的栅线驱动装置的连接结构示意图；以及
图10是根据本公开一实施例的应用于移位寄存器单元的驱动方法的流程图。
具体实施方式
下面将结合附图对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，也属于本公开保护的范围。
图1图示了一种已知的移位寄存器单元的电路结构。如图1所示，该移位寄存器单元包括：输入晶体管M1，其栅极和漏极连接在一起，并且连接到移位寄存器单元的输入端，其源极连接到上拉节点PU；输出晶体管M3，其栅极连接上拉节点PU，漏极连接到第一时钟信号端CLK，源极连接到移位寄存器单元的输出端；电容C1，并联在输出晶体管M3的栅极和源极之间；上拉节点复位晶体管M2，其栅极连接到移位寄存器单元的复位端，漏极连接到上拉节点，源极连接到低电平输入端VSS；输出复位晶体管M14，其栅极连接到移位寄存器单元的复位端，漏极连接到移位寄存器单元的输出端，源极连接到低电平输入端VSS；上拉节点电平控制晶体管M10，其栅极连接到下拉节点PD，漏极连接到上拉节点PU，源极连接到低电平输入端VSS；输出端电平控制晶体管M11和M12，其中，M11的栅极连接到下拉节点PD，漏极连接到移位寄存器单元的输出端，源极连接到低电平输入端VSS；M12的栅极连接到第二时钟信号端CLKB，漏极连接到移位寄存器单元的输出端，源极连接到低电平输入端VSS；晶体管M13，其栅极与第二时钟信号端进行连接，漏极与移位寄存器单元的输入端连接，源极与上拉节点连接；下拉节点控制模块，其中包括晶体管M9、M5、M8和M6，其中M9的栅极和漏极连接到第二时钟信号端，源极连接下拉控制节点PD_CN；M5的栅极连接到下拉控制节点PD_CN，M5的漏极连接到第二时钟信号端，源极连接到下拉节点PD；M8的漏极连接到下拉控制节点PD_CN，M8 的栅极连接到上拉节点PU，M8的源极连接到低电平输入端VSS；M6的栅极连接到上拉节点PU，漏极连接到下拉节点PD，源极连接到低电平输入端VSS。
以下参照图2所示的信号时序来说明图1图示的移位寄存器单元的工作原理，在图2所示的a、b、c、d和e所示的五个阶段中，该移位寄存器单元进行如下操作：
在第一阶段a中，第一时钟信号端输入的时钟信号CLK为低电平，第二时钟信号端输入时钟信号CLKB为高电平，输入端INPUT接入的输入信号为高电平；应注意，在图1图示的移位寄存器单元作为第一级时，其输入端接入帧开始信号STV；由于输入端输入高电平，晶体管M1开启，使得高电平的输入信号对上拉节点PU进行充电；由于第二时钟信号CLKB为高电平，晶体管M13开启，加速上拉节点PU的充电过程；由此，上拉节点PU被充电到第一高电平，输出晶体管M3开启，向输出端输出低电平的时钟信号CLK；晶体管M9开启，对下拉控制节点PD_CN充电，然而，由于上拉节点PU处于第一高电平，晶体管M6和M8开启；在晶体管的设计上，可以将晶体管M8与M9的尺寸比配置为在M9和M8均开启时，下拉控制节点PD_CN的电平被下拉到低电平，在这种情况下，PD_CN为低电平，晶体管M5保持关断；由于晶体管M6开启，下拉节点PD的电平被下拉到低电平，从而晶体管M10和M11在此阶段处于关断状态；由于CLKB为高电平，晶体管M12开启，可以确保将移位寄存器单元的输出端拉低到低电平VSS；
在第二阶段b中，第一时钟信号端输入的时钟信号CLK为高电平，第二时钟信号端输入的时钟信号CLKB为低电平，输入端INPUT输入的信号为低电平；晶体管M1、M13、M9、M5和M12关断；输出晶体管M3开启，将高电平的时钟信号CLK输出，作为栅线驱动信号；由于存储电容C1的自举效应，上拉节点PU的电平进一步升高，达到第二高电平，使得输出晶体管M3的导通更充分；由于上拉节点PU的电平相对于阶段a的电平被提升，晶体管M8和M6的导通更充分，分别将下拉控制节点PD_CN和下拉节点PD进一步拉低；由于下拉节点PD为低电平，晶体管M10和M11保持关断状态，从而不会影响移位寄存器单元正常输出栅线驱动信号；
在第三阶段c中，第一时钟信号端输入的时钟信号CLK为低电平，第二时钟信号端输入的时钟信号CLKB为高电平，输入端INPUT继续接入低电平，复位端RESET接入高电平；由于复位端接入高电平，晶体管M2和M14开启，分别将 上拉节点PU和移位寄存器单元的输出端下拉到低电平VSS；而晶体管M1关断，晶体管M13开启，将低电平接入上拉节点PU，对上拉节点PU进行放电；上拉节点PU被放电到低电平，使得晶体管M3关断；由于第二时钟信号CLKB为高电平，晶体管M12开启，将移位寄存器单元的输出端拉低到低电平VSS；晶体管M9开启，对下拉控制节点PD_CN充电，进而使得晶体管M5开启，从而对下拉节点PD充电；由于上拉节点PU处于低电平，晶体管M6和M8关断；下拉节点PD被充电到高电平，晶体管M10和M11开启，分别将上拉节点PU和移位寄存器单元的输出端下拉到低电平VSS；
在第四阶段d中，第一时钟信号端输入的时钟信号CLK为高电平，第二时钟信号端输入的时钟信号CLKB为低电平，输入端INPUT继续接入低电平，复位端接入低电平；晶体管M1、M13、M2、M14、M9和M12关断；由于上拉节点PU保持低电平，晶体管M6和M8继续关断；由于晶体管M8和M9均关断，下拉控制节点PD_CN的放电路径被关闭，下拉控制节点PD_CN保持之前的高电平，从而使得晶体管M5保持开启，由于第二时钟信号CLKB为低电平，因此，下拉节点PD被放电。由于下拉节点PD处于低电平，晶体管M10和M11被关断，分别将上拉节点的放电路径和移位寄存器单元的输出端的放电路径关闭，从而使得上拉节点PU和输出端处于浮置状态。需注意，尽管在此阶段，移位寄存器单元处于非输出阶段，上拉节点PU和输出端均应维持之前的低电平状态，然而，由于第一时钟信号CLK为高电平，并且如图1所示，在输出晶体管M3的栅极和漏极之间存在耦合电容Cp，使得第一时钟信号CLK的高电平可能经由耦合电容Cp而耦合到上拉节点PU处形成噪声，并且最终导致晶体管M3略微开启，而在输出端产生噪声；关于这一点，可以参见图2的时序图所示的以虚线表示的波形；
在第五阶段e中，第一时钟信号端输入的时钟信号CLK为低电平，第二时钟信号端输入的时钟信号CLKB为高电平，输入端INPUT继续接入低电平，复位端接入低电平；晶体管M1、M2、M14关断；晶体管M13开启，将低电平接入上拉节点PU，对上拉节点PU进行放电，确保关断晶体管M3；CLKB为高电平，晶体管M12开启，将移位寄存器单元的输出端拉低到低电平VSS，消除移位寄存器单元的输出端的噪声；晶体管M9开启，对下拉控制节点PD_CN充电，使得晶体管M5的开启更充分，并且对下拉节点PD充电，使得下拉节点PD变成高电平； 由于上拉节点PU被放电，晶体管M6和M8关断；下拉节点PD的高电平使得晶体管M10和M11开启，分别将上拉节点PU和移位寄存器单元的输出端下拉到低电平VSS，消除了在上拉节点和输出端处形成的噪声。
之后，移位寄存器单元重复阶段d和e的操作，直至下一个有效输入信号到来。
由此可见，在上述移位寄存器单元中，由于移位寄存器单元中耦合电容Cp的存在，在移位寄存器单元的非输出阶段，具体是低电平维持阶段(例如图2所示的阶段d中，移位寄存器单元的上拉节点PU和输出端的电位易于受到输出晶体管M3所连接的时钟信号CLK的高电平的影响而产生噪声，特别是在高温工作条件下，输出晶体管的阈值电压Vth产生漂移，导致上拉节点PU和输出端受到的影响更严重，使得对应的栅线在关闭阶段出现不正常的信号，从而有可能使得与该栅线连接的像素单元的工作状态不正常，导致显示面板的显示质量的降低。
有鉴于此，根据本公开的一个方面，提出了一种移位寄存器单元。如图3所示，该移位寄存器单元包括：充电子电路110，连接在输入信号端INPUT和上拉节点PU之间，被配置为在输入信号端输入的信号的控制下，为上拉节点PU充电；输出子电路120，连接在上拉节点PU、第一时钟信号端CLK和输出端OUT之间，被配置为在上拉节点PU的电平的控制下，经由输出端输出第一时钟信号端提供的时钟信号作为驱动信号；第一下拉子电路130，与上拉节点PU、输出端OUT和第一下拉节点PD1连接，被配置为在第一下拉节点PD1的电平控制下，对上拉节点PU和输出端OUT进行下拉；以及复位子电路140，与上拉节点PU、输出端OUT和复位信号端RESET连接，被配置为在复位信号端输入的复位信号的控制下，对上拉节点PU和输出端OUT进行复位。
在根据本公开的上述移位寄存器单元中，由于配置了第一下拉子电路130，可以在移位寄存器单元驱动过程中的低电平维持阶段，根据第一下拉节点PD1的电平对上拉节点PU和输出端OUT进行下拉，消除了由于耦合电容的存在引起的噪声，从而保证向移位寄存器单元连接的栅线输出正确的驱动信号，最终确保像素显示的质量。
可选地，如图3所示，该移位寄存器单元，还包括：第一控制子电路150，与上拉节点PU、第一时钟信号端CLK和第一下拉节点PD1连接，被配置为在 上拉节点PU和第一时钟信号端CLK的电平的控制下，控制第一下拉节点PD1的电平。
由此，可以通过第一时钟信号CLK来控制第一下拉节点PD1的电平，使得在CLK输出高电平而上拉节点PU处于低电平时，将第一下拉节点PD1的电平拉高，以便开启第一下拉子电路，从而消除上拉节点PU和输出端由于耦合电容产生的噪声。
可选地，如图3所示，该移位寄存器单元，还包括：第二下拉子电路160，与上拉节点PU、输出端OUT和第二下拉节点PD2连接，被配置为在第二下拉节点PD2的电平控制下，对上拉节点PU和输出端OUT进行下拉。
由此，可以利用第二下拉子电路在第二下拉节点的控制下，对上拉节点PU和输出端OUT进行下拉，使得移位寄存器单元在输出阶段之后，当第一时钟信号为低电平时，确保上拉节点和输出端处于低电平状态。
可选地，如图3所示，该移位寄存器单元，还包括：第二控制子电路170，与第二时钟信号端CLKB和第二下拉节点PD2连接，被配置为在第二时钟信号端CLKB提供的第二时钟信号的控制下，控制第二下拉节点PD2的电平。
由此，可以通过第二时钟信号CLKB来控制第二下拉节点PD2的电平，使得在CLKB输出高电平而上拉节点PU处于低电平时，将第二下拉节点PD2的电平拉高，以便开启第二下拉子电路，从而确保上拉节点PU和输出端处于低电平。
根据上述实施例，可以在移位寄存器单元的低电平维持阶段，通过第一下拉子电路和第二下拉子电路的工作，保证上拉节点和输出端维持在低电平状态。
可选地，如图3所示，该移位寄存器单元，还包括：输出下拉子电路180，其与第二时钟信号端CLKB和输出端OUT连接，被配置为在第二时钟信号端的控制下，对输出端OUT进行下拉。
由此，可以利用输出下拉子电路在第二时钟信号的控制下对移位寄存器单元的输出端进行下拉，使得移位寄存器单元的输出端在非输出阶段中输出低电平。通过这种方式，可以增加系统的可靠性和冗余性，并且可以减小用于下拉移位寄存器单元的输出端的其它晶体管的尺寸，降低成本。
图4图示了根据本公开一实施例的移位寄存器单元的示意性的电路结 构。以下结合图3和图4对该移位寄存器单元的电路结构进行详细说明。
可选地，如图4所示，充电子电路110包括：第一薄膜晶体管(TFT)M1，其第一极和第二极连接到输入信号端INPUT，第三极连接到上拉节点PU。
可选地，如图4所示，输出子电路120包括：第二TFT M13，其第一极连接到上拉节点，第二极连接到第一时钟信号端CLK，第三极连接到输出端OUT；以及电容C1，连接在上拉节点和输出端之间。
可选地，如图4所示，第一下拉子电路130包括：第三TFT M4，其第一极连接到第一下拉节点PD1，第二极连接到上拉节点，第三极连接到低电平信号端VSS；以及第四TFT M11，其第一极连接到第一下拉节点PD1，第二极连接到输出端OUT，第三极连接到低电平信号端VSS。
可选地，如图4所示，复位子电路140包括：第五TFT M2，其第一极连接到复位信号端RESET，第二极连接到上拉节点，第三极连接到低电平信号端VSS；以及第六TFT M15，其第一极连接到复位信号端，第二极连接到输出端，第三极连接到低电平信号端VSS。
可选地，如图4所示，第一控制子电路150包括：第七TFT M9，其第一极连接到上拉节点PU，第二极连接到第一下拉节点PD1，第三极连接到低电平信号端VSS；以及第八TFT M12，其第一极和第二极连接到第一时钟信号端CLK，第三极连接到第一下拉节点PD1。
可选地，如图4所示，输出下拉子电路180包括：第九TFT M10，其第一极连接到第二时钟信号端CLKB，第二极连接到输出端OUT，第三极连接到低电平信号端VSS。
可选地，如图4所示，第二下拉子电路160包括：第十TFT M3，其第一极连接到第二下拉节点PD2，第二极连接到上拉节点，第三极连接到低电平信号端VSS；以及第十一TFT M14，其第一极连接到第二下拉节点PD2，第二极连接到输出端OUT，第三极连接到低电平信号端VSS。
可选地，如图4所示，第二控制子电路170包括：第十二TFT M5、第十三TFT M7、第十四TFT M6和第十五TFT M8；其中，第十二TFT M5的第一极和第二极连接到第二时钟信号端CLKB，第三极连接到第十三TFT M7的第一极；第十三TFTM7的第二极连接到第二时钟信号端，第三极连接到第二下拉节点；第十四TFT M6的第一极连接到上拉节点，第二极连接到第十三TFT M7 的第一极，第三极连接到低电平信号端；以及第十五TFT M8的第一极连接到上拉节点，第二极连接到第二下拉节点，第三极连接到低电平信号端VSS。
可选地，在上述移位寄存器单元中，TFT的第一极是栅极，第二极是漏极，第三极是源极。
此外，应理解，由于这里采用的TFT晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。若选取源极作为信号输入端、则漏极作为信号输出端，反之亦然。
另外，在图4中，以所有的TFT采用N型TFT为例进行了说明。然而，应理解，其中的一部分或者全部TFT可以采用P型TFT，只要相应地调整其栅极的控制电平以及向其提供的电源电压即可，这样的实施方式也在本公开的保护范围之内。
此外，尽管在图4中，低电平信号端被示为均接入低电平VSS。然而，为实现本公开的原理，低电平信号端可以接入到不同的低电平，例如具有不同电压值的低电平VSS和VGL。例如，与用于下拉移位寄存器单元输出端的晶体管连接的低电平可以接入低电平VGL，而与用于下拉移位寄存器单元的上拉节点的晶体管连接的低电平可以接入低电平VSS，其中VGL的电平低于VSS的电平。通过这种方式，可以在上拉节点和输出端均被下拉到低电平时，将移位寄存器单元的输出晶体管的栅源电势反偏，即便输出晶体管采用耗尽型晶体管时，也能保证输出晶体管的完全关断。
以下以图4所示的移位寄存器单元为例，参照图5所示的信号时序来说明其具体的工作原理。其中，该移位寄存器单元的第一时钟信号端接第一时钟信号CLK，第二时钟信号端接第二时钟信号CLKB，其输入端接STV信号；可选地，在该移位寄存器单元作为第一级时，STV表示帧起始信号，当该移位寄存器单元作为其他各级时，STV表示来自与该移位寄存器单元串联的上一级移位寄存器单元的输出信号。在图5所示的a、b、c、d和e所示的五个阶段中，该移位寄存器单元进行如下操作：
在第一阶段a中，第一时钟信号端输入的时钟信号CLK为低电平，第二时钟信号端输入的时钟信号CLKB为高电平，输入信号端INPUT接入的STV为高电平；由于输入信号端输入的STV为高电平，晶体管M1开启，使得高电平的输入 信号对上拉节点PU进行充电，到达第一高电平；由于时钟信号CLKB为高电平，晶体管M5开启，对下拉控制节点PD_CN充电，然而由于上拉节点PU处于第一高电平，晶体管M6和M8开启；在晶体管的设计上，可以将晶体管M5与M6的尺寸比配置为在M5和M6均开启时，下拉控制节点PD_CN的电平被下拉到低电平，因此，晶体管M7未被开启；由于晶体管M8开启且M7关断，因此，第二下拉节点PD2被下拉到低电平，从而保证晶体管M3和M14在此阶段处于关断状态；另外，由于第一时钟信号CLK为低电平，M12关断，而上拉节点PU为高，M9开启，因此第一下拉节点PD1被下拉到低电平，晶体管M4和M11被关断；由于上拉节点PU为高电平，为存储电容C1充电，使得输出晶体管M13开启，向输出端输出低电平的时钟信号CLK；此外，由于第二时钟信号CLKB为高电平，晶体管M10开启，从而可以确保将移位寄存器单元的输出端拉低到低电平VSS。
在第二阶段b中，第一时钟信号端输入的时钟信号CLK为高电平，第二时钟信号端输入的时钟信号CLKB为低电平，输入端INPUT接入的STV为低电平；晶体管M1、M5和M10关断；输出晶体管M13维持开启，向输出端输出高电平的第一时钟信号；由于存储电容C1的自举作用，将上拉节点PU的电位进一步提升到第二高电平，使得输出晶体管M13的导通更加充分；由于上拉节点PU的电位被进一步提升，晶体管M6和M8的导通更加充分，由于晶体管M5被关断，因此，下拉控制节点PD_CN的电平被拉得更低；晶体管M7依旧保持关断，第二下拉节点PD2的电平也被拉得更低，晶体管M3和M14依旧保持关断，从而不会影响移位寄存器单元正常输出移位信号；由于第一时钟信号CLK为高，晶体管M12开启，然而，由于上拉节点PU处于第二高电平，晶体管M9的导通更加充分，并且在设计上，可以将晶体管M9与M12的尺寸比配置为在M9和M12均开启时，第一下拉节点PD1被下拉到低电平；在这种情况下，第一下拉节点PD1的电平被下拉的更低，晶体管M4和M11保持关断，从而不会影响移位寄存器单元正常输出移位信号。
在第三阶段c中，第一时钟信号端输入的时钟信号CLK为低电平，第二时钟信号端输入的时钟信号CLKB为高电平，输入端INPUT接入的STV为低电平，晶体管M1继续保持关断，晶体管M10在高电平的CLKB的控制下开启，使得移位寄存器单元的输出端被下拉到VSS；由于复位信号端RESET为高电平，晶体管M2和M15开启，分别将上拉节点PU和输出端拉低；由于上拉节点PU被拉低到 VSS，晶体管M6、M8和M13关断，电容C1被放电；由于CLKB为高电平，晶体管M5开启，下拉控制节点PD_CN被充电，由此，下拉控制节点PD_CN被充电到高电平，从而开启晶体管M7，并且经由开启的晶体管M7，利用高电平的CLKB信号对第二下拉节点PD2充电，使得第二下拉节点PD2也被充电到高电平；由于上拉节点PU被拉低，晶体管M9关断，且由于CLK为低电平，晶体管M12也被关断，第一下拉节点PD1的电平尽管略有提升，但仍然保持低电平；尽管由于第一下拉节点PD1为低电平，晶体管M4和M11保持关断，然而由于第二下拉节点PD2为高电平，晶体管M3和M14开启，从而确保分别将上拉节点PU和输出端拉低。
在第四阶段d中，第一时钟信号端输入的时钟信号CLK为高电平，第二时钟信号端输入的时钟信号CLKB为低电平，输入端INPUT接入的STV为低电平，复位信号端RESET为低电平，晶体管M1继续保持关断，晶体管M5、M10关断；由于上拉节点PU保持低电平，晶体管M6、M8、M9和M13保持关断；由于晶体管M5和M6均关断，下拉控制节点PD_CN的放电路径被关闭，下拉控制节点PD_CN保持之前的高电平，晶体管M7保持开启，从而经由开启的晶体管M7将低电平的CLKB接入第二下拉节点PD2；由于CLK为高电平，晶体管M12开启，上拉节点PU为低电平，晶体管M9关断，因此经由开启的晶体管M12向第一下拉节点PD1充电，使之变为高电平；尽管第二下拉节点PD2为低电平，晶体管M3和M14被关断，然而，由于第一下拉节点PD1为高电平，晶体管M4和M11被开启，从而确保分别将上拉节点PU和输出端拉低。由此可见，与前一阶段相比，晶体管M4取代M3对上拉节点进行下拉，而晶体管M11取代M14对输出端进行下拉。
与图1图示的移位寄存器单元相比，在第四阶段d中，即便存在耦合电容Cp，然而由于高电平的时钟信号CLK将开启晶体管M12，并且将第一下拉节点PD1充电为高电平，从而开启晶体管M4和M11，以便分别将上拉节点PU和输出端拉低，消除了可能出现的噪声。
在第五阶段e中，第一时钟信号端输入的时钟信号CLK为低电平，第二时钟信号端输入的时钟信号CLKB为高电平，输入端INPUT接入的STV为低电平，复位信号端接入低电平；由于STV为低电平，晶体管M1继续保持关断；由于CLKB为高电平，晶体管M5和M10开启；由于上拉节点PU保持低电平，晶体管M6、M8、M9和M13保持关断；经由开启的晶体管M5，下拉控制节点PD_CN接入高电平的 时钟信号CLKB，可以保持之前的高电平；晶体管M7继续开启，将高电平的CLKB接入第二下拉节点PD2，使得第二下拉节点PD2变为高电平；由于CLK为低电平，晶体管M12关断，上拉节点PU为低电平，晶体管M9保持关断，第一下拉节点PD1的放电路径被关闭，第一下拉节点PD1保持之前的高电平；在这种情况下，由于第一下拉节点PD1保持高电平，晶体管M4和M11保持开启，分别将上拉节点PU和输出端拉低；此外，由于第二下拉节点PD2也为高电平，晶体管M3和M14也被开启，从而确保分别将上拉节点PU和输出端拉低。
之后的阶段将重复第四阶段和第五阶段的操作，直至STV信号下一个高电平的到来。
根据本公开的另一实施例，还可以对图3图示的移位寄存器单元进行简化。如图6所示，该移位寄存器单元包括：充电子电路110，连接在输入信号端INPUT和上拉节点PU之间，被配置为在输入信号端输入的信号的控制下，为上拉节点PU充电；输出子电路120，连接在上拉节点PU、第一时钟信号端CLK和输出端OUT之间，被配置为在上拉节点PU的电平的控制下，经由输出端输出第一时钟信号端提供的时钟信号作为驱动信号；第一下拉子电路130，与上拉节点PU、输出端OUT和第一下拉节点PD1连接，被配置为在第一下拉节点PD1的电平控制下，对上拉节点PU和输出端OUT进行下拉；以及复位子电路140，与上拉节点PU、输出端OUT和复位信号端RESET连接，被配置为在复位信号端输入的复位信号的控制下，对上拉节点PU和输出端OUT进行复位。
可选地，如图6所示，该移位寄存器单元，还包括：第一控制子电路150，与上拉节点PU、第一时钟信号端CLK和第一下拉节点PD1连接，被配置为在上拉节点PU和第一时钟信号端CLK的电平的控制下，控制第一下拉节点PD1的电平。
可选地，如图6所示，该移位寄存器单元，还包括：输出下拉子电路180，其与第二时钟信号端CLKB和输出端OUT连接，被配置为在第二时钟信号端的控制下，对输出端OUT进行下拉。
由此可见，与图3所示的移位寄存器单元的区别主要在于，该移位寄存器单元中也可以不包括第二下拉子电路和第二控制子电路。
在根据本公开的上述移位寄存器单元中，由于配置了第一下拉子电路 130，可以在移位寄存器单元驱动过程中的低电平维持阶段，根据第一下拉节点PD1的电平对上拉节点PU和输出端OUT进行下拉，消除了由于耦合电容的存在引起的噪声，从而保证向移位寄存器单元连接的栅线输出正确的驱动信号，最终确保像素显示的质量。
此外，由于配置了第一控制子电路，因此可以通过第一时钟信号CLK来控制第一下拉节点PD1的电平，使得在CLK输出高电平而上拉节点PU处于低电平时，将第一下拉节点PD1的电平拉高，以便开启第一下拉子电路，从而消除上拉节点PU和输出端由于耦合电容产生的噪声。
根据上述实施例，可以在移位寄存器单元的低电平维持阶段，通过第一下拉子电路的工作，保证上拉节点和输出端维持在低电平状态。
此外，在上拉节点PU的充电阶段，可以利用输出下拉子电路在第二时钟信号的控制下对移位寄存器单元的输出端进行下拉，使得移位寄存器单元的输出端在此阶段输出低电平。
图7图示了根据本公开另一实施例的移位寄存器单元的示意性的电路结构。以下结合图6和图7对该移位寄存器单元的电路结构进行详细说明。
可选地，如图7所示，充电子电路110包括：第一薄膜晶体管(TFT)M1，其第一极和第二极连接到输入信号端INPUT，第三极连接到上拉节点PU。
可选地，如图7所示，输出子电路120包括：第二TFT M13，其第一极连接到上拉节点，第二极连接到第一时钟信号端CLK，第三极连接到输出端OUT；以及电容C1，连接在上拉节点和输出端之间。
可选地，如图7所示，第一下拉子电路130包括：第三TFT M4，其第一极连接到第一下拉节点PD1，第二极连接到上拉节点，第三极连接到低电平信号端VSS；以及第四TFT M11，其第一极连接到第一下拉节点PD1，第二极连接到输出端OUT，第三极连接到低电平信号端VSS。
可选地，如图7所示，复位子电路140包括：第五TFT M2，其第一极连接到复位信号端RESET，第二极连接到上拉节点，第三极连接到低电平信号端VSS；以及第六TFT M15，其第一极连接到复位信号端，第二极连接到输出端，第三极连接到低电平信号端VSS。
可选地，如图7所示，第一控制子电路150包括：第七TFT M9，其第一极连接到上拉节点PU，第二极连接到第一下拉节点PD1，第三极连接到低电 平信号端VSS；以及第八TFT M12，其第一极和第二极连接到第一时钟信号端CLK，第三极连接到第一下拉节点PD1。
可选地，如图7所示，输出下拉子电路180包括：第九TFT M10，其第一极连接到第二时钟信号端CLKB，第二极连接到输出端OUT，第三极连接到低电平信号端VSS。
与图4图示的移位寄存器单元电路相比，图7图示的移位寄存器单元电路移除了第二下拉子电路和第二控制子电路，简化了电路结构。
可选地，在上述移位寄存器单元中，TFT的第一极是栅极，第二极是漏极，第三极是源极。
此外，应理解，由于这里采用的TFT晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。若选取源极作为信号输入端、则漏极作为信号输出端，反之亦然。
另外，在图7中，以所有的TFT采用N型TFT为例进行了说明。然而，应理解，其中的一部分或者全部TFT可以采用P型TFT，只要相应地调整其栅极的控制电平以及向其提供的电源电压即可，这样的实施方式也在本公开的保护范围之内。
此外，尽管在图7中，低电平信号端被示为均接入低电平VSS。然而，为实现本公开的原理，低电平信号端可以接入到不同的低电平，例如具有不同电压值的低电平VSS和VGL。例如，与用于下拉移位寄存器单元输出端的晶体管连接的低电平可以接入低电平VGL，而与用于下拉移位寄存器单元的上拉节点的低电平可以接入低电平VSS，其中VGL的电平低于VSS的电平。通过这种方式，可以在上拉节点和输出端均被下拉到低电平时，将移位寄存器单元的输出晶体管的栅源电势反偏，即便输出晶体管采用耗尽型晶体管时，也能保证输出晶体管的完全关断。
以下以图7所示的移位寄存器单元为例，参照图8所示的信号时序来说明其具体的工作原理。其中，该移位寄存器单元的第一时钟信号端接第一时钟信号CLK，第二时钟信号端接第二时钟信号CLKB，其输入端接STV信号；可选地，在该移位寄存器单元作为第一级时，STV表示帧起始信号，当该移位寄存器单元作为其他各级时，STV表示来自与该移位寄存器单元串联的上一级移位 寄存器单元的输出信号。在图8所示的a、b、c、d和e所示的五个阶段中，该移位寄存器单元进行如下操作：
在第一阶段a中，第一时钟信号端输入的时钟信号CLK为低电平，第二时钟信号端输入的时钟信号CLKB为高电平，输入信号端INPUT接入的STV为高电平；由于输入信号端输入的STV为高电平，晶体管M1开启，使得高电平的输入信号对上拉节点PU进行充电，达到第一高电平；由于第一时钟信号CLK为低电平，M12关断，而上拉节点PU为高，M9开启，因此第一下拉节点PD1被下拉到低电平，晶体管M4和M11被关断；由于上拉节点PU为高电平，为存储电容C1充电，使得输出晶体管M13开启，向输出端输出低电平的时钟信号CLK；此外，由于第二时钟信号CLKB为高电平，晶体管M10开启，从而可以确保将移位寄存器单元的输出端拉低到低电平VSS。
在第二阶段b中，第一时钟信号端输入的时钟信号CLK为高电平，第二时钟信号端输入的时钟信号CLKB为低电平，输入端INPUT接入的STV为低电平；晶体管M1和M10关断；输出晶体管M13维持开启，向输出端输出高电平的第一时钟信号；由于存储电容C1的自举作用，将上拉节点PU的电位进一步提升到第二高电平，使得输出晶体管M13的导通更加充分，保证栅线连接的像素的充电；由于第一时钟信号CLK为高，晶体管M12开启，然而，由于上拉节点PU被进一步提示到第二高电平，晶体管M9的导通更加充分，并且在设计上，可以将晶体管M9与M12的尺寸比配置为在M9和M12均开启时，第一下拉节点PD1被下拉到低电平；在这种情况下，第一下拉节点PD1的电平被下拉的更低，晶体管M4和M11保持关断，从而不会影响移位寄存器单元正常输出移位信号。
在第三阶段c中，第一时钟信号端输入的时钟信号CLK为低电平，第二时钟信号端输入的时钟信号CLKB为高电平，输入端INPUT接入的STV为低电平，晶体管M1继续保持关断，晶体管M10在高电平的CLKB的控制下开启，使得移位寄存器单元的输出端被下拉到VSS；由于复位信号端RESET为高电平，晶体管M2和M15开启，分别将上拉节点PU和输出端拉低；由于上拉节点PU被拉低到VSS，电容C1被放电；由于上拉节点PU被拉低，晶体管M9关断，且由于CLK为低电平，晶体管M12也被关断，第一下拉节点PD1的电平尽管略有提升，但仍然保持低电平；尽管由于第一下拉节点PD1为低电平，晶体管M4和M11保持关断，然而由于复位信号端输入高电平，开启晶体管M2和M15,从而确保分别将 上拉节点PU和输出端拉低。
在第四阶段d中，第一时钟信号端输入的时钟信号CLK为高电平，第二时钟信号端输入的时钟信号CLKB为低电平，输入端INPUT接入的STV为低电平，复位信号端RESET为低电平，晶体管M1继续保持关断，晶体管M10关断；由于上拉节点PU保持低电平，M13保持关断；由于CLK为高电平，晶体管M12开启，而上拉节点PU为低电平，晶体管M9关断，因此经由开启的晶体管M12向第一下拉节点PD1充电，使之变为高电平；由于第一下拉节点PD1为高电平，晶体管M4和M11被开启，从而确保分别将上拉节点PU和输出端拉低。
与图1图示的移位寄存器单元相比，在第四阶段d中，即便存在耦合电容Cp，然而由于高电平的时钟信号CLK将开启晶体管M12，并且将第一下拉节点PD1充电为高电平，从而开启晶体管M4和M11，以便分别将上拉节点PU和输出端拉低，消除了可能出现的噪声。
在第五阶段e中，第一时钟信号端输入的时钟信号CLK为低电平，第二时钟信号端输入的时钟信号CLKB为高电平，输入端INPUT接入的STV为低电平，复位信号端接入低电平；由于STV为低电平，晶体管M1继续保持关断；由于CLKB为高电平，晶体管M10开启；由于上拉节点PU保持低电平，晶体管M13保持关断；由于CLK为低电平，晶体管M12关断，而上拉节点PU为低电平，晶体管M9保持关断，第一下拉节点PD1的放电路径被关闭，第一下拉节点PD1保持之前的高电平；在这种情况下，由于第一下拉节点PD1保持高电平，晶体管M4和M11保持开启，分别将上拉节点PU和输出端拉低。
之后的阶段将重复第四阶段和第五阶段的操作，直至STV信号下一个高电平的到来。
由此可见，根据图7所示的移位寄存器单元电路，也可以实现在移位寄存器单元的低电平维持阶段，消除由于耦合电容所引起的噪声。
根据本公开的另一方面，还提供了一种栅线驱动装置。如图9所示，该栅线驱动装置包括多级前述的移位寄存器单元。
可选地，其中，每一级移位寄存器单元的输出端连接一条栅线；奇数级移位寄存器单元连接第一和第三时钟信号，偶数级的移位寄存器单元连接第二和第四时钟信号；奇数级移位寄存器单元彼此串联连接，偶数级移位寄存器单元彼此串联连接；在串联的两级移位寄存器单元中，第一时钟信号端和 第二时钟信号端输入的时钟信号互换，前一级移位寄存器单元的输出端连接到后一级移位寄存器单元的输入信号端，该前一级移位寄存器单元的复位信号端连接到该后一级移位寄存器单元的输出端。如图9所示，以第N级移位寄存器单元为例，其输出端OUTPUT连接到第N条栅线G(n)和第(N+2)级移位寄存器单元的输入信号端INPUT，其输入端连接到第(n-2)级移位寄存器单元的输出端OUT，其复位信号端RESET连接到第(N+2)级移位寄存器单元的输出端。
根据本公开的又一方面，还提供了一种用于对图3或图6所示的移位寄存器单元进行驱动控制的方法。如图10所示，该方法主要包括步骤：S1010，向输入信号端输入有效电平，将上拉节点充电到第一高电平，开启输出子电路；S1020，经由输出子电路向栅线输出高电平的第一时钟信号作为驱动信号；S1030，向复位信号端输入有效复位电平，将上拉节点和输出端放电拉低到低电平，关闭输出子电路；S1040，输入高电平的第一时钟信号，开启第一下拉子电路，保持上拉节点和输出端为低电平直至输入信号端输入下一个有效电平。
可选地，在步骤S1010中，输入高电平的第二时钟信号，以便对输出端进行下拉。
可选地，在步骤S1040中，通过输入的高电平的第一时钟信号开启第一控制子电路，为第一下拉节点充电，以便开启第一下拉子电路。
在根据本公开实施例的移位寄存器单元的驱动方法中，在移位寄存器单元的低电平维持阶段，通过第一时钟信号开启第一控制子电路，为第一下拉节点充电，从而开启第一下拉子电路而将上拉节点和输出端拉低，以便消除由耦合电容引起的噪声，改善输出到栅线的信号波形，提高了像素的显示质量。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开实施例公开的技术范围内，可轻易想到的变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应该以权利要求的保护范围为准。
本申请要求于2016年5月30日递交的中国专利申请第201610371835.7号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的 一部分。

Claims (18)

  1. 一种移位寄存器电路，包括：
    充电子电路，与输入信号端和上拉节点连接，被配置为在输入信号端输入的信号的控制下，为上拉节点充电；
    输出子电路，与上拉节点、第一时钟信号端和输出端连接，被配置为在上拉节点的电平的控制下，通过输出端输出第一时钟信号端提供的时钟信号作为驱动信号；
    第一下拉子电路，与上拉节点、输出端和第一下拉节点连接，被配置为在第一下拉节点的电平控制下，对上拉节点和输出端进行下拉；
    复位子电路，与上拉节点、输出端和复位信号端连接，被配置为在复位信号端输入的复位信号的控制下，对上拉节点和输出端进行复位；以及，
    第一控制子电路，与上拉节点、第一时钟信号端和第一下拉节点连接，被配置为在上拉节点和第一时钟信号端的电平的控制下，控制第一下拉节点的电平。
  2. 根据权利要求1所述的移位寄存器电路，还包括：
    输出下拉子电路，其与第二时钟信号端和输出端连接，被配置为在第二时钟信号端的控制下，对输出端进行下拉。
  3. 根据权利要求1-2任一项所述的移位寄存器电路，还包括：
    第二下拉子电路，与上拉节点、输出端和第二下拉节点连接，被配置为在第二下拉节点的电平控制下，对上拉节点和输出端进行下拉。
  4. 根据权利要求1-3任一项所述的移位寄存器电路，还包括：
    第二控制子电路，与第二时钟信号端和第二下拉节点连接，被配置为在第二时钟信号端提供的第二时钟信号的控制下，控制第二下拉节点的电平。
  5. 根据权利要求1-4任一项所述的移位寄存器电路，其中，所述充电子电路包括：
    第一薄膜晶体管TFT，其第一极和第二极连接到输入信号端，第三极连接到上拉节点。
  6. 根据权利要求1-5任一项所述的移位寄存器电路，其中，所述输出子电路包括：
    第二TFT，其第一极连接到上拉节点，第二极连接到第一时钟信号端，第三极连接到输出端；以及
    电容，连接在上拉节点和输出端之间。
  7. 根据权利要求1-6任一项所述的移位寄存器电路，其中，所述第一下拉子电路包括：
    第三TFT，其第一极连接到第一下拉节点，第二极连接到上拉节点，第三极连接到低电平信号端；以及
    第四TFT，其第一极连接到第一下拉节点，第二极连接到输出端，第三极连接到低电平信号端。
  8. 根据权利要求1-7任一项所述的移位寄存器电路，其中，复位子电路包括：
    第五TFT，其第一极连接到复位信号端，第二极连接到上拉节点，第三极连接到低电平信号端；以及
    第六TFT，其第一极连接到复位信号端，第二极连接到输出端，第三极连接到低电平信号端。
  9. 根据权利要求1-8任一项所述的移位寄存器电路，其中，第一控制子电路包括：
    第七TFT，其第一极连接到上拉节点，第二极连接到第一下拉节点，第三极连接到低电平信号端；以及
    第八TFT，其第一极和第二极连接到第一时钟信号端，第三极连接到第一下拉节点。
  10. 根据权利要求2所述的移位寄存器电路，其中，输出下拉子电路包括：
    第九TFT，其第一极连接到第二时钟信号端，第二极连接到输出端，第三极连接到低电平信号端。
  11. 根据权利要求3所述的移位寄存器电路，其中，第二下拉子电路包括：
    第十TFT，其第一极连接到第二下拉节点，第二极连接到上拉节点，第三极连接到低电平信号端；以及
    第十一TFT，其第一极连接到第二下拉节点，第二极连接到输出端，第 三极连接到低电平信号端。
  12. 根据权利要求4所述的移位寄存器电路，其中，第二控制子电路包括：第十二TFT、第十三TFT、第十四TFT和第十五TFT；
    其中，第十二TFT的第一极和第二极连接到第二时钟信号端，第三极连接到第十三TFT的第一极；
    第十三TFT的第二极连接到第二时钟信号端，第三极连接到第二下拉节点；
    第十四TFT的第一极连接到上拉节点，第二极连接到第十三TFT的第一极，第三极连接到低电平信号端；以及
    第十五TFT的第一极连接到上拉节点，第二极连接到第二下拉节点，第三极连接到低电平信号端。
  13. 一种栅线驱动电路，包括多级根据权利要求1-12任一项所述的移位寄存器电路。
  14. 根据权利要求13所述的栅线驱动电路，其中，每一级移位寄存器电路的输出端连接一条栅线；奇数级移位寄存器电路连接第一和第三时钟信号，偶数级的移位寄存器电路连接第二和第四时钟信号；奇数级移位寄存器电路彼此串联连接，偶数级移位寄存器电路彼此串联连接，在串联的两级移位寄存器电路中，第一时钟信号端和第二时钟信号端输入的时钟信号互换，前一级移位寄存器电路的输出端连接到后一级移位寄存器电路的输入信号端，该前一级移位寄存器电路的复位信号端连接到该后一级移位寄存器电路的输出端。
  15. 一种阵列基板，包括根据权利要求13或14所述的栅线驱动电路。
  16. 一种应用于移位寄存器电路的驱动方法，所述移位寄存器电路包括：
    充电子电路，与输入信号端和上拉节点连接；输出子电路，与上拉节点、第一时钟信号端和输出端连接；第一下拉子电路，与上拉节点、输出端和第一下拉节点连接；复位子电路，与上拉节点、输出端和复位信号端连接；以及，第一控制子电路，与上拉节点、第一时钟信号端和第一下拉节点连接；
    所述驱动方法包括：
    向输入信号端输入有效电平，将上拉节点充电到第一高电平，开启输出子电路；
    经由输出子电路向栅线输出高电平的第一时钟信号作为驱动信号；
    向复位信号端输入有效复位电平，将上拉节点和输出端放电拉低到低电平，关闭输出子电路；以及
    输入高电平的第一时钟信号，开启第一下拉子电路，保持上拉节点和输出端为低电平直至输入信号端输入下一个有效电平。
  17. 根据权利要求16所述的驱动方法，其中，在对上拉节点进行充电时，输入高电平的第二时钟信号，以便对输出端进行下拉。
  18. 根据权利要求16或17所述的驱动方法，其中，输入高电平的第一时钟信号，开启第一控制子电路为第一下拉节点充电，以便开启第一下拉子电路。
PCT/CN2017/086071 2016-05-30 2017-05-26 移位寄存器电路及其驱动方法、栅线驱动电路和阵列基板 WO2017206806A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/742,723 US20180211606A1 (en) 2016-05-30 2017-05-26 Shift register circuit and driving method therefor, gate line driving circuit and array substrate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610371835.7 2016-05-30
CN201610371835.7A CN105810170B (zh) 2016-05-30 2016-05-30 移位寄存器单元及其驱动方法、栅线驱动电路和阵列基板

Publications (1)

Publication Number Publication Date
WO2017206806A1 true WO2017206806A1 (zh) 2017-12-07

Family

ID=56427755

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/086071 WO2017206806A1 (zh) 2016-05-30 2017-05-26 移位寄存器电路及其驱动方法、栅线驱动电路和阵列基板

Country Status (3)

Country Link
US (1) US20180211606A1 (zh)
CN (1) CN105810170B (zh)
WO (1) WO2017206806A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109448630A (zh) * 2019-01-11 2019-03-08 合肥鑫晟光电科技有限公司 一种移位寄存器及其驱动方法、栅极驱动电路、显示装置

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105810170B (zh) * 2016-05-30 2018-10-26 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅线驱动电路和阵列基板
CN106448533A (zh) 2016-09-30 2017-02-22 京东方科技集团股份有限公司 移位寄存器单元、栅极扫描电路、驱动方法、显示装置
CN106448538B (zh) 2016-11-01 2019-11-12 合肥鑫晟光电科技有限公司 栅极驱动单元、栅极驱动电路及其驱动方法和显示装置
CN106409267B (zh) * 2016-12-16 2019-04-05 上海中航光电子有限公司 一种扫描电路、栅极驱动电路及显示装置
CN106814911B (zh) * 2017-01-18 2019-10-08 京东方科技集团股份有限公司 触控式电子设备、触控显示装置及阵列基板栅极驱动电路
CN107146570A (zh) 2017-07-17 2017-09-08 京东方科技集团股份有限公司 移位寄存器单元、扫描驱动电路、阵列基板和显示装置
CN107705762B (zh) * 2017-09-27 2020-03-10 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动装置和显示装置
CN108597431A (zh) * 2018-02-12 2018-09-28 京东方科技集团股份有限公司 移位寄存器单元及其控制方法、栅极驱动电路、显示装置
CN108447438B (zh) * 2018-04-10 2020-12-08 京东方科技集团股份有限公司 显示装置、栅极驱动电路、移位寄存器及其控制方法
CN109064993B (zh) * 2018-11-06 2020-01-21 合肥京东方光电科技有限公司 移位寄存器及其驱动方法、栅极驱动电路和显示装置
CN109243357B (zh) * 2018-11-12 2021-11-12 中国科学院微电子研究所 像素扫描的驱动电路及方法
CN109377934A (zh) * 2018-12-27 2019-02-22 厦门天马微电子有限公司 移位寄存器单元、其驱动方法、栅极驱动电路及显示装置
CN111243543B (zh) 2020-03-05 2021-07-23 苏州华星光电技术有限公司 Goa电路、tft基板、显示装置及电子设备
CN113035258A (zh) * 2021-03-09 2021-06-25 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路及显示面板
CN113724637B (zh) * 2021-08-31 2023-12-26 京东方科技集团股份有限公司 栅极驱动电路、移位寄存单元及其驱动方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101556833A (zh) * 2008-04-11 2009-10-14 北京京东方光电科技有限公司 移位寄存器及液晶显示器栅极驱动装置
JP2010086637A (ja) * 2008-10-02 2010-04-15 Mitsubishi Electric Corp シフトレジスタ回路およびそれを備える画像表示装置
CN104464600A (zh) * 2014-12-26 2015-03-25 合肥鑫晟光电科技有限公司 移位寄存器单元及其驱动方法、移位寄存器电路以及显示装置
CN105551421A (zh) * 2016-03-02 2016-05-04 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路和显示装置
CN105810170A (zh) * 2016-05-30 2016-07-27 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅线驱动电路和阵列基板

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI323869B (en) * 2006-03-14 2010-04-21 Au Optronics Corp Shift register circuit
JP5079301B2 (ja) * 2006-10-26 2012-11-21 三菱電機株式会社 シフトレジスタ回路およびそれを備える画像表示装置
JP4912186B2 (ja) * 2007-03-05 2012-04-11 三菱電機株式会社 シフトレジスタ回路およびそれを備える画像表示装置
KR100843430B1 (ko) * 2007-04-04 2008-07-03 삼성전기주식회사 솔리톤을 이용한 광도파로 제조 방법
CN102012591B (zh) * 2009-09-04 2012-05-30 北京京东方光电科技有限公司 移位寄存器单元及液晶显示器栅极驱动装置
CN102254503B (zh) * 2010-05-19 2013-06-12 北京京东方光电科技有限公司 移位寄存器单元、显示器用栅极驱动装置及液晶显示器
JP5193263B2 (ja) * 2010-10-21 2013-05-08 シャープ株式会社 文書生成装置、文書生成方法、コンピュータプログラムおよび記録媒体
CN102467890B (zh) * 2010-10-29 2014-05-07 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动装置及液晶显示器
CN102651186B (zh) * 2011-04-07 2015-04-01 北京京东方光电科技有限公司 移位寄存器及栅线驱动装置
CN102654982B (zh) * 2011-05-16 2013-12-04 京东方科技集团股份有限公司 移位寄存器单元电路、移位寄存器、阵列基板及液晶显示器
CN102654986A (zh) * 2011-11-25 2012-09-05 京东方科技集团股份有限公司 移位寄存器的级、栅极驱动器、阵列基板以及显示装置
CN102708778B (zh) * 2011-11-28 2014-04-23 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动装置与显示装置
KR101963595B1 (ko) * 2012-01-12 2019-04-01 삼성디스플레이 주식회사 게이트 구동 회로 및 이를 구비한 표시 장치
CN102915698B (zh) * 2012-10-18 2016-02-17 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路和显示装置
CN102930814A (zh) * 2012-10-29 2013-02-13 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动装置与显示装置
CN102945650B (zh) * 2012-10-30 2015-04-22 合肥京东方光电科技有限公司 一种移位寄存器及阵列基板栅极驱动装置
CN103198781B (zh) * 2013-03-01 2015-04-29 合肥京东方光电科技有限公司 移位寄存器单元、栅极驱动装置及显示装置
CN103258500B (zh) * 2013-04-24 2015-02-04 合肥京东方光电科技有限公司 一种移位寄存单元及显示装置
US9437324B2 (en) * 2013-08-09 2016-09-06 Boe Technology Group Co., Ltd. Shift register unit, driving method thereof, shift register and display device
CN103700356A (zh) * 2013-12-27 2014-04-02 合肥京东方光电科技有限公司 移位寄存器单元及其驱动方法、移位寄存器、显示装置
CN104616616B (zh) * 2015-02-12 2017-12-15 京东方科技集团股份有限公司 栅极驱动电路及其驱动方法、阵列基板、显示装置
CN105118414B (zh) * 2015-09-17 2017-07-28 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路、显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101556833A (zh) * 2008-04-11 2009-10-14 北京京东方光电科技有限公司 移位寄存器及液晶显示器栅极驱动装置
JP2010086637A (ja) * 2008-10-02 2010-04-15 Mitsubishi Electric Corp シフトレジスタ回路およびそれを備える画像表示装置
CN104464600A (zh) * 2014-12-26 2015-03-25 合肥鑫晟光电科技有限公司 移位寄存器单元及其驱动方法、移位寄存器电路以及显示装置
CN105551421A (zh) * 2016-03-02 2016-05-04 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路和显示装置
CN105810170A (zh) * 2016-05-30 2016-07-27 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅线驱动电路和阵列基板

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109448630A (zh) * 2019-01-11 2019-03-08 合肥鑫晟光电科技有限公司 一种移位寄存器及其驱动方法、栅极驱动电路、显示装置

Also Published As

Publication number Publication date
US20180211606A1 (en) 2018-07-26
CN105810170B (zh) 2018-10-26
CN105810170A (zh) 2016-07-27

Similar Documents

Publication Publication Date Title
WO2017206806A1 (zh) 移位寄存器电路及其驱动方法、栅线驱动电路和阵列基板
US11263942B2 (en) Shift register unit and driving method thereof, gate driving circuit, and display device
JP7315469B2 (ja) シフトレジスタユニットおよびその駆動方法、ゲート駆動回路および表示装置
US11176871B2 (en) Shift register unit and driving method thereof, gate driving circuit and display device
US11328672B2 (en) Shift register unit and driving method thereof, gate driving circuit, and display device
US11081058B2 (en) Shift register unit, gate drive circuit, display device and driving method
US11087855B2 (en) Shift register unit and driving method, gate drive circuit and display device
WO2017059792A1 (zh) 移位寄存器单元、栅线驱动装置以及驱动方法
US9177666B2 (en) Shift register unit and driving method thereof, shift register and display apparatus
US9396813B2 (en) Shift register cell, shift register, gate driver and display panel
US8531224B2 (en) Shift register, scanning signal line drive circuit provided with same, and display device
EP1911037B1 (en) A multiple input circuit
EP2787508B1 (en) Drive circuit, shift register, gate drive, array substrate and display device
US9824771B2 (en) Gate shift register and display device using the same
KR101552420B1 (ko) 주사 신호선 구동 회로, 그것을 구비한 표시 장치 및 주사 신호선의 구동 방법
US7738623B2 (en) Shift register circuit and image display apparatus containing the same
TWI540554B (zh) Liquid crystal display device and driving method thereof
US20180330687A1 (en) GOA Drive Unit And Drive Circuit
US20170102814A1 (en) Shift register unit, a shift register, a driving method, and an array substrate
WO2020010852A1 (zh) 移位寄存器单元、驱动方法、栅极驱动电路和显示装置
WO2019242317A1 (zh) 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
US20160240159A1 (en) Shift register and display device
US10923064B2 (en) Scanning signal line drive circuit and display device equipped with same
WO2019218625A1 (zh) 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
US20190108810A1 (en) Shift register and display device provided with same

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15742723

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17805751

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17805751

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 28.06.2019)

122 Ep: pct application non-entry in european phase

Ref document number: 17805751

Country of ref document: EP

Kind code of ref document: A1