WO2017156808A1 - 薄膜晶体管的制作方法 - Google Patents

薄膜晶体管的制作方法 Download PDF

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Publication number
WO2017156808A1
WO2017156808A1 PCT/CN2016/078761 CN2016078761W WO2017156808A1 WO 2017156808 A1 WO2017156808 A1 WO 2017156808A1 CN 2016078761 W CN2016078761 W CN 2016078761W WO 2017156808 A1 WO2017156808 A1 WO 2017156808A1
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Prior art keywords
thin film
film transistor
layer
region
metal
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PCT/CN2016/078761
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English (en)
French (fr)
Inventor
卢马才
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US15/121,928 priority Critical patent/US10340365B2/en
Publication of WO2017156808A1 publication Critical patent/WO2017156808A1/zh
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    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
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    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
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    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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    • G02F2202/00—Materials and properties
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Definitions

  • the present invention relates to the field of transistor fabrication, and in particular to a method of fabricating a thin film transistor.
  • Low temperature polysilicon thin film transistor The TFT substrate can be applied to high-order displays such as an LCD (Liquid Crystal Display) and an AMOLED (Active Matrix Organic Light Emitting Diode).
  • LCD Liquid Crystal Display
  • AMOLED Active Matrix Organic Light Emitting Diode
  • Low-temperature polysilicon thin film transistors have higher carrier mobility than other TFTs, and higher carrier mobility tends to cause hot carrier effects and may even cause failure of thin film transistors.
  • a shallow doping transition region is formed in the source and the drain of the low temperature polysilicon thin film transistor by ion implantation.
  • an ion implantation operation is performed on the source and the drain of the low-temperature polysilicon thin film transistor, it is difficult to form a symmetrical shallow doping transition region on both sides of the source and the drain, which tends to cause misalignment or offset of the gate region.
  • the present invention provides a method for fabricating a thin film transistor which can form a symmetric low-doped region on both sides of a source and a drain, and which has a simple fabrication process, and is difficult to solve the existing method for fabricating a thin film transistor.
  • a symmetric shallow doped transition region is formed on both sides of the source and the drain, thereby easily causing a technical problem of doping deviation or offset of the gate region.
  • Embodiments of the present invention provide a method of fabricating a thin film transistor, including:
  • Metal etching is performed on a gate region of the first metal layer and a region other than the low doped region to expose the insulating layer;
  • the step of depositing a buffer layer on the substrate substrate and patterning the buffer layer includes:
  • the polysilicon buffer layer is patterned.
  • the step of performing the removing operation on the photoresist further comprises:
  • the metal semi-transmissive mask is etched.
  • the first metal layer is a single metal layer or a plurality of stacked metal layers composed of at least one of molybdenum and aluminum.
  • the implanted ions are phosphorus ions or arsenic ions.
  • the implanted ions are boron ions.
  • the embodiment of the invention further provides a method for fabricating a thin film transistor, which comprises:
  • Metal etching is performed on a gate region of the first metal layer and a region other than the low doped region to expose the insulating layer;
  • the photoresist is removed.
  • the step of performing the removing operation on the photoresist further comprises:
  • the metal semi-transmissive mask is etched.
  • the step of performing the removing operation on the photoresist further comprises:
  • the step of depositing a buffer layer on the substrate substrate and patterning the buffer layer comprises:
  • the polysilicon buffer layer is patterned.
  • the first metal layer is a single metal layer or a plurality of stacked metal layers composed of at least one of molybdenum and aluminum.
  • the implanted ions are phosphorus ions or arsenic ions.
  • the implanted ions are boron ions.
  • the embodiment of the invention further provides a method for fabricating a thin film transistor, which comprises:
  • Metal etching is performed on the first gate region, the low doped region, and the region outside the second gate region of the first metal layer to expose the insulating layer;
  • the third photoresist is subjected to a removal operation.
  • the step of performing the removing operation on the first photoresist and the second photoresist further includes:
  • the metal semi-transmissive mask is etched.
  • the step of performing the removing operation on the third photoresist further comprises:
  • the step of depositing a buffer layer on the substrate substrate and patterning the buffer layer comprises:
  • the polysilicon buffer layer is patterned.
  • the first metal layer is a single metal layer or a plurality of stacked metal layers composed of at least one of molybdenum and aluminum.
  • the implanted ions are phosphorus ions or arsenic ions.
  • the implanted ions are boron ions.
  • the manufacturing method of the thin film transistor of the invention realizes the doping operation of the low doped region by the metal semi-transparent mask, ensures the formation of a symmetrical low-doped region on both sides of the source and the drain, and the fabrication process is simple;
  • the fabrication method of the existing thin film transistor is difficult to form a symmetrical shallow doping transition region on both sides of the source and the drain, thereby easily causing a technical problem of doping deviation or offset of the gate region.
  • 2A to 2H are specific manufacturing flowcharts of a first preferred embodiment of a method of fabricating a thin film transistor of the present invention
  • FIG. 3 is a flow chart showing a second preferred embodiment of a method of fabricating a thin film transistor of the present invention.
  • 4A to 4M are flowcharts showing a specific fabrication of a second preferred embodiment of the method of fabricating the thin film transistor of the present invention.
  • FIG. 1 is a flow chart of a first preferred embodiment of a method for fabricating a thin film transistor of the present invention.
  • the manufacturing method of the thin film transistor of the preferred embodiment includes:
  • Step S101 providing a substrate substrate
  • Step S102 depositing a buffer layer on the substrate, and patterning the buffer layer to form an active region of the thin film transistor;
  • Step S103 sequentially depositing an insulating layer and a first metal layer on the base substrate;
  • Step S104 applying a photoresist on the gate region and the low doping region of the first metal layer
  • Step S105 performing metal etching on the gate region of the first metal layer and the region outside the low doped region to expose the insulating layer;
  • Step S106 performing ashing treatment on the photoresist to expose the low doped region of the first metal layer
  • Step S107 performing metal etching on the first metal layer of the low doped region to form a metal semi-transmissive mask
  • Step S108 performing ion implantation on the active region to form a source region, a source low doping region, a channel region, a drain low doping region, and a drain region of the thin film transistor;
  • Step S109 performing a removal operation on the photoresist
  • Step S110 depositing a dielectric layer on the substrate, and forming a source via and a drain via on the dielectric layer;
  • Step S111 depositing a second metal layer on the substrate, and patterning the second metal layer to form a source and a drain of the thin film transistor through the source via and the drain via;
  • Step S112 depositing an organic flat layer on the base substrate, and forming a pixel electrode through hole on the organic flat layer;
  • Step S113 depositing a pixel electrode layer on the base substrate, and patterning the pixel electrode layer to form a corresponding pixel electrode through the pixel electrode through hole.
  • step S101 a base substrate 21 is provided, and then the process proceeds to step S102.
  • an amorphous silicon buffer layer is deposited on the base substrate 21; the material of the amorphous silicon buffer layer may be at least one of silicon nitride and silicon oxide; the amorphous silicon buffer layer is subsequently subjected to quasi-alignment Molecular laser annealing causes amorphous silicon to be converted into polysilicon to form a polysilicon buffer layer. Then, patterning treatment such as photoresist coating, exposure development, and etching is performed to form the active layer 22 of the thin film transistor. Next, the photoresist is peeled off, and the process proceeds to step S103.
  • step S103 an insulating layer 23 and a first metal layer 24 are sequentially deposited on the base substrate 21.
  • the material of the insulating layer 23 may be at least one of silicon nitride and silicon oxide, and the first metal layer 24 is made of molybdenum. And a single metal layer or a plurality of stacked metal layers composed of at least one metal of aluminum. Then it proceeds to step S104.
  • step S104 a photoresist 25 is coated on the gate region 241 of the first metal layer 24 and the low doped region 242, and the projection of the active region 22 on the first metal layer 24 covers the gate region 241 and the low doping
  • the structure of the thin film transistor after coating please refer to FIG. 2A. Then it proceeds to step S105.
  • step S105 the gate region 241 of the first metal layer 24 and the region other than the low doped region 242 are metal etched to expose the insulating layer 23; the structure of the thin film transistor after metal etching is shown in the figure. 2B. Then it proceeds to step S106.
  • step S106 the photoresist 25 is subjected to ashing treatment to expose the low-doped region 242 of the first metal layer 24; since the effect of the ashing treatment on both sides of the photoresist 25 is the same, thus in the first metal The areas of the low doped regions 242 exposed on both sides of the layer 24 are the same.
  • ashing treatment to expose the low-doped region 242 of the first metal layer 24; since the effect of the ashing treatment on both sides of the photoresist 25 is the same, thus in the first metal
  • the areas of the low doped regions 242 exposed on both sides of the layer 24 are the same.
  • step S107 the first metal layer 24 of the low doped region 242 is metal etched, that is, the first metal layer 24 of the partially doped region 242 is etched away, and the first metal of the remaining low doped region 242 is removed.
  • Layer 24 constitutes a metal semi-transmissive mask.
  • the structure of the thin film transistor after metal etching please refer to FIG. 2D. Then it proceeds to step S108.
  • step S108 the active region 22 is ion-implanted, and the source region 221 and the drain region 222 of the thin film transistor are formed after implanting ions in the active region without the metal layer blocking; the active layer having the metal semi-transmissive mask blocking 22 implanting ions to form a source low doped region 223 and a drain low doped region 224 of the thin film transistor; the active layer 22 having the photoresist layer and the metal layer blocking is not implanted with ions, and the active layer 22 of the region forms a thin film The channel region 225 of the transistor.
  • the implanted ions are phosphorus ions or arsenic ions; if the thin film transistor is a P-type metal-oxide-semiconductor thin film transistor, the implanted ions are boron ions. Please refer to FIG. 2E for details. Then it proceeds to step S109.
  • step S109 the photoresist 25 is removed.
  • the structure of the thin film transistor after the removal operation please refer to FIG. 2F.
  • the metal semi-transmissive mask can also be etched, and the structure of the thin film transistor after the etching process is as shown in FIG. 2G. Then it proceeds to step S110.
  • step S110 a dielectric layer 26 is deposited on the base substrate 21, and a source via hole 261 and a drain via 262 are formed on the dielectric layer 26 through photoresist coating, exposure development, and etch hole drilling; Go to step S111.
  • step S111 a second metal layer is deposited on the base substrate 21, and the second metal layer is patterned to pass through the source via 261 and the drain via 262 to form the source 271 of the thin film transistor and The drain 272; then proceeds to step S112.
  • step S112 an organic flat layer 28 is deposited on the base substrate 21, and a pixel electrode via 281 is formed on the organic flat layer 28; then, the process proceeds to step S113.
  • step S113 a pixel electrode layer is deposited on the base substrate 21, and the pixel electrode layer is patterned to pass through the pixel electrode via 281 to form a corresponding pixel electrode 29.
  • a pixel electrode layer is deposited on the base substrate 21, and the pixel electrode layer is patterned to pass through the pixel electrode via 281 to form a corresponding pixel electrode 29.
  • the fabrication method of the thin film transistor of the preferred embodiment realizes the doping operation of the low doped region through the metal semi-transparent mask, and ensures a symmetric low-doped region on both sides of the source and the drain, and the fabrication process is simple.
  • FIG. 3 is a flow chart of a second preferred embodiment of a method for fabricating a thin film transistor of the present invention.
  • the manufacturing method of the thin film transistor of the preferred embodiment includes:
  • Step S201 providing a substrate substrate
  • Step S202 depositing a buffer layer on the substrate, and patterning the buffer layer to form a first active region of the first thin film transistor and a second active region of the second thin film transistor;
  • Step S203 sequentially depositing an insulating layer and a first metal layer on the base substrate;
  • Step S204 applying a first photoresist on the first gate region, the low doping region, and the second gate region of the first metal layer;
  • Step S205 performing metal etching on the first gate region, the low doping region, and the region outside the second gate region of the first metal layer to expose the insulating layer;
  • Step S206 applying a second photoresist in a region of the second thin film transistor
  • Step S207 performing ashing treatment on the first photoresist to expose a low doped region of the first metal layer
  • Step S208 performing metal etching on the first metal layer of the low doped region to form a metal semi-transmissive mask
  • Step S209 performing ion implantation on the first active region to form a source region, a source low doping region, a channel region, a drain low doping region, and a drain region of the first thin film transistor;
  • Step S210 performing a removal operation on the first photoresist and the second photoresist
  • Step S211 applying a third photoresist in a region of the first thin film transistor
  • Step S212 performing ion implantation on the second active region to form a source region, a channel region, and a drain region of the second thin film transistor;
  • Step S213, performing a removal operation on the third photoresist
  • Step S214 depositing a dielectric layer on the substrate, and forming a source via and a drain via on the dielectric layer;
  • Step S215 depositing a second metal layer on the base substrate, and patterning the second metal layer to form a source and a drain of the first thin film transistor through the source via hole and the drain via hole. And a source and a drain of the second thin film transistor;
  • Step S216 depositing an organic flat layer on the base substrate, and forming a pixel electrode through hole on the organic flat layer;
  • Step S217 depositing a pixel electrode layer on the base substrate, and patterning the pixel electrode layer to form a corresponding pixel electrode through the pixel electrode through hole.
  • step S201 a base substrate 41 is provided, and then the process proceeds to step S202.
  • an amorphous silicon buffer layer 42 is deposited on the base substrate 41; the material of the amorphous silicon buffer layer may be at least one of silicon nitride and silicon oxide; then the amorphous silicon buffer layer is Excimer laser annealing causes amorphous silicon to be converted into polysilicon to form a polysilicon buffer layer, as shown in FIG. 4A. Then, the polysilicon buffer layer is subjected to patterning processing such as photoresist coating, exposure development, and etching to form a first active region 421 of the first thin film transistor and a second active region 422 of the second thin film transistor, as shown in FIG. 4B. Shown. Then it proceeds to step S203.
  • patterning processing such as photoresist coating, exposure development, and etching to form a first active region 421 of the first thin film transistor and a second active region 422 of the second thin film transistor, as shown in FIG. 4B. Shown. Then it proceeds to step S203.
  • step S203 an insulating layer 43 and a first metal layer 44 are sequentially deposited on the base substrate 41; the material of the insulating layer 43 may be at least one of silicon nitride and silicon oxide, and the first metal layer 44 is made of molybdenum And a single metal layer or a plurality of stacked metal layers composed of at least one metal of aluminum. Then it proceeds to step S204.
  • a first photoresist 45 is coated on the first gate region 441, the low doped region 442, and the second gate region 443 of the first metal layer 44, wherein the first active region 421 is at the first
  • the projection on the metal layer 22 covers the first gate region 441 and the low doped region 442.
  • the projection of the second active layer 422 on the first metal layer 22 covers the second gate region 443.
  • step S205 a region other than the first gate region 441, the low doped region 442, and the second gate region 443 of the first metal layer 44 is metal etched to expose the insulating layer 43; after metal etching Please refer to FIG. 4D for the structure of the thin film transistor. Then it proceeds to step S207.
  • step S206 the second photoresist 46 is applied to the region of the second thin film transistor.
  • the structure of the coated thin film transistor please refer to FIG. 4E, and then the process goes to step S207.
  • step S207 the first photoresist 45 is ashed to expose the low doped region 442 of the first metal layer 44; since the effect of the ashing process on both sides of the photoresist is the same, this is the first The area of the low doped region 442 exposed on both sides of the metal layer 44 is the same.
  • the structure of the coated thin film transistor please refer to FIG. 4F, and then go to step S208.
  • step S208 the first metal layer 44 of the low doped region 442 is metal etched, that is, the first metal layer 44 of the partially doped region 442 is etched away, and the first metal of the remaining low doped region 442 is removed.
  • Layer 44 constitutes a metal semi-transmissive mask. Then it proceeds to step S209.
  • the first active region 421 is ion-implanted, and the first active region not blocked by the metal layer implants ions to form the source region 4211 and the drain region 4212 of the first thin film transistor;
  • the first active layer of the film shielding implants ions to form a source low doped region 4213 of the first thin film transistor and a drain low doped region 4214; the first active layer with the photoresist layer and the metal layer is not implanted with ions
  • the active layer of the region forms a channel region 4215 of the first thin film transistor.
  • the implanted ions are phosphorus ions or arsenic ions; if the first thin film transistor is a P-type metal-oxide-semiconductor thin film transistor, the implanted ions are boron ions. . Please refer to FIG. 4G for details. Then it proceeds to step S210.
  • step S210 the first photoresist 45 and the second photoresist 46 are removed.
  • the metal semi-transparent mask can also be etched, and the structure of the thin film transistor after the etching process is as shown in FIG. 4L. Then it proceeds to step S211.
  • step S211 a third photoresist 47 is applied to the region of the first thin film transistor; for the structure of the applied thin film transistor, please refer to FIG. Then it proceeds to step S212.
  • step S212 the second active region 422 is ion-implanted, and the second active region 422 without the metal layer is implanted with ions to form the source region 4221 and the drain region 4222 of the second thin film transistor, having a photoresist layer.
  • the second active layer 422, which is blocked by the metal layer, is not implanted with ions, and the active layer of the region forms the channel region 4223 of the second thin film transistor. Then it proceeds to step S213.
  • step S213 the third photoresist 47 is removed.
  • the structure of the thin film transistor after the removal operation please refer to FIG. 4J. Then it proceeds to step S214.
  • step S214 a dielectric layer 48 is deposited on the base substrate 41, and a source via 481 and a drain via 482 are formed on the dielectric layer 48 through photoresist coating, exposure development, and etch hole drilling; Go to step S215.
  • step S215 a second metal layer is deposited on the base substrate 41, and the second metal layer is patterned to form a source of the first thin film transistor through the source via 481 and the drain via 482. 491 and the drain 492, and the source 493 and the drain 494 of the second thin film transistor. Then it proceeds to step S216.
  • step S216 an organic flat layer 410 is deposited on the base substrate 41, and a pixel electrode via 411 is formed on the organic flat layer 410; subsequently, the process proceeds to step S217.
  • step S217 a pixel electrode layer is deposited on the base substrate 41, and the pixel electrode layer is patterned to pass through the pixel electrode via 411 to form a corresponding pixel electrode 412; the structure of the thin film transistor after the fabrication is completed.
  • the metal semi-transmissive mask is etched; for the structure of the thin film transistor after fabrication, please refer to FIG. 4M.
  • the method for fabricating the thin film transistor of the preferred embodiment can select a plurality of thin film transistors on the same substrate to be fabricated in a low-doped region, thereby further improving the thin film transistor and the corresponding liquid crystal display.
  • the working stability of the panel can be selected a plurality of thin film transistors on the same substrate to be fabricated in a low-doped region, thereby further improving the thin film transistor and the corresponding liquid crystal display.
  • the manufacturing method of the thin film transistor of the invention realizes the doping operation of the low doped region by the metal semi-transparent mask, ensures the formation of a symmetrical low-doped region on both sides of the source and the drain, and the fabrication process is simple;
  • the fabrication method of the existing thin film transistor is difficult to form a symmetrical shallow doping transition region on both sides of the source and the drain, thereby easily causing a technical problem of doping deviation or offset of the gate region.

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Abstract

一种薄膜晶体管的制作方法，包括：提供衬底基板（21）；沉积缓冲层，并对缓冲层进行图形化处理；依次沉积绝缘层（23）以及第一金属层（24）；在第一金属层（24）上涂布光阻；对第一金属层（24）进行金属刻蚀；对光阻（25）进行灰化处理；对低掺杂区（242）的第一金属层（24）进行金属刻蚀；对有源区（22）进行离子注入；对光阻（25）进行去除操作。

Description

薄膜晶体管的制作方法 技术领域
本发明涉及晶体管制作领域，特别涉及一种薄膜晶体管的制作方法。
 背景技术
低温多晶硅薄膜晶体管（LTPS TFT）基板可以应用于LCD（液晶显示器）及AMOLED（主动矩阵有机发光二极管）等高阶显示器。低温多晶硅薄膜晶体管相较于其他TFT拥有较高的载流子迁移率，较高的载流子迁移率容易导致出现热载流子效应，甚至可能会造成薄膜晶体管的失效。
为了避免热载流子效应的产生，制作低温多晶硅薄膜晶体管时，会通过离子注入的方式在低温多晶硅薄膜晶体管的源极和漏极形成浅掺杂过渡区。但是对低温多晶硅薄膜晶体管的源极和漏极进行离子注入操作时，难以在源极和漏极两侧形成对称的浅掺杂过渡区，从而容易导致掺杂偏差或栅极区域的偏移。
故，有必要提供一种薄膜晶体管的制作方法，以解决现有技术所存在的问题。
 技术问题
有鉴于此，本发明提供一种可在源极和漏极两侧形成对称的低掺杂区，且制作流程简单的薄膜晶体管的制作方法；以解决现有的薄膜晶体管的制作方法的难以在源极和漏极两侧形成对称的浅掺杂过渡区，从而容易导致掺杂偏差或栅极区域的偏移的技术问题。
 技术解决方案
本发明实施例提供一种薄膜晶体管的制作方法，其包括：
提供一衬底基板；
在所述衬底基板上沉积缓冲层，并对所述缓冲层进行图形化处理，以形成所述薄膜晶体管的有源区；
在所述衬底基板上依次沉积绝缘层以及第一金属层；
在所述第一金属层的栅极区以及低掺杂区上涂布光阻，其中所述有源区在所述第一金属层上的投影覆盖所述栅极区和所述低掺杂区；
对所述第一金属层的栅极区以及低掺杂区之外的区域进行金属刻蚀，以露出所述绝缘层；
对所述光阻进行灰化处理，以露出所述第一金属层的低掺杂区；
对所述低掺杂区的第一金属层进行金属刻蚀，以形成金属半透掩膜；
对所述有源区进行离子注入，以形成所述薄膜晶体管的源极区、源极低掺杂区、沟道区、漏极低掺杂区以及漏极区；
对所述光阻进行去除操作；
在所述衬底基板上沉积介质层，并在所述介质层上形成源极通孔以及漏极通孔；
在所述衬底基板上沉积第二金属层，并对所述第二金属层进行图形化处理，以通过所述源极通孔以及所述漏极通孔，形成所述薄膜晶体管的源极以及漏极；
在所述衬底基板上沉积有机平坦层，并在所述有机平坦层上形成像素电极通孔；以及
在所述衬底基板上沉积像素电极层，并对所述像素电极层进行图形化处理，以通过所述像素电极通孔，形成相应的像素电极；
其中所述在所述衬底基板上沉积缓冲层，并对所述缓冲层进行图形化处理的步骤包括：
在所述衬底基板上沉积非晶硅缓冲层；
对所述非晶硅缓冲层进行退火处理，以形成多晶硅缓冲层；以及
对所述多晶硅缓冲层进行图形化处理。
在本发明所述的薄膜晶体管的制作方法中，所述对所述光阻进行去除操作的步骤之后还包括：
对所述金属半透掩膜进行刻蚀处理。
在本发明所述的薄膜晶体管的制作方法中，所述第一金属层为由钼和铝中至少一种金属构成的单层金属层或多层叠加金属层。
在本发明所述的薄膜晶体管的制作方法中，如所述薄膜晶体管为N型金属-氧化物-半导体薄膜晶体管，则注入离子为磷离子或砷离子。
在本发明所述的薄膜晶体管的制作方法中，如所述薄膜晶体管为P型金属-氧化物-半导体薄膜晶体管，则注入离子为硼离子。
本发明实施例还提供一种薄膜晶体管的制作方法，其包括：
提供一衬底基板；
在所述衬底基板上沉积缓冲层，并对所述缓冲层进行图形化处理，以形成所述薄膜晶体管的有源区；
在所述衬底基板上依次沉积绝缘层以及第一金属层；
在所述第一金属层的栅极区以及低掺杂区上涂布光阻，其中所述有源区在所述第一金属层上的投影覆盖所述栅极区和所述低掺杂区；
对所述第一金属层的栅极区以及低掺杂区之外的区域进行金属刻蚀，以露出所述绝缘层；
对所述光阻进行灰化处理，以露出所述第一金属层的低掺杂区；
对所述低掺杂区的第一金属层进行金属刻蚀，以形成金属半透掩膜；
对所述有源区进行离子注入，以形成所述薄膜晶体管的源极区、源极低掺杂区、沟道区、漏极低掺杂区以及漏极区；以及
对所述光阻进行去除操作。
在本发明所述的薄膜晶体管的制作方法中，所述对所述光阻进行去除操作的步骤之后还包括：
对所述金属半透掩膜进行刻蚀处理。
在本发明所述的薄膜晶体管的制作方法中，所述对所述光阻进行去除操作的步骤之后还包括：
在所述衬底基板上沉积介质层，并在所述介质层上形成源极通孔以及漏极通孔；
在所述衬底基板上沉积第二金属层，并对所述第二金属层进行图形化处理，以通过所述源极通孔以及所述漏极通孔，形成所述薄膜晶体管的源极以及漏极；
在所述衬底基板上沉积有机平坦层，并在所述有机平坦层上形成像素电极通孔；以及
在所述衬底基板上沉积像素电极层，并对所述像素电极层进行图形化处理，以通过所述像素电极通孔，形成相应的像素电极。
在本发明所述的薄膜晶体管的制作方法中，所述在所述衬底基板上沉积缓冲层，并对所述缓冲层进行图形化处理的步骤包括：
在所述衬底基板上沉积非晶硅缓冲层；
对所述非晶硅缓冲层进行退火处理，以形成多晶硅缓冲层；以及
对所述多晶硅缓冲层进行图形化处理。
在本发明所述的薄膜晶体管的制作方法中，所述第一金属层为由钼和铝中至少一种金属构成的单层金属层或多层叠加金属层。
在本发明所述的薄膜晶体管的制作方法中，如所述薄膜晶体管为N型金属-氧化物-半导体薄膜晶体管，则注入离子为磷离子或砷离子。
在本发明所述的薄膜晶体管的制作方法中，如所述薄膜晶体管为P型金属-氧化物-半导体薄膜晶体管，则注入离子为硼离子。
本发明实施例还提供一种薄膜晶体管的制作方法，其包括：
提供一衬底基板；
在所述衬底基板上沉积缓冲层，并对所述缓冲层进行图形化处理，以形成第一薄膜晶体管的第一有源区和第二薄膜晶体管的第二有源区；
在所述衬底基板上依次沉积绝缘层以及第一金属层；
在所述第一金属层的第一栅极区、低掺杂区以及第二栅极区上涂布第一光阻，其中所述第一有源区在所述第一金属层上的投影覆盖所述第一栅极区和所述低掺杂区，所述第二有源区在所述第一金属层上的投影覆盖所述第二栅极区；
对所述第一金属层的第一栅极区、低掺杂区以及第二栅极区之外的区域进行金属刻蚀，以露出所述绝缘层；
在所述第二薄膜晶体管的区域涂布第二光阻；
对所述第一光阻进行灰化处理，以露出所述第一金属层的低掺杂区；
对所述低掺杂区的第一金属层进行金属刻蚀，以形成金属半透掩膜；
对所述第一有源区进行离子注入，以形成所述第一薄膜晶体管的源极区、源极低掺杂区、沟道区、漏极低掺杂区以及漏极区；
对所述第一光阻和所述第二光阻进行去除操作；
在所述第一薄膜晶体管的区域涂布第三光阻；
对所述第二有源区进行离子注入，以形成所述第二薄膜晶体管的源极区、沟道区、以及漏极区；以及
对所述第三光阻进行去除操作。
在本发明所述的薄膜晶体管的制作方法中，所述对所述第一光阻和所述第二光阻进行去除操作的步骤之后还包括：
对所述金属半透掩膜进行刻蚀处理。
在本发明所述的薄膜晶体管的制作方法中，所述对所述第三光阻进行去除操作的步骤之后还包括：
在所述衬底基板上沉积介质层，并在所述介质层上形成源极通孔以及漏极通孔；
在所述衬底基板上沉积第二金属层，并对所述第二金属层进行图形化处理，以通过所述源极通孔以及所述漏极通孔，形成所述第一薄膜晶体管的源极以及漏极，和所述第二薄膜晶体管的源极以及漏极；
在所述衬底基板上沉积有机平坦层，并在所述有机平坦层上形成像素电极通孔；以及
在所述衬底基板上沉积像素电极层，并对所述像素电极层进行图形化处理，以通过所述像素电极通孔，形成相应的像素电极。
在本发明所述的薄膜晶体管的制作方法中，所述在所述衬底基板上沉积缓冲层，并对所述缓冲层进行图形化处理的步骤包括：
在所述衬底基板上沉积非晶硅缓冲层；
对所述非晶硅缓冲层进行退火处理，以形成多晶硅缓冲层；以及
对所述多晶硅缓冲层进行图形化处理。
在本发明所述的薄膜晶体管的制作方法中，如所述第一金属层为由钼和铝中至少一种金属构成的单层金属层或多层叠加金属层。
在本发明所述的薄膜晶体管的制作方法中，如所述薄膜晶体管为N型金属-氧化物-半导体薄膜晶体管，则注入离子为磷离子或砷离子。
在本发明所述的薄膜晶体管的制作方法中，如所述薄膜晶体管为P型金属-氧化物-半导体薄膜晶体管，则注入离子为硼离子。
 有益效果
本发明的薄膜晶体管的制作方法通过金属半透掩膜实现对低掺杂区的掺杂操作，保证了在源极和漏极两侧形成对称的低掺杂区，且制作流程简单；解决了现有的薄膜晶体管的制作方法的难以在源极和漏极两侧形成对称的浅掺杂过渡区，从而容易导致掺杂偏差或栅极区域的偏移的技术问题。
 附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面对实施例中所需要使用的附图作简单的介绍。下面描述中的附图仅为本发明的部分实施例，对于本领域普通技术人员而言，在不付出创造性劳动的前提下，还可以根据这些附图获取其他的附图。
图1为本发明的薄膜晶体管的制作方法的第一优选实施例的流程图；
图2A至图2H为本发明的薄膜晶体管的制作方法的第一优选实施例的具体制作流程图；
图3为本发明的薄膜晶体管的制作方法的第二优选实施例的流程图；
图4A至图4M为本发明的薄膜晶体管的制作方法的第二优选实施例的具体制作流程图。
 本发明的最佳实施方式
请参照附图中的图式，其中相同的组件符号代表相同的组件。以下的说明是基于所例示的本发明具体实施例，其不应被视为限制本发明未在此详述的其它具体实施例。
请参照图1，图1为本发明的薄膜晶体管的制作方法的第一优选实施例的流程图。本优选实施例的薄膜晶体管的制作方法包括：
步骤S101，提供一衬底基板；
步骤S102，在衬底基板上沉积缓冲层，并对缓冲层进行图形化处理，以形成薄膜晶体管的有源区；
步骤S103，在衬底基板上依次沉积绝缘层以及第一金属层；
步骤S104，在第一金属层的栅极区以及低掺杂区上涂布光阻；
步骤S105，对第一金属层的栅极区以及低掺杂区之外的区域进行金属刻蚀，以露出绝缘层；
步骤S106，对光阻进行灰化处理，以露出第一金属层的低掺杂区；
步骤S107，对低掺杂区的第一金属层进行金属刻蚀，以形成金属半透掩膜；
步骤S108，对有源区进行离子注入，以形成薄膜晶体管的源极区、源极低掺杂区、沟道区、漏极低掺杂区以及漏极区；
步骤S109，对光阻进行去除操作；
步骤S110，在衬底基板上沉积介质层，并在介质层上形成源极通孔以及漏极通孔；
步骤S111，在衬底基板上沉积第二金属层，并对第二金属层进行图形化处理，以通过源极通孔以及漏极通孔，形成薄膜晶体管的源极以及漏极；
步骤S112，在衬底基板上沉积有机平坦层，并在有机平坦层上形成像素电极通孔；
步骤S113，在衬底基板上沉积像素电极层，并对像素电极层进行图形化处理，以通过像素电极通孔，形成相应的像素电极。
下面详细说明本优选实施例的薄膜晶体管的制作方法的各步骤的具体流程。
在步骤S101中，提供一衬底基板21，随后转到步骤S102。
在步骤S102中，在衬底基板21上沉积非晶硅缓冲层；该非晶硅缓冲层的材料可为氮化硅以及氧化硅中的至少一种；随后对该非晶硅缓冲层进行准分子激光退火，使得非晶硅转换为多晶硅，以形成多晶硅缓冲层。然后经过光阻涂布、曝光显影以及刻蚀等图形化处理，形成薄膜晶体管的有源层22。接着对光阻进行剥离后转到步骤S103。
在步骤S103中，在衬底基板21上依次沉积绝缘层23以及第一金属层24；绝缘层23的材料可为氮化硅以及氧化硅中的至少一种，第一金属层24为由钼和铝中至少一种金属构成的单层金属层或多层叠加金属层。随后转到步骤S104。
在步骤S104中，在第一金属层24的栅极区241以及低掺杂区242上涂布光阻25，有源区22在第一金属层24上的投影覆盖栅极区241和低掺杂区242；涂布后的薄膜晶体管的结构具体请参照图2A。随后转到步骤S105。
在步骤S105中，对第一金属层24的栅极区241以及低掺杂区242之外的区域进行金属刻蚀，以露出绝缘层23；金属刻蚀后的薄膜晶体管的结构具体请参照图2B。随后转到步骤S106。
在步骤S106中，对光阻25进行灰化处理，以露出第一金属层24的低掺杂区242；由于对光阻25两侧的灰化处理的效果是相同的，这样在第一金属层24两侧露出的低掺杂区242的面积是相同的。灰化处理后的薄膜晶体管的结构具体请参照图2C。随后转到步骤S107。
在步骤S107中，对低掺杂区242的第一金属层24进行金属刻蚀，即刻蚀掉部分低掺杂区242的第一金属层24，剩下的低掺杂区242的第一金属层24构成金属半透掩膜。金属刻蚀后的薄膜晶体管的结构具体请参照图2D。随后转到步骤S108。
在步骤S108中，对有源区22进行离子注入，没有金属层遮挡的有源区注入离子后形成薄膜晶体管的源极区221以及漏极区222；具有金属半透掩膜遮挡的有源层22注入离子后形成薄膜晶体管的源极低掺杂区223以及漏极低掺杂区224；具有光阻层和金属层阻挡的有源层22未注入离子，该区域的有源层22形成薄膜晶体管的沟道区225。
如薄膜晶体管为N型金属-氧化物-半导体薄膜晶体管，则注入离子为磷离子或砷离子；如薄膜晶体管为P型金属-氧化物-半导体薄膜晶体管，则注入离子为硼离子。具体请参照图2E。随后转到步骤S109。
在步骤S109中，对光阻25进行去除操作；去除操作后的薄膜晶体管的结构具体请参照图2F。当然这里也可将金属半透掩膜进行刻蚀处理，刻蚀处理后的薄膜晶体管的结构具体请参照图2G。随后转到步骤S110。
在步骤S110中，在衬底基板21上沉积介质层26，经过光阻涂布、曝光显影以及刻蚀挖孔等操作在介质层26上形成源极通孔261以及漏极通孔262；随后转到步骤S111。
在步骤S111中，在衬底基板21上沉积第二金属层，并对第二金属层进行图形化处理，以通过源极通孔261以及漏极通孔262，形成薄膜晶体管的源极271以及漏极272；随后转到步骤S112。
在步骤S112中，在衬底基板21上沉积有机平坦层28，并在有机平坦层28上形成像素电极通孔281；随后转到步骤S113。
在步骤S113中，在衬底基板21上沉积像素电极层，并对像素电极层进行图形化处理，以通过像素电极通孔281，形成相应的像素电极29。制作完成后的薄膜晶体管的结构具体请参照图2H。
这样即完成了本优选实施例的薄膜晶体管的制作以及使用过程。
本优选实施例的薄膜晶体管的制作方法通过金属半透掩膜实现对低掺杂区的掺杂操作，保证了在源极和漏极两侧形成对称的低掺杂区，且制作流程简单。
请参照图3，图3为本发明的薄膜晶体管的制作方法的第二优选实施例的流程图。本优选实施例的薄膜晶体管的制作方法包括：
步骤S201，提供一衬底基板；
步骤S202，在衬底基板上沉积缓冲层，并对缓冲层进行图形化处理，以形成第一薄膜晶体管的第一有源区和第二薄膜晶体管的第二有源区；
步骤S203，在衬底基板上依次沉积绝缘层以及第一金属层；
步骤S204，在第一金属层的第一栅极区、低掺杂区以及第二栅极区上涂布第一光阻；
步骤S205，对第一金属层的第一栅极区、低掺杂区以及第二栅极区之外的区域进行金属刻蚀，以露出绝缘层；
步骤S206，在第二薄膜晶体管的区域涂布第二光阻；
步骤S207，对第一光阻进行灰化处理，以露出第一金属层的低掺杂区；
步骤S208，对低掺杂区的第一金属层进行金属刻蚀，以形成金属半透掩膜；
步骤S209，对第一有源区进行离子注入，以形成第一薄膜晶体管的源极区、源极低掺杂区、沟道区、漏极低掺杂区以及漏极区；
步骤S210，对第一光阻和第二光阻进行去除操作；
步骤S211，在第一薄膜晶体管的区域涂布第三光阻；
步骤S212，对第二有源区进行离子注入，以形成第二薄膜晶体管的源极区、沟道区、以及漏极区；
步骤S213，对第三光阻进行去除操作；
步骤S214，在衬底基板上沉积介质层，并在介质层上形成源极通孔以及漏极通孔；
步骤S215，在衬底基板上沉积第二金属层，并对第二金属层进行图形化处理，以通过源极通孔以述漏极通孔，形成第一薄膜晶体管的源极以及漏极，和第二薄膜晶体管的源极以及漏极；
步骤S216，在衬底基板上沉积有机平坦层，并在有机平坦层上形成像素电极通孔；
步骤S217，在衬底基板上沉积像素电极层，并对像素电极层进行图形化处理，以通过像素电极通孔，形成相应的像素电极。
下面详细说明本优选实施例的薄膜晶体管的制作方法的各步骤的具体流程。
在步骤S201中，提供一衬底基板41，随后转到步骤S202。
在步骤S202中，在衬底基板41上沉积非晶硅缓冲层42；该非晶硅缓冲层的材料可为氮化硅以及氧化硅中的至少一种；随后对该非晶硅缓冲层进行准分子激光退火，使得非晶硅转换为多晶硅，以形成多晶硅缓冲层，具体如图4A所示。然后对多晶硅缓冲层进行光阻涂布、曝光显影以及刻蚀等图形化处理，形成第一薄膜晶体管的第一有源区421和第二薄膜晶体管的第二有源区422，具体如图4B所示。随后转到步骤S203。
在步骤S203中，在衬底基板41上依次沉积绝缘层43以及第一金属层44；绝缘层43的材料可为氮化硅以及氧化硅中的至少一种，第一金属层44为由钼和铝中至少一种金属构成的单层金属层或多层叠加金属层。随后转到步骤S204。
在步骤S204中，在第一金属层44的第一栅极区441、低掺杂区442以及第二栅极区443上涂布第一光阻45，其中第一有源区421在第一金属层22上的投影覆盖第一栅极区441和低掺杂区442。第二有源层422在第一金属层22上的投影覆盖第二栅极区443。涂布后的薄膜晶体管的结构具体请参照图4C，随后转到步骤S205。
在步骤S205中，对第一金属层44的第一栅极区441、低掺杂区442以及第二栅极区443之外的区域进行金属刻蚀，以露出绝缘层43；金属刻蚀后的薄膜晶体管的结构具体请参照图4D。随后转到步骤S207。
在步骤S206中，在第二薄膜晶体管的区域涂布第二光阻46，涂布后的薄膜晶体管的结构具体请参照图4E，随后转到步骤S207。
在步骤S207中，对第一光阻45进行灰化处理，以露出第一金属层44的低掺杂区442；由于对光阻两侧的灰化处理的效果是相同的，这样在第一金属层44两侧露出的低掺杂区442的面积是相同的。涂布后的薄膜晶体管的结构具体请参照图4F，随后转到步骤S208。
在步骤S208中，对低掺杂区442的第一金属层44进行金属刻蚀，即刻蚀掉部分低掺杂区442的第一金属层44，剩下的低掺杂区442的第一金属层44构成金属半透掩膜。随后转到步骤S209。
在步骤S209中，对第一有源区421进行离子注入，没有金属层遮挡的第一有源区注入离子后形成第一薄膜晶体管的源极区4211以及漏极区4212；具有金属半透掩膜遮挡的第一有源层注入离子后形成第一薄膜晶体管的源极低掺杂区4213以及漏极低掺杂区4214；具有光阻层和金属层阻挡的第一有源层未注入离子，该区域的有源层形成第一薄膜晶体管的沟道区4215。
如第一薄膜晶体管为N型金属-氧化物-半导体薄膜晶体管，则注入离子为磷离子或砷离子；如第一薄膜晶体管为P型金属-氧化物-半导体薄膜晶体管，则注入离子为硼离子。具体请参照图4G。随后转到步骤S210。
在步骤S210中，对第一光阻45和第二光阻46进行去除操作，去除操作后的薄膜晶体管的结构具体请参照图4H。当然这里也可将金属半透掩膜进行刻蚀处理，刻蚀处理后的薄膜晶体管的结构具体请参照图4L。随后转到步骤S211。
在步骤S211中，在第一薄膜晶体管的区域涂布第三光阻47；涂布后的薄膜晶体管的结构具体请参照图4I。随后转到步骤S212。
在步骤S212中，对第二有源区422进行离子注入，没有金属层遮挡的第二有源区422注入离子后形成第二薄膜晶体管的源极区4221以及漏极区4222，具有光阻层和金属层阻挡的第二有源层422未注入离子，该区域的有源层形成第二薄膜晶体管的沟道区4223。随后转到步骤S213。
在步骤S213中，对第三光阻47进行去除操作；去除操作后的薄膜晶体管的结构具体请参照图4J。随后转到步骤S214。
在步骤S214中，在衬底基板41上沉积介质层48，经过光阻涂布、曝光显影以及刻蚀挖孔等操作在介质层48上形成源极通孔481以及漏极通孔482；随后转到步骤S215。
在步骤S215中，在衬底基板41上沉积第二金属层，并对第二金属层进行图形化处理，以通过源极通孔481以及漏极通孔482，形成第一薄膜晶体管的源极491以及漏极492，和第二薄膜晶体管的源极493以及漏极494。随后转到步骤S216。
在步骤S216中，在衬底基板41上沉积有机平坦层410，并在有机平坦层410上形成像素电极通孔411；随后转到步骤S217。
在步骤S217中，在衬底基板41上沉积像素电极层，并对像素电极层进行图形化处理，以通过像素电极通孔411，形成相应的像素电极412；制作完成后的薄膜晶体管的结构具体请参照图4K。如在步骤S210中对金属半透掩膜进行了刻蚀处理；则制作完成后的薄膜晶体管的结构具体请参照图4M。
这样即完成了本优选实施例的薄膜晶体管的制作以及使用过程。
在第一优选实施例的基础上，本优选实施例的薄膜晶体管的制作方法可对同一基板上的多个薄膜晶体管选择进行低掺杂区的制作，因此进一步提高了薄膜晶体管以及相应的液晶显示面板的工作稳定性。
本发明的薄膜晶体管的制作方法通过金属半透掩膜实现对低掺杂区的掺杂操作，保证了在源极和漏极两侧形成对称的低掺杂区，且制作流程简单；解决了现有的薄膜晶体管的制作方法的难以在源极和漏极两侧形成对称的浅掺杂过渡区，从而容易导致掺杂偏差或栅极区域的偏移的技术问题。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (19)

  1. 一种薄膜晶体管的制作方法，其包括：
    提供一衬底基板；
    在所述衬底基板上沉积缓冲层，并对所述缓冲层进行图形化处理，以形成所述薄膜晶体管的有源区；
    在所述衬底基板上依次沉积绝缘层以及第一金属层；
    在所述第一金属层的栅极区以及低掺杂区上涂布光阻，其中所述有源区在所述第一金属层上的投影覆盖所述栅极区和所述低掺杂区；
    对所述第一金属层的栅极区以及低掺杂区之外的区域进行金属刻蚀，以露出所述绝缘层；
    对所述光阻进行灰化处理，以露出所述第一金属层的低掺杂区；
    对所述低掺杂区的第一金属层进行金属刻蚀，以形成金属半透掩膜；
    对所述有源区进行离子注入，以形成所述薄膜晶体管的源极区、源极低掺杂区、沟道区、漏极低掺杂区以及漏极区；
    对所述光阻进行去除操作；
    在所述衬底基板上沉积介质层，并在所述介质层上形成源极通孔以及漏极通孔；
    在所述衬底基板上沉积第二金属层，并对所述第二金属层进行图形化处理，以通过所述源极通孔以及所述漏极通孔，形成所述薄膜晶体管的源极以及漏极；
    在所述衬底基板上沉积有机平坦层，并在所述有机平坦层上形成像素电极通孔；以及
    在所述衬底基板上沉积像素电极层，并对所述像素电极层进行图形化处理，以通过所述像素电极通孔，形成相应的像素电极；
    其中所述在所述衬底基板上沉积缓冲层，并对所述缓冲层进行图形化处理的步骤包括：
    在所述衬底基板上沉积非晶硅缓冲层；
    对所述非晶硅缓冲层进行退火处理，以形成多晶硅缓冲层；以及
    对所述多晶硅缓冲层进行图形化处理。
  2. 根据权利要求1所述的薄膜晶体管的制作方法，其中所述对所述光阻进行去除操作的步骤之后还包括：
    对所述金属半透掩膜进行刻蚀处理。
  3. 根据权利要求1所述的薄膜晶体管的制作方法，其中所述第一金属层为由钼和铝中至少一种金属构成的单层金属层或多层叠加金属层。
  4. 根据权利要求1所述的薄膜晶体管的制作方法，其中如所述薄膜晶体管为N型金属-氧化物-半导体薄膜晶体管，则注入离子为磷离子或砷离子。
  5. 根据权利要求1所述的薄膜晶体管的制作方法，其中如所述薄膜晶体管为P型金属-氧化物-半导体薄膜晶体管，则注入离子为硼离子。
  6. 一种薄膜晶体管的制作方法，其包括：
    提供一衬底基板；
    在所述衬底基板上沉积缓冲层，并对所述缓冲层进行图形化处理，以形成所述薄膜晶体管的有源区；
    在所述衬底基板上依次沉积绝缘层以及第一金属层；
    在所述第一金属层的栅极区以及低掺杂区上涂布光阻，其中所述有源区在所述第一金属层上的投影覆盖所述栅极区和所述低掺杂区；
    对所述第一金属层的栅极区以及低掺杂区之外的区域进行金属刻蚀，以露出所述绝缘层；
    对所述光阻进行灰化处理，以露出所述第一金属层的低掺杂区；
    对所述低掺杂区的第一金属层进行金属刻蚀，以形成金属半透掩膜；
    对所述有源区进行离子注入，以形成所述薄膜晶体管的源极区、源极低掺杂区、沟道区、漏极低掺杂区以及漏极区；以及
    对所述光阻进行去除操作。
  7. 根据权利要求6所述的薄膜晶体管的制作方法，其中所述对所述光阻进行去除操作的步骤之后还包括：
    对所述金属半透掩膜进行刻蚀处理。
  8. 根据权利要求6所述的薄膜晶体管的制作方法，其中所述对所述光阻进行去除操作的步骤之后还包括：
    在所述衬底基板上沉积介质层，并在所述介质层上形成源极通孔以及漏极通孔；
    在所述衬底基板上沉积第二金属层，并对所述第二金属层进行图形化处理，以通过所述源极通孔以及所述漏极通孔，形成所述薄膜晶体管的源极以及漏极；
    在所述衬底基板上沉积有机平坦层，并在所述有机平坦层上形成像素电极通孔；以及
    在所述衬底基板上沉积像素电极层，并对所述像素电极层进行图形化处理，以通过所述像素电极通孔，形成相应的像素电极。
  9. 根据权利要求6所述的薄膜晶体管的制作方法，其中所述在所述衬底基板上沉积缓冲层，并对所述缓冲层进行图形化处理的步骤包括：
    在所述衬底基板上沉积非晶硅缓冲层；
    对所述非晶硅缓冲层进行退火处理，以形成多晶硅缓冲层；以及
    对所述多晶硅缓冲层进行图形化处理。
  10. 根据权利要求6所述的薄膜晶体管的制作方法，其中所述第一金属层为由钼和铝中至少一种金属构成的单层金属层或多层叠加金属层。
  11. 根据权利要求6所述的薄膜晶体管的制作方法，其中如所述薄膜晶体管为N型金属-氧化物-半导体薄膜晶体管，则注入离子为磷离子或砷离子。
  12. 根据权利要求6所述的薄膜晶体管的制作方法，其中如所述薄膜晶体管为P型金属-氧化物-半导体薄膜晶体管，则注入离子为硼离子。
  13. 一种薄膜晶体管的制作方法，其包括：
    提供一衬底基板；
    在所述衬底基板上沉积缓冲层，并对所述缓冲层进行图形化处理，以形成第一薄膜晶体管的第一有源区和第二薄膜晶体管的第二有源区；
    在所述衬底基板上依次沉积绝缘层以及第一金属层；
    在所述第一金属层的第一栅极区、低掺杂区以及第二栅极区上涂布第一光阻，其中所述第一有源区在所述第一金属层上的投影覆盖所述第一栅极区和所述低掺杂区，所述第二有源区在所述第一金属层上的投影覆盖所述第二栅极区；
    对所述第一金属层的第一栅极区、低掺杂区以及第二栅极区之外的区域进行金属刻蚀，以露出所述绝缘层；
    在所述第二薄膜晶体管的区域涂布第二光阻；
    对所述第一光阻进行灰化处理，以露出所述第一金属层的低掺杂区；
    对所述低掺杂区的第一金属层进行金属刻蚀，以形成金属半透掩膜；
    对所述第一有源区进行离子注入，以形成所述第一薄膜晶体管的源极区、源极低掺杂区、沟道区、漏极低掺杂区以及漏极区；
    对所述第一光阻和所述第二光阻进行去除操作；
    在所述第一薄膜晶体管的区域涂布第三光阻；
    对所述第二有源区进行离子注入，以形成所述第二薄膜晶体管的源极区、沟道区、以及漏极区；以及
    对所述第三光阻进行去除操作。
  14. 根据权利要求13所述的薄膜晶体管的制作方法，其中所述对所述第一光阻和所述第二光阻进行去除操作的步骤之后还包括：
    对所述金属半透掩膜进行刻蚀处理。
  15. 根据权利要求13所述的薄膜晶体管的制作方法，其中所述对所述第三光阻进行去除操作的步骤之后还包括：
    在所述衬底基板上沉积介质层，并在所述介质层上形成源极通孔以及漏极通孔；
    在所述衬底基板上沉积第二金属层，并对所述第二金属层进行图形化处理，以通过所述源极通孔以及所述漏极通孔，形成所述第一薄膜晶体管的源极以及漏极，和所述第二薄膜晶体管的源极以及漏极；
    在所述衬底基板上沉积有机平坦层，并在所述有机平坦层上形成像素电极通孔；以及
    在所述衬底基板上沉积像素电极层，并对所述像素电极层进行图形化处理，以通过所述像素电极通孔，形成相应的像素电极。
  16. 根据权利要求13所述的薄膜晶体管的制作方法，其中所述在所述衬底基板上沉积缓冲层，并对所述缓冲层进行图形化处理的步骤包括：
    在所述衬底基板上沉积非晶硅缓冲层；
    对所述非晶硅缓冲层进行退火处理，以形成多晶硅缓冲层；以及
    对所述多晶硅缓冲层进行图形化处理。
  17. 根据权利要求13所述的薄膜晶体管的制作方法，其中所述第一金属层为由钼和铝中至少一种金属构成的单层金属层或多层叠加金属层。
  18. 根据权利要求13所述的薄膜晶体管的制作方法，其中如所述薄膜晶体管为N型金属-氧化物-半导体薄膜晶体管，则注入离子为磷离子或砷离子。
  19. 根据权利要求13所述的薄膜晶体管的制作方法，其中如所述薄膜晶体管为P型金属-氧化物-半导体薄膜晶体管，则注入离子为硼离子。
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