WO2017135037A1 - Dispositif à semi-conducteur, son procédé de fabrication, et dispositif de conversion de puissance l'utilisant - Google Patents

Dispositif à semi-conducteur, son procédé de fabrication, et dispositif de conversion de puissance l'utilisant Download PDF

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WO2017135037A1
WO2017135037A1 PCT/JP2017/001622 JP2017001622W WO2017135037A1 WO 2017135037 A1 WO2017135037 A1 WO 2017135037A1 JP 2017001622 W JP2017001622 W JP 2017001622W WO 2017135037 A1 WO2017135037 A1 WO 2017135037A1
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semiconductor layer
layer
gate
type
semiconductor device
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PCT/JP2017/001622
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English (en)
Japanese (ja)
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智之 三好
悠次郎 竹内
智康 古川
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株式会社日立パワーデバイス
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Priority to DE112017000224.9T priority Critical patent/DE112017000224B4/de
Publication of WO2017135037A1 publication Critical patent/WO2017135037A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8613—Mesa PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
    • H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7391—Gated diode structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections

Definitions

  • the present invention relates to a semiconductor device, a manufacturing method thereof, and a power conversion device using the same.
  • the present invention relates to a semiconductor device suitable for a wide range of use from a low-power device such as an air conditioner or a microwave oven to a high-power device such as an inverter of a railway or a steel mill, a manufacturing method thereof, and a power converter using the same .
  • IGBTs Insulated Gate Bipolar Transistors
  • Patent Document 1 provides “[Problem] To provide a power diode capable of simultaneously realizing low on-resistance and soft recovery. [Solution] P-type emitter layer 2 on the surface of N ⁇ -type base layer 1, back surface An N + -type emitter layer is formed on the P-type emitter layer 2 and a trench groove having a depth reaching the N ⁇ -type base layer 1 is formed on the surface of the P-type emitter layer 2, and a gate electrode is formed in the trench groove via a gate insulating film 3. 4 is embedded (see [Summary]), and a technique relating to a diode is disclosed.
  • Patent Document 1 has the following problems.
  • the present invention has been made in view of the above-described problems, and an object of the present invention is to provide a semiconductor device that has both low conduction loss performance and low recovery loss performance, a driving device thereof, and a manufacturing method thereof.
  • a semiconductor device of the present invention includes a first conductive type first semiconductor layer, a first conductive type second semiconductor layer adjacent to the first semiconductor layer, and having a lower impurity concentration than the first semiconductor layer, A third semiconductor layer of a second conductivity type adjacent to the second semiconductor layer, a first electrode electrically connected to the third semiconductor layer, and a first electrode electrically connected to the first semiconductor layer.
  • the present invention it is possible to provide a semiconductor device that achieves both low conduction loss performance and low recovery loss performance, a manufacturing method thereof, and a power conversion device using the same.
  • FIG. 1 shows typically the example of the cross-section of the semiconductor device which concerns on 1st Embodiment of this invention, (a) partially represents the vicinity of two trench gate type
  • FIG. It is a figure which shows the example of the forward direction characteristic of the diode of the semiconductor device which concerns on 1st Embodiment of this invention. It is a figure which shows the example of the input signal of the gate of the diode of the semiconductor device which concerns on 1st Embodiment of this invention, and the input signal of the gate of IGBT of a pair arm.
  • FIG. 6 is a diagram illustrating an example of a transient characteristic of an anode current of a diode and a cathode-anode voltage when the control by the input signal of FIG. 5 is applied to the diode of the semiconductor device according to the first embodiment of the present invention. It is a figure which shows typically the example of the cross-section of the semiconductor device which concerns on 2nd Embodiment of this invention. It is a figure which shows typically the carrier profile of a hole and an electron when the voltage applied to the insulated gate electrode of the diode of the semiconductor device which concerns on 2nd Embodiment of this invention is made into zero. It is a figure which shows typically the example of the cross-section of the semiconductor device which concerns on 3rd Embodiment of this invention.
  • FIG. 1 It is a figure which shows typically the path
  • FIG. 10 is a diagram showing an example of a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention, where (a) shows the state of the semiconductor device before the second P ⁇ -type anode layer is formed, and (b) Represents the state of the semiconductor device after the second P ⁇ -type anode layer is formed. It is a figure which shows the example of the manufacturing method of the semiconductor device which concerns on 6th Embodiment of this invention, (a) represents the state of the semiconductor device before a 2nd P ⁇ type anode layer is formed, (b) Represents the state of the semiconductor device after the second P ⁇ -type anode layer is formed.
  • FIG. 6 is a diagram illustrating an example of a cross-sectional structure of a diode having an insulated gate according to Comparative Example 2.
  • FIG. 10 is a diagram showing energy bands in a cross section of a central portion of an anode electrode and a P ⁇ type anode layer of a diode having an insulated gate according to Comparative Example 2.
  • FIG. 1 is a diagram schematically showing an example of a cross-sectional structure of a semiconductor device 100 according to the first embodiment of the present invention.
  • FIG. 1 (a) is a partial view of the vicinity of two trench gate type insulated gates 3.
  • (B) shows a state in which a plurality of trench gate type insulated gates 3 are arranged.
  • the semiconductor device 100 is a trench gate control type diode. That is, the trench gate type insulated gate 3 is provided between the anode electrode 6 and the cathode electrode 9 forming the diode, and the diode characteristics of the semiconductor device 100 are changed by the voltage applied to the insulated gate electrode 1 of the insulated gate 3. Be controlled.
  • the semiconductor device 100 is characterized in that the second P ⁇ -type anode layer 5 having a reduced carrier lifetime is provided in the first P ⁇ -type anode layer 4 in the first embodiment of the present invention. It is that.
  • Comparative Example 1 As Comparative Example 1, a general diode (not having a gate electrode structure for controlling the diode characteristics) is connected in reverse parallel to the IGBT, and a plurality of IGBTs are used to convert an inverter (converting DC power into AC power). A configuration example will be described.
  • FIG. 17 shows an example of a partial circuit of an inverter (DC power-AC power converter) configured to include a plurality of IGBTs 43 in Comparative Example 1 and a plurality of diodes 47 respectively connected in reverse parallel to the IGBTs 43.
  • DC power-AC power converter DC power-AC power converter
  • the diode 47 is connected to the IGBT 43 in antiparallel.
  • the upper arm and the lower arm are constituted by two IGBTs 43 connected in series.
  • the upper arm and the lower arm are driven by the respective gate drive circuits 45, and are turned on and off at high speeds.
  • the DC power (DC voltage) of the DC power supply 40 is exchanged. It is controlled to convert it into electric power (alternating voltage).
  • the control circuit 46 that controls the plurality of IGBTs 43 in an integrated manner controls the U phase, the V phase, and the W phase, respectively. Generate AC power (AC voltage) for the phase.
  • the generated U-phase, V-phase, and W-phase three-phase AC power (three-phase AC voltage) is applied to and supplied to a three-phase AC motor (inductive load) 48 to drive the three-phase AC motor 48.
  • the IGBT 43 and the diode 47 generate conduction loss when conducting, and generate switching loss when switching.
  • the switching loss includes a turn-on loss and a turn-off loss generated from the IGBT 43 and a recovery loss generated from the diode 47 when the IGBT is turned on.
  • Comparative example 2 As Comparative Example 2, a diode (gate-controlled diode) having an insulated gate according to a conventional technique (for example, cited document 1) will be described.
  • FIG. 15A shows a circuit configuration for characteristic evaluation
  • FIG. 15B shows a partial configuration of a circuit used as an inverter.
  • the diode 42 having an insulated gate is different from the IGBT that constitutes the upper arm (not shown in FIG. 15A, FIG. 15B). Used as a free-wheeling diode connected in reverse parallel to the upper arm IGBT 43).
  • control circuit 46 and the gate drive circuit 45 control the IGBT 43 and the diode 42 having an insulated gate.
  • the delay circuit block 44 gives a delay to the on / off of the IGBT 43.
  • control circuit 46 controls the upper arm and the lower arm, whereby the DC power (DC voltage) of the DC power supply 40 is converted into AC power (AC voltage) and an inductive load (for example, a part of the motor) 41. Is supplied with AC power (AC voltage).
  • FIGS. 15A and 15B are also used in the embodiment of the present invention, and the details will be described later.
  • the diode 42 having an insulated gate has a buried insulated gate provided inside the trench.
  • a forward voltage is reduced by applying a negative voltage to the insulated gate during conduction to form a hole accumulation layer.
  • the gate voltage zero during recovery hole injection from the anode is suppressed and recovery loss is reduced.
  • the diode 42 having the insulated gate in the comparative example 2 can control the hole injection efficiency from the anode by the voltage applied to the insulated gate, thereby improving the trade-off between the forward voltage related to the conduction loss and the recovery loss. be able to. That is, the comparative example 2 is improved with respect to the reduction of the recovery loss than the comparative example 1.
  • Comparative Example 2 has the following problems.
  • FIG. 18 is a diagram showing an example of a cross-sectional structure of a diode having an insulated gate according to Comparative Example 2.
  • P comprises a layer containing a P-type impurity - -type anode layer (anode region) 4 and contacts the anode electrode 6, P - -type anode layer (anode region) gate insulating film in contact with the 4 (insulating oxide film ) 2 and an insulated gate 3 composed of an insulated gate electrode 1 is disposed.
  • an N ⁇ type drift layer 7 made of a layer containing a low concentration of N type impurities is provided below the P ⁇ type anode layer (anode region) 4 (corresponding to the lower side of the drawing) in order to ensure high breakdown voltage performance.
  • an N + type cathode layer 8 made of a layer containing a high concentration impurity for electrical connection with the cathode electrode 9 is disposed.
  • ⁇ Hole carrier distribution when forward voltage is applied ⁇ In FIG. 19, a negative voltage (11) was applied to the insulated gate electrode 1 of the diode having an insulated gate according to Comparative Example 2, and a forward voltage (12) was applied between the cathode electrode 9 and the anode electrode 6. It is a figure which shows typically distribution of the hole carrier at the time.
  • hole carriers (14) accumulate in the region in contact with the gate insulating film 2 inside the P ⁇ -type anode layer 4 due to the electric field due to the applied negative voltage.
  • the accumulated hole carriers (14) are injected into the N ⁇ -type drift layer 7 by the applied forward voltage (12).
  • the hole carriers injected into the N ⁇ type drift layer 7 are denoted as hole carriers (15).
  • FIG. 20 is a diagram schematically illustrating the distribution of hole carriers when the voltage applied to the insulated gate electrode 1 of the diode having the insulated gate according to Comparative Example 2 is zero.
  • the impurity concentration of the P ⁇ -type anode layer 4 is increased, the concentration of hole carriers accumulated at the interface of the insulated gate 3 when a gate voltage is applied is increased, and the conduction loss is decreased. Is an important structural design item.
  • FIG. 21 is a diagram showing an energy band in the cross section of the central portion of the anode electrode 6 and the P ⁇ -type anode layer 4 of the diode having an insulated gate according to Comparative Example 2.
  • the horizontal axis represents “depth” from the interface between the anode electrode 6 and the P ⁇ -type anode layer 4, and the vertical axis represents “energy (energy level) (eV)”.
  • the characteristic line 51 indicates the energy level of the anode electrode.
  • the characteristic line 52 shows the energy level of the valence band when the anode P ⁇ layer concentration is high.
  • the characteristic line 53 shows the energy level of the valence band when the anode P ⁇ layer concentration is low.
  • the characteristic line 54 shows the energy level of the conduction band when the anode P ⁇ layer concentration is high.
  • the characteristic line 55 shows the energy level of the conduction band when the anode P ⁇ layer concentration is low.
  • An arrow 50 represents the boundary surface (interface) between the anode electrode and the anode P ⁇ layer.
  • Arrow 56 indicates a decrease in the hole injection barrier with increasing anode P ⁇ layer concentration.
  • An arrow 57 indicates the anode electrode region.
  • Arrow 58 indicates the anode P ⁇ layer region.
  • P - by the concentration of P-type layer type anode layer 4 increases, P - -type energy level (52) of the valence band of the anode layer 4 anode electrode 6 and the P - interface type anode layer 4 (50 ) Increases in the vicinity, and the hole injection barrier from the anode electrode 6 to the P ⁇ -type anode layer 4 decreases (56).
  • FIG. 22 shows the diode when the negative voltage is applied to the gate and when the P-type impurity concentration of the P ⁇ -type anode layer 4 of the diode having the insulated gate according to Comparative Example 2 is low and high. It is a figure which shows the forward direction characteristic.
  • the horizontal axis represents “forward voltage, VF (V)”, and the vertical axis represents “forward current density, JF (A / cm 2 )”.
  • a characteristic line 59 is a forward characteristic of the diode when a negative bias is applied between the gate and the anode when the concentration of the P ⁇ -type anode layer 4 is low.
  • a characteristic line 60 is a forward characteristic of the diode when the gate-anode gap is zero bias when the concentration of the P ⁇ -type anode layer 4 is low.
  • a characteristic line 61 is a forward characteristic of the diode when a negative bias is applied between the gate and the anode when the concentration of the P ⁇ -type anode layer 4 is high.
  • the characteristic line 62 is the forward characteristic of the diode when the gate-anode gap is zero bias when the concentration of the P ⁇ -type anode layer 4 is high.
  • the P-type impurity concentration is increased while the gate and anode are both negatively biased (negative voltage). This shows that the forward voltage of the diode is reduced. That is, the effect of reducing conduction loss can be confirmed.
  • FIG. 1 is a diagram showing a cross-sectional structure of the semiconductor device 100 according to the first embodiment of the present invention.
  • FIG. 1A is a partial view of the vicinity of two trench gate type insulating gates 3.
  • (B) shows a state in which a plurality of trench gate type insulated gates 3 are arranged.
  • the notations N ⁇ , N, and N + indicate that the semiconductor layer is N-type (first conductivity type), and the impurity concentration of pentavalent atoms is relatively higher in this order. Indicates high.
  • the notations P ⁇ , P, and P + indicate that the semiconductor layer is P-type (second conductivity type) and that the impurity concentration of trivalent atoms is relatively high in this order.
  • the semiconductor device 100 is a trench gate control type diode. That is, a trench gate type insulated gate 3 is provided between an anode electrode 6 (first electrode) and a cathode electrode 9 (second electrode) forming a diode, and is applied to the insulated gate electrode 1 of the insulated gate 3. The diode characteristics are controlled by the voltage.
  • the semiconductor device 100 as a first embodiment of the present invention is characterized in that the second P ⁇ type in which the lifetime of carriers is reduced in the first P ⁇ type anode layer 4 (third semiconductor layer).
  • the anode layer 5 (fourth semiconductor layer) is provided.
  • the second P ⁇ -type anode layer 5 is formed by irradiating a part of the first P ⁇ -type anode layer 4 with a lifetime killer. Therefore, the second P ⁇ type anode layer 5 is formed inside the first P ⁇ type anode layer 4.
  • the N ⁇ type drift layer 7 (second semiconductor layer), the first P ⁇ type anode layer 4 adjacent to the N ⁇ type drift layer 7 in the vertical direction (the vertical direction of the paper surface), and the first An N + -type cathode layer 8 (first semiconductor layer) adjacent to the N ⁇ -type drift layer 7 in the vertical direction is provided on the side opposite to the P ⁇ -type anode layer 4.
  • a trench gate type insulating gate 3 having an insulating gate electrode 1 provided on the surface of the first P ⁇ -type anode layer 4 via the gate insulating film 2 is provided. .
  • the first P ⁇ -type anode layer 4 includes a second P ⁇ -type anode layer 5 with a reduced carrier lifetime, and the second P ⁇ -type anode layer 5 is gate-insulated. It is in contact with the membrane 2.
  • the anode electrode 6 and the first P ⁇ -type anode layer 4 are in contact with each other at the metal-semiconductor contact surface 10. That is, the anode electrode 6 made of metal and the first P ⁇ -type anode layer 4 made of semiconductor are electrically connected by Schottky contact or ohmic contact.
  • the cathode electrode 9 by ohmic contact with the N + -type cathode layer 8, N + -type cathode layer 8 and are electrically connected. Further, the cathode electrode 9 and the N ⁇ type drift layer 7 are electrically connected via the N + type cathode layer 8.
  • the semiconductor substrate on which the first P ⁇ -type anode layer 4, the second P ⁇ -type anode layer 5, the N ⁇ -type drift layer 7 and the N + -type cathode layer 8 are based is silicon (silicon, Si) or It is formed from silicon carbide (SiC), and the gate insulating film 2 is formed from silicon dioxide (SiO 2 ).
  • a plurality of insulated gates 3 formed in the trench groove are arranged in the horizontal direction (the horizontal direction of the paper).
  • the width of the trench is indicated by W, and the interval between the trenches is indicated by S.
  • FIG. 1B the description of each element shown in FIG. 1A other than the trench structure (groove) and the insulated gate 3 is omitted.
  • the semiconductor device 100 is configured by repeatedly forming a plurality of the structures shown in FIG. 1B.
  • the trench width W is preferably larger than the trench spacing S.
  • a negative voltage is applied to the insulated gate electrode 1 of the semiconductor device 100 according to the first embodiment of the present invention, and a forward voltage for conducting the diode is applied between the cathode electrode 9 and the anode electrode 6. It is a figure which shows typically distribution of the hole carrier at the time of being done.
  • a hole carrier accumulation layer (14) having the same concentration is also formed at the interface between the second P ⁇ -type anode layer 5 and the gate insulating film 2 in which the carrier lifetime is reduced.
  • Many hole carriers (15) are injected into the N ⁇ -type drift layer 7 via the hole carrier accumulation layer (14), the forward voltage (VF) of the diode is lowered, and the conduction loss is reduced.
  • electrons are represented as electron carriers 16.
  • Figure 2 is a second P - is a hole carrier distribution in the case where a type anode layer 5, a second P shown in FIG. 19 - -type anode layer 5 is the same as the hole carrier distribution in the absence of .
  • the voltage applied to the insulated gate electrode 1 of the semiconductor device 100 according to the first embodiment of the present invention is set to zero, and a forward voltage is applied between the cathode electrode 9 and the anode electrode 6. It is a figure which shows typically distribution of the hole carrier at the time.
  • hole carriers are injected into this region (second P ⁇ -type anode layer) by the second P ⁇ -type anode layer 5 provided in the first P ⁇ -type anode layer 4 and having a reduced carrier lifetime. 5), the injection into the N ⁇ -type drift layer 7 can be further suppressed as compared with the case where the present invention is not applied, and the controllability of the hole carrier injection amount by the gate voltage can be improved.
  • FIG. 3 shows a distribution in which the amount of injected hole carriers is smaller than that in FIG.
  • the hole carrier injection amount is as shown in FIG. 3 and FIG. Less than comparison.
  • FIG. 4 is a diagram illustrating an example of forward characteristics of the diode of the semiconductor device 100 according to the first embodiment of the present invention.
  • the horizontal axis is “forward voltage, VF (V)”, and the vertical axis is “forward current density, JF (A / cm 2 )”.
  • a characteristic line 20 is a forward characteristic of the diode when a negative bias is applied between the gate and the anode when the second P ⁇ -type anode layer 5 with reduced carrier lifetime is not present.
  • a characteristic line 21 is a forward characteristic of the diode when a zero bias is applied between the gate and the anode when the second P ⁇ -type anode layer 5 with reduced carrier lifetime is not present.
  • a characteristic line 22 is a forward characteristic of the diode when a negative bias is applied between the gate and the anode when the second P ⁇ -type anode layer 5 having a reduced carrier lifetime is present.
  • a characteristic line 23 is a forward characteristic of the diode when a zero bias is applied between the gate and the anode when the second P ⁇ -type anode layer 5 in which the lifetime of carriers is reduced is present.
  • the gate voltage controllability of the forward voltage (VF) of the diode can be significantly improved as compared with the diode of Comparative Example 2 to which the present invention is not applied.
  • the characteristic line 21 corresponding to Comparative Example 2 is compared with the characteristic line 23 of the semiconductor device 100 according to the first embodiment of the present invention. As shown by the characteristic line 23, the forward voltage (VF) of the diode is greatly increased.
  • FIG. 5 is a diagram showing an example of the input signal 24 of the gate (insulated gate electrode 1: FIG. 1) of the diode and the input signal 25 of the gate of the IGBT of the pair arm of the semiconductor device 100 according to the first embodiment of the present invention. It is.
  • the input signal 24 varies between a negative voltage and a zero voltage
  • the input signal 25 varies between a negative voltage and a positive voltage.
  • FIG. 15A is an evaluation circuit, and the circuit shown in FIG. 15B is actually used.
  • the input signal 25 in FIG. 5 is input to the gate of the IGBT 43 constituting the lower arm of FIG.
  • the input signal 24 (FIG. 5) input to the insulated gate electrode 1 (FIG. 1) of the diode 42 of the semiconductor device 100 according to the first embodiment of the present invention is turned on and the input signal 25 input to the gate of the IGBT 43 of the opposite arm is turned on.
  • the forward voltage (VF) of the diode is high as described above, that is, hole carrier injection from the anode electrode 6 (FIG. 1) and conductivity modulation are performed.
  • the suppressed state (27: FIG. 5) it becomes possible to shift to the recovery state.
  • FIG. 6 shows the anode current (characteristic line 31) of the diode (100) and the cathode-anode when the control by the input signal of FIG. 5 is applied to the diode of the semiconductor device 100 according to the first embodiment of the invention. It is a figure which shows the example of the transient characteristic of a voltage (characteristic line 29).
  • the horizontal axis represents time (time transition: 1 scale is 1 ⁇ sec). Also, the right vertical axis represents the cathode-anode voltage of the diode, and the left vertical axis represents the current density flowing through the diode.
  • the characteristic line 29 indicates the cathode-anode voltage.
  • the characteristic line 30 is a characteristic of current density flowing through the diode of Comparative Example 2
  • the characteristic line 31 is a characteristic of current density flowing through the diode of the semiconductor device 100 according to the first embodiment of the present invention.
  • the reverse current due to recovery observed when the voltage between the cathode and the anode rises is significantly larger than the conventional anode current (characteristic line 30). Can be reduced.
  • FIG. 7 is a diagram schematically showing an example of a cross-sectional structure of a semiconductor device 200 according to the second embodiment of the present invention.
  • an anode electrode 6 (first electrode), a cathode electrode 9 (second electrode), an insulated gate 3, an insulated gate electrode 1, a gate insulating film 2, a first P ⁇ -type anode layer 4 (third semiconductor layer). ),
  • the second P ⁇ -type anode layer 5 (fourth semiconductor layer), the N ⁇ -type drift layer 7 (second semiconductor layer), and the N + -type cathode layer 8 (first semiconductor layer) are shown in FIG. Since the configuration is the same as that of the semiconductor device 100, a duplicate description is omitted.
  • the semiconductor device 200 of FIG. 7 differs from the semiconductor device 100 of FIG. 1 in that it has a second N ⁇ type drift layer 32 (fifth semiconductor layer) with a reduced carrier lifetime.
  • the second N ⁇ type drift layer 32 is formed by irradiating a part of the N ⁇ type drift layer 7 with a lifetime killer. Therefore, the second N ⁇ type drift layer 32 is formed inside the N ⁇ type drift layer 7 (first N ⁇ type drift layer).
  • the diode of the semiconductor device 200 of the second embodiment includes the second N ⁇ type drift layer 32, the voltage applied to the insulated gate electrode 1 is higher than the diode of the semiconductor device 100 of the first embodiment.
  • the injection controllability of internal charges (for example, hole carriers) due to can be improved.
  • FIG. 8 is a diagram schematically showing a hole and electron carrier profile when the voltage applied to the insulated gate electrode 1 of the diode of the semiconductor device 200 according to the second embodiment of the present invention is zero.
  • FIG. 8 what is different from FIG. 3 is an influence due to the presence of the second N ⁇ -type drift layer 32.
  • the hole carrier (17) is blocked from being injected into the N ⁇ -type drift layer 7 (hole carrier 15) by the second N ⁇ -type drift layer 32 with a reduced carrier lifetime, and the electrons (34) are transferred to the carrier
  • the second N ⁇ type drift layer 32 having a reduced lifetime works to block the injection into the first P ⁇ type anode layer 4, and the conductivity modulation can be further suppressed.
  • FIG. 9 is a diagram schematically showing an example of a cross-sectional structure of a semiconductor device 300 according to the third embodiment of the present invention.
  • the semiconductor device 300 is a side gate control type diode.
  • a side gate control type insulating gate (insulating side gate) 37 is provided between the anode electrode 6 (first electrode) and the cathode electrode 9 (second electrode) forming the diode, and the insulating gate 37 is insulated.
  • the diode characteristics are controlled by the voltage applied to the gate electrode (insulated side gate electrode) 35.
  • a second P ⁇ type anode layer 5 (fourth semiconductor layer) with a reduced carrier lifetime is provided in the first P ⁇ type anode layer 4 (third semiconductor layer).
  • the N ⁇ type drift layer 7 (second semiconductor layer), the first P ⁇ type anode layer 4 vertically adjacent to the N ⁇ type drift layer 7, and the first P ⁇ type anode layer 4 And an N + type cathode layer 8 (first semiconductor layer) adjacent to the N ⁇ type drift layer 7 in the vertical direction on the opposite side.
  • the side facing the first P ⁇ type anode layer 4 includes a so-called side gate type insulating gate 37 in which an insulating film (oxide film) 38 is disposed and the first P ⁇ -type anode layer 4 is present only on one side with respect to the insulating gate electrode 35. .
  • the first P ⁇ -type anode layer 4 includes a second P ⁇ -type anode layer 5 with a reduced carrier lifetime, and the second P ⁇ -type anode layer 5 is gate-insulated. It is in contact with the film 36.
  • the anode electrode 6 and the first P ⁇ -type anode layer 4 are in contact with each other at the metal-semiconductor contact surface 10. That is, the anode electrode 6 made of metal and the first P ⁇ -type anode layer 4 made of semiconductor are electrically connected by Schottky contact or ohmic contact.
  • the cathode electrode 9 by ohmic contact with the N + -type cathode layer 8, N + -type cathode layer 8 and are electrically connected. Further, the cathode electrode 9 and the N ⁇ type drift layer 7 are electrically connected via the N + type cathode layer 8.
  • the semiconductor substrate on which the first P ⁇ -type anode layer 4, the second P ⁇ -type anode layer 5, the N ⁇ -type drift layer 7 and the N + -type cathode layer 8 are based is silicon (silicon, Si) or It is formed from silicon carbide (SiC), and the gate insulating film 2 is formed from silicon dioxide (SiO 2 ).
  • the recovery current can be further reduced by the diode of the semiconductor device 300 of the present embodiment (third embodiment) than the diode (semiconductor device 100) described in the first embodiment.
  • FIG. 10 is a diagram schematically showing a recovery current path of the diode of the semiconductor device 100 according to the first embodiment of the present invention.
  • FIG. 11 is a diagram schematically showing a recovery current path of the diode of the semiconductor device 300 according to the third embodiment of the present invention.
  • the recovery current path of the diode of the semiconductor device 100 is a recovery current that returns to the anode electrode 6 from the region facing the insulated gate 3 in addition to the path 70 from the N ⁇ -type drift layer 7.
  • the path 71 exists.
  • FIG. 12 is a diagram showing drive gate signals for driving an insulated gate vertical semiconductor device according to the fourth embodiment of the present invention.
  • the horizontal axis represents time (time transition)
  • the vertical axis represents the respective voltages of the input signals 24 and 25.
  • This transient state is the recovery state (28: FIG. 12).
  • the input signal 24 to the gate of the diode 42 is turned off (0 V) immediately before the recovery to reduce the injected charge amount of hole carriers (27, time t2). It is necessary to make.
  • FIG. 13 is a diagram showing an example of a manufacturing method of the semiconductor device 100 (FIG. 1) according to the fifth embodiment of the present invention.
  • FIG. 13 (a) shows a state before the second P ⁇ -type anode layer 5 is formed. The state of the semiconductor device 100 is shown, and (b) shows the state of the semiconductor device 100 after the second P ⁇ -type anode layer 5 is formed.
  • the fifth embodiment of the present invention is a method for manufacturing a trench gate control type diode, and in particular, a method for forming a second P ⁇ -type anode layer 5 in the first P ⁇ -type anode layer 4 will be described. .
  • the semiconductor device (100) includes an anode electrode 6 (first electrode), a cathode electrode 9 (second electrode), an insulating gate 3, an insulating gate electrode 1, a gate insulating film 2, A first P ⁇ -type anode layer 4 (third semiconductor layer), an N ⁇ -type drift layer 7 (second semiconductor layer), and an N + -type cathode layer 8 (first semiconductor layer) are provided.
  • FIG. 13A The difference between FIG. 13A and FIG. 13B is the presence or absence of the second P ⁇ -type anode layer 5 (fourth semiconductor layer).
  • a method for manufacturing the second P ⁇ -type anode layer 5 (fourth semiconductor layer) will be described. The description of the manufacturing method other than the second P ⁇ -type anode layer 5 (fourth semiconductor layer) is omitted.
  • helium (He), protons (P, H + ), electron beams, etc. are mainly directed toward a predetermined position of a part of the first P ⁇ -type anode layer 4.
  • a lifetime killer is irradiated (63).
  • the portion of the first P ⁇ -type anode layer 4 that has been irradiated with the lifetime killer is damaged in the crystal structure (crystal defects), carriers (holes and electrons) are difficult to move, and the carrier lifetime is reduced.
  • the second P ⁇ -type anode layer 5 is formed.
  • FIG. 13B shows a state in which the second P ⁇ -type anode layer 5 is formed.
  • the second P ⁇ -type anode layer 5 in FIG. 13B is formed by irradiating a lifetime killer based on the first P ⁇ -type anode layer 4.
  • the P ⁇ -type anode layer 5 is included in the first P ⁇ -type anode layer 4.
  • ⁇ Effect of Fifth Embodiment> As described above, since the second P ⁇ -type anode layer 5 is formed by irradiating a part of the first P ⁇ -type anode layer 4 with a lifetime killer, it is easy and low in the manufacturing process. A semiconductor device (gate-controlled diode) having desired characteristics can be obtained at low cost.
  • Sixth Embodiment: Manufacturing Method of Semiconductor Device >> A method for manufacturing a semiconductor device (insulated gate type vertical semiconductor device) according to a sixth embodiment of the present invention will be described with reference to FIG.
  • FIG. 14 is a view showing an example of a manufacturing method of the semiconductor device 300 (FIG. 9) according to the sixth embodiment of the present invention.
  • FIG. 14 (a) shows a state before the second P ⁇ -type anode layer 5 is formed. The state of the semiconductor device is shown, and (b) shows the state of the semiconductor device after the second P ⁇ -type anode layer 5 is formed.
  • the sixth embodiment of the present invention is a method for manufacturing a side gate control type diode, and in particular, a method for forming a second P ⁇ -type anode layer 5 in the first P ⁇ -type anode layer 4 will be described. .
  • the semiconductor device (300) includes an anode electrode 6 (first electrode), a cathode electrode 9 (second electrode), an insulating gate 37, an insulating gate electrode 35, a gate insulating film 36, An oxide film 38, a first P ⁇ type anode layer 4 (third semiconductor layer), an N ⁇ type drift layer 7 (second semiconductor layer), and an N + type cathode layer 8 (first semiconductor layer) are provided.
  • FIG. 14A The difference between FIG. 14A and FIG. 14B is the presence or absence of the second P ⁇ -type anode layer 5 (fourth semiconductor layer).
  • a method for manufacturing the second P ⁇ -type anode layer 5 (fourth semiconductor layer) will be described. The description of the manufacturing method other than the second P ⁇ -type anode layer 5 (fourth semiconductor layer) is omitted.
  • helium (He), protons (P, H + ), electron beams, etc. are mainly directed toward a predetermined position of a part of the first P ⁇ -type anode layer 4.
  • a lifetime killer is irradiated (63).
  • the portion of the first P ⁇ -type anode layer 4 that has been irradiated with the lifetime killer is damaged in the crystal structure (crystal defects), carriers (holes and electrons) are difficult to move, and the carrier lifetime is reduced.
  • the second P ⁇ -type anode layer 5 is formed.
  • FIG. 14B shows a state in which the second P ⁇ type anode layer 5 is formed.
  • the second P ⁇ -type anode layer 5 in FIG. 14B is formed by irradiating the lifetime killer based on the first P ⁇ -type anode layer 4.
  • the P ⁇ -type anode layer 5 is included in the first P ⁇ -type anode layer 4.
  • ⁇ Effects of Sixth Embodiment> As described above, since the second P ⁇ -type anode layer 5 is formed by irradiating a part of the first P ⁇ -type anode layer 4 with a lifetime killer, it is easy and low in the manufacturing process. A semiconductor device (gate-controlled diode) having desired characteristics can be obtained at low cost.
  • Driving Device for Semiconductor Circuit A semiconductor circuit (semiconductor device) drive device according to a seventh embodiment of the present invention will be described with reference to FIG.
  • FIG. 15 is a diagram illustrating an example of a circuit configuration of a driving device of a semiconductor circuit (semiconductor device) according to a seventh embodiment of the present invention, where (a) illustrates a circuit configuration for characteristic evaluation, and (b) illustrates The partial structure of the circuit used as an inverter is shown.
  • a diode (gate-controlled diode) 42 having an insulated gate is replaced with an IGBT constituting the upper arm. Used as a freewheeling diode connected in antiparallel.
  • control circuit 46 the gate drive circuit 45, and the delay circuit block 44 control the IGBT 43 and the diode 42 having an insulated gate.
  • the delay circuit block 44 generates the delay timing of the gate of the IGBT 43 and the gate of the diode 42. Then, as shown in the fourth embodiment with reference to FIG. 12, the insulated gate (3: FIG. 1) of the diode 42 is turned off immediately before the IGBT 43 of the pair arm is turned on and the diode 42 reaches the recovery state. It is controlled in the same way.
  • the delay constant circuit (not shown) provided in the delay circuit block 44 is mainly a so-called RC delay circuit composed of a resistor and a capacitor.
  • the gate drive circuit 45 mainly has a function of a level shift circuit that converts the input from the control circuit 46 into input signals of the gates of the IGBT 43 and the diode 42, respectively.
  • FIG. 15A the diode 42 is arranged in the upper arm, the IGBT 43 is arranged in the lower arm, and the inverter circuit is partially extracted and described.
  • FIG. 15B IGBTs are arranged in the upper arm and diodes are arranged in the lower arm, and the above-described drive circuit network is also arranged for these.
  • the control circuit 46 controls the upper arm and the lower arm in an integrated manner, so that the DC power (DC voltage) of the DC power supply 40 is converted into AC power (AC voltage) and an inductive load (for example, AC power (AC voltage) is supplied to a part of the motor 41.
  • a power conversion device such as a low-loss inverter can be provided by a drive device for a semiconductor circuit (semiconductor device) including the control circuit 46, the gate drive circuit 45, and the delay circuit block 44.
  • a power conversion device including any one of the semiconductor devices according to the first to third embodiments will be described.
  • FIG. 16 is a diagram illustrating an example of a circuit configuration of the power conversion device according to the eighth embodiment of the present invention. Note that the three-phase AC motor 48 is not included in the power converter.
  • the upper arm is constituted by an IGBT 43U (switching element) and a diode (gate control type diode) 42U having an insulated gate
  • the lower arm is constituted by an IGBT 43D (switching element) and a diode (gate control type diode) 42D having an insulated gate. And are configured.
  • the pair of the upper arm and the lower arm constitutes a power conversion leg for one phase.
  • the output signals of the delay circuit block 44 (6 in total) are input to the gates of the three IGBTs 43U and the three IGBTs 43D, respectively.
  • a total of six gate drive circuits 45 drive the diodes 42U (three in total), the diodes 42D (three in total), and the delay circuit blocks 44 (total six).
  • control circuit 46 controls the total of six gate drive circuits 45 so that the DC power (DC voltage) of the DC power supply 40 is converted into three-phase AC power (three-phase AC voltage).
  • the three-phase AC motor 48 is supplied.
  • the second P ⁇ -type anode layer 5 is formed by irradiating the first P ⁇ -type anode layer 4 with the lifetime killer, but the irradiated position is a region close to the anode electrode 6.
  • the anode electrode 6 and the second P ⁇ -type anode layer 5 are formed in contact with each other.
  • anode electrode 6 and the second P ⁇ -type anode layer 5 are in metal-semiconductor contact, they are in Schottky contact or ohmic contact.
  • the diode characteristics change, and this structure can be used for applications where this characteristic is desirable.
  • the lifetime killer irradiation causes damage (crystal defects) to the crystal structure of first P ⁇ -type anode layer 4, and the lifetime of carriers is reduced.
  • the method for forming the reduced second P ⁇ -type anode layer 5 has been described.
  • annealing may be performed. Good.
  • This annealing treatment recovers more than necessary crystal defects, and the second P ⁇ -type anode layer 5 needs to be performed to such an extent that the lifetime of the carrier is kept reduced.
  • the annealing process is performed at several hundred degrees Celsius.
  • a first semiconductor layer (N + -type cathode layer) and a second semiconductor layer (N ⁇ -type drift layer) are constituted by N-type semiconductor layers, and a third semiconductor layer (first P ⁇ -type) is formed.
  • the anode layer) and the fourth semiconductor layer (second P ⁇ -type anode layer) are composed of P-type semiconductor layers.
  • the power converter according to the present embodiment is also effective. It is. ⁇ Equipment equipped with diode with insulated gate ⁇ In FIG. 15 or FIG. 16, the example in which the diodes 42, 42U, and 42D having the insulated gate, which is the semiconductor device according to the embodiment of the present invention, are provided in the power conversion device as the inverter has been described.
  • diodes 42, 42U, and 42D having insulating gates which are semiconductor devices according to the embodiment of the present invention, are used as a free-wheeling diode connected in reverse parallel to a switching element (IGBT) of a converter that converts AC power into DC power. You may prepare.
  • IGBT switching element
  • devices such as a booster circuit device and a power factor correction device may include diodes 42, 42U, and 42D having an insulating gate, which is a semiconductor device according to the embodiment of the present invention.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Inverter Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thyristors (AREA)

Abstract

La présente invention, qui aborde le problème de fournir un dispositif à semi-conducteur présentant de faibles pertes de conduction et de faibles pertes de recouvrement, un procédé de fabrication dudit dispositif à semi-conducteur et un dispositif de conversion de puissance utilisant ledit dispositif à semi-conducteur, est caractérisée en ce qu'elle comprend : une première couche semi-conductrice (8) d'un premier type de conductivité ; une deuxième couche semi-conductrice (7) du premier type de conductivité, ladite couche (7) étant adjacente à la première couche semi-conductrice (8) et ayant une concentration d'impuretés inférieure à celle de la première couche semi-conductrice (8) ; une troisième couche semi-conductrice (4) d'un second type de conductivité, ladite couche (4) étant adjacente à la deuxième couche semi-conductrice (7) ; une première électrode (6) qui est connectée électriquement à la troisième couche semi-conductrice (4) ; une seconde électrode (9) qui est connectée électriquement à la première couche semi-conductrice (8) ; une quatrième couche semi-conductrice (5) du second type de conductivité, ladite couche (5) étant incluse dans la troisième couche semi-conductrice (4) et ayant une durée de vie de porteurs réduite par comparaison à celle de la troisième couche semi-conductrice (4) ; et une grille isolée (3) qui est en contact avec la troisième couche semi-conductrice.
PCT/JP2017/001622 2016-02-05 2017-01-19 Dispositif à semi-conducteur, son procédé de fabrication, et dispositif de conversion de puissance l'utilisant WO2017135037A1 (fr)

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CN112447824A (zh) * 2019-08-30 2021-03-05 株式会社东芝 半导体装置及半导体模块
CN112786696A (zh) * 2019-11-01 2021-05-11 株式会社东芝 半导体装置
CN113497033A (zh) * 2020-03-19 2021-10-12 株式会社东芝 半导体装置及其控制方法
CN116454119A (zh) * 2023-06-15 2023-07-18 广东巨风半导体有限公司 一种快恢复二极管及其制备方法
EP4071813A4 (fr) * 2019-12-06 2023-12-06 Hitachi, Ltd. Procédé de commande de circuit semi-conducteur et convertisseur de puissance l'adoptant

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JP2023106016A (ja) * 2022-01-20 2023-08-01 株式会社日立製作所 電力変換装置
JP2023144454A (ja) * 2022-03-28 2023-10-11 株式会社 日立パワーデバイス 半導体装置、半導体装置および電力変換装置

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CN116454119A (zh) * 2023-06-15 2023-07-18 广东巨风半导体有限公司 一种快恢复二极管及其制备方法

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