WO2017135037A1 - Semiconductor device, method for producing same, and power conversion device using same - Google Patents

Semiconductor device, method for producing same, and power conversion device using same Download PDF

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Publication number
WO2017135037A1
WO2017135037A1 PCT/JP2017/001622 JP2017001622W WO2017135037A1 WO 2017135037 A1 WO2017135037 A1 WO 2017135037A1 JP 2017001622 W JP2017001622 W JP 2017001622W WO 2017135037 A1 WO2017135037 A1 WO 2017135037A1
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semiconductor layer
layer
gate
type
semiconductor device
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PCT/JP2017/001622
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French (fr)
Japanese (ja)
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智之 三好
悠次郎 竹内
智康 古川
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株式会社日立パワーデバイス
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Priority to DE112017000224.9T priority Critical patent/DE112017000224B4/en
Publication of WO2017135037A1 publication Critical patent/WO2017135037A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8613—Mesa PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
    • H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7391—Gated diode structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections

Definitions

  • the present invention relates to a semiconductor device, a manufacturing method thereof, and a power conversion device using the same.
  • the present invention relates to a semiconductor device suitable for a wide range of use from a low-power device such as an air conditioner or a microwave oven to a high-power device such as an inverter of a railway or a steel mill, a manufacturing method thereof, and a power converter using the same .
  • IGBTs Insulated Gate Bipolar Transistors
  • Patent Document 1 provides “[Problem] To provide a power diode capable of simultaneously realizing low on-resistance and soft recovery. [Solution] P-type emitter layer 2 on the surface of N ⁇ -type base layer 1, back surface An N + -type emitter layer is formed on the P-type emitter layer 2 and a trench groove having a depth reaching the N ⁇ -type base layer 1 is formed on the surface of the P-type emitter layer 2, and a gate electrode is formed in the trench groove via a gate insulating film 3. 4 is embedded (see [Summary]), and a technique relating to a diode is disclosed.
  • Patent Document 1 has the following problems.
  • the present invention has been made in view of the above-described problems, and an object of the present invention is to provide a semiconductor device that has both low conduction loss performance and low recovery loss performance, a driving device thereof, and a manufacturing method thereof.
  • a semiconductor device of the present invention includes a first conductive type first semiconductor layer, a first conductive type second semiconductor layer adjacent to the first semiconductor layer, and having a lower impurity concentration than the first semiconductor layer, A third semiconductor layer of a second conductivity type adjacent to the second semiconductor layer, a first electrode electrically connected to the third semiconductor layer, and a first electrode electrically connected to the first semiconductor layer.
  • the present invention it is possible to provide a semiconductor device that achieves both low conduction loss performance and low recovery loss performance, a manufacturing method thereof, and a power conversion device using the same.
  • FIG. 1 shows typically the example of the cross-section of the semiconductor device which concerns on 1st Embodiment of this invention, (a) partially represents the vicinity of two trench gate type
  • FIG. It is a figure which shows the example of the forward direction characteristic of the diode of the semiconductor device which concerns on 1st Embodiment of this invention. It is a figure which shows the example of the input signal of the gate of the diode of the semiconductor device which concerns on 1st Embodiment of this invention, and the input signal of the gate of IGBT of a pair arm.
  • FIG. 6 is a diagram illustrating an example of a transient characteristic of an anode current of a diode and a cathode-anode voltage when the control by the input signal of FIG. 5 is applied to the diode of the semiconductor device according to the first embodiment of the present invention. It is a figure which shows typically the example of the cross-section of the semiconductor device which concerns on 2nd Embodiment of this invention. It is a figure which shows typically the carrier profile of a hole and an electron when the voltage applied to the insulated gate electrode of the diode of the semiconductor device which concerns on 2nd Embodiment of this invention is made into zero. It is a figure which shows typically the example of the cross-section of the semiconductor device which concerns on 3rd Embodiment of this invention.
  • FIG. 1 It is a figure which shows typically the path
  • FIG. 10 is a diagram showing an example of a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention, where (a) shows the state of the semiconductor device before the second P ⁇ -type anode layer is formed, and (b) Represents the state of the semiconductor device after the second P ⁇ -type anode layer is formed. It is a figure which shows the example of the manufacturing method of the semiconductor device which concerns on 6th Embodiment of this invention, (a) represents the state of the semiconductor device before a 2nd P ⁇ type anode layer is formed, (b) Represents the state of the semiconductor device after the second P ⁇ -type anode layer is formed.
  • FIG. 6 is a diagram illustrating an example of a cross-sectional structure of a diode having an insulated gate according to Comparative Example 2.
  • FIG. 10 is a diagram showing energy bands in a cross section of a central portion of an anode electrode and a P ⁇ type anode layer of a diode having an insulated gate according to Comparative Example 2.
  • FIG. 1 is a diagram schematically showing an example of a cross-sectional structure of a semiconductor device 100 according to the first embodiment of the present invention.
  • FIG. 1 (a) is a partial view of the vicinity of two trench gate type insulated gates 3.
  • (B) shows a state in which a plurality of trench gate type insulated gates 3 are arranged.
  • the semiconductor device 100 is a trench gate control type diode. That is, the trench gate type insulated gate 3 is provided between the anode electrode 6 and the cathode electrode 9 forming the diode, and the diode characteristics of the semiconductor device 100 are changed by the voltage applied to the insulated gate electrode 1 of the insulated gate 3. Be controlled.
  • the semiconductor device 100 is characterized in that the second P ⁇ -type anode layer 5 having a reduced carrier lifetime is provided in the first P ⁇ -type anode layer 4 in the first embodiment of the present invention. It is that.
  • Comparative Example 1 As Comparative Example 1, a general diode (not having a gate electrode structure for controlling the diode characteristics) is connected in reverse parallel to the IGBT, and a plurality of IGBTs are used to convert an inverter (converting DC power into AC power). A configuration example will be described.
  • FIG. 17 shows an example of a partial circuit of an inverter (DC power-AC power converter) configured to include a plurality of IGBTs 43 in Comparative Example 1 and a plurality of diodes 47 respectively connected in reverse parallel to the IGBTs 43.
  • DC power-AC power converter DC power-AC power converter
  • the diode 47 is connected to the IGBT 43 in antiparallel.
  • the upper arm and the lower arm are constituted by two IGBTs 43 connected in series.
  • the upper arm and the lower arm are driven by the respective gate drive circuits 45, and are turned on and off at high speeds.
  • the DC power (DC voltage) of the DC power supply 40 is exchanged. It is controlled to convert it into electric power (alternating voltage).
  • the control circuit 46 that controls the plurality of IGBTs 43 in an integrated manner controls the U phase, the V phase, and the W phase, respectively. Generate AC power (AC voltage) for the phase.
  • the generated U-phase, V-phase, and W-phase three-phase AC power (three-phase AC voltage) is applied to and supplied to a three-phase AC motor (inductive load) 48 to drive the three-phase AC motor 48.
  • the IGBT 43 and the diode 47 generate conduction loss when conducting, and generate switching loss when switching.
  • the switching loss includes a turn-on loss and a turn-off loss generated from the IGBT 43 and a recovery loss generated from the diode 47 when the IGBT is turned on.
  • Comparative example 2 As Comparative Example 2, a diode (gate-controlled diode) having an insulated gate according to a conventional technique (for example, cited document 1) will be described.
  • FIG. 15A shows a circuit configuration for characteristic evaluation
  • FIG. 15B shows a partial configuration of a circuit used as an inverter.
  • the diode 42 having an insulated gate is different from the IGBT that constitutes the upper arm (not shown in FIG. 15A, FIG. 15B). Used as a free-wheeling diode connected in reverse parallel to the upper arm IGBT 43).
  • control circuit 46 and the gate drive circuit 45 control the IGBT 43 and the diode 42 having an insulated gate.
  • the delay circuit block 44 gives a delay to the on / off of the IGBT 43.
  • control circuit 46 controls the upper arm and the lower arm, whereby the DC power (DC voltage) of the DC power supply 40 is converted into AC power (AC voltage) and an inductive load (for example, a part of the motor) 41. Is supplied with AC power (AC voltage).
  • FIGS. 15A and 15B are also used in the embodiment of the present invention, and the details will be described later.
  • the diode 42 having an insulated gate has a buried insulated gate provided inside the trench.
  • a forward voltage is reduced by applying a negative voltage to the insulated gate during conduction to form a hole accumulation layer.
  • the gate voltage zero during recovery hole injection from the anode is suppressed and recovery loss is reduced.
  • the diode 42 having the insulated gate in the comparative example 2 can control the hole injection efficiency from the anode by the voltage applied to the insulated gate, thereby improving the trade-off between the forward voltage related to the conduction loss and the recovery loss. be able to. That is, the comparative example 2 is improved with respect to the reduction of the recovery loss than the comparative example 1.
  • Comparative Example 2 has the following problems.
  • FIG. 18 is a diagram showing an example of a cross-sectional structure of a diode having an insulated gate according to Comparative Example 2.
  • P comprises a layer containing a P-type impurity - -type anode layer (anode region) 4 and contacts the anode electrode 6, P - -type anode layer (anode region) gate insulating film in contact with the 4 (insulating oxide film ) 2 and an insulated gate 3 composed of an insulated gate electrode 1 is disposed.
  • an N ⁇ type drift layer 7 made of a layer containing a low concentration of N type impurities is provided below the P ⁇ type anode layer (anode region) 4 (corresponding to the lower side of the drawing) in order to ensure high breakdown voltage performance.
  • an N + type cathode layer 8 made of a layer containing a high concentration impurity for electrical connection with the cathode electrode 9 is disposed.
  • ⁇ Hole carrier distribution when forward voltage is applied ⁇ In FIG. 19, a negative voltage (11) was applied to the insulated gate electrode 1 of the diode having an insulated gate according to Comparative Example 2, and a forward voltage (12) was applied between the cathode electrode 9 and the anode electrode 6. It is a figure which shows typically distribution of the hole carrier at the time.
  • hole carriers (14) accumulate in the region in contact with the gate insulating film 2 inside the P ⁇ -type anode layer 4 due to the electric field due to the applied negative voltage.
  • the accumulated hole carriers (14) are injected into the N ⁇ -type drift layer 7 by the applied forward voltage (12).
  • the hole carriers injected into the N ⁇ type drift layer 7 are denoted as hole carriers (15).
  • FIG. 20 is a diagram schematically illustrating the distribution of hole carriers when the voltage applied to the insulated gate electrode 1 of the diode having the insulated gate according to Comparative Example 2 is zero.
  • the impurity concentration of the P ⁇ -type anode layer 4 is increased, the concentration of hole carriers accumulated at the interface of the insulated gate 3 when a gate voltage is applied is increased, and the conduction loss is decreased. Is an important structural design item.
  • FIG. 21 is a diagram showing an energy band in the cross section of the central portion of the anode electrode 6 and the P ⁇ -type anode layer 4 of the diode having an insulated gate according to Comparative Example 2.
  • the horizontal axis represents “depth” from the interface between the anode electrode 6 and the P ⁇ -type anode layer 4, and the vertical axis represents “energy (energy level) (eV)”.
  • the characteristic line 51 indicates the energy level of the anode electrode.
  • the characteristic line 52 shows the energy level of the valence band when the anode P ⁇ layer concentration is high.
  • the characteristic line 53 shows the energy level of the valence band when the anode P ⁇ layer concentration is low.
  • the characteristic line 54 shows the energy level of the conduction band when the anode P ⁇ layer concentration is high.
  • the characteristic line 55 shows the energy level of the conduction band when the anode P ⁇ layer concentration is low.
  • An arrow 50 represents the boundary surface (interface) between the anode electrode and the anode P ⁇ layer.
  • Arrow 56 indicates a decrease in the hole injection barrier with increasing anode P ⁇ layer concentration.
  • An arrow 57 indicates the anode electrode region.
  • Arrow 58 indicates the anode P ⁇ layer region.
  • P - by the concentration of P-type layer type anode layer 4 increases, P - -type energy level (52) of the valence band of the anode layer 4 anode electrode 6 and the P - interface type anode layer 4 (50 ) Increases in the vicinity, and the hole injection barrier from the anode electrode 6 to the P ⁇ -type anode layer 4 decreases (56).
  • FIG. 22 shows the diode when the negative voltage is applied to the gate and when the P-type impurity concentration of the P ⁇ -type anode layer 4 of the diode having the insulated gate according to Comparative Example 2 is low and high. It is a figure which shows the forward direction characteristic.
  • the horizontal axis represents “forward voltage, VF (V)”, and the vertical axis represents “forward current density, JF (A / cm 2 )”.
  • a characteristic line 59 is a forward characteristic of the diode when a negative bias is applied between the gate and the anode when the concentration of the P ⁇ -type anode layer 4 is low.
  • a characteristic line 60 is a forward characteristic of the diode when the gate-anode gap is zero bias when the concentration of the P ⁇ -type anode layer 4 is low.
  • a characteristic line 61 is a forward characteristic of the diode when a negative bias is applied between the gate and the anode when the concentration of the P ⁇ -type anode layer 4 is high.
  • the characteristic line 62 is the forward characteristic of the diode when the gate-anode gap is zero bias when the concentration of the P ⁇ -type anode layer 4 is high.
  • the P-type impurity concentration is increased while the gate and anode are both negatively biased (negative voltage). This shows that the forward voltage of the diode is reduced. That is, the effect of reducing conduction loss can be confirmed.
  • FIG. 1 is a diagram showing a cross-sectional structure of the semiconductor device 100 according to the first embodiment of the present invention.
  • FIG. 1A is a partial view of the vicinity of two trench gate type insulating gates 3.
  • (B) shows a state in which a plurality of trench gate type insulated gates 3 are arranged.
  • the notations N ⁇ , N, and N + indicate that the semiconductor layer is N-type (first conductivity type), and the impurity concentration of pentavalent atoms is relatively higher in this order. Indicates high.
  • the notations P ⁇ , P, and P + indicate that the semiconductor layer is P-type (second conductivity type) and that the impurity concentration of trivalent atoms is relatively high in this order.
  • the semiconductor device 100 is a trench gate control type diode. That is, a trench gate type insulated gate 3 is provided between an anode electrode 6 (first electrode) and a cathode electrode 9 (second electrode) forming a diode, and is applied to the insulated gate electrode 1 of the insulated gate 3. The diode characteristics are controlled by the voltage.
  • the semiconductor device 100 as a first embodiment of the present invention is characterized in that the second P ⁇ type in which the lifetime of carriers is reduced in the first P ⁇ type anode layer 4 (third semiconductor layer).
  • the anode layer 5 (fourth semiconductor layer) is provided.
  • the second P ⁇ -type anode layer 5 is formed by irradiating a part of the first P ⁇ -type anode layer 4 with a lifetime killer. Therefore, the second P ⁇ type anode layer 5 is formed inside the first P ⁇ type anode layer 4.
  • the N ⁇ type drift layer 7 (second semiconductor layer), the first P ⁇ type anode layer 4 adjacent to the N ⁇ type drift layer 7 in the vertical direction (the vertical direction of the paper surface), and the first An N + -type cathode layer 8 (first semiconductor layer) adjacent to the N ⁇ -type drift layer 7 in the vertical direction is provided on the side opposite to the P ⁇ -type anode layer 4.
  • a trench gate type insulating gate 3 having an insulating gate electrode 1 provided on the surface of the first P ⁇ -type anode layer 4 via the gate insulating film 2 is provided. .
  • the first P ⁇ -type anode layer 4 includes a second P ⁇ -type anode layer 5 with a reduced carrier lifetime, and the second P ⁇ -type anode layer 5 is gate-insulated. It is in contact with the membrane 2.
  • the anode electrode 6 and the first P ⁇ -type anode layer 4 are in contact with each other at the metal-semiconductor contact surface 10. That is, the anode electrode 6 made of metal and the first P ⁇ -type anode layer 4 made of semiconductor are electrically connected by Schottky contact or ohmic contact.
  • the cathode electrode 9 by ohmic contact with the N + -type cathode layer 8, N + -type cathode layer 8 and are electrically connected. Further, the cathode electrode 9 and the N ⁇ type drift layer 7 are electrically connected via the N + type cathode layer 8.
  • the semiconductor substrate on which the first P ⁇ -type anode layer 4, the second P ⁇ -type anode layer 5, the N ⁇ -type drift layer 7 and the N + -type cathode layer 8 are based is silicon (silicon, Si) or It is formed from silicon carbide (SiC), and the gate insulating film 2 is formed from silicon dioxide (SiO 2 ).
  • a plurality of insulated gates 3 formed in the trench groove are arranged in the horizontal direction (the horizontal direction of the paper).
  • the width of the trench is indicated by W, and the interval between the trenches is indicated by S.
  • FIG. 1B the description of each element shown in FIG. 1A other than the trench structure (groove) and the insulated gate 3 is omitted.
  • the semiconductor device 100 is configured by repeatedly forming a plurality of the structures shown in FIG. 1B.
  • the trench width W is preferably larger than the trench spacing S.
  • a negative voltage is applied to the insulated gate electrode 1 of the semiconductor device 100 according to the first embodiment of the present invention, and a forward voltage for conducting the diode is applied between the cathode electrode 9 and the anode electrode 6. It is a figure which shows typically distribution of the hole carrier at the time of being done.
  • a hole carrier accumulation layer (14) having the same concentration is also formed at the interface between the second P ⁇ -type anode layer 5 and the gate insulating film 2 in which the carrier lifetime is reduced.
  • Many hole carriers (15) are injected into the N ⁇ -type drift layer 7 via the hole carrier accumulation layer (14), the forward voltage (VF) of the diode is lowered, and the conduction loss is reduced.
  • electrons are represented as electron carriers 16.
  • Figure 2 is a second P - is a hole carrier distribution in the case where a type anode layer 5, a second P shown in FIG. 19 - -type anode layer 5 is the same as the hole carrier distribution in the absence of .
  • the voltage applied to the insulated gate electrode 1 of the semiconductor device 100 according to the first embodiment of the present invention is set to zero, and a forward voltage is applied between the cathode electrode 9 and the anode electrode 6. It is a figure which shows typically distribution of the hole carrier at the time.
  • hole carriers are injected into this region (second P ⁇ -type anode layer) by the second P ⁇ -type anode layer 5 provided in the first P ⁇ -type anode layer 4 and having a reduced carrier lifetime. 5), the injection into the N ⁇ -type drift layer 7 can be further suppressed as compared with the case where the present invention is not applied, and the controllability of the hole carrier injection amount by the gate voltage can be improved.
  • FIG. 3 shows a distribution in which the amount of injected hole carriers is smaller than that in FIG.
  • the hole carrier injection amount is as shown in FIG. 3 and FIG. Less than comparison.
  • FIG. 4 is a diagram illustrating an example of forward characteristics of the diode of the semiconductor device 100 according to the first embodiment of the present invention.
  • the horizontal axis is “forward voltage, VF (V)”, and the vertical axis is “forward current density, JF (A / cm 2 )”.
  • a characteristic line 20 is a forward characteristic of the diode when a negative bias is applied between the gate and the anode when the second P ⁇ -type anode layer 5 with reduced carrier lifetime is not present.
  • a characteristic line 21 is a forward characteristic of the diode when a zero bias is applied between the gate and the anode when the second P ⁇ -type anode layer 5 with reduced carrier lifetime is not present.
  • a characteristic line 22 is a forward characteristic of the diode when a negative bias is applied between the gate and the anode when the second P ⁇ -type anode layer 5 having a reduced carrier lifetime is present.
  • a characteristic line 23 is a forward characteristic of the diode when a zero bias is applied between the gate and the anode when the second P ⁇ -type anode layer 5 in which the lifetime of carriers is reduced is present.
  • the gate voltage controllability of the forward voltage (VF) of the diode can be significantly improved as compared with the diode of Comparative Example 2 to which the present invention is not applied.
  • the characteristic line 21 corresponding to Comparative Example 2 is compared with the characteristic line 23 of the semiconductor device 100 according to the first embodiment of the present invention. As shown by the characteristic line 23, the forward voltage (VF) of the diode is greatly increased.
  • FIG. 5 is a diagram showing an example of the input signal 24 of the gate (insulated gate electrode 1: FIG. 1) of the diode and the input signal 25 of the gate of the IGBT of the pair arm of the semiconductor device 100 according to the first embodiment of the present invention. It is.
  • the input signal 24 varies between a negative voltage and a zero voltage
  • the input signal 25 varies between a negative voltage and a positive voltage.
  • FIG. 15A is an evaluation circuit, and the circuit shown in FIG. 15B is actually used.
  • the input signal 25 in FIG. 5 is input to the gate of the IGBT 43 constituting the lower arm of FIG.
  • the input signal 24 (FIG. 5) input to the insulated gate electrode 1 (FIG. 1) of the diode 42 of the semiconductor device 100 according to the first embodiment of the present invention is turned on and the input signal 25 input to the gate of the IGBT 43 of the opposite arm is turned on.
  • the forward voltage (VF) of the diode is high as described above, that is, hole carrier injection from the anode electrode 6 (FIG. 1) and conductivity modulation are performed.
  • the suppressed state (27: FIG. 5) it becomes possible to shift to the recovery state.
  • FIG. 6 shows the anode current (characteristic line 31) of the diode (100) and the cathode-anode when the control by the input signal of FIG. 5 is applied to the diode of the semiconductor device 100 according to the first embodiment of the invention. It is a figure which shows the example of the transient characteristic of a voltage (characteristic line 29).
  • the horizontal axis represents time (time transition: 1 scale is 1 ⁇ sec). Also, the right vertical axis represents the cathode-anode voltage of the diode, and the left vertical axis represents the current density flowing through the diode.
  • the characteristic line 29 indicates the cathode-anode voltage.
  • the characteristic line 30 is a characteristic of current density flowing through the diode of Comparative Example 2
  • the characteristic line 31 is a characteristic of current density flowing through the diode of the semiconductor device 100 according to the first embodiment of the present invention.
  • the reverse current due to recovery observed when the voltage between the cathode and the anode rises is significantly larger than the conventional anode current (characteristic line 30). Can be reduced.
  • FIG. 7 is a diagram schematically showing an example of a cross-sectional structure of a semiconductor device 200 according to the second embodiment of the present invention.
  • an anode electrode 6 (first electrode), a cathode electrode 9 (second electrode), an insulated gate 3, an insulated gate electrode 1, a gate insulating film 2, a first P ⁇ -type anode layer 4 (third semiconductor layer). ),
  • the second P ⁇ -type anode layer 5 (fourth semiconductor layer), the N ⁇ -type drift layer 7 (second semiconductor layer), and the N + -type cathode layer 8 (first semiconductor layer) are shown in FIG. Since the configuration is the same as that of the semiconductor device 100, a duplicate description is omitted.
  • the semiconductor device 200 of FIG. 7 differs from the semiconductor device 100 of FIG. 1 in that it has a second N ⁇ type drift layer 32 (fifth semiconductor layer) with a reduced carrier lifetime.
  • the second N ⁇ type drift layer 32 is formed by irradiating a part of the N ⁇ type drift layer 7 with a lifetime killer. Therefore, the second N ⁇ type drift layer 32 is formed inside the N ⁇ type drift layer 7 (first N ⁇ type drift layer).
  • the diode of the semiconductor device 200 of the second embodiment includes the second N ⁇ type drift layer 32, the voltage applied to the insulated gate electrode 1 is higher than the diode of the semiconductor device 100 of the first embodiment.
  • the injection controllability of internal charges (for example, hole carriers) due to can be improved.
  • FIG. 8 is a diagram schematically showing a hole and electron carrier profile when the voltage applied to the insulated gate electrode 1 of the diode of the semiconductor device 200 according to the second embodiment of the present invention is zero.
  • FIG. 8 what is different from FIG. 3 is an influence due to the presence of the second N ⁇ -type drift layer 32.
  • the hole carrier (17) is blocked from being injected into the N ⁇ -type drift layer 7 (hole carrier 15) by the second N ⁇ -type drift layer 32 with a reduced carrier lifetime, and the electrons (34) are transferred to the carrier
  • the second N ⁇ type drift layer 32 having a reduced lifetime works to block the injection into the first P ⁇ type anode layer 4, and the conductivity modulation can be further suppressed.
  • FIG. 9 is a diagram schematically showing an example of a cross-sectional structure of a semiconductor device 300 according to the third embodiment of the present invention.
  • the semiconductor device 300 is a side gate control type diode.
  • a side gate control type insulating gate (insulating side gate) 37 is provided between the anode electrode 6 (first electrode) and the cathode electrode 9 (second electrode) forming the diode, and the insulating gate 37 is insulated.
  • the diode characteristics are controlled by the voltage applied to the gate electrode (insulated side gate electrode) 35.
  • a second P ⁇ type anode layer 5 (fourth semiconductor layer) with a reduced carrier lifetime is provided in the first P ⁇ type anode layer 4 (third semiconductor layer).
  • the N ⁇ type drift layer 7 (second semiconductor layer), the first P ⁇ type anode layer 4 vertically adjacent to the N ⁇ type drift layer 7, and the first P ⁇ type anode layer 4 And an N + type cathode layer 8 (first semiconductor layer) adjacent to the N ⁇ type drift layer 7 in the vertical direction on the opposite side.
  • the side facing the first P ⁇ type anode layer 4 includes a so-called side gate type insulating gate 37 in which an insulating film (oxide film) 38 is disposed and the first P ⁇ -type anode layer 4 is present only on one side with respect to the insulating gate electrode 35. .
  • the first P ⁇ -type anode layer 4 includes a second P ⁇ -type anode layer 5 with a reduced carrier lifetime, and the second P ⁇ -type anode layer 5 is gate-insulated. It is in contact with the film 36.
  • the anode electrode 6 and the first P ⁇ -type anode layer 4 are in contact with each other at the metal-semiconductor contact surface 10. That is, the anode electrode 6 made of metal and the first P ⁇ -type anode layer 4 made of semiconductor are electrically connected by Schottky contact or ohmic contact.
  • the cathode electrode 9 by ohmic contact with the N + -type cathode layer 8, N + -type cathode layer 8 and are electrically connected. Further, the cathode electrode 9 and the N ⁇ type drift layer 7 are electrically connected via the N + type cathode layer 8.
  • the semiconductor substrate on which the first P ⁇ -type anode layer 4, the second P ⁇ -type anode layer 5, the N ⁇ -type drift layer 7 and the N + -type cathode layer 8 are based is silicon (silicon, Si) or It is formed from silicon carbide (SiC), and the gate insulating film 2 is formed from silicon dioxide (SiO 2 ).
  • the recovery current can be further reduced by the diode of the semiconductor device 300 of the present embodiment (third embodiment) than the diode (semiconductor device 100) described in the first embodiment.
  • FIG. 10 is a diagram schematically showing a recovery current path of the diode of the semiconductor device 100 according to the first embodiment of the present invention.
  • FIG. 11 is a diagram schematically showing a recovery current path of the diode of the semiconductor device 300 according to the third embodiment of the present invention.
  • the recovery current path of the diode of the semiconductor device 100 is a recovery current that returns to the anode electrode 6 from the region facing the insulated gate 3 in addition to the path 70 from the N ⁇ -type drift layer 7.
  • the path 71 exists.
  • FIG. 12 is a diagram showing drive gate signals for driving an insulated gate vertical semiconductor device according to the fourth embodiment of the present invention.
  • the horizontal axis represents time (time transition)
  • the vertical axis represents the respective voltages of the input signals 24 and 25.
  • This transient state is the recovery state (28: FIG. 12).
  • the input signal 24 to the gate of the diode 42 is turned off (0 V) immediately before the recovery to reduce the injected charge amount of hole carriers (27, time t2). It is necessary to make.
  • FIG. 13 is a diagram showing an example of a manufacturing method of the semiconductor device 100 (FIG. 1) according to the fifth embodiment of the present invention.
  • FIG. 13 (a) shows a state before the second P ⁇ -type anode layer 5 is formed. The state of the semiconductor device 100 is shown, and (b) shows the state of the semiconductor device 100 after the second P ⁇ -type anode layer 5 is formed.
  • the fifth embodiment of the present invention is a method for manufacturing a trench gate control type diode, and in particular, a method for forming a second P ⁇ -type anode layer 5 in the first P ⁇ -type anode layer 4 will be described. .
  • the semiconductor device (100) includes an anode electrode 6 (first electrode), a cathode electrode 9 (second electrode), an insulating gate 3, an insulating gate electrode 1, a gate insulating film 2, A first P ⁇ -type anode layer 4 (third semiconductor layer), an N ⁇ -type drift layer 7 (second semiconductor layer), and an N + -type cathode layer 8 (first semiconductor layer) are provided.
  • FIG. 13A The difference between FIG. 13A and FIG. 13B is the presence or absence of the second P ⁇ -type anode layer 5 (fourth semiconductor layer).
  • a method for manufacturing the second P ⁇ -type anode layer 5 (fourth semiconductor layer) will be described. The description of the manufacturing method other than the second P ⁇ -type anode layer 5 (fourth semiconductor layer) is omitted.
  • helium (He), protons (P, H + ), electron beams, etc. are mainly directed toward a predetermined position of a part of the first P ⁇ -type anode layer 4.
  • a lifetime killer is irradiated (63).
  • the portion of the first P ⁇ -type anode layer 4 that has been irradiated with the lifetime killer is damaged in the crystal structure (crystal defects), carriers (holes and electrons) are difficult to move, and the carrier lifetime is reduced.
  • the second P ⁇ -type anode layer 5 is formed.
  • FIG. 13B shows a state in which the second P ⁇ -type anode layer 5 is formed.
  • the second P ⁇ -type anode layer 5 in FIG. 13B is formed by irradiating a lifetime killer based on the first P ⁇ -type anode layer 4.
  • the P ⁇ -type anode layer 5 is included in the first P ⁇ -type anode layer 4.
  • ⁇ Effect of Fifth Embodiment> As described above, since the second P ⁇ -type anode layer 5 is formed by irradiating a part of the first P ⁇ -type anode layer 4 with a lifetime killer, it is easy and low in the manufacturing process. A semiconductor device (gate-controlled diode) having desired characteristics can be obtained at low cost.
  • Sixth Embodiment: Manufacturing Method of Semiconductor Device >> A method for manufacturing a semiconductor device (insulated gate type vertical semiconductor device) according to a sixth embodiment of the present invention will be described with reference to FIG.
  • FIG. 14 is a view showing an example of a manufacturing method of the semiconductor device 300 (FIG. 9) according to the sixth embodiment of the present invention.
  • FIG. 14 (a) shows a state before the second P ⁇ -type anode layer 5 is formed. The state of the semiconductor device is shown, and (b) shows the state of the semiconductor device after the second P ⁇ -type anode layer 5 is formed.
  • the sixth embodiment of the present invention is a method for manufacturing a side gate control type diode, and in particular, a method for forming a second P ⁇ -type anode layer 5 in the first P ⁇ -type anode layer 4 will be described. .
  • the semiconductor device (300) includes an anode electrode 6 (first electrode), a cathode electrode 9 (second electrode), an insulating gate 37, an insulating gate electrode 35, a gate insulating film 36, An oxide film 38, a first P ⁇ type anode layer 4 (third semiconductor layer), an N ⁇ type drift layer 7 (second semiconductor layer), and an N + type cathode layer 8 (first semiconductor layer) are provided.
  • FIG. 14A The difference between FIG. 14A and FIG. 14B is the presence or absence of the second P ⁇ -type anode layer 5 (fourth semiconductor layer).
  • a method for manufacturing the second P ⁇ -type anode layer 5 (fourth semiconductor layer) will be described. The description of the manufacturing method other than the second P ⁇ -type anode layer 5 (fourth semiconductor layer) is omitted.
  • helium (He), protons (P, H + ), electron beams, etc. are mainly directed toward a predetermined position of a part of the first P ⁇ -type anode layer 4.
  • a lifetime killer is irradiated (63).
  • the portion of the first P ⁇ -type anode layer 4 that has been irradiated with the lifetime killer is damaged in the crystal structure (crystal defects), carriers (holes and electrons) are difficult to move, and the carrier lifetime is reduced.
  • the second P ⁇ -type anode layer 5 is formed.
  • FIG. 14B shows a state in which the second P ⁇ type anode layer 5 is formed.
  • the second P ⁇ -type anode layer 5 in FIG. 14B is formed by irradiating the lifetime killer based on the first P ⁇ -type anode layer 4.
  • the P ⁇ -type anode layer 5 is included in the first P ⁇ -type anode layer 4.
  • ⁇ Effects of Sixth Embodiment> As described above, since the second P ⁇ -type anode layer 5 is formed by irradiating a part of the first P ⁇ -type anode layer 4 with a lifetime killer, it is easy and low in the manufacturing process. A semiconductor device (gate-controlled diode) having desired characteristics can be obtained at low cost.
  • Driving Device for Semiconductor Circuit A semiconductor circuit (semiconductor device) drive device according to a seventh embodiment of the present invention will be described with reference to FIG.
  • FIG. 15 is a diagram illustrating an example of a circuit configuration of a driving device of a semiconductor circuit (semiconductor device) according to a seventh embodiment of the present invention, where (a) illustrates a circuit configuration for characteristic evaluation, and (b) illustrates The partial structure of the circuit used as an inverter is shown.
  • a diode (gate-controlled diode) 42 having an insulated gate is replaced with an IGBT constituting the upper arm. Used as a freewheeling diode connected in antiparallel.
  • control circuit 46 the gate drive circuit 45, and the delay circuit block 44 control the IGBT 43 and the diode 42 having an insulated gate.
  • the delay circuit block 44 generates the delay timing of the gate of the IGBT 43 and the gate of the diode 42. Then, as shown in the fourth embodiment with reference to FIG. 12, the insulated gate (3: FIG. 1) of the diode 42 is turned off immediately before the IGBT 43 of the pair arm is turned on and the diode 42 reaches the recovery state. It is controlled in the same way.
  • the delay constant circuit (not shown) provided in the delay circuit block 44 is mainly a so-called RC delay circuit composed of a resistor and a capacitor.
  • the gate drive circuit 45 mainly has a function of a level shift circuit that converts the input from the control circuit 46 into input signals of the gates of the IGBT 43 and the diode 42, respectively.
  • FIG. 15A the diode 42 is arranged in the upper arm, the IGBT 43 is arranged in the lower arm, and the inverter circuit is partially extracted and described.
  • FIG. 15B IGBTs are arranged in the upper arm and diodes are arranged in the lower arm, and the above-described drive circuit network is also arranged for these.
  • the control circuit 46 controls the upper arm and the lower arm in an integrated manner, so that the DC power (DC voltage) of the DC power supply 40 is converted into AC power (AC voltage) and an inductive load (for example, AC power (AC voltage) is supplied to a part of the motor 41.
  • a power conversion device such as a low-loss inverter can be provided by a drive device for a semiconductor circuit (semiconductor device) including the control circuit 46, the gate drive circuit 45, and the delay circuit block 44.
  • a power conversion device including any one of the semiconductor devices according to the first to third embodiments will be described.
  • FIG. 16 is a diagram illustrating an example of a circuit configuration of the power conversion device according to the eighth embodiment of the present invention. Note that the three-phase AC motor 48 is not included in the power converter.
  • the upper arm is constituted by an IGBT 43U (switching element) and a diode (gate control type diode) 42U having an insulated gate
  • the lower arm is constituted by an IGBT 43D (switching element) and a diode (gate control type diode) 42D having an insulated gate. And are configured.
  • the pair of the upper arm and the lower arm constitutes a power conversion leg for one phase.
  • the output signals of the delay circuit block 44 (6 in total) are input to the gates of the three IGBTs 43U and the three IGBTs 43D, respectively.
  • a total of six gate drive circuits 45 drive the diodes 42U (three in total), the diodes 42D (three in total), and the delay circuit blocks 44 (total six).
  • control circuit 46 controls the total of six gate drive circuits 45 so that the DC power (DC voltage) of the DC power supply 40 is converted into three-phase AC power (three-phase AC voltage).
  • the three-phase AC motor 48 is supplied.
  • the second P ⁇ -type anode layer 5 is formed by irradiating the first P ⁇ -type anode layer 4 with the lifetime killer, but the irradiated position is a region close to the anode electrode 6.
  • the anode electrode 6 and the second P ⁇ -type anode layer 5 are formed in contact with each other.
  • anode electrode 6 and the second P ⁇ -type anode layer 5 are in metal-semiconductor contact, they are in Schottky contact or ohmic contact.
  • the diode characteristics change, and this structure can be used for applications where this characteristic is desirable.
  • the lifetime killer irradiation causes damage (crystal defects) to the crystal structure of first P ⁇ -type anode layer 4, and the lifetime of carriers is reduced.
  • the method for forming the reduced second P ⁇ -type anode layer 5 has been described.
  • annealing may be performed. Good.
  • This annealing treatment recovers more than necessary crystal defects, and the second P ⁇ -type anode layer 5 needs to be performed to such an extent that the lifetime of the carrier is kept reduced.
  • the annealing process is performed at several hundred degrees Celsius.
  • a first semiconductor layer (N + -type cathode layer) and a second semiconductor layer (N ⁇ -type drift layer) are constituted by N-type semiconductor layers, and a third semiconductor layer (first P ⁇ -type) is formed.
  • the anode layer) and the fourth semiconductor layer (second P ⁇ -type anode layer) are composed of P-type semiconductor layers.
  • the power converter according to the present embodiment is also effective. It is. ⁇ Equipment equipped with diode with insulated gate ⁇ In FIG. 15 or FIG. 16, the example in which the diodes 42, 42U, and 42D having the insulated gate, which is the semiconductor device according to the embodiment of the present invention, are provided in the power conversion device as the inverter has been described.
  • diodes 42, 42U, and 42D having insulating gates which are semiconductor devices according to the embodiment of the present invention, are used as a free-wheeling diode connected in reverse parallel to a switching element (IGBT) of a converter that converts AC power into DC power. You may prepare.
  • IGBT switching element
  • devices such as a booster circuit device and a power factor correction device may include diodes 42, 42U, and 42D having an insulating gate, which is a semiconductor device according to the embodiment of the present invention.

Abstract

The present invention, which addresses the problem of providing a semiconductor device that exhibits both low conduction loss and low recovery loss, a method for producing said semiconductor device, and a power conversion device that uses said semiconductor device, is characterized by being provided with: a first semiconductor layer 8 of a first conductivity type; a second semiconductor layer 7 of the first conductivity type, said layer 7 being adjacent to the first semiconductor layer 8 and having a lower concentration of impurities than the first semiconductor layer 8; a third semiconductor layer 4 of a second conductivity type, said layer 4 being adjacent to the second semiconductor layer 7; a first electrode 6 that is electrically connected to the third semiconductor layer 4; a second electrode 9 that is electrically connected to the first semiconductor layer 8; a fourth semiconductor layer 5 of the second conductivity type, said layer 5 being included in the third semiconductor layer 4 and having a reduced carrier lifetime compared to the third semiconductor layer 4; and an insulated gate 3 that is in contact with the third semiconductor layer.

Description

半導体装置、その製造方法、及びそれを用いた電力変換装置Semiconductor device, manufacturing method thereof, and power conversion device using the same
　本発明は、半導体装置、その製造方法、及びそれを用いた電力変換装置に関する。例えば、エアコンや電子レンジなどの小電力機器から、鉄道や製鉄所のインバータなどの大電力機器まで広く使われているものに好適な半導体装置、その製造方法、及びそれを用いた電力変換装置に関する。 The present invention relates to a semiconductor device, a manufacturing method thereof, and a power conversion device using the same. For example, the present invention relates to a semiconductor device suitable for a wide range of use from a low-power device such as an air conditioner or a microwave oven to a high-power device such as an inverter of a railway or a steel mill, a manufacturing method thereof, and a power converter using the same .
　地球温暖化が世界共通の重要な緊急課題となっており、その対策の一つとしてパワーエレクトロニクス技術の貢献期待度が高まっている。例えば、電力変換機能を司るインバータの高効率化に向けて、それを構成するパワースイッチング機能を果たすＩＧＢＴ(Insulated Gate Bipolar Transistor)と、整流機能を果たすダイオードを主としたパワー半導体デバイスの低消費電力化が求められている。 Global warming has become an important urgent issue common to the world, and the contribution expectation of power electronics technology is increasing as one of the countermeasures. For example, in order to increase the efficiency of inverters that control power conversion functions, low power consumption of power semiconductor devices mainly composed of IGBTs (Insulated Gate Bipolar Transistors) that perform power switching functions and diodes that perform rectification functions Is required.
　直流電力を交流電力に変換するインバータでは、詳細を後記するように、スイッチング時の損失であるＩＧＢＴから発生するターンオン損失とターンオフ損失、ダイオードから発生する導通損失とリカバリー損失を低減する必要がある。 In an inverter that converts DC power into AC power, as will be described in detail later, it is necessary to reduce the turn-on loss and turn-off loss generated from the IGBT, which is the loss at the time of switching, and the conduction loss and recovery loss generated from the diode.
　例えば、特許文献１には、「［課題］低いオン抵抗およびソフトリカバリを同時に実現できる電力用ダイオードを提供すること。［解決手段］Ｎ- 型ベース層１の表面にＰ型エミッタ層２、裏面にＮ+ 型エミッタ層を形成し、さらにＰ型エミッタ層２の表面にＮ- 型ベース層１に達する深さのトレンチ溝を形成し、このトレンチ溝内にゲート絶縁膜３を介してゲート電極４を埋め込み形成する。（［要約］を参照）」と記載され、ダイオードに関わる技術が開示されている。 For example, Patent Document 1 provides “[Problem] To provide a power diode capable of simultaneously realizing low on-resistance and soft recovery. [Solution] P-type emitter layer 2 on the surface of N − -type base layer 1, back surface An N + -type emitter layer is formed on the P-type emitter layer 2 and a trench groove having a depth reaching the N − -type base layer 1 is formed on the surface of the P-type emitter layer 2, and a gate electrode is formed in the trench groove via a gate insulating film 3. 4 is embedded (see [Summary]), and a technique relating to a diode is disclosed.
特開平１０－１６３４６９号公報JP-A-10-163469
　しかしながら、前記の特許文献１に開示された技術には、次のような課題がある。 However, the technique disclosed in Patent Document 1 has the following problems.
　特許文献１に開示された技術のダイオードでは、詳細を後記するように、絶縁ゲートを有するダイオードのゲート電圧印加時においては、ダイオードの順方向電圧が下げられ、導通損失の低減効果はあるものの、ゲート電圧を印加しない状態でのホール注入量が上昇して、ゲート電圧印加時と同様に順方向電圧が低減してしまい、本状態でのリカバリー損失が上昇してしまう副作用が生ずるという課題がある。 In the diode of the technique disclosed in Patent Document 1, as will be described later in detail, when the gate voltage of the diode having an insulated gate is applied, the forward voltage of the diode is lowered, and there is an effect of reducing conduction loss. When the gate voltage is not applied, the amount of hole injection is increased, the forward voltage is reduced in the same manner as when the gate voltage is applied, and there is a problem that the recovery loss in this state is increased. .
　本発明は、前記した課題に鑑みて創案されたものであり、低導通損失性能と低リカバリー損失性能を両立する半導体装置、その駆動装置、及びその製造方法を提供することを課題とする。 The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a semiconductor device that has both low conduction loss performance and low recovery loss performance, a driving device thereof, and a manufacturing method thereof.
　前記の課題を解決して、本発明の目的を達成するために、以下のように構成した。 In order to solve the above-described problems and achieve the object of the present invention, the following configuration is provided.
　すなわち、本発明の半導体装置は、第１導電型の第１半導体層と、前記第１半導体層に隣接し、前記第１半導体層よりも不純物濃度が低い第１導電型の第２半導体層と、前記第２半導体層に隣接する第２導電型の第３半導体層と、前記第３半導体層と電気的に接続された第１電極と、前記第１半導体層と電気的に接続された第２電極と、前記第３半導体層に含まれ、前記第３半導体層よりもキャリアのライフタイムが低減された第２導電型の第４半導体層と、前記第３半導体層に接する絶縁ゲートと、を備える、ことを特徴とする。 That is, a semiconductor device of the present invention includes a first conductive type first semiconductor layer, a first conductive type second semiconductor layer adjacent to the first semiconductor layer, and having a lower impurity concentration than the first semiconductor layer, A third semiconductor layer of a second conductivity type adjacent to the second semiconductor layer, a first electrode electrically connected to the third semiconductor layer, and a first electrode electrically connected to the first semiconductor layer. Two electrodes, a fourth semiconductor layer of a second conductivity type contained in the third semiconductor layer and having a carrier lifetime reduced as compared with the third semiconductor layer, an insulated gate in contact with the third semiconductor layer, It is characterized by comprising.
　また、その他の手段は、発明を実施するための形態のなかで説明する。 Further, other means will be described in the embodiment for carrying out the invention.
　本発明によれば、低導通損失性能と低リカバリー損失性能を両立する半導体装置、その製造方法、及びそれを用いた電力変換装置を提供することができる。 According to the present invention, it is possible to provide a semiconductor device that achieves both low conduction loss performance and low recovery loss performance, a manufacturing method thereof, and a power conversion device using the same.
本発明の第１実施形態に係る半導体装置の断面構造の例を模式的に示す図であり、（ａ）は、二つのトレンチゲート型の絶縁ゲートの近傍を部分的に表記したものであり、（ｂ）は、トレンチゲート型の絶縁ゲートが複数個、配置されている様子を示すものである。BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows typically the example of the cross-section of the semiconductor device which concerns on 1st Embodiment of this invention, (a) partially represents the vicinity of two trench gate type | mold insulated gates, (B) shows a state in which a plurality of trench gate type insulated gates are arranged. 本発明の第１実施形態に係る半導体装置の絶縁ゲート電極に負電圧を印加し、さらにカソード電極とアノード電極との間に、導通させる順方向電圧が印加された際のホールキャリアの分布を模式的に示す図である。Schematic representation of the distribution of hole carriers when a negative voltage is applied to the insulated gate electrode of the semiconductor device according to the first embodiment of the present invention and a forward voltage is applied between the cathode electrode and the anode electrode. FIG. 本発明の第１実施形態に係る半導体装置の絶縁ゲート電極に印加する電圧をゼロにし、カソード電極とアノード電極との間に、導通させる順方向電圧が印加された際のホールキャリアの分布を模式的に示す図である。The distribution of hole carriers when a voltage applied to the insulated gate electrode of the semiconductor device according to the first embodiment of the present invention is zeroed and a forward voltage is applied between the cathode electrode and the anode electrode is schematically shown. FIG. 本発明の第１実施形態に係る半導体装置のダイオードの順方向特性の例を示す図である。It is a figure which shows the example of the forward direction characteristic of the diode of the semiconductor device which concerns on 1st Embodiment of this invention. 本発明の第１実施形態に係る半導体装置のダイオードのゲートの入力信号、及び対アームのＩＧＢＴのゲートの入力信号の例を示す図である。It is a figure which shows the example of the input signal of the gate of the diode of the semiconductor device which concerns on 1st Embodiment of this invention, and the input signal of the gate of IGBT of a pair arm. 本発明の第１実施形態に係る半導体装置のダイオードに図５の入力信号による制御を適用した場合における、ダイオードのアノード電流と、カソード・アノード間電圧の過渡特性の例を示す図である。FIG. 6 is a diagram illustrating an example of a transient characteristic of an anode current of a diode and a cathode-anode voltage when the control by the input signal of FIG. 5 is applied to the diode of the semiconductor device according to the first embodiment of the present invention. 本発明の第２実施形態に係る半導体装置の断面構造の例を模式的に示す図である。It is a figure which shows typically the example of the cross-section of the semiconductor device which concerns on 2nd Embodiment of this invention. 本発明の第２実施形態に係る半導体装置のダイオードの絶縁ゲート電極に印加する電圧をゼロにした場合における、ホールと電子のキャリアプロファイルを模式的に示す図である。It is a figure which shows typically the carrier profile of a hole and an electron when the voltage applied to the insulated gate electrode of the diode of the semiconductor device which concerns on 2nd Embodiment of this invention is made into zero. 本発明の第３実施形態に係る半導体装置の断面構造の例を模式的に示す図である。It is a figure which shows typically the example of the cross-section of the semiconductor device which concerns on 3rd Embodiment of this invention. 本発明の第１実施形態に係る半導体装置のダイオードのリカバリー電流の経路を模式的に示す図である。It is a figure which shows typically the path | route of the recovery current of the diode of the semiconductor device which concerns on 1st Embodiment of this invention. 本発明の第３実施形態に係る半導体装置のダイオードのリカバリー電流の経路を模式的に示す図である。It is a figure which shows typically the path | route of the recovery current of the diode of the semiconductor device which concerns on 3rd Embodiment of this invention. 本発明の第４実施形態における絶縁ゲート型の縦型半導体装置を駆動する駆動ゲート信号を示す図である。It is a figure which shows the drive gate signal which drives the insulated gate vertical semiconductor device in 4th Embodiment of this invention. 本発明の第５実施形態に係る半導体装置の製造方法の例を示す図であり、（ａ）は第２のＰ－型アノード層が形成される前の半導体装置の状態を表し、（ｂ）は第２のＰ－型アノード層が形成された後の半導体装置の状態を表している。FIG. 10 is a diagram showing an example of a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention, where (a) shows the state of the semiconductor device before the second P − -type anode layer is formed, and (b) Represents the state of the semiconductor device after the second P − -type anode layer is formed. 本発明の第６実施形態に係る半導体装置の製造方法の例を示す図であり、（ａ）は第２のＰ－型アノード層が形成される前の半導体装置の状態を表し、（ｂ）は第２のＰ－型アノード層が形成された後の半導体装置の状態を表している。It is a figure which shows the example of the manufacturing method of the semiconductor device which concerns on 6th Embodiment of this invention, (a) represents the state of the semiconductor device before a 2nd P − type anode layer is formed, (b) Represents the state of the semiconductor device after the second P − -type anode layer is formed. 本発明の第７実施形態に係る半導体回路の駆動装置の回路構成の例を示す図であり、（ａ）は特性評価用の回路構成を示し、（ｂ）はインバータとして用いる回路の部分構成を示している。It is a figure which shows the example of the circuit structure of the drive device of the semiconductor circuit which concerns on 7th Embodiment of this invention, (a) shows the circuit structure for characteristic evaluation, (b) shows the partial structure of the circuit used as an inverter. Show. 本発明の第８実施形態に係る電力変換装置の回路構成の例を示す図である。It is a figure which shows the example of the circuit structure of the power converter device which concerns on 8th Embodiment of this invention. 比較例１における複数のＩＧＢＴと、このＩＧＢＴにそれぞれ逆並列に接続された複数のダイオードを備えて構成されるインバータの部分回路の例を示す図である。It is a figure which shows the example of the partial circuit of the inverter comprised including the some IGBT in the comparative example 1, and the some diode respectively connected to this IGBT in antiparallel. 比較例２による絶縁ゲートを有するダイオードの断面構造の例を示す図である。6 is a diagram illustrating an example of a cross-sectional structure of a diode having an insulated gate according to Comparative Example 2. FIG. 比較例２による絶縁ゲートを有するダイオードの絶縁ゲート電極に負電圧を印加し、さらにカソード電極とアノード電極との間に、順方向電圧を印加した際の、ホールキャリアの分布を模式的に示す図である。The figure which shows typically distribution of a hole carrier when a negative voltage is applied to the insulated gate electrode of the diode which has the insulated gate by the comparative example 2, and also a forward voltage is applied between a cathode electrode and an anode electrode. It is. 比較例２による絶縁ゲートを有するダイオードの絶縁ゲート電極に印加する電圧をゼロにした場合のホールキャリアの分布を模式的に示す図である。It is a figure which shows typically distribution of a hole carrier when the voltage applied to the insulated gate electrode of the diode which has the insulated gate by the comparative example 2 is made into zero. 比較例２による絶縁ゲートを有するダイオードのアノード電極とＰ－型アノード層の中心部断面における、エネルギーバンドを示す図である。FIG. 10 is a diagram showing energy bands in a cross section of a central portion of an anode electrode and a P − type anode layer of a diode having an insulated gate according to Comparative Example 2. 比較例２による絶縁ゲートを有するダイオードのＰ－型アノード層のＰ型不純物濃度が低い場合と高い場合とにおいて、ゲートに負電圧を印加した時と、印加しない時のダイオードの順方向特性を示す図である。The forward characteristics of the diode when the negative voltage is applied to the gate and when the P-type impurity concentration of the P − -type anode layer of the diode having the insulated gate according to Comparative Example 2 is low and high are shown. FIG.
　以下、本発明を実施するための形態（以下においては「実施形態」と表記する）を、適宜、図面を参照して説明する。
≪第１実施形態：その１≫
　本発明の第１実施形態の絶縁ゲート型（ゲート制御型）の縦型半導体装置（半導体装置）１００を、図１を参照して説明する。 Hereinafter, modes for carrying out the present invention (hereinafter referred to as “embodiments”) will be described with reference to the drawings as appropriate.
<< First Embodiment: Part 1 >>
An insulated gate type (gate control type) vertical semiconductor device (semiconductor device) 100 according to a first embodiment of the present invention will be described with reference to FIG.
　図１は、本発明の第１実施形態に係る半導体装置１００の断面構造の例を模式的に示す図であり、（ａ）は、二つのトレンチゲート型の絶縁ゲート３の近傍を部分的に表記したものであり、（ｂ）は、トレンチゲート型の絶縁ゲート３が複数個、配置されている様子を示すものである。 FIG. 1 is a diagram schematically showing an example of a cross-sectional structure of a semiconductor device 100 according to the first embodiment of the present invention. FIG. 1 (a) is a partial view of the vicinity of two trench gate type insulated gates 3. (B) shows a state in which a plurality of trench gate type insulated gates 3 are arranged.
　図１（ａ）において、半導体装置１００は、トレンチゲート制御型のダイオードである。すなわち、ダイオードを形成するアノード電極６とカソード電極９との間に、トレンチゲート型の絶縁ゲート３が備えられ、絶縁ゲート３の絶縁ゲート電極１に印加する電圧によって、半導体装置１００のダイオード特性が制御される。 1A, the semiconductor device 100 is a trench gate control type diode. That is, the trench gate type insulated gate 3 is provided between the anode electrode 6 and the cathode electrode 9 forming the diode, and the diode characteristics of the semiconductor device 100 are changed by the voltage applied to the insulated gate electrode 1 of the insulated gate 3. Be controlled.
　また、半導体装置１００における本発明の第１実施形態としての特徴は、第１のＰ－型アノード層４の中にキャリアのライフタイムが低減された第２のＰ－型アノード層５が備えられていることである。 Further, the semiconductor device 100 is characterized in that the second P − -type anode layer 5 having a reduced carrier lifetime is provided in the first P − -type anode layer 4 in the first embodiment of the present invention. It is that.
　図１の構造による半導体装置１００（トレンチゲート制御型のダイオード）の特性や効果をわかりやすく説明するために、まず、比較例１および比較例２として従来の構造例や特性を先に説明し、その後に、≪第１実施形態：その２≫として、半導体装置１００の構造と特性を詳細に再度、説明する。
≪比較例１≫
　比較例１として、一般的なダイオード（ダイオード特性を制御するゲート電極構造を有していない）をＩＧＢＴに逆並列接続して、複数のＩＧＢＴを用いてインバータ（直流電力を交流電力に変換）の構成例を説明する。 In order to explain the characteristics and effects of the semiconductor device 100 (trench gate control type diode) having the structure of FIG. 1 in an easy-to-understand manner, first, conventional structural examples and characteristics will be described first as Comparative Example 1 and Comparative Example 2. Thereafter, the structure and characteristics of the semiconductor device 100 will be described again in detail as << first embodiment: part 2 >>.
≪Comparative example 1≫
As Comparative Example 1, a general diode (not having a gate electrode structure for controlling the diode characteristics) is connected in reverse parallel to the IGBT, and a plurality of IGBTs are used to convert an inverter (converting DC power into AC power). A configuration example will be described.
　図１７は、比較例１における複数のＩＧＢＴ４３と、このＩＧＢＴ４３にそれぞれ逆並列に接続された複数のダイオード４７を備えて構成されるインバータ（直流電力－交流電力変換装置）の部分回路の例を示す図である。 FIG. 17 shows an example of a partial circuit of an inverter (DC power-AC power converter) configured to include a plurality of IGBTs 43 in Comparative Example 1 and a plurality of diodes 47 respectively connected in reverse parallel to the IGBTs 43. FIG.
　図１７において、前記したように、ＩＧＢＴ４３には、逆並列にダイオード４７が接続されている。二つの直列接続されたＩＧＢＴ４３によって上アームと下アームが構成され、それぞれのゲート駆動回路４５で、駆動されて、高速にターンオン、ターンオフを繰り返して、直流電源４０の直流電力（直流電圧）を交流電力（交流電圧）に変換するように、制御される。 In FIG. 17, as described above, the diode 47 is connected to the IGBT 43 in antiparallel. The upper arm and the lower arm are constituted by two IGBTs 43 connected in series. The upper arm and the lower arm are driven by the respective gate drive circuits 45, and are turned on and off at high speeds. The DC power (DC voltage) of the DC power supply 40 is exchanged. It is controlled to convert it into electric power (alternating voltage).
　前記の二つのＩＧＢＴ４３によって構成される上アームと下アームの対の組は、合計で３組あって、これら複数のＩＧＢＴ４３を統合的に制御する制御回路４６によって、それぞれＵ相、Ｖ相、Ｗ相の交流電力（交流電圧）を生成する。 There are a total of three pairs of upper and lower arms configured by the two IGBTs 43. The control circuit 46 that controls the plurality of IGBTs 43 in an integrated manner controls the U phase, the V phase, and the W phase, respectively. Generate AC power (AC voltage) for the phase.
　生成されたＵ相、Ｖ相、Ｗ相の三相交流電力（三相交流電圧）は、三相交流モータ（誘導性負荷）４８に印加、供給されて、三相交流モータ４８を駆動する。 The generated U-phase, V-phase, and W-phase three-phase AC power (three-phase AC voltage) is applied to and supplied to a three-phase AC motor (inductive load) 48 to drive the three-phase AC motor 48.
　以上の過程において、ＩＧＢＴ４３とダイオード４７は、導通時に導通損失を発生し、スイッチング時にスイッチング損失を発生する。 In the above process, the IGBT 43 and the diode 47 generate conduction loss when conducting, and generate switching loss when switching.
　そのため、インバータを小型化・高効率化するには、ＩＧＢＴ４３とダイオード４７の導通損失とスイッチング損失を低減する必要がある。 Therefore, in order to reduce the size and increase the efficiency of the inverter, it is necessary to reduce the conduction loss and switching loss between the IGBT 43 and the diode 47.
　なお、スイッチング損失は、ＩＧＢＴ４３から発生するターンオン損失とターンオフ損失と、ＩＧＢＴのターンオン時にダイオード４７から発生するリカバリー損失から構成される。 The switching loss includes a turn-on loss and a turn-off loss generated from the IGBT 43 and a recovery loss generated from the diode 47 when the IGBT is turned on.
　比較例１の場合において、これらのターンオン損失とターンオフ損失とリカバリー損失からなるスイッチング損失は、発熱や電力効率の観点から無視できない課題である。
≪比較例２≫
　比較例２として、従来技術（例えば引用文献１）による絶縁ゲートを有するダイオード（ゲート制御型ダイオード）について、説明する。 In the case of the comparative example 1, the switching loss including the turn-on loss, the turn-off loss, and the recovery loss is a problem that cannot be ignored from the viewpoint of heat generation and power efficiency.
≪Comparative example 2≫
As Comparative Example 2, a diode (gate-controlled diode) having an insulated gate according to a conventional technique (for example, cited document 1) will be described.
　図１５（ａ）、（ｂ）の詳細は後記するが、図１５（ａ）は特性評価用の回路構成を示し、図１５（ｂ）はインバータとして用いる回路の部分構成を示している。 Although details of FIGS. 15A and 15B will be described later, FIG. 15A shows a circuit configuration for characteristic evaluation, and FIG. 15B shows a partial configuration of a circuit used as an inverter.
　図１５（ａ）に示すように、例えば下アームを構成するＩＧＢＴ４３に対して、絶縁ゲートを有するダイオード４２は、上アームを構成するＩＧＢＴ（図１５（ａ）では不図示、図１５（ｂ）の上アームのＩＧＢＴ４３）に逆並列に接続される還流ダイオードとして用いられる。 As shown in FIG. 15A, for example, with respect to the IGBT 43 that constitutes the lower arm, the diode 42 having an insulated gate is different from the IGBT that constitutes the upper arm (not shown in FIG. 15A, FIG. 15B). Used as a free-wheeling diode connected in reverse parallel to the upper arm IGBT 43).
　そして、制御回路４６およびゲート駆動回路４５によって、ＩＧＢＴ４３と絶縁ゲートを有するダイオード４２は、制御される。 Then, the control circuit 46 and the gate drive circuit 45 control the IGBT 43 and the diode 42 having an insulated gate.
　なお、遅延回路ブロック４４は、ＩＧＢＴ４３のオンオフに遅延を与えるものである。 The delay circuit block 44 gives a delay to the on / off of the IGBT 43.
　また、制御回路４６が上アームと下アームを制御することによって、直流電源４０の直流電力（直流電圧）は、交流電力（交流電圧）に変換され、誘導性負荷（例えばモータの一部）４１に交流電力（交流電圧）が供給される。 Further, the control circuit 46 controls the upper arm and the lower arm, whereby the DC power (DC voltage) of the DC power supply 40 is converted into AC power (AC voltage) and an inductive load (for example, a part of the motor) 41. Is supplied with AC power (AC voltage).
　なお、図１５（ａ）、（ｂ）の回路構成は、本発明の実施形態においても用いられるので、詳細については後記する。 Note that the circuit configurations of FIGS. 15A and 15B are also used in the embodiment of the present invention, and the details will be described later.
　絶縁ゲートを有するダイオード４２は、トレンチ溝内部に設けられる埋め込み絶縁ゲートを備えている。導通時に絶縁ゲートに負電圧を印加し、ホール蓄積層を形成することで、順方向電圧を低減する。一方、リカバリー時にはゲート電圧をゼロにすることにより、アノードからのホール注入を抑制して、リカバリー損失を低減する。 The diode 42 having an insulated gate has a buried insulated gate provided inside the trench. A forward voltage is reduced by applying a negative voltage to the insulated gate during conduction to form a hole accumulation layer. On the other hand, by making the gate voltage zero during recovery, hole injection from the anode is suppressed and recovery loss is reduced.
　このように、比較例２における絶縁ゲートを有するダイオード４２は、アノードからのホール注入効率を絶縁ゲートに印加する電圧により制御できるので、導通損失に係る順方向電圧とリカバリー損失のトレードオフを改善することができる。すなわち、比較例２は、比較例１よりも、リカバリー損失の低減については、改善されている。 As described above, the diode 42 having the insulated gate in the comparative example 2 can control the hole injection efficiency from the anode by the voltage applied to the insulated gate, thereby improving the trade-off between the forward voltage related to the conduction loss and the recovery loss. be able to. That is, the comparative example 2 is improved with respect to the reduction of the recovery loss than the comparative example 1.
　しかしながら、比較例２には、次のような課題があることを、本願の発明者は見出した。 However, the inventors of the present application have found that Comparative Example 2 has the following problems.
　そのため、比較例２について、詳細に説明する。 Therefore, Comparative Example 2 will be described in detail.
　比較例２の課題を説明するにあたって、「（比較例２による）絶縁ゲートを有するダイオードの断面構造」、「順方向電圧を印加した際のホールキャリアの分布」、「絶縁ゲート電極に印加する電圧をゼロにした場合のホールキャリアの分布」、「中心部断面におけるエネルギーバンド図」、「Ｐ型不純物濃度が低い場合、高い場合において、ゲートに負電圧を印加した時と、印加しない時の、順方向特性」、について順に説明する。 In explaining the problem of Comparative Example 2, “a cross-sectional structure of a diode having an insulated gate (according to Comparative Example 2)”, “a distribution of hole carriers when a forward voltage is applied”, “a voltage applied to an insulated gate electrode” Distribution of hole carriers when zero is set to zero, “energy band diagram in the central cross section”, “when the P-type impurity concentration is low and high, when a negative voltage is applied to the gate and when not applied, The “forward characteristics” will be described in order.
　そして、比較例２はスイッチング損失の低減の観点において、比較例１よりも改善されるものの、比較例２においても、低導通損失と低リカバリー損失の両立が困難であることを説明する。
《比較例２による絶縁ゲートを有するダイオードの断面構造》
　図１８は、比較例２による絶縁ゲートを有するダイオードの断面構造の例を示す図である。 Then, although Comparative Example 2 is improved from Comparative Example 1 in terms of reducing switching loss, it will be described that it is difficult to achieve both low conduction loss and low recovery loss in Comparative Example 2 as well.
<< Cross-sectional structure of a diode having an insulated gate according to Comparative Example 2 >>
FIG. 18 is a diagram showing an example of a cross-sectional structure of a diode having an insulated gate according to Comparative Example 2.
　図１８において、Ｐ型の不純物を含む層から成るＰ－型アノード層（アノード領域）４とアノード電極６が接触し、Ｐ－型アノード層（アノード領域）４に接するゲート絶縁膜（絶縁酸化膜）２と絶縁ゲート電極１から成る絶縁ゲート３を配置して形成されている。 In Figure 18, P comprises a layer containing a P-type impurity - -type anode layer (anode region) 4 and contacts the anode electrode 6, P - -type anode layer (anode region) gate insulating film in contact with the 4 (insulating oxide film ) 2 and an insulated gate 3 composed of an insulated gate electrode 1 is disposed.
　また、Ｐ－型アノード層（アノード領域）４の下側（紙面の下側に相当）に、高耐圧性能を確保するため、低濃度のＮ型不純物を含む層から成るＮ－型ドリフト層７と、カソード電極９と電気的に接続するための高濃度不純物を含む層から成るＮ＋型カソード層８が配置されている。
《順方向電圧を印加した際のホールキャリアの分布》
　図１９は、比較例２による絶縁ゲートを有するダイオードの絶縁ゲート電極１に負電圧（１１）を印加し、さらにカソード電極９とアノード電極６との間に、順方向電圧（１２）を印加した際の、ホールキャリアの分布を模式的に示す図である。 In addition, an N − type drift layer 7 made of a layer containing a low concentration of N type impurities is provided below the P − type anode layer (anode region) 4 (corresponding to the lower side of the drawing) in order to ensure high breakdown voltage performance. In addition, an N + type cathode layer 8 made of a layer containing a high concentration impurity for electrical connection with the cathode electrode 9 is disposed.
《Hole carrier distribution when forward voltage is applied》
In FIG. 19, a negative voltage (11) was applied to the insulated gate electrode 1 of the diode having an insulated gate according to Comparative Example 2, and a forward voltage (12) was applied between the cathode electrode 9 and the anode electrode 6. It is a figure which shows typically distribution of the hole carrier at the time.
　図１９に示すように、Ｐ－型アノード層４内部のゲート絶縁膜２に接する領域において、印加された負電圧による電界によって、ホールキャリア（１４）が蓄積する。 As shown in FIG. 19, hole carriers (14) accumulate in the region in contact with the gate insulating film 2 inside the P − -type anode layer 4 due to the electric field due to the applied negative voltage.
　さらに印加された順方向電圧（１２）によって、蓄積されたホールキャリア（１４）は、Ｎ－型ドリフト層７に注入される。このＮ－型ドリフト層７に注入されたホールキャリアをホールキャリア（１５）と表記する。 Furthermore, the accumulated hole carriers (14) are injected into the N − -type drift layer 7 by the applied forward voltage (12). The hole carriers injected into the N − type drift layer 7 are denoted as hole carriers (15).
　このホールキャリア（１５）と、カソード電極９から注入される電子（１６）が再結合することによって、Ｎ－型ドリフト層７の内部で伝導度変調が生じ、ダイオードの導通を維持するに必要なダイオードの順方向電圧が低減される。
《絶縁ゲート電極に印加する電圧をゼロにした場合のホールキャリアの分布》
　図２０は、比較例２による絶縁ゲートを有するダイオードの絶縁ゲート電極１に印加する電圧をゼロにした場合の、ホールキャリアの分布を模式的に示す図である。 This hole carrier (15) and electrons (16) injected from the cathode electrode 9 are recombined, whereby conductivity modulation occurs inside the N − -type drift layer 7 and is necessary for maintaining the conduction of the diode. The forward voltage of the diode is reduced.
<< Hole carrier distribution when voltage applied to insulated gate electrode is zero >>
FIG. 20 is a diagram schematically illustrating the distribution of hole carriers when the voltage applied to the insulated gate electrode 1 of the diode having the insulated gate according to Comparative Example 2 is zero.
　図２０において、絶縁ゲート電極１の電圧がゼロのため、Ｐ－型アノード層４内部のゲート絶縁膜２に接する領域において、ホールキャリアの蓄積層が消失し、Ｐ－型アノード層４内部のホールキャリア濃度が大幅に低減する。 In Figure 20, the voltage of the insulated gate electrode 1 is zero, P - -type in the anode layer 4 region in contact with the gate insulating film 2 in the accumulation layer of hole carriers is lost, P - -type anode layer 4 inside the hole The carrier concentration is greatly reduced.
　このホールキャリア濃度の低減によって、Ｎ－型ドリフト層７内部の伝導度変調効果が失われ、導通を維持するに必要なダイオードの順方向電圧が上昇する。 By reducing the hole carrier concentration, the conductivity modulation effect inside the N − -type drift layer 7 is lost, and the forward voltage of the diode required to maintain conduction increases.
　この状態において、カソード電極９とアノード電極６との間に、正の高電圧が印加されると、内部電荷が、カソード電極９、アノード電極６に戻ることで生ずるリカバリー電流が無くなり、リカバリー損失を大幅に低減することができる。 In this state, when a positive high voltage is applied between the cathode electrode 9 and the anode electrode 6, the recovery current generated when the internal charges return to the cathode electrode 9 and the anode electrode 6 disappears, and recovery loss is reduced. It can be greatly reduced.
　以上の様に、絶縁ゲート電極１に印加する電圧を制御することで、Ｐ－型アノード層４からＮ－型ドリフト層７に注入するホールキャリア（１５）の濃度、即ち伝導度変調の起こり易さを変調することができ、導通損失とリカバリー損失の両損失を共に下げることが可能となり、高効率なダイオードを実現することが可能となる。 As described above, by controlling the voltage applied to the insulated gate electrode 1, the concentration of hole carriers (15) injected from the P − -type anode layer 4 into the N − -type drift layer 7, that is, conductivity modulation is likely to occur. Therefore, both the conduction loss and the recovery loss can be reduced, and a highly efficient diode can be realized.
　ここで、低損失性能を実現するにおいて、Ｐ－型アノード層４の不純物濃度を上昇し、ゲート電圧を印加した際の絶縁ゲート３の界面に蓄積するホールキャリア濃度を上昇し、導通損失を下げることが重要な構造設計項目となる。 Here, in realizing low loss performance, the impurity concentration of the P − -type anode layer 4 is increased, the concentration of hole carriers accumulated at the interface of the insulated gate 3 when a gate voltage is applied is increased, and the conduction loss is decreased. Is an important structural design item.
　ただし、ここで、Ｐ型不純物濃度を上昇させた場合、ゲート電圧印加時での順方向電圧が下げられる一方で、ゲート電圧を印加しない状態でのホール注入量が上昇してしまう副作用が発生する。 However, when the P-type impurity concentration is increased, the forward voltage when the gate voltage is applied is lowered, while the side effect of increasing the hole injection amount when the gate voltage is not applied occurs. .
　この副作用の現象を、次に、図２１と図２２を参照して説明する。
《中心部断面におけるエネルギーバンド図》
　図２１は、比較例２による絶縁ゲートを有するダイオードのアノード電極６とＰ－型アノード層４の中心部断面における、エネルギーバンドを示す図である。 This side effect phenomenon will now be described with reference to FIGS.
《Energy band diagram in the central section》
FIG. 21 is a diagram showing an energy band in the cross section of the central portion of the anode electrode 6 and the P − -type anode layer 4 of the diode having an insulated gate according to Comparative Example 2.
　図２１において、横軸は、アノード電極６とＰ－型アノード層４との界面からの「深さ」であり、縦軸は、「エネルギー（エネルギー準位）（ｅＶ）」を示している。 In FIG. 21, the horizontal axis represents “depth” from the interface between the anode electrode 6 and the P − -type anode layer 4, and the vertical axis represents “energy (energy level) (eV)”.
　また、特性線５１は、アノード電極のエネルギー準位を示している。特性線５２は、アノードＰ－層濃度が高い場合の価電子帯のエネルギー準位を示している。特性線５３は、アノードＰ－層濃度が低い場合の価電子帯のエネルギー準位を示している。特性線５４は、アノードＰ－層濃度が高い場合の伝導帯のエネルギー準位を示している。特性線５５は、アノードＰ－層濃度が低い場合の伝導帯のエネルギー準位を示している。 The characteristic line 51 indicates the energy level of the anode electrode. The characteristic line 52 shows the energy level of the valence band when the anode P − layer concentration is high. The characteristic line 53 shows the energy level of the valence band when the anode P − layer concentration is low. The characteristic line 54 shows the energy level of the conduction band when the anode P − layer concentration is high. The characteristic line 55 shows the energy level of the conduction band when the anode P − layer concentration is low.
　また、矢印５０は、アノード電極とアノードＰ－層の境界面（界面）を表している。矢印５６は、アノードＰ－層濃度の上昇に伴うホール注入障壁の低下を示している。矢印５７は、アノード電極領域を示している。矢印５８は、アノードＰ－層領域を示している。 An arrow 50 represents the boundary surface (interface) between the anode electrode and the anode P − layer. Arrow 56 indicates a decrease in the hole injection barrier with increasing anode P − layer concentration. An arrow 57 indicates the anode electrode region. Arrow 58 indicates the anode P − layer region.
　Ｐ－型アノード層４のＰ型層の濃度が上昇することにより、Ｐ－型アノード層４の価電子帯のエネルギー準位（５２）がアノード電極６とＰ－型アノード層４の界面（５０）付近において上昇し、アノード電極６からＰ－型アノード層４へのホールの注入障壁が低下（５６）する。 P - by the concentration of P-type layer type anode layer 4 increases, P - -type energy level (52) of the valence band of the anode layer 4 anode electrode 6 and the P - interface type anode layer 4 (50 ) Increases in the vicinity, and the hole injection barrier from the anode electrode 6 to the P − -type anode layer 4 decreases (56).
　すなわち、ゲート電圧を印加しない状態においても、カソード・アノード間に順方向電圧が印加されると、ホールが注入し易い状態が生ずる。
《Ｐ型不純物濃度が低い場合と高い場合とにおいて、ゲートに負電圧を印加した時と、印加しない時の順方向特性》
　図２２は、比較例２による絶縁ゲートを有するダイオードのＰ－型アノード層４のＰ型不純物濃度が低い場合と高い場合とにおいて、ゲートに負電圧を印加した時と、印加しない時の、ダイオードの順方向特性を示す図である。 That is, even when no gate voltage is applied, if a forward voltage is applied between the cathode and the anode, a state in which holes are easily injected occurs.
<< Forward characteristics when a negative voltage is applied to the gate and when the P-type impurity concentration is low and when it is not applied >>
FIG. 22 shows the diode when the negative voltage is applied to the gate and when the P-type impurity concentration of the P − -type anode layer 4 of the diode having the insulated gate according to Comparative Example 2 is low and high. It is a figure which shows the forward direction characteristic.
　図２２において、横軸は「順方向電圧、ＶＦ（Ｖ）」であり、縦軸は「順方向電流密度、ＪＦ（Ａ／ｃｍ２）」である。 In FIG. 22, the horizontal axis represents “forward voltage, VF (V)”, and the vertical axis represents “forward current density, JF (A / cm 2 )”.
　また、特性線５９は、Ｐ－型アノード層４の濃度が低い場合のゲート・アノード間に負バイアスを印加した際のダイオードの順方向特性である。 A characteristic line 59 is a forward characteristic of the diode when a negative bias is applied between the gate and the anode when the concentration of the P − -type anode layer 4 is low.
　特性線６０は、Ｐ－型アノード層４の濃度が低い場合のゲート・アノード間がゼロバイアス時のダイオードの順方向特性である。 A characteristic line 60 is a forward characteristic of the diode when the gate-anode gap is zero bias when the concentration of the P − -type anode layer 4 is low.
　特性線６１は、Ｐ－型アノード層４の濃度が高い場合のゲート・アノード間に負バイアスを印加した際のダイオードの順方向特性である。 A characteristic line 61 is a forward characteristic of the diode when a negative bias is applied between the gate and the anode when the concentration of the P − -type anode layer 4 is high.
　特性線６２は、Ｐ－型アノード層４の濃度が高い場合のゲート・アノード間がゼロバイアス時のダイオードの順方向特性である。 The characteristic line 62 is the forward characteristic of the diode when the gate-anode gap is zero bias when the concentration of the P − -type anode layer 4 is high.
　図２２における特性線５９（濃度が低い）と特性線６１（濃度が高い）とを比較することによって、共にゲート・アノード間に負バイアス（負電圧）でありながら、Ｐ型不純物濃度を高くすることで、ダイオードの順方向電圧が低下していることが分かる。すなわち、導通損失の低減効果を確認できる。 By comparing the characteristic line 59 (concentration is low) and the characteristic line 61 (concentration is high) in FIG. 22, the P-type impurity concentration is increased while the gate and anode are both negatively biased (negative voltage). This shows that the forward voltage of the diode is reduced. That is, the effect of reducing conduction loss can be confirmed.
　一方で、図２２における特性線６０（濃度が低い）と特性線６２（濃度が高い）とを比較することによって、共にゲート・アノード間に負バイアス（負電圧）を印加しないゼロバイアス（ゼロ電圧）時の順方向特性に着目すると、Ｐ型不純物濃度が上昇（高く）することで、負電圧印加時と同様に、大きく順方向電圧が低減してしまい、本状態でのリカバリー損失が上昇してしまう副作用が生ずることを示している。
＜比較例２における低導通損失と低リカバリー損失の両立の実現困難について＞
　すなわち、Ｐ型不純物濃度を上昇して、導通損失を下げようとすると、ゲート電圧（ゲート・アノード間電圧）によるホール注入の制御性が失われ、ゲート電圧によるＰ－型アノード層４（アノード領域）のホールキャリア濃度を制御することで低導通損失と低リカバリー損失を両立させる本来の構造コンセプトが実現困難であることを示している。
≪第１実施形態：その２≫
　以上の「ゲート電圧によるホール注入量の制御性を向上し、低導通損失性能と低リカバリー損失性能を両立する」という課題を踏まえて、本発明の第１実施形態について、再度、詳細に説明する。
《半導体装置１００の断面構造》
　前記したように、図１は、本発明の第１実施形態に係る半導体装置１００の断面構造を示す図であり、（ａ）は、二つのトレンチゲート型の絶縁ゲート３の近傍を部分的に表記したものであり、（ｂ）は、トレンチゲート型の絶縁ゲート３が複数個、配置されている様子を示すものである。 On the other hand, by comparing the characteristic line 60 (low density) and the characteristic line 62 (high density) in FIG. 22, a zero bias (zero voltage) in which no negative bias (negative voltage) is applied between the gate and the anode is obtained. ) When focusing on the forward characteristics, the increase in the P-type impurity concentration (increase) causes the forward voltage to decrease significantly, as in the case of negative voltage application, resulting in an increase in recovery loss in this state. This shows that side effects occur.
<Difficulty in realizing both low conduction loss and low recovery loss in Comparative Example 2>
That is, if the P-type impurity concentration is increased to reduce the conduction loss, the controllability of hole injection by the gate voltage (gate-anode voltage) is lost, and the P − -type anode layer 4 (anode region) by the gate voltage is lost. This shows that it is difficult to realize the original structural concept that achieves both low conduction loss and low recovery loss by controlling the hole carrier concentration of
<< First Embodiment: Part 2 >>
The first embodiment of the present invention will be described in detail again in light of the above-mentioned problem “improves controllability of the hole injection amount by the gate voltage and achieves both low conduction loss performance and low recovery loss performance”. .
<< Cross-sectional structure of semiconductor device 100 >>
As described above, FIG. 1 is a diagram showing a cross-sectional structure of the semiconductor device 100 according to the first embodiment of the present invention. FIG. 1A is a partial view of the vicinity of two trench gate type insulating gates 3. (B) shows a state in which a plurality of trench gate type insulated gates 3 are arranged.
　なお、以下の説明において、Ｎ―、Ｎ、Ｎ＋という表記は、半導体層がＮ型（第１導電型）であることを示し、かつ、この順に５価の原子の不純物濃度が相対的に高いことを示す。また、Ｐ－、Ｐ、Ｐ＋という表記は、半導体層がＰ型（第２導電型）であることを示し、かつ、この順に３価の原子の不純物濃度が相対的に高いことを示す。 In the following description, the notations N − , N, and N + indicate that the semiconductor layer is N-type (first conductivity type), and the impurity concentration of pentavalent atoms is relatively higher in this order. Indicates high. In addition, the notations P − , P, and P + indicate that the semiconductor layer is P-type (second conductivity type) and that the impurity concentration of trivalent atoms is relatively high in this order.
　図１（ａ）において、半導体装置１００は、トレンチゲート制御型のダイオードである。すなわち、ダイオードを形成するアノード電極６（第１電極）とカソード電極９（第２電極）との間に、トレンチゲート型の絶縁ゲート３が備えられ、絶縁ゲート３の絶縁ゲート電極１に印加する電圧によって、ダイオード特性が制御される。 1A, the semiconductor device 100 is a trench gate control type diode. That is, a trench gate type insulated gate 3 is provided between an anode electrode 6 (first electrode) and a cathode electrode 9 (second electrode) forming a diode, and is applied to the insulated gate electrode 1 of the insulated gate 3. The diode characteristics are controlled by the voltage.
　また、半導体装置１００における本発明の第１実施形態としての特徴は、第１のＰ－型アノード層４（第３半導体層）の中にキャリアのライフタイムが低減された第２のＰ－型アノード層５（第４半導体層）が備えられていることである。 Further, the semiconductor device 100 as a first embodiment of the present invention is characterized in that the second P − type in which the lifetime of carriers is reduced in the first P − type anode layer 4 (third semiconductor layer). The anode layer 5 (fourth semiconductor layer) is provided.
　なお、詳細は後記するが、第２のＰ－型アノード層５は、第１のＰ－型アノード層４の一部の所定の位置にライフタイムキラーを照射して形成される。そのため、第２のＰ－型アノード層５は、第１のＰ－型アノード層４の内部に形成されている。 Although the details will be described later, the second P − -type anode layer 5 is formed by irradiating a part of the first P − -type anode layer 4 with a lifetime killer. Therefore, the second P − type anode layer 5 is formed inside the first P − type anode layer 4.
　また、Ｎ－型ドリフト層７（第２半導体層）と、このＮ－型ドリフト層７に縦方向（紙面の縦方向）で隣接する第１のＰ－型アノード層４と、この第１のＰ－型アノード層４とは反対側においてＮ－型ドリフト層７と縦方向で隣接するＮ＋型カソード層８（第１半導体層）と、を備える。 Further, the N − type drift layer 7 (second semiconductor layer), the first P − type anode layer 4 adjacent to the N − type drift layer 7 in the vertical direction (the vertical direction of the paper surface), and the first An N + -type cathode layer 8 (first semiconductor layer) adjacent to the N − -type drift layer 7 in the vertical direction is provided on the side opposite to the P − -type anode layer 4.
　さらに、いわゆるトレンチ溝内において、ゲート絶縁膜２を介して、第１のＰ－型アノード層４の表面上に設けられる絶縁ゲート電極１を有するトレンチゲート型の前記した絶縁ゲート３を備えている。 Further, in the so-called trench groove, a trench gate type insulating gate 3 having an insulating gate electrode 1 provided on the surface of the first P − -type anode layer 4 via the gate insulating film 2 is provided. .
　第１のＰ－型アノード層４の内部には、キャリアのライフタイムが低減された第２のＰ－型アノード層５が含まれており、この第２のＰ－型アノード層５はゲート絶縁膜２に接している。 The first P − -type anode layer 4 includes a second P − -type anode layer 5 with a reduced carrier lifetime, and the second P − -type anode layer 5 is gate-insulated. It is in contact with the membrane 2.
　アノード電極６と第１のＰ－型アノード層４とは、金属－半導体接触面１０において接触している。すなわち、金属であるアノード電極６と半導体である第１のＰ－型アノード層４とは、ショットキー接触あるいは、オーミック接触によって、電気的に接続される。 The anode electrode 6 and the first P − -type anode layer 4 are in contact with each other at the metal-semiconductor contact surface 10. That is, the anode electrode 6 made of metal and the first P − -type anode layer 4 made of semiconductor are electrically connected by Schottky contact or ohmic contact.
　さらに、カソード電極９は、Ｎ＋型カソード層８とオーミック接触することによって、Ｎ＋型カソード層８と電気的に接続される。さらに、このＮ＋型カソード層８を介して、カソード電極９とＮ－型ドリフト層７とが電気的に接続される。 Further, the cathode electrode 9 by ohmic contact with the N + -type cathode layer 8, N + -type cathode layer 8 and are electrically connected. Further, the cathode electrode 9 and the N − type drift layer 7 are electrically connected via the N + type cathode layer 8.
　なお、第１のＰ－型アノード層４、第２のＰ－型アノード層５、Ｎ－型ドリフト層７、Ｎ＋型カソード層８の基となる半導体基板は、ケイ素（シリコン、Ｓｉ）もしくは炭化ケイ素(ＳｉＣ)から形成され、ゲート絶縁膜２は二酸化ケイ素（ＳｉＯ２）から形成される。 The semiconductor substrate on which the first P − -type anode layer 4, the second P − -type anode layer 5, the N − -type drift layer 7 and the N + -type cathode layer 8 are based is silicon (silicon, Si) or It is formed from silicon carbide (SiC), and the gate insulating film 2 is formed from silicon dioxide (SiO 2 ).
　図１（ｂ）において、トレンチ溝内に形成された絶縁ゲート３が横方向（紙面の横方向）に複数個、配置されている。トレンチの幅をＷで、トレンチの間隔をＳで示している。 In FIG. 1B, a plurality of insulated gates 3 formed in the trench groove are arranged in the horizontal direction (the horizontal direction of the paper). The width of the trench is indicated by W, and the interval between the trenches is indicated by S.
　図１（ｂ）において、前記のトレンチ構造（溝）と絶縁ゲート３以外の図１（ａ）で示した各要素の記載は省略している。 In FIG. 1B, the description of each element shown in FIG. 1A other than the trench structure (groove) and the insulated gate 3 is omitted.
　半導体装置１００は、図１（ｂ）に示すように、図１（ａ）で示した構造が複数個、繰り返し形成され、構成されている。 As shown in FIG. 1B, the semiconductor device 100 is configured by repeatedly forming a plurality of the structures shown in FIG.
　なお、トレンチの幅Ｗは、トレンチの間隔Ｓよりも大きいことが望ましい。
《半導体装置１００の作用・特性》
　次に、本発明の第１実施形態に係る半導体装置１００の作用・特性について説明する。 The trench width W is preferably larger than the trench spacing S.
<< Operation and Characteristics of Semiconductor Device 100 >>
Next, functions and characteristics of the semiconductor device 100 according to the first embodiment of the present invention will be described.
　図２は、本発明の第１実施形態に係る半導体装置１００の絶縁ゲート電極１に負電圧を印加し、さらにカソード電極９とアノード電極６との間に、ダイオードを導通させる順方向電圧が印加された際のホールキャリアの分布を模式的に示す図である。 In FIG. 2, a negative voltage is applied to the insulated gate electrode 1 of the semiconductor device 100 according to the first embodiment of the present invention, and a forward voltage for conducting the diode is applied between the cathode electrode 9 and the anode electrode 6. It is a figure which shows typically distribution of the hole carrier at the time of being done.
　図２において、絶縁ゲート電極１をアノード電極６に対して負電圧（負バイアス）とすることで、第１のＰ－型アノード層４とゲート絶縁膜２との界面にホールキャリアの蓄積層（１４）が形成される。 In FIG. 2, by setting the insulated gate electrode 1 to a negative voltage (negative bias) with respect to the anode electrode 6, a hole carrier accumulation layer (at the interface between the first P − -type anode layer 4 and the gate insulating film 2 ( 14) is formed.
　また、同様にキャリアのライフタイムが低減された第２のＰ－型アノード層５とゲート絶縁膜２との界面においても、同濃度のホールキャリアの蓄積層（１４）が形成される。
このホールキャリアの蓄積層（１４）を経由して、Ｎ－型ドリフト層７に多くのホールキャリア（１５）が注入され、ダイオードの順方向電圧(ＶＦ)が低下し、導通損失が低減する。なお、図２で電子は電子キャリア１６として表記している。 Similarly, a hole carrier accumulation layer (14) having the same concentration is also formed at the interface between the second P − -type anode layer 5 and the gate insulating film 2 in which the carrier lifetime is reduced.
Many hole carriers (15) are injected into the N − -type drift layer 7 via the hole carrier accumulation layer (14), the forward voltage (VF) of the diode is lowered, and the conduction loss is reduced. In FIG. 2, electrons are represented as electron carriers 16.
　図２は、第２のＰ－型アノード層５を有する場合におけるホールキャリア分布であるが、図１９に示した第２のＰ－型アノード層５が存在しない場合のホールキャリア分布と同一である。 Figure 2 is a second P - is a hole carrier distribution in the case where a type anode layer 5, a second P shown in FIG. 19 - -type anode layer 5 is the same as the hole carrier distribution in the absence of .
　すなわち、絶縁ゲート電極１に負電圧を印加する場合には、第２のＰ－型アノード層５の有無は、ホールキャリア分布に影響を与えない。
《順方向電圧が印加された際のホールキャリアの分布》
　図３は、本発明の第１実施形態に係る半導体装置１００の絶縁ゲート電極１に印加する電圧をゼロにし、カソード電極９とアノード電極６との間に、導通させる順方向電圧が印加された際のホールキャリアの分布を模式的に示す図である。 That is, when a negative voltage is applied to the insulated gate electrode 1, the presence or absence of the second P − -type anode layer 5 does not affect the hole carrier distribution.
《Hole carrier distribution when forward voltage is applied》
In FIG. 3, the voltage applied to the insulated gate electrode 1 of the semiconductor device 100 according to the first embodiment of the present invention is set to zero, and a forward voltage is applied between the cathode electrode 9 and the anode electrode 6. It is a figure which shows typically distribution of the hole carrier at the time.
　図３において、絶縁ゲート電極１に印加する電圧をゼロにすることで、第１のＰ－型アノード層４とゲート絶縁膜２との界面のホールキャリアの蓄積層が消失し、Ｎ－型ドリフト層７へのホールキャリアの注入量を抑制することができる。 In FIG. 3, by making the voltage applied to the insulated gate electrode 1 zero, the hole carrier accumulation layer at the interface between the first P − -type anode layer 4 and the gate insulating film 2 disappears, and the N − -type drift is eliminated. The amount of hole carriers injected into the layer 7 can be suppressed.
　さらに第１のＰ－型アノード層４の内部に設けられたキャリアのライフタイムを低減した第２のＰ－型アノード層５によって、ホールキャリアの注入を本領域（第２のＰ－型アノード層５）で阻止し、Ｎ－型ドリフト層７への注入を、本発明を適用しない場合に対しさらに抑制することができ、ゲート電圧によるホールキャリアの注入量の制御性を向上できる。 Furthermore, hole carriers are injected into this region (second P − -type anode layer) by the second P − -type anode layer 5 provided in the first P − -type anode layer 4 and having a reduced carrier lifetime. 5), the injection into the N − -type drift layer 7 can be further suppressed as compared with the case where the present invention is not applied, and the controllability of the hole carrier injection amount by the gate voltage can be improved.
　なお、図３は図１９と比較してホールキャリアの注入量が少ない分布となっている。ただし、図３と図１９は共に模式的に示しているので実際には、図４の順方向の電圧－電流特性でも説明するように、ホールキャリアの注入量は、図３と図１９との比較以上に少ない。
《ダイオードの順方向特性》
　図４は、本発明の第１実施形態に係る半導体装置１００のダイオードの順方向特性の例を示す図である。 Note that FIG. 3 shows a distribution in which the amount of injected hole carriers is smaller than that in FIG. However, since both FIG. 3 and FIG. 19 are schematically shown, in practice, the hole carrier injection amount is as shown in FIG. 3 and FIG. Less than comparison.
<Forward characteristics of diode>
FIG. 4 is a diagram illustrating an example of forward characteristics of the diode of the semiconductor device 100 according to the first embodiment of the present invention.
　図４において、横軸は「順方向電圧、ＶＦ（Ｖ）」であり、縦軸は「順方向電流密度、ＪＦ（Ａ／ｃｍ２）」である。 In FIG. 4, the horizontal axis is “forward voltage, VF (V)”, and the vertical axis is “forward current density, JF (A / cm 2 )”.
　特性線２０は、キャリアのライフタイムが低減された第２のＰ－型アノード層５が存在しない場合のゲート・アノード間に負バイアスを印加した際のダイオードの順方向特性である。 A characteristic line 20 is a forward characteristic of the diode when a negative bias is applied between the gate and the anode when the second P − -type anode layer 5 with reduced carrier lifetime is not present.
　特性線２１は、キャリアのライフタイムが低減された第２のＰ－型アノード層５が存在しない場合のゲート・アノード間にゼロバイアス印加時のダイオードの順方向特性である。 A characteristic line 21 is a forward characteristic of the diode when a zero bias is applied between the gate and the anode when the second P − -type anode layer 5 with reduced carrier lifetime is not present.
　特性線２２は、キャリアのライフタイムが低減された第２のＰ－型アノード層５が存在する場合のゲート・アノード間に負バイアスを印加した際のダイオードの順方向特性である。 A characteristic line 22 is a forward characteristic of the diode when a negative bias is applied between the gate and the anode when the second P − -type anode layer 5 having a reduced carrier lifetime is present.
　特性線２３は、キャリアのライフタイムが低減された第２のＰ－型アノード層５が存在する場合のゲート・アノード間にゼロバイアス印加時のダイオードの順方向特性である。 A characteristic line 23 is a forward characteristic of the diode when a zero bias is applied between the gate and the anode when the second P − -type anode layer 5 in which the lifetime of carriers is reduced is present.
　以上より、本発明の第１実施形態に係る半導体装置１００の第１のＰ－型アノード層４の内部に設けられたキャリアのライフタイムが低減された第２のＰ－型アノード層５の効果により、ダイオードの順方向電圧（ＶＦ）のゲート電圧制御性を、本発明を適用しない比較例２のダイオードに対し、大幅に改善できる効果を確認できる。 As described above, the effect of the second P − -type anode layer 5 in which the lifetime of the carriers provided in the first P − -type anode layer 4 of the semiconductor device 100 according to the first embodiment of the present invention is reduced. Thus, it can be confirmed that the gate voltage controllability of the forward voltage (VF) of the diode can be significantly improved as compared with the diode of Comparative Example 2 to which the present invention is not applied.
　特に、ゲート・アノード間にゲート電圧を印加しない（ゼロバイアス）条件においては、比較例２に相当する特性線２１と本発明の第１実施形態に係る半導体装置１００の特性線２３との比較において、特性線２３で示すようにダイオードの順方向電圧（ＶＦ）が大きく上昇している。 In particular, in a condition where no gate voltage is applied between the gate and the anode (zero bias), the characteristic line 21 corresponding to Comparative Example 2 is compared with the characteristic line 23 of the semiconductor device 100 according to the first embodiment of the present invention. As shown by the characteristic line 23, the forward voltage (VF) of the diode is greatly increased.
　すなわち、キャリアのライフタイムが低減された第２のＰ－型アノード層５によって、第１のＰ－型アノード層４からのホールキャリアがブロック（１７：図３）され、Ｎ－型ドリフト層７内部での伝導度変調が抑制された効果を示している。
《ダイオードのゲートの入力信号と対アームのＩＧＢＴのゲートの入力信号》
　次に、リカバリー時における本発明の第１実施形態の効果を説明する。 That is, hole carriers from the first P − -type anode layer 4 are blocked (17: FIG. 3) by the second P − -type anode layer 5 with reduced carrier lifetime, and the N − -type drift layer 7 This shows the effect of suppressing the internal conductivity modulation.
《Diode gate input signal and anti-IGBT gate input signal》
Next, the effect of the first embodiment of the present invention at the time of recovery will be described.
　図５は、本発明の第１実施形態に係る半導体装置１００のダイオードのゲート（絶縁ゲート電極１：図１）の入力信号２４、及び対アームのＩＧＢＴのゲートの入力信号２５の例を示す図である。なお、入力信号２４は負電圧と０電圧との間、入力信号２５は負電圧と正電圧との間で変化する。また、入力信号２４と入力信号２５との立ち上がりには時間ｔ１の時間差がある。 FIG. 5 is a diagram showing an example of the input signal 24 of the gate (insulated gate electrode 1: FIG. 1) of the diode and the input signal 25 of the gate of the IGBT of the pair arm of the semiconductor device 100 according to the first embodiment of the present invention. It is. The input signal 24 varies between a negative voltage and a zero voltage, and the input signal 25 varies between a negative voltage and a positive voltage. Further, there is a time difference of time t1 between the rising edge of the input signal 24 and the input signal 25.
　また、前記の入力信号２４および入力信号２５を適用する回路は、図１５（ａ）である。前記したように、図１５（ａ）は評価用の回路であって、実際には、図１５（ｂ）に示す回路が用いられる。 Further, a circuit to which the input signal 24 and the input signal 25 are applied is shown in FIG. As described above, FIG. 15A is an evaluation circuit, and the circuit shown in FIG. 15B is actually used.
　図５における入力信号２４は、図１５（ａ）の絶縁ゲートを有するダイオード４２のゲートに入力する。 5 is inputted to the gate of the diode 42 having the insulated gate shown in FIG.
　また、図５における入力信号２５は、図１５（ａ）の下アームを構成するＩＧＢＴ４３のゲートに入力する。 Further, the input signal 25 in FIG. 5 is input to the gate of the IGBT 43 constituting the lower arm of FIG.
　ＩＧＢＴ４３のゲートの入力信号２５がオン（正電圧）になることで、絶縁ゲートを有するダイオード４２に流れていた誘導性負荷との還流電流が急峻になくなると同時に、ダイオード４２のカソード・アノード間の電圧が上昇し、ダイオード４２は急速に逆方向状態に推移する。この過渡的な状態をリカバリー状態と呼び、以下、このリカバリー状態における本発明の効果を述べる。 When the input signal 25 of the gate of the IGBT 43 is turned on (positive voltage), the return current to the inductive load flowing in the diode 42 having the insulated gate is sharply eliminated, and at the same time, between the cathode and the anode of the diode 42. The voltage rises and the diode 42 rapidly changes to the reverse direction. This transient state is called a recovery state, and the effects of the present invention in this recovery state will be described below.
　本発明の第１実施形態に係る半導体装置１００のダイオード４２の絶縁ゲート電極１（図１）に入力する入力信号２４（図５）を、対アームのＩＧＢＴ４３のゲートに入力する入力信号２５がオンするよりも前に、オフ（０Ｖ：図５）することで、前述した通りダイオードの順方向電圧（ＶＦ）が高い、すなわちアノード電極６（図１）からのホールキャリアの注入と伝導度変調が抑制された状態（２７：図５）で、リカバリー状態に移行することが可能となる。
《ダイオードのアノード電流とカソード・アノード間電圧の過渡特性》
　図６は、本発明の第１実施形態に係る半導体装置１００のダイオードに図５の入力信号による制御を適用した場合における、ダイオード（１００）のアノード電流（特性線３１）と、カソード・アノード間電圧（特性線２９）の過渡特性の例を示す図である。 The input signal 24 (FIG. 5) input to the insulated gate electrode 1 (FIG. 1) of the diode 42 of the semiconductor device 100 according to the first embodiment of the present invention is turned on and the input signal 25 input to the gate of the IGBT 43 of the opposite arm is turned on. Before turning on (0V: FIG. 5), the forward voltage (VF) of the diode is high as described above, that is, hole carrier injection from the anode electrode 6 (FIG. 1) and conductivity modulation are performed. In the suppressed state (27: FIG. 5), it becomes possible to shift to the recovery state.
<Transient characteristics of diode anode current and cathode-anode voltage>
FIG. 6 shows the anode current (characteristic line 31) of the diode (100) and the cathode-anode when the control by the input signal of FIG. 5 is applied to the diode of the semiconductor device 100 according to the first embodiment of the invention. It is a figure which shows the example of the transient characteristic of a voltage (characteristic line 29).
　図６において、横軸は、時間（時間の推移：１目盛が１μｓｅｃ.）を表している。また、右側の縦軸がダイオードのカソード・アノード間電圧を示し、左側の縦軸がダイオードに流れる電流密度を示している。 In FIG. 6, the horizontal axis represents time (time transition: 1 scale is 1 μsec). Also, the right vertical axis represents the cathode-anode voltage of the diode, and the left vertical axis represents the current density flowing through the diode.
　また、特性線２９は、カソード・アノード間電圧を示している。特性線３０は、比較例２のダイオードに流れる電流密度の特性であり、特性線３１は本発明の第１実施形態に係る半導体装置１００のダイオードに流れる電流密度の特性である。 The characteristic line 29 indicates the cathode-anode voltage. The characteristic line 30 is a characteristic of current density flowing through the diode of Comparative Example 2, and the characteristic line 31 is a characteristic of current density flowing through the diode of the semiconductor device 100 according to the first embodiment of the present invention.
　本発明の半導体装置１００のダイオードのアノード電流（特性線３１）では、カソード・アノード間の電圧が上昇する際に観られるリカバリーによる逆電流を、従来のアノード電流（特性線３０）に対して大幅に低減できる。 In the anode current (characteristic line 31) of the diode of the semiconductor device 100 of the present invention, the reverse current due to recovery observed when the voltage between the cathode and the anode rises is significantly larger than the conventional anode current (characteristic line 30). Can be reduced.
　カソード・アノード間の電圧が上昇する本期間にておいては、リカバリー電流とカソード・アノード間電圧によって電力消費が発生するため、リカバリー電流が下がることは、リカバリー損失を低減することを示している。 In this period when the cathode-anode voltage rises, power consumption occurs due to the recovery current and the cathode-anode voltage, so a decrease in the recovery current indicates a reduction in recovery loss. .
　このように本発明により、ゲート電圧をゼロにした際、アノード領域内部のライフタイムを低減した領域において、アノード電極からのホール注入と伝導度変調が抑制されたため、ホールがアノードに戻ることにより生ずるリカバリー電流を低減することができる。
＜第１実施形態の効果＞
以上より、本発明の第１実施形態によって、ゲートに負電圧を印加した際、ゼロにした際の、内部キャリア量の制御性を向上し、低導通損失と低リカバリー損失を併せ持つダイオードが実現できる。
≪第２実施形態≫
　本発明の第２実施形態の絶縁ゲート型の縦型半導体装置（半導体装置）２００を、図７を参照して説明する。
《絶縁ゲート型（トレンチゲート制御型）の縦型半導体装置の断面図》
　図７は、本発明の第２実施形態に係る半導体装置２００の断面構造の例を模式的に示す図である。 As described above, according to the present invention, when the gate voltage is reduced to zero, hole injection from the anode electrode and conductivity modulation are suppressed in the region where the lifetime inside the anode region is reduced. Recovery current can be reduced.
<Effects of First Embodiment>
As described above, according to the first embodiment of the present invention, when a negative voltage is applied to the gate, the controllability of the internal carrier amount when it is reduced to zero can be improved, and a diode having both low conduction loss and low recovery loss can be realized. .
<< Second Embodiment >>
An insulated gate vertical semiconductor device (semiconductor device) 200 according to a second embodiment of the present invention will be described with reference to FIG.
<< Cross Sectional View of Insulated Gate Type (Trench Gate Control Type) Vertical Semiconductor Device >>
FIG. 7 is a diagram schematically showing an example of a cross-sectional structure of a semiconductor device 200 according to the second embodiment of the present invention.
　図７において、アノード電極６（第１電極）、カソード電極９（第２電極）、絶縁ゲート３、絶縁ゲート電極１、ゲート絶縁膜２、第１のＰ－型アノード層４（第３半導体層）、第２のＰ－型アノード層５（第４半導体層）、Ｎ－型ドリフト層７（第２半導体層）、Ｎ＋型カソード層８（第１半導体層）は、図１に示した半導体装置１００と同じ構成であるので、重複する説明は省略する。 In FIG. 7, an anode electrode 6 (first electrode), a cathode electrode 9 (second electrode), an insulated gate 3, an insulated gate electrode 1, a gate insulating film 2, a first P − -type anode layer 4 (third semiconductor layer). ), The second P − -type anode layer 5 (fourth semiconductor layer), the N − -type drift layer 7 (second semiconductor layer), and the N + -type cathode layer 8 (first semiconductor layer) are shown in FIG. Since the configuration is the same as that of the semiconductor device 100, a duplicate description is omitted.
　図７の半導体装置２００が図１の半導体装置１００と異なるのは、キャリアのライフタイムが低減された第２のＮ－型ドリフト層３２（第５半導体層）を有することである。 The semiconductor device 200 of FIG. 7 differs from the semiconductor device 100 of FIG. 1 in that it has a second N − type drift layer 32 (fifth semiconductor layer) with a reduced carrier lifetime.
　第２のＮ－型ドリフト層３２は、Ｎ－型ドリフト層７の一部の所定の位置にライフタイムキラーを照射して形成される。そのため、第２のＮ－型ドリフト層３２は、Ｎ－型ドリフト層７（第１のＮ－型ドリフト層）の内部に形成されている。 The second N − type drift layer 32 is formed by irradiating a part of the N − type drift layer 7 with a lifetime killer. Therefore, the second N − type drift layer 32 is formed inside the N − type drift layer 7 (first N − type drift layer).
　この第２実施形態の半導体装置２００のダイオードは、第２のＮ－型ドリフト層３２を備えたことによって、第１実施形態の半導体装置１００のダイオードよりも、絶縁ゲート電極１に印加された電圧による内部電荷（例えばホールキャリア）の注入制御性を向上することができる。 Since the diode of the semiconductor device 200 of the second embodiment includes the second N − type drift layer 32, the voltage applied to the insulated gate electrode 1 is higher than the diode of the semiconductor device 100 of the first embodiment. The injection controllability of internal charges (for example, hole carriers) due to can be improved.
　この制御性の向上は、アノード電極６からのホールキャリアの注入を促す要因として、カソード電極９から第１のＰ－型アノード層４を介してアノード電極６へ注入される電子の濃度が一因として存在することによる。そのため、第２のＮ－型ドリフト層３２がＮ－型ドリフト層７（第１のＮ－型ドリフト層）の内部に存在することが制御性の向上に関係するのである。 This improvement in controllability is partly due to the concentration of electrons injected from the cathode electrode 9 into the anode electrode 6 through the first P − -type anode layer 4 as a factor for promoting the injection of hole carriers from the anode electrode 6. As it exists. Therefore, the presence of the second N − -type drift layer 32 inside the N − -type drift layer 7 (first N − -type drift layer) is related to improvement in controllability.
　次に、前記の第２のＮ－型ドリフト層３２が制御性の向上に関係することを、キャリアプロファイルを示して説明する。
《ホールと電子のキャリアプロファイル》
　図８は、本発明の第２実施形態に係る半導体装置２００のダイオードの絶縁ゲート電極１に印加する電圧をゼロにした場合における、ホールと電子のキャリアプロファイルを模式的に示す図である。 Next, the fact that the second N − type drift layer 32 is related to improvement in controllability will be described with reference to a carrier profile.
《Hall and electron carrier profile》
FIG. 8 is a diagram schematically showing a hole and electron carrier profile when the voltage applied to the insulated gate electrode 1 of the diode of the semiconductor device 200 according to the second embodiment of the present invention is zero.
　図８において、第１のＰ－型アノード層４とキャリアのライフタイムを低減した第２のＰ－型アノード層５の作用効果については、前記した図３の説明と同じであるので、重複する説明は省略する。 In FIG. 8, the operation and effect of the first P − -type anode layer 4 and the second P − -type anode layer 5 with reduced carrier lifetime are the same as those described above with reference to FIG. Description is omitted.
　図８において、図３と異なるのは、第２のＮ－型ドリフト層３２が存在することによる影響である。ホールキャリア（１７）が、キャリアのライフタイム低減された第２のＮ－型ドリフト層３２により、Ｎ－型ドリフト層７への注入（ホールキャリア１５）がブロックされ、電子（３４）が、キャリアのライフタイムが低減された第２のＮ－型ドリフト層３２により、第１のＰ－型アノード層４への注入がブロックされる効果が働き、伝導度変調をさらに抑制することができる。 In FIG. 8, what is different from FIG. 3 is an influence due to the presence of the second N − -type drift layer 32. The hole carrier (17) is blocked from being injected into the N − -type drift layer 7 (hole carrier 15) by the second N − -type drift layer 32 with a reduced carrier lifetime, and the electrons (34) are transferred to the carrier The second N − type drift layer 32 having a reduced lifetime works to block the injection into the first P − type anode layer 4, and the conductivity modulation can be further suppressed.
　なお、表記の都合上、図８と図３において、ホールや電子の個数を同じように記載しているが、実際には差異がある。
＜第２実施形態の効果＞
　以上、本発明の第２実施形態によって、ゲートに負電圧をかけた場合のダイオードの順方向電圧と、電圧をゼロにした場合のダイオードの順方向電圧の差を広げることができる。すなわち、ゲート電圧によるダイオード特性の制御性をさらに向上することができる。
≪第３実施形態≫
　本発明の第３実施形態の絶縁ゲート型の縦型半導体装置（半導体装置）３００を、図９を参照して説明する。
《絶縁ゲート型（サイドゲート制御型）の縦型半導体装置の断面図》
　図９は、本発明の第３実施形態に係る半導体装置３００の断面構造の例を模式的に示す図である。 For convenience of description, the numbers of holes and electrons are shown in the same way in FIGS. 8 and 3, but there are actually differences.
<Effects of Second Embodiment>
As described above, according to the second embodiment of the present invention, the difference between the forward voltage of the diode when a negative voltage is applied to the gate and the forward voltage of the diode when the voltage is zero can be widened. That is, the controllability of the diode characteristics by the gate voltage can be further improved.
«Third embodiment»
An insulated gate vertical semiconductor device (semiconductor device) 300 according to a third embodiment of the present invention will be described with reference to FIG.
<< Cross Section of Insulated Gate Type (Side Gate Control Type) Vertical Semiconductor Device >>
FIG. 9 is a diagram schematically showing an example of a cross-sectional structure of a semiconductor device 300 according to the third embodiment of the present invention.
　図９において、半導体装置３００は、サイドゲート制御型のダイオードである。 In FIG. 9, the semiconductor device 300 is a side gate control type diode.
　すなわち、ダイオードを形成するアノード電極６（第１電極）とカソード電極９（第２電極）との間に、サイドゲート制御型の絶縁ゲート（絶縁サイドゲート）３７が備えられ、絶縁ゲート３７の絶縁ゲート電極（絶縁サイドゲート電極）３５に印加する電圧によって、ダイオード特性が制御される。 That is, a side gate control type insulating gate (insulating side gate) 37 is provided between the anode electrode 6 (first electrode) and the cathode electrode 9 (second electrode) forming the diode, and the insulating gate 37 is insulated. The diode characteristics are controlled by the voltage applied to the gate electrode (insulated side gate electrode) 35.
　また、第１のＰ－型アノード層４（第３半導体層）の中にキャリアのライフタイムが低減された第２のＰ－型アノード層５（第４半導体層）が備えられている。 In addition, a second P − type anode layer 5 (fourth semiconductor layer) with a reduced carrier lifetime is provided in the first P − type anode layer 4 (third semiconductor layer).
　また、Ｎ－型ドリフト層７（第２半導体層）と、このＮ－型ドリフト層７に縦方向で隣接する第１のＰ－型アノード層４と、この第１のＰ－型アノード層４とは反対側においてＮ－型ドリフト層７と縦方向で隣接するＮ＋型カソード層８（第１半導体層）を備える。 The N − type drift layer 7 (second semiconductor layer), the first P − type anode layer 4 vertically adjacent to the N − type drift layer 7, and the first P − type anode layer 4 And an N + type cathode layer 8 (first semiconductor layer) adjacent to the N − type drift layer 7 in the vertical direction on the opposite side.
　また、ゲート絶縁膜（サイドゲート絶縁膜）３６を介して、第１のＰ－型アノード層４の表面上に設けられる絶縁ゲート電極３５において、第１のＰ－型アノード層４と対向する側には、絶縁膜（酸化膜）３８が配置され、絶縁ゲート電極３５に対して片側にしか、第１のＰ－型アノード層４が存在しない、いわゆるサイドゲート型の絶縁ゲート３７を備えている。 In addition, in the insulated gate electrode 35 provided on the surface of the first P − type anode layer 4 through the gate insulating film (side gate insulating film) 36, the side facing the first P − type anode layer 4 Includes a so-called side gate type insulating gate 37 in which an insulating film (oxide film) 38 is disposed and the first P − -type anode layer 4 is present only on one side with respect to the insulating gate electrode 35. .
　第１のＰ－型アノード層４の内部には、キャリアのライフタイムが低減された第２のＰ－型アノード層５が含まれており、この第２のＰ－型アノード層５はゲート絶縁膜３６に接している。 The first P − -type anode layer 4 includes a second P − -type anode layer 5 with a reduced carrier lifetime, and the second P − -type anode layer 5 is gate-insulated. It is in contact with the film 36.
　アノード電極６と第１のＰ－型アノード層４とは、金属－半導体接触面１０において接触している。すなわち、金属であるアノード電極６と半導体である第１のＰ－型アノード層４とは、ショットキー接触、あるいは、オーミック接触によって、電気的に接続される。 The anode electrode 6 and the first P − -type anode layer 4 are in contact with each other at the metal-semiconductor contact surface 10. That is, the anode electrode 6 made of metal and the first P − -type anode layer 4 made of semiconductor are electrically connected by Schottky contact or ohmic contact.
　さらに、カソード電極９は、Ｎ＋型カソード層８とオーミック接触することによって、Ｎ＋型カソード層８と電気的に接続される。さらに、このＮ＋型カソード層８を介して、カソード電極９とＮ－型ドリフト層７とが電気的に接続される。 Further, the cathode electrode 9 by ohmic contact with the N + -type cathode layer 8, N + -type cathode layer 8 and are electrically connected. Further, the cathode electrode 9 and the N − type drift layer 7 are electrically connected via the N + type cathode layer 8.
　なお、第１のＰ－型アノード層４、第２のＰ－型アノード層５、Ｎ－型ドリフト層７、Ｎ＋型カソード層８の基となる半導体基板は、ケイ素（シリコン、Ｓｉ）もしくは炭化ケイ素(ＳｉＣ)から形成され、ゲート絶縁膜２は二酸化ケイ素（ＳｉＯ２）から形成される。 The semiconductor substrate on which the first P − -type anode layer 4, the second P − -type anode layer 5, the N − -type drift layer 7 and the N + -type cathode layer 8 are based is silicon (silicon, Si) or It is formed from silicon carbide (SiC), and the gate insulating film 2 is formed from silicon dioxide (SiO 2 ).
　本実施形態（第３実施形態）の半導体装置３００のダイオードによって、第１実施形態に記載されたダイオード（半導体装置１００）よりも、さらにリカバリー電流を低減することができる。 The recovery current can be further reduced by the diode of the semiconductor device 300 of the present embodiment (third embodiment) than the diode (semiconductor device 100) described in the first embodiment.
　その理由を、図１０、図１１を参照して、次に説明する。
《第１実施形態および第３実施形態のダイオードのリカバリー電流の経路》
　図１０は、本発明の第１実施形態に係る半導体装置１００のダイオードのリカバリー電流の経路を模式的に示す図である。 The reason will be described next with reference to FIGS.
<< Recovery Current Path of Diode of First Embodiment and Third Embodiment >>
FIG. 10 is a diagram schematically showing a recovery current path of the diode of the semiconductor device 100 according to the first embodiment of the present invention.
　図１１は、本発明の第３実施形態に係る半導体装置３００のダイオードのリカバリー電流の経路を模式的に示す図である。 FIG. 11 is a diagram schematically showing a recovery current path of the diode of the semiconductor device 300 according to the third embodiment of the present invention.
　図１０において、半導体装置１００のダイオードのリカバリー電流の経路は、Ｎ－型ドリフト層７からの経路７０以外に、絶縁ゲート３に対して、対向する領域から回りこんでアノード電極６に戻るリカバリー電流の経路７１が存在する。 In FIG. 10, the recovery current path of the diode of the semiconductor device 100 is a recovery current that returns to the anode electrode 6 from the region facing the insulated gate 3 in addition to the path 70 from the N − -type drift layer 7. The path 71 exists.
　一方で、図１１において、半導体装置３００のダイオードでは、Ｎ－型ドリフト層７からの経路７０と経路７２は存在するが、図１０に示した、前記の対向する領域から回りこんでアノード電極６に戻るリカバリー電流の経路３９に相当する電流経路は存在しない。 On the other hand, in FIG. 11, in the diode of the semiconductor device 300, the path 70 and the path 72 from the N − type drift layer 7 exist, but the anode electrode 6 wraps around from the above-described facing region shown in FIG. There is no current path corresponding to the recovery current path 39 that goes back to.
　したがって、リカバリー電流量を削減でき、リカバリー損失の低減効果をさらに向上することができる。
＜第３実施形態の効果＞
　すなわち、本発明の第３実施形態である半導体装置３００のダイオードは、第１実施形態である半導体装置１００のダイオードに対し、導通損失とリカバリー損失をさらに向上した高効率性能を実現することができる。
≪第４実施形態≫
　本発明の第４実施形態として、絶縁ゲート型の縦型半導体装置を駆動する駆動ゲート信号を、図１２を参照して説明する。
《絶縁ゲート型の縦型半導体装置の駆動ゲート信号》
　図１２は、本発明の第４実施形態における絶縁ゲート型の縦型半導体装置を駆動する駆動ゲート信号を示す図である。 Therefore, the amount of recovery current can be reduced, and the effect of reducing recovery loss can be further improved.
<Effect of the third embodiment>
That is, the diode of the semiconductor device 300 according to the third embodiment of the present invention can realize high efficiency performance with further improved conduction loss and recovery loss compared to the diode of the semiconductor device 100 according to the first embodiment. .
<< Fourth Embodiment >>
As a fourth embodiment of the present invention, a drive gate signal for driving an insulated gate vertical semiconductor device will be described with reference to FIG.
<< Drive gate signal of insulated gate type vertical semiconductor device >>
FIG. 12 is a diagram showing drive gate signals for driving an insulated gate vertical semiconductor device according to the fourth embodiment of the present invention.
　図１２において、本発明の第１～第３実施形態の半導体装置のダイオードを図１５に示す駆動回路に用いる場合に、絶縁ゲートを有するダイオード４２のゲートの入力信号２４、及び対アームのＩＧＢＴ４３のゲートの入力信号２５を示している。 In FIG. 12, when the diodes of the semiconductor devices of the first to third embodiments of the present invention are used in the drive circuit shown in FIG. 15, the input signal 24 of the gate of the diode 42 having an insulated gate and the IGBT 43 of the pair arm The gate input signal 25 is shown.
　また、横軸は時間（時間の推移）であり、縦軸は入力信号２４、２５のそれぞれの電圧を表している。 Also, the horizontal axis represents time (time transition), and the vertical axis represents the respective voltages of the input signals 24 and 25.
　図１２において、対アームのＩＧＢＴ４３（図１５）のゲートの入力信号２５がオン（正電圧）になることで、ダイオード４２（図１５）に流れていた誘導性負荷４１（図１５）との還流電流が急峻になくなると同時に、ダイオード４２のカソード・アノード間の電圧が上昇し、ダイオード４２は急速に逆方向状態に推移する。 In FIG. 12, when the input signal 25 of the gate of the IGBT 43 (FIG. 15) of the pair arm is turned on (positive voltage), it is returned to the inductive load 41 (FIG. 15) flowing in the diode 42 (FIG. 15). At the same time as the current disappears steeply, the voltage between the cathode and anode of the diode 42 increases, and the diode 42 rapidly changes to the reverse direction.
　この過渡的な状態がリカバリー状態（２８：図１２）である。低リカバリー電流、即ち低リカバリー損失を実現するには、リカバリー直前に、ダイオード４２のゲートの入力信号２４をオフ（０Ｖ）して、ホールキャリアの注入電荷量を低減する状態（２７、時間ｔ２）を作ることが必要である。 This transient state is the recovery state (28: FIG. 12). In order to realize a low recovery current, that is, a low recovery loss, the input signal 24 to the gate of the diode 42 is turned off (0 V) immediately before the recovery to reduce the injected charge amount of hole carriers (27, time t2). It is necessary to make.
　この過程において、ダイオード４２のゲートの入力信号２４がオン（負電圧）してホールキャリアの注入量が上昇した状態から、オフ（０Ｖ）して注入量が低減された状態に至るまで、ホールキャリアのライフタイムによって、ホールキャリアを消失することが必要である。その間の時間ｔ２は、オフ信号（０Ｖ）を入力してからホールキャリアのライフタイムを考慮し、２μ秒以上、とることが望ましい。 In this process, the hole carrier from the state where the input signal 24 of the gate of the diode 42 is turned on (negative voltage) and the injection amount of hole carriers is increased to the state where it is turned off (0 V) and the injection amount is reduced. It is necessary to eliminate the hole carrier according to the lifetime of It is desirable that the time t2 during that time be 2 μsec or more in consideration of the lifetime of the hole carrier after the OFF signal (0 V) is input.
　２μ秒以上の期間（時間ｔ２）を設けた後、対アームのＩＧＢＴ４３のゲートの入力信号２５をオン（正電圧）することで、ダイオード４２はリカバリー状態となるが、低リカバリー電流、即ち低リカバリー損失性能を実現できる。
≪第５実施形態：半導体装置の製造方法≫
　本発明の第５実施形態の半導体装置（絶縁ゲート型の縦型半導体装置）の製造方法を、図１３を参照して説明する。 After providing a period of 2 μs or more (time t2), turning on the input signal 25 of the gate of the IGBT 43 of the opposite arm (positive voltage) causes the diode 42 to be in a recovery state, but a low recovery current, that is, a low recovery Loss performance can be realized.
<< Fifth Embodiment: Manufacturing Method of Semiconductor Device >>
A method for manufacturing a semiconductor device (insulated gate type vertical semiconductor device) according to a fifth embodiment of the present invention will be described with reference to FIG.
　図１３は、本発明の第５実施形態に係る半導体装置１００（図１）の製造方法の例を示す図であり、（ａ）は第２のＰ－型アノード層５が形成される前の半導体装置１００の状態を表し、（ｂ）は第２のＰ－型アノード層５が形成された後の半導体装置１００の状態を表している。 FIG. 13 is a diagram showing an example of a manufacturing method of the semiconductor device 100 (FIG. 1) according to the fifth embodiment of the present invention. FIG. 13 (a) shows a state before the second P − -type anode layer 5 is formed. The state of the semiconductor device 100 is shown, and (b) shows the state of the semiconductor device 100 after the second P − -type anode layer 5 is formed.
　本発明の第５実施形態は、トレンチゲート制御型のダイオードの製造方法であって、特に第１のＰ－型アノード層４内に第２のＰ－型アノード層５を形成する方法について説明する。 The fifth embodiment of the present invention is a method for manufacturing a trench gate control type diode, and in particular, a method for forming a second P − -type anode layer 5 in the first P − -type anode layer 4 will be described. .
　図１３（ａ）、（ｂ）において、半導体装置（１００）は、アノード電極６（第１電極）、カソード電極９（第２電極）、絶縁ゲート３、絶縁ゲート電極１、ゲート絶縁膜２、第１のＰ－型アノード層４（第３半導体層）、Ｎ－型ドリフト層７（第２半導体層）、Ｎ＋型カソード層８（第１半導体層）を備えている。 13A and 13B, the semiconductor device (100) includes an anode electrode 6 (first electrode), a cathode electrode 9 (second electrode), an insulating gate 3, an insulating gate electrode 1, a gate insulating film 2, A first P − -type anode layer 4 (third semiconductor layer), an N − -type drift layer 7 (second semiconductor layer), and an N + -type cathode layer 8 (first semiconductor layer) are provided.
　図１３（ａ）と図１３（ｂ）の相違は、第２のＰ－型アノード層５（第４半導体層）の有無である。次に第２のＰ－型アノード層５（第４半導体層）の製造方法について説明する。なお、第２のＰ－型アノード層５（第４半導体層）以外の製造方法については、説明を省略する。 The difference between FIG. 13A and FIG. 13B is the presence or absence of the second P − -type anode layer 5 (fourth semiconductor layer). Next, a method for manufacturing the second P − -type anode layer 5 (fourth semiconductor layer) will be described. The description of the manufacturing method other than the second P − -type anode layer 5 (fourth semiconductor layer) is omitted.
　図１３（ａ）に示した状態において、第１のＰ－型アノード層４の一部の所定の位置に向けてヘリウム（Ｈｅ）、プロトン（Ｐ、Ｈ＋）、電子線などを主としたライフタイムキラーを照射（６３）する。 In the state shown in FIG. 13A, helium (He), protons (P, H + ), electron beams, etc. are mainly directed toward a predetermined position of a part of the first P − -type anode layer 4. A lifetime killer is irradiated (63).
　このライフタイムキラーの照射を受けた部分の第１のＰ－型アノード層４は、結晶構造にダメージ（結晶欠陥）が生じ、キャリア（ホールおよび電子）が移動しにくい、キャリアのライフタイムが低減した第２のＰ－型アノード層５が形成される。 The portion of the first P − -type anode layer 4 that has been irradiated with the lifetime killer is damaged in the crystal structure (crystal defects), carriers (holes and electrons) are difficult to move, and the carrier lifetime is reduced. Thus, the second P − -type anode layer 5 is formed.
　この第２のＰ－型アノード層５が形成された状態を示すのが図１３（ｂ）である。 FIG. 13B shows a state in which the second P − -type anode layer 5 is formed.
　なお、前記したように、図１３（ｂ）における第２のＰ－型アノード層５は、第１のＰ－型アノード層４を基にライフタイムキラーを照射して形成されるので、第２のＰ－型アノード層５は、第１のＰ－型アノード層４の内部に含まれる。
＜第５実施形態の効果＞
　以上、第２のＰ－型アノード層５を第１のＰ－型アノード層４の一部の所定の位置にライフタイムキラーを照射して形成されるので、製作工程上、容易に、かつ低コストで所望の特性の半導体装置（ゲート制御型ダイオード）が得られる。
≪第６実施形態：半導体装置の製造方法≫
　本発明の第６実施形態の半導体装置（絶縁ゲート型の縦型半導体装置）の製造方法を、図１４を参照して説明する。 As described above, the second P − -type anode layer 5 in FIG. 13B is formed by irradiating a lifetime killer based on the first P − -type anode layer 4. The P − -type anode layer 5 is included in the first P − -type anode layer 4.
<Effect of Fifth Embodiment>
As described above, since the second P − -type anode layer 5 is formed by irradiating a part of the first P − -type anode layer 4 with a lifetime killer, it is easy and low in the manufacturing process. A semiconductor device (gate-controlled diode) having desired characteristics can be obtained at low cost.
<< Sixth Embodiment: Manufacturing Method of Semiconductor Device >>
A method for manufacturing a semiconductor device (insulated gate type vertical semiconductor device) according to a sixth embodiment of the present invention will be described with reference to FIG.
　図１４は、本発明の第６実施形態に係る半導体装置３００（図９）の製造方法の例を示す図であり、（ａ）は第２のＰ－型アノード層５が形成される前の半導体装置の状態を表し、（ｂ）は第２のＰ－型アノード層５が形成された後の半導体装置の状態を表している。 FIG. 14 is a view showing an example of a manufacturing method of the semiconductor device 300 (FIG. 9) according to the sixth embodiment of the present invention. FIG. 14 (a) shows a state before the second P − -type anode layer 5 is formed. The state of the semiconductor device is shown, and (b) shows the state of the semiconductor device after the second P − -type anode layer 5 is formed.
　本発明の第６実施形態は、サイドゲート制御型のダイオードの製造方法であって、特に第１のＰ－型アノード層４内に第２のＰ－型アノード層５を形成する方法について説明する。 The sixth embodiment of the present invention is a method for manufacturing a side gate control type diode, and in particular, a method for forming a second P − -type anode layer 5 in the first P − -type anode layer 4 will be described. .
　図１４（ａ）、（ｂ）において、半導体装置（３００）は、アノード電極６（第１電極）、カソード電極９（第２電極）、絶縁ゲート３７、絶縁ゲート電極３５、ゲート絶縁膜３６、酸化膜３８、第１のＰ－型アノード層４（第３半導体層）、Ｎ－型ドリフト層７（第２半導体層）、Ｎ＋型カソード層８（第１半導体層）を備えている。 14A and 14B, the semiconductor device (300) includes an anode electrode 6 (first electrode), a cathode electrode 9 (second electrode), an insulating gate 37, an insulating gate electrode 35, a gate insulating film 36, An oxide film 38, a first P − type anode layer 4 (third semiconductor layer), an N − type drift layer 7 (second semiconductor layer), and an N + type cathode layer 8 (first semiconductor layer) are provided.
　図１４（ａ）と図１４（ｂ）の相違は、第２のＰ－型アノード層５（第４半導体層）の有無である。次に第２のＰ－型アノード層５（第４半導体層）の製造方法について説明する。なお、第２のＰ－型アノード層５（第４半導体層）以外の製造方法については、説明を省略する。 The difference between FIG. 14A and FIG. 14B is the presence or absence of the second P − -type anode layer 5 (fourth semiconductor layer). Next, a method for manufacturing the second P − -type anode layer 5 (fourth semiconductor layer) will be described. The description of the manufacturing method other than the second P − -type anode layer 5 (fourth semiconductor layer) is omitted.
　図１４（ａ）に示した状態において、第１のＰ－型アノード層４の一部の所定の位置に向けてヘリウム（Ｈｅ）、プロトン（Ｐ、Ｈ＋）、電子線などを主としたライフタイムキラーを照射（６３）する。 In the state shown in FIG. 14A, helium (He), protons (P, H + ), electron beams, etc. are mainly directed toward a predetermined position of a part of the first P − -type anode layer 4. A lifetime killer is irradiated (63).
　このライフタイムキラーの照射を受けた部分の第１のＰ－型アノード層４は、結晶構造にダメージ（結晶欠陥）が生じ、キャリア（ホールおよび電子）が移動しにくい、キャリアのライフタイムが低減した第２のＰ－型アノード層５が形成される。 The portion of the first P − -type anode layer 4 that has been irradiated with the lifetime killer is damaged in the crystal structure (crystal defects), carriers (holes and electrons) are difficult to move, and the carrier lifetime is reduced. Thus, the second P − -type anode layer 5 is formed.
　この第２のＰ－型アノード層５が形成された状態を示すのが図１４（ｂ）である。 FIG. 14B shows a state in which the second P − type anode layer 5 is formed.
　なお、前記したように、図１４（ｂ）における第２のＰ－型アノード層５は、第１のＰ－型アノード層４を基にライフタイムキラーを照射して形成されるので、第２のＰ－型アノード層５は、第１のＰ－型アノード層４の内部に含まれる。
＜第６実施形態の効果＞
　以上、第２のＰ－型アノード層５を第１のＰ－型アノード層４の一部の所定の位置にライフタイムキラーを照射して形成されるので、製作工程上、容易に、かつ低コストで所望の特性の半導体装置（ゲート制御型ダイオード）が得られる。
≪第７実施形態：半導体回路の駆動装置≫
　本発明の第７実施形態の半導体回路（半導体装置）の駆動装置を、図１５を参照して説明する。 As described above, the second P − -type anode layer 5 in FIG. 14B is formed by irradiating the lifetime killer based on the first P − -type anode layer 4. The P − -type anode layer 5 is included in the first P − -type anode layer 4.
<Effects of Sixth Embodiment>
As described above, since the second P − -type anode layer 5 is formed by irradiating a part of the first P − -type anode layer 4 with a lifetime killer, it is easy and low in the manufacturing process. A semiconductor device (gate-controlled diode) having desired characteristics can be obtained at low cost.
<< Seventh Embodiment: Driving Device for Semiconductor Circuit >>
A semiconductor circuit (semiconductor device) drive device according to a seventh embodiment of the present invention will be described with reference to FIG.
　図１５は、本発明の第７実施形態に係る半導体回路（半導体装置）の駆動装置の回路構成の例を示す図であり、（ａ）は特性評価用の回路構成を示し、（ｂ）はインバータとして用いる回路の部分構成を示している。 FIG. 15 is a diagram illustrating an example of a circuit configuration of a driving device of a semiconductor circuit (semiconductor device) according to a seventh embodiment of the present invention, where (a) illustrates a circuit configuration for characteristic evaluation, and (b) illustrates The partial structure of the circuit used as an inverter is shown.
　図１５（ａ）、（ｂ）に示すように、例えば下アームを構成するＩＧＢＴ４３（スイッチング素子）に対して、絶縁ゲートを有するダイオード（ゲート制御型ダイオード）４２は、上アームを構成するＩＧＢＴに逆並列に接続される還流ダイオードとして用いられる。 As shown in FIGS. 15A and 15B, for example, with respect to the IGBT 43 (switching element) constituting the lower arm, a diode (gate-controlled diode) 42 having an insulated gate is replaced with an IGBT constituting the upper arm. Used as a freewheeling diode connected in antiparallel.
　そして、制御回路４６、ゲート駆動回路４５、遅延回路ブロック４４によって、ＩＧＢＴ４３と絶縁ゲートを有するダイオード４２は、制御される。 Then, the control circuit 46, the gate drive circuit 45, and the delay circuit block 44 control the IGBT 43 and the diode 42 having an insulated gate.
　なお、遅延回路ブロック４４は、ＩＧＢＴ４３のゲートとダイオード４２のゲートの遅延タイミングを生成する。そして、図１２を参照して第４実施形態において示した通り、対アームのＩＧＢＴ４３がオンして、ダイオード４２がリカバリー状態に至る直前に、ダイオード４２の絶縁ゲート（３：図１）がオフする様に制御している。 Note that the delay circuit block 44 generates the delay timing of the gate of the IGBT 43 and the gate of the diode 42. Then, as shown in the fourth embodiment with reference to FIG. 12, the insulated gate (3: FIG. 1) of the diode 42 is turned off immediately before the IGBT 43 of the pair arm is turned on and the diode 42 reaches the recovery state. It is controlled in the same way.
　なお、遅延回路ブロック４４に備えられる遅延定数回路（不図示）は、抵抗と容量から成るいわゆるＲＣ遅延回路が主なものである。 The delay constant circuit (not shown) provided in the delay circuit block 44 is mainly a so-called RC delay circuit composed of a resistor and a capacitor.
　また、ゲート駆動回路４５は、制御回路４６からの入力を、ＩＧＢＴ４３とダイオード４２のそれぞれのゲートの入力信号に変換するレベルシフト回路の機能が主なものである。 The gate drive circuit 45 mainly has a function of a level shift circuit that converts the input from the control circuit 46 into input signals of the gates of the IGBT 43 and the diode 42, respectively.
　また、本実施形態（第７実施形態）において、図１５（ａ）では、上アームにダイオード４２を配置し、下アームにＩＧＢＴ４３を配置し、インバータ回路を部分的に抽出して記載しているが、実際のインバータには、図１５（ｂ）に示す様に、上アームにもＩＧＢＴが、下アームにもダイオードが配置され、これらに対しても前述の駆動回路網が配置される。 Further, in this embodiment (seventh embodiment), in FIG. 15A, the diode 42 is arranged in the upper arm, the IGBT 43 is arranged in the lower arm, and the inverter circuit is partially extracted and described. However, in the actual inverter, as shown in FIG. 15B, IGBTs are arranged in the upper arm and diodes are arranged in the lower arm, and the above-described drive circuit network is also arranged for these.
　以上の回路構成で制御回路４６が上アームと下アームを統合的に制御することによって、直流電源４０の直流電力（直流電圧）は、交流電力（交流電圧）に変換され、誘導性負荷（例えばモータの一部）４１に交流電力（交流電圧）が供給される。
＜第７実施形態の効果＞
　以上、制御回路４６、ゲート駆動回路４５、遅延回路ブロック４４を備える半導体回路（半導体装置）の駆動装置によって、低損失のインバータ等の電力変換装置が提供できる。
≪第８実施形態：電力変換装置≫
　次に、第１～第３実施形態のいずれかの半導体装置を備えた電力変換装置について説明する。 With the above circuit configuration, the control circuit 46 controls the upper arm and the lower arm in an integrated manner, so that the DC power (DC voltage) of the DC power supply 40 is converted into AC power (AC voltage) and an inductive load (for example, AC power (AC voltage) is supplied to a part of the motor 41.
<Effect of 7th Embodiment>
As described above, a power conversion device such as a low-loss inverter can be provided by a drive device for a semiconductor circuit (semiconductor device) including the control circuit 46, the gate drive circuit 45, and the delay circuit block 44.
«Eighth embodiment: power conversion device»
Next, a power conversion device including any one of the semiconductor devices according to the first to third embodiments will be described.
　図１６は、本発明の第８実施形態に係る電力変換装置の回路構成の例を示す図である。なお、三相交流モータ４８は、電力変換装置に含まれていない。 FIG. 16 is a diagram illustrating an example of a circuit configuration of the power conversion device according to the eighth embodiment of the present invention. Note that the three-phase AC motor 48 is not included in the power converter.
　図１６において、ＩＧＢＴ４３Ｕ（スイッチング素子）と絶縁ゲートを有するダイオード（ゲート制御型ダイオード）４２Ｕとによって上アームが、ＩＧＢＴ４３Ｄ（スイッチング素子）と絶縁ゲートを有するダイオード（ゲート制御型ダイオード）４２Ｄとによって下アームとが構成されている。この上アームと下アームの組によって、１相分の電力変換用のレッグが構成されている。 In FIG. 16, the upper arm is constituted by an IGBT 43U (switching element) and a diode (gate control type diode) 42U having an insulated gate, and the lower arm is constituted by an IGBT 43D (switching element) and a diode (gate control type diode) 42D having an insulated gate. And are configured. The pair of the upper arm and the lower arm constitutes a power conversion leg for one phase.
　この電力変換用のレッグは、３組あって、それぞれＵ相、Ｖ相、Ｗ相の交流電力（交流電圧）を生成する。 There are three sets of legs for power conversion, and generate U-phase, V-phase, and W-phase AC power (AC voltage), respectively.
　３個のＩＧＢＴ４３Ｕと３個のＩＧＢＴ４３Ｄのゲートにはそれぞれ遅延回路ブロック４４（計６個）の出力信号が入力している。 The output signals of the delay circuit block 44 (6 in total) are input to the gates of the three IGBTs 43U and the three IGBTs 43D, respectively.
　また、合計６個のゲート駆動回路４５がそれぞれダイオード４２Ｕ（計３個）とダイオード４２Ｄ（計３個）、および遅延回路ブロック４４（計６個）を駆動している。 In addition, a total of six gate drive circuits 45 drive the diodes 42U (three in total), the diodes 42D (three in total), and the delay circuit blocks 44 (total six).
　また、制御回路４６は、合計６個のゲート駆動回路４５を統合的に制御することにより、直流電源４０の直流電力（直流電圧）は、３相交流電力（３相交流電圧）に変換され、三相交流モータ４８に供給される。
＜第８実施形態の効果＞
　以上、第１～第３実施形態の半導体装置、すなわち絶縁ゲートを有するダイオード４２を、インバータを構成するＩＧＢＴに逆並列に接続される還流ダイオードとして用いることにより、低損失の電力変換装置が提供できる。
≪その他の実施形態≫
　なお、本発明は、以上に説明した実施形態に限定されるものでなく、さらに様々な変形例が含まれる。例えば、前記の実施形態は、本発明をわかりやすく説明するために、詳細に説明したものであり、必ずしも説明したすべての構成を備えるものに限定されるものではない。また、ある実施形態の構成の一部を他の実施形態の構成の一部で置き換えることが可能であり、さらに、ある実施形態の構成に他の実施形態の構成の一部または全部を加えることも可能である。 In addition, the control circuit 46 controls the total of six gate drive circuits 45 so that the DC power (DC voltage) of the DC power supply 40 is converted into three-phase AC power (three-phase AC voltage). The three-phase AC motor 48 is supplied.
<Effects of Eighth Embodiment>
As described above, by using the semiconductor device of the first to third embodiments, that is, the diode 42 having an insulated gate, as a freewheeling diode connected in reverse parallel to the IGBT constituting the inverter, a low-loss power conversion device can be provided. .
<< Other Embodiments >>
In addition, this invention is not limited to embodiment described above, Furthermore, various modifications are included. For example, the above-described embodiment has been described in detail in order to explain the present invention in an easy-to-understand manner, and is not necessarily limited to one having all the configurations described. Further, a part of the configuration of an embodiment can be replaced with a part of the configuration of another embodiment, and further, a part or all of the configuration of the other embodiment is added to the configuration of the certain embodiment. Is also possible.
　以下に、その他の実施形態や変形例について、さらに説明する。
《第２のＰ－型アノード層５とＮ－型ドリフト層７との関係》
　図１に示した第１実施形態、図７に示した第２実施形態、および図９で示した第３実施形態において、キャリアのライフタイムが低減された第２のＰ－型アノード層５と、Ｎ－型ドリフト層７とは接せずに記載されているが、第２のＰ－型アノード層５とＮ－型ドリフト層７とが接していても、同様の効果が得られる。
《アノード電極６と第２のＰ－型アノード層５との関係》
　図１（ａ）に示した第１実施形態において、アノード電極６と第１のＰ－型アノード層４が接触していることを説明したが、それのみならず、アノード電極６と第２のＰ－型アノード層５が接触していてもよい。 Other embodiments and modifications will be further described below.
<< Relationship Between Second P - type Anode Layer 5 and N - type Drift Layer 7 >>
In the first embodiment shown in FIG. 1, the second embodiment shown in FIG. 7, and the third embodiment shown in FIG. 9, the second P − -type anode layer 5 with reduced carrier lifetime and , N - are described without contact from the type drift layer 7, a second P - -type anode layer 5 and the N - even -type drift layer 7 is in contact, the same effect can be obtained.
<< Relationship Between Anode Electrode 6 and Second P - type Anode Layer 5 >>
In the first embodiment shown in FIG. 1A, it has been described that the anode electrode 6 and the first P − -type anode layer 4 are in contact with each other. The P − -type anode layer 5 may be in contact.
　前記したように、第２のＰ－型アノード層５は、第１のＰ－型アノード層４にライフタイムキラーが照射されて形成されるが、照射される位置がアノード電極６の近接した領域にも到達している場合には、アノード電極６と第２のＰ－型アノード層５が接触して形成される。 As described above, the second P − -type anode layer 5 is formed by irradiating the first P − -type anode layer 4 with the lifetime killer, but the irradiated position is a region close to the anode electrode 6. In this case, the anode electrode 6 and the second P − -type anode layer 5 are formed in contact with each other.
　このとき、アノード電極６と第２のＰ－型アノード層５とは、金属－半導体の接触となるので、ショットキー接触あるいは、オーミック接触となる。 At this time, since the anode electrode 6 and the second P − -type anode layer 5 are in metal-semiconductor contact, they are in Schottky contact or ohmic contact.
　特に、アノード電極６と第２のＰ－型アノード層５がショットキー接触している場合にダイオード特性が変化して、この特性が望ましい用途には、この構造を用いることもできる。
《アニール》
　図１３を参照して第５実施形態の半導体製造方法において、ライフタイムキラーの照射により、第１のＰ－型アノード層４の結晶構造にダメージ（結晶欠陥）が生じさせ、キャリアのライフタイムが低減した第２のＰ－型アノード層５を形成する方法について説明した。 In particular, when the anode electrode 6 and the second P − type anode layer 5 are in Schottky contact, the diode characteristics change, and this structure can be used for applications where this characteristic is desirable.
《Annealing》
Referring to FIG. 13, in the semiconductor manufacturing method of the fifth embodiment, the lifetime killer irradiation causes damage (crystal defects) to the crystal structure of first P − -type anode layer 4, and the lifetime of carriers is reduced. The method for forming the reduced second P − -type anode layer 5 has been described.
　この際、第１のＰ－型アノード層４や第２のＰ－型アノード層５にリーク等が生ずるような大きな結晶欠陥が生じている可能性がある場合には、アニール処理を行ってもよい。 At this time, if there is a possibility that a large crystal defect such as leakage occurs in the first P − -type anode layer 4 or the second P − -type anode layer 5, annealing may be performed. Good.
　このアニール処理は、必要以上の結晶欠陥を回復するものであって、かつ、第２のＰ－型アノード層５は、キャリアのライフタイムが低減した状態を保つ程度に行われる必要がある。 This annealing treatment recovers more than necessary crystal defects, and the second P − -type anode layer 5 needs to be performed to such an extent that the lifetime of the carrier is kept reduced.
　そのため、前記のアニール処理は、数１００℃で行われることが望ましい。 Therefore, it is desirable that the annealing process is performed at several hundred degrees Celsius.
　《Ｐ型とＮ型の逆の構成》
　図１において、第１半導体層（Ｎ＋型カソード層）と第２半導体層（Ｎ－型ドリフト層）をＮ型の半導体層で構成し、また、第３半導体層（第１のＰ－型アノード層）と第４半導体層（第２のＰ－型アノード層）をＰ型の半導体層で構成する説明をした。 《P type and N type reverse configuration》
In FIG. 1, a first semiconductor layer (N + -type cathode layer) and a second semiconductor layer (N − -type drift layer) are constituted by N-type semiconductor layers, and a third semiconductor layer (first P − -type) is formed. In the above description, the anode layer) and the fourth semiconductor layer (second P − -type anode layer) are composed of P-type semiconductor layers.
　しかしながら、これらのＰ型とＮ型の半導体の構成を逆にしてもよい。ただし、電源やスイッチング素子の極性を逆にする。また、制御方法もそれらの極性を反映した方法をとる。
《遅延回路ブロック４４とゲート駆動回路４５との関係》
　図１５を参照して第７実施形態の説明では、遅延定数回路を含む遅延回路ブロック４４は、ゲート駆動回路４５の後段に挿入された例を示しているが、ゲート駆動回路４５の前段に配置して、ＩＧＢＴ４３のゲート入力とダイオード４２のゲート入力用に、それぞれゲート駆動回路４５を設ける回路ブロック構成でもよい。
《スイッチング素子》
　図１５、図１６において、スイッチング素子をＩＧＢＴで説明したが、ＭＯＳＦＥＴ（metal-oxide-semiconductor field-effect transistor）やスーパージャンクションＭＯＳＦＥＴの場合でも、同じように、本実施形態の電力変換装置は、有効である。
《絶縁ゲートを有するダイオードを搭載する機器》
　図１５または図１６において、本発明の実施形態に係る半導体装置である絶縁ゲートを有するダイオード４２、４２Ｕ、４２Ｄを、インバータとしての電力変換装置に備えた例を説明したが、これに限定されない。 However, the configurations of these P-type and N-type semiconductors may be reversed. However, the polarity of the power supply or switching element is reversed. Moreover, the control method takes the method reflecting those polarities.
<< Relationship Between Delay Circuit Block 44 and Gate Drive Circuit 45 >>
In the description of the seventh embodiment with reference to FIG. 15, an example in which the delay circuit block 44 including the delay constant circuit is inserted in the subsequent stage of the gate drive circuit 45 is shown. A circuit block configuration in which a gate driving circuit 45 is provided for the gate input of the IGBT 43 and the gate input of the diode 42 may be employed.
<Switching element>
15 and 16, the switching element has been described as an IGBT. However, even in the case of a MOSFET (metal-oxide-semiconductor field-effect transistor) or a super-junction MOSFET, the power converter according to the present embodiment is also effective. It is.
《Equipment equipped with diode with insulated gate》
In FIG. 15 or FIG. 16, the example in which the diodes 42, 42U, and 42D having the insulated gate, which is the semiconductor device according to the embodiment of the present invention, are provided in the power conversion device as the inverter has been described.
　例えば、交流電力を直流電力に変換するコンバータのスイッチング素子（ＩＧＢＴ）に逆並列に接続される還流ダイオードとして、本発明の実施形態に係る半導体装置である絶縁ゲートを有するダイオード４２、４２Ｕ、４２Ｄを備えてもよい。 For example, diodes 42, 42U, and 42D having insulating gates, which are semiconductor devices according to the embodiment of the present invention, are used as a free-wheeling diode connected in reverse parallel to a switching element (IGBT) of a converter that converts AC power into DC power. You may prepare.
　また、電力変換装置に限らず、昇圧回路装置や力率改善装置などの機器に、本発明の実施形態に係る半導体装置である絶縁ゲートを有するダイオード４２、４２Ｕ、４２Ｄを備えてもよい。 Further, not limited to the power conversion device, devices such as a booster circuit device and a power factor correction device may include diodes 42, 42U, and 42D having an insulating gate, which is a semiconductor device according to the embodiment of the present invention.
　１　　絶縁ゲート電極
　２　　ゲート絶縁膜
　３　　絶縁ゲート
　４　　第１のＰ－型アノード層（第３半導体層）
　５　　第２のＰ－型アノード層（第４半導体層）
　６　　アノード電極（第１電極）
　７　　Ｎ－型ドリフト層、第１のＮ－型ドリフト層（第２半導体層）
　８　　Ｎ＋型カソード層（第１半導体層）
　９　　カソード電極（第２電極）
　１０　　金属－半導体接触面
　１４、１５、１７　　ホールキャリア
　１６　　電子キャリア
　３２　　第２のＮ－型ドリフト層（第５半導体層）
　３５　　絶縁ゲート電極、絶縁サイドゲート電極
　３６　　サイドゲート絶縁膜
　３７　　絶縁ゲート、絶縁サイドゲート
　３８　　絶縁膜
　４０　　直流電源
　４１　　誘導性負荷(インダクタンス)
　４２、４２Ｕ、４２Ｄ　　ゲート制御型ダイオード（半導体装置）
　４３、４３Ｕ、４３Ｄ　　ＩＧＢＴ（スイッチング素子）
　４４　　遅延回路ブロック
　４５　　ゲート駆動回路
　４６　　制御回路
　４７　　ダイオード
　４８　　誘導性負荷（モータ）
　１００、２００、３００　　半導体装置 DESCRIPTION OF SYMBOLS 1 Insulated gate electrode 2 Gate insulating film 3 Insulated gate 4 1st P < - > type | mold anode layer (3rd semiconductor layer)
5 Second P − -type anode layer (fourth semiconductor layer)
6 Anode electrode (first electrode)
7 N − type drift layer, first N − type drift layer (second semiconductor layer)
8 N + type cathode layer (first semiconductor layer)
9 Cathode electrode (second electrode)
10 Metal- semiconductor contact surface 14, 15, 17 Hole carrier 16 Electron carrier 32 Second N − -type drift layer (fifth semiconductor layer)
35 Insulated gate electrode, insulated side gate electrode 36 Side gate insulating film 37 Insulated gate, insulated side gate 38 Insulating film 40 DC power supply 41 Inductive load (inductance)
42, 42U, 42D Gate controlled diode (semiconductor device)
43, 43U, 43D IGBT (switching element)
44 Delay circuit block 45 Gate drive circuit 46 Control circuit 47 Diode 48 Inductive load (motor)
100, 200, 300 Semiconductor device

Claims (12)

  1. 　第１導電型の第１半導体層と、
    　前記第１半導体層に隣接し、前記第１半導体層よりも不純物濃度が低い第１導電型の第２半導体層と、
    　前記第２半導体層に隣接する第２導電型の第３半導体層と、
    　前記第３半導体層と電気的に接続された第１電極と、
    　前記第１半導体層と電気的に接続された第２電極と、
    　前記第３半導体層に含まれ、前記第３半導体層よりもキャリアのライフタイムが低減された第２導電型の第４半導体層と、
    　前記第３半導体層に接する絶縁ゲートと、
    を備える、
    ことを特徴とする半導体装置。     A first semiconductor layer of a first conductivity type;
    A second semiconductor layer of a first conductivity type adjacent to the first semiconductor layer and having a lower impurity concentration than the first semiconductor layer;
    A third semiconductor layer of a second conductivity type adjacent to the second semiconductor layer;
    A first electrode electrically connected to the third semiconductor layer;
    A second electrode electrically connected to the first semiconductor layer;
    A fourth semiconductor layer of a second conductivity type, which is included in the third semiconductor layer and has a carrier lifetime reduced as compared with the third semiconductor layer;
    An insulated gate in contact with the third semiconductor layer;
    Comprising
    A semiconductor device.
  2. 　請求項１において、
    　さらに、
    　前記第２半導体層に含まれ、前記第２半導体層よりもキャリアのライフタイムが低減された第１導電型の第５半導体層を備える、
    ことを特徴とする半導体装置。     In claim 1,
    further,
    A fifth semiconductor layer of a first conductivity type, which is included in the second semiconductor layer and has a carrier lifetime lower than that of the second semiconductor layer;
    A semiconductor device.
  3. 　請求項１または請求項２において、
    　前記第４半導体層が前記絶縁ゲートに接している、
    ことを特徴とする半導体装置。     In claim 1 or claim 2,
    The fourth semiconductor layer is in contact with the insulated gate;
    A semiconductor device.
  4. 　請求項３において、
    　前記第３半導体層または前記第４半導体層と、前記第１電極とで接触する面が、ショットキー接合である、
    ことを特徴とする半導体装置。     In claim 3,
    The surface that contacts the third semiconductor layer or the fourth semiconductor layer and the first electrode is a Schottky junction.
    A semiconductor device.
  5. 　請求項１において、
    　前記絶縁ゲートは、複数であり、それぞれトレンチ形状の複数のトレンチ構内に設けられ、
    　前記第３半導体層と前記第４半導体層は、二つの前記絶縁ゲートに挟まれている、
    ことを特徴とする半導体装置。     In claim 1,
    A plurality of the insulated gates, each provided in a plurality of trench-shaped trenches;
    The third semiconductor layer and the fourth semiconductor layer are sandwiched between two insulated gates,
    A semiconductor device.
  6. 　請求項５において、
    　前記絶縁ゲートが設けられた複数のトレンチのそれぞれの幅は、互いに隣接するトレンチの間隔よりも大きい、
    ことを特徴とする半導体装置。     In claim 5,
    The width of each of the plurality of trenches provided with the insulated gate is larger than the interval between adjacent trenches,
    A semiconductor device.
  7. 　請求項１において、
    　前記第１半導体層、第２半導体層、第３半導体層、第４半導体層は、ケイ素もしくは炭化ケイ素を基に構成され、
    　前記絶縁ゲートは二酸化ケイ素から構成されるゲート絶縁膜を有する、
    ことを特徴とする半導体装置。     In claim 1,
    The first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are configured based on silicon or silicon carbide,
    The insulating gate has a gate insulating film made of silicon dioxide;
    A semiconductor device.
  8. 　請求項１に記載の半導体装置において、
    　前記第４半導体層は、前記第３半導体層の内部の所定の領域に、ライフタイムキラーを照射することによって形成される、
    ことを特徴とする半導体装置の製造方法。     The semiconductor device according to claim 1,
    The fourth semiconductor layer is formed by irradiating a predetermined region inside the third semiconductor layer with a lifetime killer.
    A method for manufacturing a semiconductor device.
  9. 　請求項２に記載の半導体装置において、
    　前記第５半導体層は、前記第２半導体層の内部の所定の領域に、ライフタイムキラーを照射することによって形成される、
    ことを特徴とする半導体装置の製造方法。     The semiconductor device according to claim 2,
    The fifth semiconductor layer is formed by irradiating a predetermined region inside the second semiconductor layer with a lifetime killer.
    A method for manufacturing a semiconductor device.
  10. 　請求項８または請求項９において、
    　前記ライフタイムキラーは、へリュウム、またはプロトン、または電子線である、
    ことを特徴とする半導体装置の製造方法。     In claim 8 or claim 9,
    The lifetime killer is helium, proton, or electron beam.
    A method for manufacturing a semiconductor device.
  11. 　請求項１乃至請求項７のいずれか一項に記載の半導体装置を備える、
    ことを特徴とする電力変換装置。     A semiconductor device according to any one of claims 1 to 7, comprising:
    The power converter characterized by the above-mentioned.
  12. 　請求項１１に記載の電力変換装置において、
    　さらに、
    　前記電力変換装置が有するスイッチング素子と絶縁ゲートを有するダイオードを駆動するゲート駆動回路と、
    　前記スイッチング素子と絶縁ゲートを有するダイオードの遅延タイミングを生成する遅延回路ブロックと、
    　前記ゲート駆動回路を統合的に制御する制御回路と、
    を具備した半導体回路の駆動装置を備える、
    ことを特徴とする電力変換装置。     The power conversion device according to claim 11,
    further,
    A gate drive circuit for driving a diode having a switching element and an insulated gate included in the power conversion device;
    A delay circuit block for generating a delay timing of the diode having the switching element and the insulated gate;
    A control circuit for comprehensively controlling the gate driving circuit;
    Comprising a semiconductor circuit drive device comprising:
    The power converter characterized by the above-mentioned.
PCT/JP2017/001622 2016-02-05 2017-01-19 Semiconductor device, method for producing same, and power conversion device using same WO2017135037A1 (en)

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