WO2017128771A1 - 一种栅极驱动电路、驱动方法及显示装置 - Google Patents

一种栅极驱动电路、驱动方法及显示装置 Download PDF

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Publication number
WO2017128771A1
WO2017128771A1 PCT/CN2016/102080 CN2016102080W WO2017128771A1 WO 2017128771 A1 WO2017128771 A1 WO 2017128771A1 CN 2016102080 W CN2016102080 W CN 2016102080W WO 2017128771 A1 WO2017128771 A1 WO 2017128771A1
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Prior art keywords
voltage
transistor
clock signal
gate
terminal
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Ceased
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PCT/CN2016/102080
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English (en)
French (fr)
Inventor
王俊伟
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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Priority to US15/511,335 priority Critical patent/US10019959B2/en
Publication of WO2017128771A1 publication Critical patent/WO2017128771A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0823—Several active elements per pixel in active matrix panels used to establish symmetry in driving, e.g. with polarity inversion
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels

Definitions

  • the present invention relates to the field of display, and in particular to a gate driving circuit, a driving method, and a display device.
  • Liquid crystal displays are widely used in electronic products such as televisions, cell phones, and displays, and generally include a matrix of pixels consisting of pixels arranged in both horizontal and vertical directions.
  • the gate driving circuit outputs a driving signal to scan each pixel of the liquid crystal display row by row, and the data driving circuit inputs the data signal into each pixel of the scanning line to display the liquid crystal display.
  • the gate driving circuit generally includes various transistors (for example, a switching transistor and a driving transistor), and a driving signal output from the gate driving circuit is usually output via one transistor, but it may happen that a transistor that outputs a driving signal is accompanied by leakage Current (especially when the ambient temperature is high), large leakage currents may cause abnormal display of the display device and reduce the display effect of the display device.
  • various transistors for example, a switching transistor and a driving transistor
  • a driving signal output from the gate driving circuit is usually output via one transistor, but it may happen that a transistor that outputs a driving signal is accompanied by leakage Current (especially when the ambient temperature is high), large leakage currents may cause abnormal display of the display device and reduce the display effect of the display device.
  • embodiments of the present invention provide a gate driving circuit, a driving method for the gate driving circuit, and a display device.
  • a gate driving circuit provided by an embodiment of the present invention includes a first driving module, a second driving module, and a first transistor.
  • the first driving module is electrically connected to the first node and has an input signal end, a first clock signal end, a reset signal end, a first voltage end, a second clock signal end, and an output signal end, where the first driving module is used And the voltage of the first node and the output signal end under the control of the first clock signal of the first clock signal end, the reset signal of the reset signal end, and the second clock signal of the second clock signal end The voltage is both aligned with the first voltage of the first voltage terminal.
  • the second driving module is electrically connected to the first node, the first clock signal end and the gate of the first transistor, the second driving module has a third clock signal end and a second voltage end, and the The second driving module is configured to: when the voltage of the first node and the voltage of the output signal terminal are aligned to a first voltage, the first clock signal at the first clock signal end and the third clock signal at the third clock signal end Controlling, the gate voltage of the first transistor is aligned with the second voltage of the second voltage terminal, and the first voltage is different from the second voltage.
  • the first end of the first transistor is connected to the third clock signal end, and the second end is connected to the output signal end.
  • the second driving module includes a driving unit and a second transistor, and a gate and a first end of the second transistor are both connected to the first node, and the second end is opposite to the first transistor The gates are connected.
  • the driving unit is electrically connected to the first clock signal end, the second voltage end, the third clock signal end and the gate of the first transistor, and is configured to be the first clock at the first clock signal end when the second transistor is turned off.
  • the gate voltage of the first transistor is aligned with the second voltage of the second voltage terminal under the control of the signal or the third clock signal of the third clock signal terminal.
  • the driving unit includes a first driving unit and a second driving unit, the first driving unit electrically connecting the first clock signal end and the second voltage end for outputting high at the first clock signal end
  • the first clock signal of the level is aligned with the gate voltage of the first transistor and the second voltage of the second voltage terminal.
  • the second driving unit is electrically connected to the third clock signal end and the second voltage end, and is configured to: when the third clock signal end outputs the third clock signal of the high level, the gate voltage of the first transistor and the second voltage end The second voltage is pulled.
  • the second driving unit includes a sixth transistor and a seventh transistor, and the gate and the first end of the sixth transistor are both connected to the third clock signal terminal, and the second terminal and the seventh transistor are a gate connection; a first end of the seventh transistor is coupled to the second voltage terminal, and a second end is coupled to the gate of the first transistor.
  • the second driving module further includes an eighth transistor, the The gate of the eight transistor is connected to the input signal terminal, the first end is connected to the second end of the third transistor, and the second end is connected to the first voltage end.
  • the second driving module further includes a ninth transistor, the gate of the ninth transistor is connected to the first node, the first end is connected to the second end of the sixth transistor, and the second end Connected to the first voltage terminal.
  • the first driving module is further configured to pull the voltage of the first node to a positive voltage under the control of an input signal of the input signal terminal.
  • the second driving module is further configured to: when a voltage of the first node is a positive voltage, pull a gate voltage of the first transistor to a positive voltage, so that the first The transistor is turned on and outputs a third clock signal of the third clock signal terminal from the signal output terminal.
  • the first voltage and the second voltage are both negative voltages, and the absolute value of the second voltage is greater than an absolute value of the first voltage.
  • Another embodiment of the present invention provides a driving method for a gate driving circuit, the gate driving circuit including a first driving module, a second driving module, and a first transistor, the first driving module being electrically connected to The first node has an input signal terminal, a first clock signal terminal, a reset signal terminal, a first voltage terminal, a second clock signal terminal, and an output signal terminal, and the second driving module is electrically connected to the first node, a clock signal end and a gate of the first transistor, the second driving module has a third clock signal end and a second voltage end, and the first end of the first transistor and the third clock signal end Connected, the second end is connected to the output signal end.
  • the driving method may include the following steps:
  • the first driving module controls the voltage of the first node and the output signal end under the control of the first clock signal of the first clock signal end, the reset signal of the reset signal end, and the second clock signal of the second clock signal end
  • the voltage is both aligned with the first voltage of the first voltage terminal
  • the gate voltage of the first transistor is aligned with the second voltage of the second voltage terminal, the first voltage being different from the second voltage.
  • the method may further comprise the steps of:
  • the first driving module pulls the voltage of the first node to a positive voltage under the control of the input signal of the input signal end;
  • the second driving module pulls the gate voltage of the first transistor to a positive voltage, so that the first transistor is turned on and the third clock signal is turned on.
  • a third clock signal of the terminal is output from the output signal terminal.
  • the second driving module includes a driving unit and a second transistor, and the second transistor is turned on when the voltage of the first node is raised to a positive voltage to pull the gate voltage of the first transistor High is a positive voltage, and is turned off when the voltage of the first node is aligned with the first voltage; when the second transistor is turned off, the first clock signal or the third clock of the driving unit at the first clock signal end The gate voltage of the first transistor is aligned with the second voltage of the second voltage terminal under the control of the third clock signal of the signal terminal.
  • the first voltage and the second voltage are both negative voltages, and the absolute value of the second voltage is greater than an absolute value of the first voltage.
  • Yet another embodiment of the present invention provides a display device, which may include a gate drive circuit as described in any of the foregoing embodiments.
  • the second driving module pulls the gate voltage of the first transistor and the second voltage, because the first voltage Different from the second voltage, the voltage difference between the gate of the first transistor and the output signal terminal is not zero, so that the first transistor can be promoted to be in the cut-off region during the period when the effective driving signal is not provided, and the first is suppressed as much as possible.
  • the leakage current of the transistor can reduce or avoid the display abnormality of the display device due to the leakage current, which is beneficial to improve the display effect.
  • FIG. 1 is a schematic structural diagram of a gate driving circuit according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a gate driving circuit according to another embodiment of the present invention.
  • FIG. 3 is a schematic diagram showing a specific circuit structure of a gate driving circuit according to another embodiment of the present invention.
  • Figure 4 is a timing diagram of signals corresponding to the embodiment shown in Figure 3;
  • FIG. 5 is a flow chart of a driving method for a gate driving circuit according to another embodiment of the present invention.
  • an embodiment of the present invention provides a gate driving circuit including: a first driving module 1 , a second driving module 2 , and a first transistor 3 .
  • the first driving module 1 is electrically connected to the first node PU, and has an input signal terminal Input, a first clock signal terminal CLK1, a reset signal terminal Reset, a first voltage terminal V1, a second clock signal terminal CLK2, and an output signal terminal Output.
  • the first driving module 1 is configured to compare the voltage of the first node PU under the control of the first clock signal of the first clock signal terminal CLK1, the reset signal of the reset signal terminal Reset, and the second clock signal of the second clock signal terminal CLK2.
  • the voltage of the output signal terminal Output is aligned with the first voltage of the first voltage terminal V1.
  • the second driving module 2 is electrically connected to the first node PU, the first clock signal terminal CLK1 and the gate of the first transistor 3.
  • the second driving module 2 has a third clock signal terminal CLK3 and a second voltage terminal V2, and the second driving module 2, when the voltage of the first node PU and the voltage of the output signal terminal Output are pulled to be the first voltage, the first clock signal of the first clock signal terminal CLK1 and the third clock signal of the third clock signal terminal CLK3 Under the control, the gate voltage of the first transistor 3 is aligned with the second voltage of the second voltage terminal V2, and the first voltage is different from the second voltage.
  • the first end of the first transistor 3 is connected to the third clock signal terminal CLK3, and the second end is connected to the output signal terminal Output.
  • the second driving module 2 aligns the gate voltage of the first transistor 3 with the second voltage. Since the first voltage is different from the second voltage, the voltage difference between the gate of the first transistor 3 and the output signal terminal is not zero, and therefore, the leakage current of the first transistor 3 can be reduced or eliminated as much as possible. Helps improve the display.
  • the first transistor 3 may be an N-type transistor, and the source of the first transistor 3 is connected to the output signal terminal Output.
  • the first voltage and the second voltage may both be negative voltages, and the absolute value of the second voltage is greater than the absolute value of the first voltage.
  • the first voltage may be, for example, -8V
  • the second voltage may be, for example, -16V
  • the first voltage may be, for example, -16V
  • the second voltage may be -32V, for example, at this time, the gate of the first transistor 3.
  • the voltage difference Vgs between the source and the source is -8V or -16V, so that the first transistor 3 is in the cut-off region during the period in which no effective driving signal is supplied, which is advantageous in reducing or eliminating the leakage current of the first transistor 3.
  • the numerical values explained above are merely examples of the first voltage, the second voltage, and the voltage difference between the gate and the source of the first transistor 3, and the specific values of the first voltage and the second voltage are not limited thereto.
  • the driving unit E electrically connects the first clock signal terminal CLK1, the second voltage terminal V2, the third clock signal terminal CLK3 and the gate of the first transistor 3 for the first clock signal terminal CLK1 when the second transistor 21 is turned off.
  • the gate voltage of the first transistor 3 and the second voltage of the second voltage terminal V2 are aligned under the control of the first clock signal or the third clock signal of the third clock signal terminal CLK3.
  • the driving unit E includes a first driving unit E1 and a second driving unit E2.
  • the first driving unit E1 is electrically connected to the first clock signal terminal CLK1 and the second voltage terminal V2 for using the gate voltage of the first transistor 3 when the first clock signal terminal CLK1 outputs the first clock signal of the high level.
  • the second voltage of the second voltage terminal V2 is aligned;
  • the second driving unit E2 is electrically connected to the third clock signal terminal CLK3 and the second voltage terminal V2 for outputting a third clock of a high level at the third clock signal terminal CLK3.
  • the signal is aligned with the gate voltage of the first transistor 3 and the second voltage of the second voltage terminal V2.
  • the first driving unit E1 includes a third transistor 22, a fourth transistor 23, and a fifth transistor 24, according to an embodiment of the present invention.
  • the gate of the third transistor 22 is coupled to the first clock signal terminal CLK1
  • the first terminal is coupled to the gate of the fourth transistor 23, and the second terminal is coupled to the first terminal of the fifth transistor 24.
  • the first end of the fourth transistor 23 is connected to the second voltage terminal V2, and the second end is connected to the gate of the first transistor 3.
  • the gate and the second end of the fifth transistor 24 are both connected to the first clock signal output terminal CLK1.
  • the second driving unit E2 includes a sixth transistor 25 and a seventh transistor 26.
  • the gate and the first end of the sixth transistor 25 are both connected to the third clock signal terminal CLK3, and the second terminal is connected to the gate of the seventh transistor 26.
  • the first end of the seventh transistor 26 is connected to the second voltage terminal V2, and the second end is connected to the gate of the first transistor 3.
  • the second transistor 21 When the second transistor 21 is turned off, a high level is outputted at the first clock signal terminal CLK1.
  • the third transistor 22 and the fifth transistor 24 are turned on, so that the fourth transistor 23 is also turned on, and the gate voltage of the first transistor 3 is aligned with the second voltage output by the second voltage terminal V2;
  • the second transistor 21 when the second transistor 21 is turned off, when the third clock signal terminal CLK3 outputs the third clock signal of the high level, the sixth transistor 25 and the seventh transistor 26 are turned on, and the gate voltage of the first transistor 3 is turned on.
  • the second voltage outputted from the second voltage terminal V2 is aligned.
  • the second driving module 2 further includes an eighth transistor 27.
  • the gate of the eighth transistor 27 is connected to the input signal terminal Input, and the first terminal and the third transistor 22 of the second driving module 2 are connected.
  • the second end is connected, and the second end is connected to the first voltage terminal V1.
  • the second driving module 2 further includes a ninth transistor 28, the gate of the ninth transistor 28 is connected to the first node PU, and the first end is connected to the sixth transistor 25 of the second driving module 2. The second end of the ninth transistor 28 is connected to the first voltage terminal V1.
  • the first driving module 1 may include a capacitor C, a tenth transistor 11, an eleventh transistor 12, a twelfth transistor 13, a thirteenth transistor 14, a fourteenth transistor 15, a fifteenth transistor 16, and a Sixteen transistor 17, seventeenth transistor 18, eighteenth transistor 19, nineteenth transistor 31, twentieth transistor 32, twenty-first transistor 33 and twenty-second transistor 34.
  • the gate of the fourteenth transistor 15 is connected to the first node PU, the first end is connected to the gate of the twelfth transistor 13 and the second end of the thirteenth transistor 14, and the second end is connected to the first voltage terminal V1;
  • the gate of the fifteenth transistor 16 is connected to the first node PU, the first end is connected to the second node PD, the second end is connected to the first voltage terminal V1, and the gate of the sixteenth transistor 17 is connected to the second node PD.
  • the first end is connected to the first node PU, the second end is connected to the first voltage terminal V1, the gate of the seventeenth transistor 18 is connected to the reset signal end Reset, the first end is connected to the first node PU, and the second end is connected. Connected to the first voltage terminal V1.
  • the gate of the eighteenth transistor 19 is connected to the first clock signal terminal CLK1, the first end is connected to the signal output terminal Output, the second end is connected to the first voltage terminal V1, and the gate of the nineteenth transistor 31 is connected to the second node.
  • the PD is connected, the first end is connected to the output signal terminal Output, the second end is connected to the first voltage terminal V1, the gate of the twentieth transistor 32 is connected to the reset signal end Reset, and the first end is connected with the output signal terminal Output, the first end
  • the second end is connected to the first voltage terminal V1;
  • the gate of the twenty-first transistor 33 is connected to the second clock signal terminal CLK2, the first end is connected to the output signal terminal Output, and the second end is connected to the first voltage terminal V1;
  • the gate of the twenty-two transistor 34 is connected to the second clock signal terminal CLK2, the first end is connected to the first node PU, the second end is connected to the first voltage terminal V1, and one end of the capacitor C is connected to the first node
  • the first driving module is further configured to pull the voltage of the first node PU to a positive voltage under the control of the input signal of the input signal terminal Input
  • the second driving module is further used in the first
  • the voltage of a node PU is a positive voltage
  • the gate voltage of the first transistor is pulled high to a positive voltage, so that the first transistor 3 is turned on and the third clock signal of the third clock signal terminal CLK3 is output from the signal output terminal.
  • each of the transistors shown in FIG. 3 is an N-type transistor
  • a P-type transistor can also be used to implement the gate drive circuit without departing from the disclosed embodiments of the present invention. principle.
  • the first voltage and the second voltage provided by the first voltage terminal V1 and the second voltage terminal V2 are also different, such that the voltage difference between the gate and source of the first transistor 3 is greater than zero, resulting in P
  • the first transistor 3 of the type is in the cut-off region during the period in which no effective driving signal is supplied, thereby suppressing the leakage current of the first transistor and improving the display effect of the display device.
  • first and second terminals of the transistor referred to herein refer to two terminals of the transistor other than the gate (control terminal), ie, the source and the drain of the transistor, the transistors mentioned The first end and the second end are interchangeable.
  • FIG. 4 illustrates timing signals of a first clock signal terminal CLK1, a second clock signal terminal CLK2, a third clock signal terminal CLK3, a signal input terminal Input, and a reset signal terminal Reset according to an embodiment of the present invention.
  • the timing signal diagram is a timing within a signal period, and one signal period includes six stages of T1, T2, T3, T4, T5, and T6.
  • the first clock signal terminal CLK1 outputs a first clock signal of a high level
  • the second clock signal terminal CKL2 outputs a second clock signal of a low level
  • the output of the third clock signal terminal CLK3 is low.
  • Level third clock signal, input signal input The input signal of the high level is output, and the reset signal of the reset signal end outputs the reset signal of the low level.
  • the thirteenth transistor 14, the eleventh transistor 12, the tenth transistor 11, the eighth transistor 27, the fifth transistor 24, and the nineteenth transistor 31 are all turned on, and the sixth transistor 25 and the seventh transistor are turned on. 26.
  • the seventeenth transistor 18, the twentieth transistor 32, the twenty-first transistor 33, and the twenty-second transistor 34 are all turned off; the voltage of the first node PU is pulled high to the second transistor 21
  • the gate voltage, the gate voltage of the third transistor 22, the gate voltage of the ninth transistor 28, the gate voltage of the fourteenth transistor 15, and the gate voltage of the fifteenth transistor 16 are all pulled high to a high level;
  • the second transistor 21, the third transistor 22, the fourteenth transistor 15, and the fifteenth transistor 16 are all turned on.
  • the gate voltage of the fourth transistor 23, the gate voltage of the seventh transistor 26, the gate voltage of the twelfth transistor 13, the gate voltage of the sixteenth transistor 17, the gate voltage of the eighteenth transistor 19, and The voltage of the second node is pulled down to the low voltage by the first voltage outputted by the first voltage terminal V1, and the fourth transistor 23, the seventh transistor 26, the twelfth transistor 13, the sixteenth transistor 17, and the eighteenth transistor 19 are turned off.
  • the gate voltage of the first transistor 3 is pulled high to a high level
  • the gate voltage of the sixteenth transistor 17 and the gate voltage of the nineteenth transistor 31 are pulled low to a low voltage, and the first transistor 3 is turned on.
  • the sixteenth transistor 17 and the nineteenth transistor 31 are turned off, the output voltage of the output signal terminal Output is pulled to the third clock signal of the low level outputted by the third clock signal terminal, and the capacitor C is charged.
  • the first clock signal terminal CLK1 outputs a low level first clock signal
  • the second clock signal terminal CKL2 outputs a low level second clock signal
  • the third clock signal output terminal CLK3 outputs a high level third signal.
  • the clock signal, the input signal terminal Input outputs a low level input signal
  • the reset signal terminal Reset outputs a low level reset signal.
  • the twenty-transistor 32, the twenty-first transistor 33, and the twenty-second transistor 34 are all turned off, the sixth transistor 25 is turned on, and the voltage of the first node PU is maintained at a high voltage.
  • the gate voltage of the second transistor 21, the gate voltage of the fourteenth transistor 15, the gate voltage of the fifteenth transistor 16 and the gate voltage of the ninth transistor 28 are maintained at a high voltage; the second transistor 21, the fourteenth The transistor 15, the fifteenth transistor 16 and the ninth transistor 28 are turned on, the gate voltage of the first transistor 3 is still pulled high to a high voltage, the voltage of the second node PD is still pulled low to a low voltage, and the seventh transistor 26
  • the gate voltage is pulled low to the low voltage by the first voltage terminal V1; the first transistor 26, the sixteenth transistor 17 and the The nineteen transistor 31 is turned off, and the first transistor 3 is turned on, so that the output voltage of the output signal terminal Output is pulled to the third clock signal of the high level outputted by the third clock signal terminal, since the capacitor C is charged in the T1 phase,
  • the voltage at the end of the capacitor C connected to the first node PU in the T2 phase is raised, so the voltage of the first node PU in the T2 phase is greater than the voltage of the first node
  • the first clock signal terminal CLK1 outputs a high level first clock signal
  • the second clock signal terminal CKL2 outputs a high level second clock signal
  • the third clock signal output terminal CLK3 outputs a low level third.
  • the clock signal, the input signal terminal Input outputs a low level input signal
  • the reset signal terminal Reset outputs a high level reset signal.
  • the tenth transistor 11, the eighth transistor 27, and the sixth transistor 25 are all turned off; and, the eleventh transistor 12, the thirteenth transistor 14, the fifth transistor 24, the eighteenth transistor 19, The seventeen transistor 18, the twentieth transistor 32, the twenty first transistor 33, and the twenty-second transistor 34 are both turned on, such that the voltage of the first node PU, the gate voltage of the second transistor 21, and the ninth transistor 28
  • the gate voltage, the gate voltage of the fourteenth transistor 15, the gate voltage of the fifteenth transistor 16 are aligned with the first voltage outputted by the first voltage terminal V1, and the voltage of the output signal terminal Output is outputted with the first voltage terminal V1.
  • the first voltage is pulled, the gate voltage of the third transistor 22 and the gate voltage of the twelfth transistor 13 are both pulled high to a high voltage; the second transistor 21, the ninth transistor 28, the fourteenth transistor 15, the tenth
  • the five transistors 16 are all turned off, and the third transistor 22 and the twelfth transistor 13 are both turned on; the gate voltage of the fourth transistor 23, the voltage of the second node PD, the gate voltage of the sixteenth transistor 17, and the nineteenth
  • the gate voltage of transistor 31 is pulled high to high
  • a fourth transistor 23, a sixteenth transistor 17, a nineteenth transistor 31 are turned on; the gate voltage of the first transistor 3 is pulled down to a second voltage V2 output from the second voltage terminal.
  • the eighteenth transistor 19, the twentieth transistor 32, the twenty-first transistor 33, the twenty-second transistor 34 are all turned off, and the sixth transistor 25 is turned on; the voltage of the first node PU and the output of the output signal terminal Output Voltage retention and first The voltage is pulled, and the second transistor 21, the ninth transistor 28, the fourteenth transistor 15, the fifteenth transistor 16, the sixteenth transistor 17, the eighteenth transistor 19, and the nineteenth transistor 31 are all turned off, and the seventh transistor
  • the gate voltage of 26 is pulled high to a high voltage, the seventh transistor 26 is turned on, and the gate voltage of the first transistor 3 is aligned with the second voltage outputted by the second voltage terminal.
  • the first clock signal terminal CLK1 outputs a high level first clock signal
  • the second clock signal terminal CKL2 outputs a low level second clock signal
  • the third clock signal output terminal CLK3 outputs a low level third.
  • the clock signal, the input signal terminal Input outputs a low level input signal
  • the reset signal terminal Reset outputs a low level reset signal.
  • the tenth transistor 11, the seventeenth transistor 18, the twentieth transistor 32, the twenty-first transistor 33, the twenty-second transistor 34, the sixth transistor 25, the seventh transistor 26, and the eighth transistor 19 is turned off; and, the thirteenth transistor, the twelfth transistor 13, the eleventh transistor 12, the third transistor 22, the fourth transistor 23, the fifth transistor 24, and the eighteenth transistor 19 are turned on to
  • the voltage of one node PU is aligned with the first voltage outputted by the first voltage terminal V1
  • the voltage of the output signal terminal Output is aligned with the first voltage outputted by the first voltage terminal V1
  • the gate voltage of the first transistor 3 is second.
  • the second voltage outputted by the voltage terminal V2 is aligned. Since the first voltage is at a low level, the second transistor 21, the ninth transistor 28, the fourteenth transistor 15 and the fifteenth transistor 16 are all turned off.
  • the first clock signal terminal CLK1 outputs a low level first clock signal
  • the second clock signal terminal CKL2 outputs a high level second clock signal
  • the third clock signal output terminal CLK3 outputs a high level third signal.
  • the clock signal, the input signal terminal Input outputs a low level input signal
  • the reset signal terminal Reset outputs a low level reset signal.
  • the eighth transistor 27, the eighteenth transistor 19, and the twentieth transistor 32 are all turned off; and the sixth transistor 25, the twenty-first transistor 33, and the twenty-second transistor 34 are both turned on; the voltage of the first node PU And the voltage outputted by the output signal terminal Output is aligned with the first voltage outputted by the first voltage terminal V1, and the second transistor 21, the ninth transistor 28, the fourteenth transistor 15, the fifteenth transistor 16, and the sixteenth transistor 17
  • the eighteenth transistor 19 and the nineteenth transistor 31 are both turned off, the gate voltage of the seventh transistor 26 is pulled high to a high voltage, the seventh transistor 26 is turned on, and the gate voltage and the second voltage of the first transistor 3 are turned on.
  • the second voltage output of the terminal is aligned.
  • the second driving module pulls the gate voltage of the first transistor and the second voltage, and the gate and the output signal end of the first transistor are different because the first voltage is different from the second voltage.
  • the voltage difference between them is not zero, the generation of the leakage current of the first transistor is suppressed, and the display abnormality due to the leakage current can be alleviated or avoided, which is advantageous for improving the display effect.
  • the gate driving circuit may include a first driving module, a second driving module and a first transistor, the first driving module is electrically connected to the first node and has an input signal end, a first clock signal end, a reset signal end, and a first voltage a second clock module and an output signal terminal, the second driving module is electrically connected to the first node, the first clock signal end and the gate of the first transistor, and the second driving module has a third clock And a signal terminal and a second voltage terminal, and the first end of the first transistor is connected to the third clock signal end, and the second end is connected to the output signal end.
  • the driving method may include the following steps:
  • the first driving module sets the voltage of the first node and the output The voltage at the signal terminal is aligned with the first voltage of the first voltage terminal;
  • the first driving module pulls the voltage of the first node to a positive voltage under the control of the input signal of the input signal end;
  • the second driving module pulls the gate voltage of the first transistor to a positive voltage, so that the first transistor is turned on and the third A third clock signal of the clock signal terminal is output from the output signal terminal.
  • the first voltage and the second voltage may both be negative voltages, and the absolute value of the second voltage is greater than the absolute value of the first voltage.
  • the first driving module pulls the voltage of the first node to a positive voltage
  • the second driving module can The gate voltage of the first transistor is pulled high to a positive voltage
  • the first driving module compares the voltage of the first node and the voltage of the output signal terminal with the first voltage of the first voltage terminal, and pulls the gate voltage of the first transistor and the second voltage of the second voltage terminal.
  • the second driving module turns the gate voltage of the first transistor. Straightening with the second voltage, since the first voltage is different from the second voltage, the voltage difference between the gate of the first transistor and the output signal terminal is not zero, thereby suppressing the generation of the leakage current of the first transistor, thereby reducing Or avoid display abnormalities caused by leakage current, which improves the display effect.
  • a person skilled in the art may understand that all or part of the steps of implementing the above embodiments may be completed by hardware, or may be instructed by a program to execute related hardware, and the program may be stored in a computer readable storage medium.
  • the storage medium mentioned may be a read only memory, a magnetic disk or an optical disk or the like.

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Abstract

一种栅极驱动电路、驱动方法及显示装置，能够减轻或缓解由于漏电电流导致的显示设备的显示异常，提高显示效果，所述栅极驱动电路包括第一驱动模块（1）、第二驱动模块（2）和第一晶体管（3）。第一驱动模块（1）电连接第一节点（PU）并具有输入信号端（Input）、第一时钟信号端（CLK1）、复位信号端（Reset）、第一电压端（V1）、第二时钟信号端（CLK2）、和输出信号端（Output）。第一晶体管（3）的第一端与第三时钟信号端（CLK3）连接，第二端与所述输出信号端(Output)连接。第二驱动模块（2）电连接至所述第一节点（PU）、第一时钟信号端（CLK1）和所述第一晶体管（3）的栅极，所述第二驱动模块（2）具有第三时钟信号端（CLK3）和第二电压端（V2）。

Description

一种栅极驱动电路、驱动方法及显示装置
相关申请的交叉引用
本申请要求于2016年1月27日向中国专利局提交的专利申请201610056220.5的优先权利益，并且在此通过引用的方式将该在先申请的内容并入本文。
技术领域
本发明涉及显示领域，特别涉及一种栅极驱动电路、驱动方法及显示装置。
背景技术
液晶显示器广泛应用于电视、手机和显示器等电子产品中，其一般包括由水平和垂直两个方向排列的像素组成的像素矩阵。在显示时，栅极驱动电路输出驱动信号，逐行对液晶显示器的各像素进行扫描，数据驱动电路将数据信号输入到扫描的各行像素中，从而使液晶显示器显示。
栅极驱动电路一般包括各种晶体管(例如，开关晶体管和驱动晶体管)，并且栅极驱动电路输出的驱动信号通常是经由一个晶体管输出，但是，可能发生的是，输出驱动信号的晶体管伴随有漏电电流(特别是在环境温度较高时)，较大的漏电电流可能导致显示设备的异常显示，降低显示设备的显示效果。
发明内容
为了缓解或减轻现有技术中的上述问题，本发明的实施例提供了一种栅极驱动电路、用于栅极驱动电路的驱动方法及显示装置。
本发明的实施例所提供的栅极驱动电路包括第一驱动模块、第二驱动模块和第一晶体管。所述第一驱动模块电连接至第一节点并具有输入信号端、第一时钟信号端、复位信号端、第一电压端、第二时钟信号端和输出信号端，所述第一驱动模块用于在所述第一时钟信号端的第一时钟信号、所述复位信号端的复位信号和所述第二时钟信号端的第二时钟信号的控制下将所述第一节点的电压和所述输出信号端的 电压均与所述第一电压端的第一电压拉齐。所述第二驱动模块电连接至所述第一节点、第一时钟信号端和所述第一晶体管的栅极，所述第二驱动模块具有第三时钟信号端和第二电压端，并且第二驱动模块用于在所述第一节点的电压和所述输出信号端的电压被拉齐为第一电压时，在第一时钟信号端的第一时钟信号和第三时钟信号端的第三时钟信号的控制下，将所述第一晶体管的栅极电压与所述第二电压端的第二电压拉齐，所述第一电压与所述第二电压不同。所述第一晶体管的第一端与所述第三时钟信号端连接，第二端与所述输出信号端连接。
在一些实施例中，所述第二驱动模块包括驱动单元和第二晶体管，所述第二晶体管的栅极和第一端均与所述第一节点相连，第二端与所述第一晶体管的栅极相连。所述驱动单元电连接第一时钟信号端、第二电压端、第三时钟信号端和第一晶体管的栅极，用于当第二晶体管关断时在所述第一时钟信号端的第一时钟信号或第三时钟信号端的第三时钟信号的控制下将第一晶体管的栅极电压与第二电压端的第二电压拉齐。
在一些实施例中，所述驱动单元包括第一驱动单元和第二驱动单元，所述第一驱动单元电连接第一时钟信号端和第二电压端，用于在第一时钟信号端输出高电平的第一时钟信号时将第一晶体管的栅极电压与第二电压端的第二电压拉齐。所述第二驱动单元电连接第三时钟信号端和第二电压端，用于在第三时钟信号端输出高电平的第三时钟信号时将第一晶体管的栅极电压与第二电压端的第二电压拉齐。
在一些实施例中，所述第一驱动单元包括第三晶体管、第四晶体管和第五晶体管，所述第三晶体管的栅极与第一时钟信号端耦接、第一端与第四晶体管的栅极连接，第二端与第五晶体管的第一端连接；所述第四晶体管的第一端与第二电压端连接，第二端与第一晶体管的栅极连接；所述第五晶体管的栅极和第二端均与第一时钟信号输出端连接。
在一些实施例中，所述第二驱动单元包括第六晶体管和第七晶体管，所述第六晶体管的栅极和第一端都与第三时钟信号端连接、第二端与第七晶体管的栅极连接；所述第七晶体管的第一端与第二电压端连接，第二端与第一晶体管的栅极连接。
在一些实施例中，所述第二驱动模块还包括第八晶体管，所述第 八晶体管的栅极与输入信号端连接，第一端与所述第三晶体管的第二端连接，第二端与第一电压端连接。
在一些实施例中，所述第二驱动模块还包括第九晶体管，所述第九晶体管的栅极与第一节点连接，第一端与所述第六晶体管的第二端连接，第二端与第一电压端连接。
在一些实施例中，所述第一驱动模块还用于在所述输入信号端的输入信号的控制下将所述第一节点的电压拉高为正电压。
在一些实施例中，所述第二驱动模块还用于在所述第一节点的电压为正电压时，将所述第一晶体管的栅极电压拉高为正电压，以使所述第一晶体管导通并将所述第三时钟信号端的第三时钟信号从所述信号输出端输出。
在一些实施例中，所述第一电压和第二电压均为负电压，且第二电压的绝对值大于第一电压的绝对值。
本发明的另一实施例提供了一种用于栅极驱动电路的驱动方法，该栅极驱动电路包括第一驱动模块、第二驱动模块和第一晶体管，所述第一驱动模块电连接至第一节点并具有输入信号端、第一时钟信号端、复位信号端、第一电压端、第二时钟信号端和输出信号端，所述第二驱动模块电连接至所述第一节点、第一时钟信号端和所述第一晶体管的栅极，所述第二驱动模块具有第三时钟信号端和第二电压端，并且所述第一晶体管的第一端与所述第三时钟信号端连接，第二端与所述输出信号端连接。所述驱动方法可包括以下步骤：
在第一时钟信号端的第一时钟信号、复位信号端的复位信号和第二时钟信号端的第二时钟信号的控制下，所述第一驱动模块将所述第一节点的电压和所述输出信号端的电压均与所述第一电压端的第一电压拉齐；以及
在所述第一节点的电压和所述输出信号端的电压被拉齐为第一电压时，所述第二驱动模块在第一时钟信号端的第一时钟信号和第三时钟信号端的第三时钟信号的控制下，将所述第一晶体管的栅极电压与所述第二电压端的第二电压拉齐，所述第一电压与所述第二电压不同。
在一些实施例中，所述方法还可包括如下步骤：
第一驱动模块在输入信号端的输入信号的控制下将第一节点的电压拉高为正电压；
在所述第一节点的电压为正电压时，第二驱动模块将所述第一晶体管的栅极电压拉高为正电压，以使所述第一晶体管导通并将所述第三时钟信号端的第三时钟信号从所述输出信号端输出。
在一些实施例中，所述第二驱动模块包括驱动单元和第二晶体管，所述第二晶体管在第一节点的电压拉高为正电压时导通，以将第一晶体管的栅极电压拉高为正电压，并且在第一节点的电压与第一电压拉齐时关断；当第二晶体管关断时，所述驱动单元在所述第一时钟信号端的第一时钟信号或第三时钟信号端的第三时钟信号的控制下将第一晶体管的栅极电压与第二电压端的第二电压拉齐。
在一些实施例中，所述第一电压和第二电压均为负电压，且第二电压的绝对值大于第一电压的绝对值。
本发明的又一实施例提供了一种显示装置，该显示装置可包括如前述实施例中任一实施例所述的栅极驱动电路。
在本发明实施例中，在第一节点的电压和输出信号端的电压均与第一电压拉齐时，第二驱动模块将第一晶体管的栅极电压与第二电压拉齐，由于第一电压与第二电压不同，使得第一晶体管的栅极与输出信号端之间的电压差不为0，从而可以促进第一晶体管在不提供有效的驱动信号期间处于截止区，尽可能地抑制第一晶体管的漏电电流，因而可以减轻或避免由于漏电电流导致的显示设备的显示异常，有利于提高显示效果。
附图说明
图1是本发明的一个实施例提供的栅极驱动电路结构示意图；
图2是本发明的另一实施例提供的栅极驱动电路结构示意图；
图3是本发明的另一实施例提供的栅极驱动电路的具体电路结构示意图；
图4是与图3所示的实施例对应的信号时序图；
图5是本发明的另一实施例提供的用于栅极驱动电路的驱动方法流程图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图 对本发明实施方式作进一步地详细描述。
参见图1，本发明实施例提供了一种栅极驱动电路，包括：第一驱动模块1、第二驱动模块2和第一晶体管3。第一驱动模块1电连接至第一节点PU，并具有输入信号端Input、第一时钟信号端CLK1、复位信号端Reset、第一电压端V1、第二时钟信号端CLK2和输出信号端Output，第一驱动模块1用于在第一时钟信号端CLK1的第一时钟信号、复位信号端Reset的复位信号和第二时钟信号端CLK2的第二时钟信号的控制下将第一节点PU的电压和输出信号端Output的电压均与第一电压端V1的第一电压拉齐。第二驱动模块2电连接第一节点PU、第一时钟信号端CLK1和第一晶体管3的栅极，第二驱动模块2具有第三时钟信号端CLK3和第二电压端V2，第二驱动模块2用于在第一节点PU的电压和输出信号端Output的电压被拉齐为第一电压时，在第一时钟信号端CLK1的第一时钟信号和第三时钟信号端CLK3的第三时钟信号的控制下，将第一晶体管3的栅极电压与第二电压端V2的第二电压拉齐，第一电压与所述第二电压不同。在图1所示的实施例中，第一晶体管3的第一端与第三时钟信号端CLK3连接，第二端与输出信号端Output连接。
在本实施例中，在第一节点PU的电压和输出信号端Output的电压均与第一电压拉齐时，第二驱动模块2将第一晶体管3的栅极电压与第二电压拉齐，由于第一电压与第二电压不同，使得第一晶体管3的栅极与输出信号端Output之间的电压差不为0，因此，可以尽可能地减小或消除第一晶体管3的漏电电流，有利于提高显示效果。在本发明的一个实施例中，第一晶体管3可以为N型晶体管，第一晶体管3的源极连接至输出信号端Output。第一电压和第二电压可均为负电压，且第二电压的绝对值大于第一电压的绝对值。第一电压例如可以为-8V，第二电压例如可以为-16V，替代性地，第一电压例如可以为-16V，第二电压例如可以为-32V，此时，第一晶体管3的栅极和源极之间的电压差Vgs为-8V或者-16V，这样使得第一晶体管3在不提供有效的驱动信号期间处于截止区，有利于减小或消除第一晶体管3的漏电电流。当然，以上说明的数值仅仅是第一电压、第二电压以及第一晶体管3的栅极源极之间的电压差的示例，第一电压和第二电压的具体数值不限于此。
根据本发明的实施例，参见图2，第二驱动模块2包括驱动单元E和第二晶体管21。第二晶体管21的栅极和第一端均与第一节点PU相连，第二端与第一晶体管3的栅极相连。在图2所示的实施例中，第二晶体管21为N型晶体管，因此，其在第一节点PU的电压拉高为正电压时导通，从而将第一晶体管3的栅极电压拉高为正电压，而在第一节点PU的电压与第一电压拉齐时关断。
驱动单元E电连接第一时钟信号端CLK1、第二电压端V2、第三时钟信号端CLK3和第一晶体管3的栅极，用于当第二晶体管21关断时在第一时钟信号端CLK1的第一时钟信号或第三时钟信号端CLK3的第三时钟信号的控制下将第一晶体管3的栅极电压与第二电压端V2的第二电压拉齐。
由于第二晶体管21在关断时能阻止第一晶体管3的栅极与第一节点PU之间的连接，从而在第二晶体管21关断时驱动单元E能够将第一晶体管3的栅极电压与第二电压拉齐。
在本发明的实施例中，参见图2，驱动单元E包括第一驱动单元E1和第二驱动单元E2。第一驱动单元E1电连接第一时钟信号端CLK1、第二电压端V2，其用于在第一时钟信号端CLK1输出高电平的第一时钟信号时将第一晶体管3的栅极电压与第二电压端V2的第二电压拉齐；第二驱动单元E2电连接第三时钟信号端CLK3和第二电压端V2，其用于在第三时钟信号端CLK3输出高电平的第三时钟信号时将第一晶体管3的栅极电压与第二电压端V2的第二电压拉齐。
参见图3，根据本发明的实施例，第一驱动单元E1包括第三晶体管22、第四晶体管23和第五晶体管24。第三晶体管22的栅极与第一时钟信号端CLK1耦接、第一端与第四晶体管23的栅极连接，第二端与第五晶体管24的第一端连接。第四晶体管23的第一端与第二电压端V2连接，第二端与第一晶体管3的栅极连接。第五晶体管24的栅极和第二端均与第一时钟信号输出端CLK1连接。
仍参见图3，第二驱动单元E2包括第六晶体管25和第七晶体管26。第六晶体管25的栅极和第一端均与第三时钟信号端CLK3连接、第二端与第七晶体管26的栅极连接。第七晶体管26的第一端与第二电压端V2连接，第二端与第一晶体管3的栅极连接。
当第二晶体管21关断时，在第一时钟信号端CLK1输出高电平的 第一时钟信号时，第三晶体管22和第五晶体管24导通，使得第四晶体管23也导通，将第一晶体管3的栅极电压与第二电压端V2输出的第二电压拉齐；或者，当第二晶体管21关断时，在第三时钟信号端CLK3输出高电平的第三时钟信号时，第六晶体管25和第七晶体管26导通，将第一晶体管3的栅极电压与第二电压端V2输出的第二电压拉齐。
在一个实施例中，参见图3，第二驱动模块2还包括第八晶体管27，第八晶体管27的栅极与输入信号端Input连接，第一端与第二驱动模块2的第三晶体管22的第二端连接，第二端与第一电压端V1连接。
在一个实施例中，参见图3，第二驱动模块2还包括第九晶体管28，第九晶体管28的栅极与第一节点PU连接，第一端与第二驱动模块2的第六晶体管25的第二端连接，第九晶体管28的第二端与第一电压端V1连接。
参见图3，第一驱动模块1可包括电容C、第十晶体管11、第十一晶体管12、第十二晶体管13、第十三晶体管14、第十四晶体管15、第十五晶体管16、第十六晶体管17、第十七晶体管18、第十八晶体管19、第十九晶体管31、第二十晶体管32、第二十一晶体管33和第二十二晶体管34。
第十晶体管11的栅极和第一端与输入信号端Input连接，第二端与第一节点PU连接；第十一晶体管12的第一端与输入信号端Input连接，栅极与第一时钟信号端CLK1连接，第二端与第一节点PU连接；第十二晶体管13的第一端与第一时钟信号端CLK1连接，栅极与第十四晶体管15的第一端和第三晶体管22的栅极连接，第二端与第二节点PD连接；第十三晶体管14的栅极和第一端与第一时钟信号端CLK1连接，第二端与第三晶体管22的栅极连接。
第十四晶体管15的栅极与第一节点PU连接，第一端与第十二晶体管13的栅极和第十三晶体管14的第二端连接，第二端与第一电压端V1连接；第十五晶体管16的栅极与第一节点PU连接，第一端与第二节点PD连接，第二端与第一电压端V1连接；第十六晶体管17的栅极与第二节点PD连接，第一端与第一节点PU连接，第二端与第一电压端V1连接；第十七晶体管18的栅极与复位信号端Reset连接，第一端与第一节点PU连接，第二端与第一电压端V1连接。
第十八晶体管19的栅极与第一时钟信号端CLK1连接，第一端与信号输出端Output连接，第二端与第一电压端V1连接；第十九晶体管31的栅极与第二节点PD连接，第一端与输出信号端Output连接，第二端与第一电压端V1连接；第二十晶体管32的栅极与复位信号端Reset连接，第一端与输出信号端Output连接，第二端与第一电压端V1连接；第二十一晶体管33的栅极与第二时钟信号端CLK2连接，第一端与输出信号端Output连接，第二端与第一电压端V1连接；第二十二晶体管34的栅极与第二时钟信号端CLK2连接，第一端与第一节点PU连接，第二端与第一电压端V1连接；电容C的一端与第一节点PU连接，另一端与输出信号端Output连接。
因此，在本发明的实施例中，第一驱动模块还可用于在输入信号端Input的输入信号的控制下将第一节点PU的电压拉高为正电压，第二驱动模块还可用于在第一节点PU的电压为正电压时，将第一晶体管的栅极电压拉高为正电压，以使第一晶体管3导通并将第三时钟信号端CLK3的第三时钟信号从信号输出端Output输出。
尽管图3中示出的各个晶体管均为N型晶体管，但是，本领域技术人员能够领会到的是，也可以采用P型晶体管来实施栅极驱动电路，而不背离本发明实施例所揭示的原理。并且在该情形中，第一电压端V1和第二电压端V2提供的第一电压和第二电压也是不同的，使得第一晶体管3的栅极源极之间的电压差大于零，导致P型的第一晶体管3在不提供有效的驱动信号期间处于截止区，从而抑制第一晶体管的漏电电流，改善显示设备的显示效果。
此外，本文提到的晶体管的第一端和第二端指的是晶体管的除了栅极(控制端)之外的两个端子，即，晶体管的源极和漏极，所提到的晶体管的第一端和第二端是可以互换的。
参见图4，图4示出了根据本发明的一个实施例的第一时钟信号端CLK1、第二时钟信号端CLK2、第三时钟信号端CLK3、信号输入端Input和复位信号端Reset的时序信号图。该时序信号图是一个信号周期内的时序，一个信号周期包括T1、T2、T3、T4、T5和T6六个阶段。
在该实施例中，在T1阶段，第一时钟信号端CLK1输出高电平的第一时钟信号，第二时钟信号端CKL2输出低电平的第二时钟信号，第三时钟信号端CLK3输出低电平的第三时钟信号，输入信号端Input 输出高电平的输入信号，复位信号端Reset输出低电平的复位信号。
这样，在T1阶段，第十三晶体管14、第十一晶体管12、第十晶体管11、第八晶体管27、第五晶体管24、第十九晶体管31均导通，第六晶体管25、第七晶体管26、第十七晶体管18、第二十晶体管32、第二十一晶体管33和第二十二晶体管34均关断；第一节点PU的电压被拉高为高电平，第二晶体管21的栅极电压，第三晶体管22的栅极电压、第九晶体管28的栅极电压、第十四晶体管15的栅极电压、第十五晶体管16的栅极电压均被拉高为高电平；第二晶体管21，第三晶体管22，第十四晶体管15，第十五晶体管16均导通。
如此，第四晶体管23的栅极电压、第七晶体管26的栅极电压、第十二晶体管13的栅极电压、第十六晶体管17的栅极电压、第十八晶体管19的栅极电压和第二节点的电压被第一电压端V1输出的第一电压拉低至低电压，第四晶体管23、第七晶体管26、第十二晶体管13、第十六晶体管17、第十八晶体管19关断；第一晶体管3的栅极电压被拉高为高电平，第十六晶体管17的栅极电压和第十九晶体管31的栅极电压被拉低为低电压，第一晶体管3导通，第十六晶体管17和第十九晶体管31关断，输出信号端Output的输出电压被拉至第三时钟信号端输出的低电平的第三时钟信号，以及电容C被充电。
在T2阶段，第一时钟信号端CLK1输出低电平的第一时钟信号，第二时钟信号端CKL2输出低电平的第二时钟信号，第三时钟信号输出端CLK3输出高电平的第三时钟信号，输入信号端Input输出低电平的输入信号，复位信号端Reset输出低电平的复位信号。
这样，在T2阶段，第三晶体管22、第四晶体管23、第十晶体管11、第十一晶体管12、第十三晶体管14、第五晶体管24、第八晶体管27、第十七晶体管18、第二十晶体管32、第二十一晶体管33和第二十二晶体管34均关断，第六晶体管25导通，以及第一节点PU的电压保持为高电压。第二晶体管21的栅极电压、第十四晶体管15的栅极电压、第十五晶体管16的栅极电压和第九晶体管28的栅极电压保持为高电压；第二晶体管21、第十四晶体管15、第十五晶体管16和第九晶体管28导通，第一晶体管3的栅极电压仍被拉高至高电压，第二节点PD的电压仍被拉低至低电压，以及第七晶体管26的栅极电压被第一电压端V1拉低至低电压；第一晶体管26、第十六晶体管17和第 十九晶体管31关断，第一晶体管3导通，这样输出信号端Output的输出电压被拉至第三时钟信号端输出的高电平的第三时钟信号，由于电容C在T1阶段充电，使得在T2阶段电容C与第一节点PU相连的一端的电压被抬升，所以在T2阶段第一节点PU的电压大于在T1阶段第一节点PU的电压。
在T3阶段，第一时钟信号端CLK1输出高电平的第一时钟信号，第二时钟信号端CKL2输出高电平的第二时钟信号，第三时钟信号输出端CLK3输出低电平的第三时钟信号，输入信号端Input输出低电平的输入信号，复位信号端Reset输出高电平的复位信号。
这样，在T3阶段，第十晶体管11、第八晶体管27和第六晶体管25均关断；以及，第十一晶体管12、第十三晶体管14、第五晶体管24、第十八晶体管19、第十七晶体管18、第二十晶体管32、第二十一晶体管33和第二十二晶体管34均导通，使得第一节点PU的电压、第二晶体管21的栅极电压、第九晶体管28的栅极电压、第十四晶体管15的栅极电压、第十五晶体管16的栅极电压与第一电压端V1输出的第一电压拉齐，输出信号端Output的电压与第一电压端V1输出的第一电压拉齐，第三晶体管22的栅极电压和第十二晶体管13的栅极电压均拉高为高电压；第二晶体管21、第九晶体管28、第十四晶体管15、第十五晶体管16均关断，第三晶体管22和第十二晶体管13均导通；第四晶体管23的栅极电压、第二节点PD的电压、第十六晶体管17的栅极电压、第十九晶体管31的栅极电压均被拉高为高电平，第四晶体管23、第十六晶体管17、第十九晶体管31均导通；第一晶体管3的栅极电压拉低至第二电压端V2输出的第二电压。
在T4阶段，第一时钟信号端CLK1输出低电平的第一时钟信号，第二时钟信号端CKL2输出低电平的第二时钟信号，第三时钟信号输出端CLK3输出高电平的第三时钟信号，输入信号端Input输出低电平的输入信号，复位信号端Reset输出低电平的复位信号。
这样，在T4阶段，第十晶体管11、第十一晶体管12、第十二晶体管13、第十三晶体管14、第四晶体管23、第五晶体管24、第八晶体管27、第十七晶体管18、第十八晶体管19、第二十晶体管32、第二十一晶体管33、第二十二晶体管34均关断，以及第六晶体管25导通；第一节点PU的电压和输出信号端Output输出的电压保持与第一 电压拉齐，第二晶体管21、第九晶体管28、第十四晶体管15、第十五晶体管16、第十六晶体管17、第十八晶体管19和第十九晶体管31均关断，第七晶体管26的栅极电压被拉高为高电压，第七晶体管26导通，第一晶体管3的栅极电压与第二电压端输出的第二电压拉齐。
在T5阶段，第一时钟信号端CLK1输出高电平的第一时钟信号，第二时钟信号端CKL2输出低电平的第二时钟信号，第三时钟信号输出端CLK3输出低电平的第三时钟信号，输入信号端Input输出低电平的输入信号，复位信号端Reset输出低电平的复位信号。
这样，在T5阶段，第十晶体管11、第十七晶体管18、第二十晶体管32、第二十一晶体管33、第二十二晶体管34、第六晶体管25、第七晶体管26和第八晶体管19均关断；以及，第十三晶体管、第十二晶体管13、第十一晶体管12、第三晶体管22、第四晶体管23、第五晶体管24、第十八晶体管19导通，以将第一节点PU的电压与第一电压端V1输出的第一电压拉齐，输出信号端Output的电压与第一电压端V1输出的第一电压拉齐以及第一晶体管3的栅极电压与第二电压端V2输出的第二电压拉齐。由于第一电压为低电平，导致第二晶体管21、第九晶体管28、第十四晶体管15和第十五晶体管16均关断。
在T6阶段，第一时钟信号端CLK1输出低电平的第一时钟信号，第二时钟信号端CKL2输出高电平的第二时钟信号，第三时钟信号输出端CLK3输出高电平的第三时钟信号，输入信号端Input输出低电平的输入信号，复位信号端Reset输出低电平的复位信号。
这样，在T6阶段，第三晶体管22、第四晶体管23、第五晶体管24、第十三晶体管14、第十二晶体管13、第十一晶体管12、第十晶体管11、第十七晶体管18、第八晶体管27、第十八晶体管19、第二十晶体管32均关断；以及，第六晶体管25、第二十一晶体管33和第二十二晶体管34均导通；第一节点PU的电压和输出信号端Output输出的电压均与第一电压端V1输出的第一电压拉齐，第二晶体管21、第九晶体管28、第十四晶体管15、第十五晶体管16、第十六晶体管17、第十八晶体管19和第十九晶体管31均关断，第七晶体管26的栅极电压被拉高为高电压，第七晶体管26导通，第一晶体管3的栅极电压与第二电压端输出的第二电压拉齐。
在本发明的上述实施例中，在第一节点的电压和输出信号端的电 压均与第一电压拉齐时，第二驱动模块将第一晶体管的栅极电压与第二电压拉齐，由于第一电压与第二电压不同，使得第一晶体管的栅极与输出信号端之间的电压差不为0，抑制了第一晶体管的漏电电流的产生，可减轻或避免由于漏电电流导致显示异常，有利于提高显示效果。
参见图5，本发明的另一实施例提供了一种用于栅极驱动电路的驱动方法，该栅极驱动电路可以是以上参照图1-图3描述的各个实施例中的栅极驱动电路。该栅极驱动电路可包括第一驱动模块、第二驱动模块和第一晶体管，第一驱动模块电连接至第一节点并具有输入信号端、第一时钟信号端、复位信号端、第一电压端、第二时钟信号端和输出信号端，第二驱动模块电连接至所述第一节点、第一时钟信号端和所述第一晶体管的栅极，所述第二驱动模块具有第三时钟信号端和第二电压端，并且所述第一晶体管的第一端与所述第三时钟信号端连接，第二端与所述输出信号端连接。所述驱动方法可包括以下步骤：
203，在第一时钟信号端的第一时钟信号、复位信号端的复位信号和第二时钟信号端的第二时钟信号的控制下，所述第一驱动模块将所述第一节点的电压和所述输出信号端的电压均与所述第一电压端的第一电压拉齐；以及
204，在所述第一节点的电压和所述输出信号端的电压被拉齐为第一电压时，所述第二驱动模块在第一时钟信号端的第一时钟信号和第三时钟信号端的第三时钟信号的控制下，将所述第一晶体管的栅极电压与所述第二电压端的第二电压拉齐，所述第一电压与所述第二电压不同。
在根据本发明的用于栅极驱动电路的驱动方法的实施例中，该方法还可包括以下步骤：
201，第一驱动模块在输入信号端的输入信号的控制下将第一节点的电压拉高为正电压；以及
202，在所述第一节点的电压为正电压时，第二驱动模块将所述第一晶体管的栅极电压拉高为正电压，以使所述第一晶体管导通并将所述第三时钟信号端的第三时钟信号从所述输出信号端输出。
在本发明的一个实施例中，第一电压和第二电压可均为负电压，且第二电压的绝对值大于第一电压的绝对值。
再次参见图4来说明本发明的用于栅极驱动电路的驱动方法的实施例，在T1和T2阶段，第一驱动模块将第一节点的电压拉高为正电压，第二驱动模块可将第一晶体管的栅极电压拉高为正电压。
在T3至T6阶段，第一驱动模块将第一节点的电压和输出信号端的电压均与第一电压端的第一电压拉齐，将第一晶体管的栅极电压与第二电压端的第二电压拉齐。
在本发明实施例中，在T3至T6阶段，第一驱动模块在将第一节点的电压和输出信号端的电压均与第一电压拉齐时，第二驱动模块将第一晶体管的栅极电压与第二电压拉齐，由于第一电压与第二电压不同，使得第一晶体管的栅极与输出信号端之间的电压差不为0，抑制了第一晶体管的漏电电流的产生，从而减轻或避免由漏电电流导致的显示异常，提高了显示效果。
本领域普通技术人员可以理解实现上述实施例的全部或部分步骤可以通过硬件来完成，也可以通过程序来指令相关的硬件完成，所述的程序可以存储于一种计算机可读存储介质中，上述提到的存储介质可以是只读存储器，磁盘或光盘等。
以上所述仅为本发明的一些实施例，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (15)

  1. 一种栅极驱动电路，所述电路包括：
    第一驱动模块、第二驱动模块和第一晶体管；
    其中所述第一驱动模块电连接至第一节点并具有输入信号端、第一时钟信号端、复位信号端、第一电压端、第二时钟信号端和输出信号端，所述第一驱动模块用于在所述第一时钟信号端的第一时钟信号、所述复位信号端的复位信号和所述第二时钟信号端的第二时钟信号的控制下将所述第一节点的电压和所述输出信号端的电压均与所述第一电压端的第一电压拉齐；
    所述第二驱动模块电连接至所述第一节点、第一时钟信号端和所述第一晶体管的栅极，所述第二驱动模块具有第三时钟信号端和第二电压端，并且第二驱动模块用于在所述第一节点的电压和所述输出信号端的电压被拉齐为第一电压时，在第一时钟信号端的第一时钟信号和第三时钟信号端的第三时钟信号的控制下，将所述第一晶体管的栅极电压与所述第二电压端的第二电压拉齐，所述第一电压与所述第二电压不同，
    并且所述第一晶体管的第一端与所述第三时钟信号端连接，第二端与所述输出信号端连接。
  2. 如权利要求1所述的栅极驱动电路，其中所述第二驱动模块包括驱动单元和第二晶体管，
    所述第二晶体管的栅极和第一端均与所述第一节点相连，第二端与所述第一晶体管的栅极相连，
    所述驱动单元电连接第一时钟信号端、第二电压端、第三时钟信号端和第一晶体管的栅极，用于当第二晶体管关断时在所述第一时钟信号端的第一时钟信号或第三时钟信号端的第三时钟信号的控制下将第一晶体管的栅极电压与第二电压端的第二电压拉齐。
  3. 如权利要求2所述的栅极驱动电路，其中所述驱动单元包括第一驱动单元和第二驱动单元，
    所述第一驱动单元电连接第一时钟信号端和第二电压端，用于在第一时钟信号端输出高电平的第一时钟信号时将第一晶体管的栅极电压与第二电压端的第二电压拉齐；
    所述第二驱动单元电连接第三时钟信号端和第二电压端，用于在第三时钟信号端输出高电平的第三时钟信号时将第一晶体管的栅极电压与第二电压端的第二电压拉齐。
  4. 如权利要求3所述的栅极驱动电路，其中所述第一驱动单元包括第三晶体管、第四晶体管和第五晶体管，
    所述第三晶体管的栅极与第一时钟信号端耦接、第一端与第四晶体管的栅极连接，第二端与第五晶体管的第一端连接；
    所述第四晶体管的第一端与第二电压端连接，第二端与第一晶体管的栅极连接；
    所述第五晶体管的栅极和第二端均与第一时钟信号输出端连接。
  5. 如权利要求3所述的栅极驱动电路，其中所述第二驱动单元包括第六晶体管和第七晶体管，
    所述第六晶体管的栅极和第一端都与第三时钟信号端连接、第二端与第七晶体管的栅极连接；
    所述第七晶体管的第一端与第二电压端连接，第二端与第一晶体管的栅极连接。
  6. 如权利要求4述的栅极驱动电路，其中所述第二驱动模块还包括第八晶体管，所述第八晶体管的栅极与输入信号端连接，第一端与所述第三晶体管的第二端连接，第二端与第一电压端连接。
  7. 如权利要求5所述的栅极驱动电路，其中所述第二驱动模块还包括第九晶体管，所述第九晶体管的栅极与第一节点连接，第一端与所述第六晶体管的第二端连接，第二端与第一电压端连接。
  8. 如权利要求1所述的栅极驱动电路，其中所述第一驱动模块还用于在所述输入信号端的输入信号的控制下将所述第一节点的电压拉高为正电压。
  9. 如权利要求1所述的栅极驱动电路，其中所述第二驱动模块还用于在所述第一节点的电压为正电压时，将所述第一晶体管的栅极电压拉高为正电压，以使所述第一晶体管导通并将所述第三时钟信号端的第三时钟信号从所述信号输出端输出。
  10. 如权利要求1-9中任一项所述的栅极驱动电路，其中所述第一电压和第二电压均为负电压，且第二电压的绝对值大于第一电压的绝对值。
  11. 一种用于栅极驱动电路的驱动方法，所述驱动方法包括：
    在第一时钟信号端的第一时钟信号、复位信号端的复位信号和第二时钟信号端的第二时钟信号的控制下，第一驱动模块将第一节点的电压和输出信号端的电压均与第一电压端的第一电压拉齐；
    在所述第一节点的电压和所述输出信号端的电压被拉齐为第一电压时，第二驱动模块在第一时钟信号端的第一时钟信号和第三时钟信号端的第三时钟信号的控制下，将第一晶体管的栅极电压与第二电压端的第二电压拉齐，所述第一电压与所述第二电压不同。
  12. 如权利要求11所述的驱动方法，其中所述方法还包括：
    第一驱动模块在输入信号端的输入信号的控制下将第一节点的电压拉高为正电压；
    在所述第一节点的电压为正电压时，第二驱动模块将所述第一晶体管的栅极电压拉高为正电压，以使所述第一晶体管导通并将所述第三时钟信号端的第三时钟信号从所述输出信号端输出。
  13. 如权利要求11所述的驱动方法，其中所述第二驱动模块包括驱动单元和第二晶体管，
    所述第二晶体管在第一节点的电压拉高为正电压时导通，以将第一晶体管的栅极电压拉高为正电压，并且在第一节点的电压与第一电压拉齐时关断；
    当第二晶体管关断时，所述驱动单元在所述第一时钟信号端的第一时钟信号或第三时钟信号端的第三时钟信号的控制下将第一晶体管的栅极电压与第二电压端的第二电压拉齐。
  14. 如权利要求11-13中任一项所述的驱动方法，其中所述第一电压和第二电压均为负电压，且第二电压的绝对值大于第一电压的绝对值。
  15. 一种显示装置，包括如权利要求1至10任一项权利要求所述的栅极驱动电路。
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CN103578446A (zh) * 2012-08-08 2014-02-12 三星显示有限公司 扫描驱动设备及其驱动方法
CN203325416U (zh) * 2013-07-03 2013-12-04 深圳市华星光电技术有限公司 阵列基板行驱动电路
CN104392701A (zh) * 2014-11-07 2015-03-04 深圳市华星光电技术有限公司 用于氧化物半导体薄膜晶体管的扫描驱动电路
CN105652537A (zh) * 2016-01-27 2016-06-08 京东方科技集团股份有限公司 一种goa电路、驱动方法及显示装置

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