WO2017128575A1 - Ltps阵列基板的制作方法 - Google Patents

Ltps阵列基板的制作方法 Download PDF

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WO2017128575A1
WO2017128575A1 PCT/CN2016/083563 CN2016083563W WO2017128575A1 WO 2017128575 A1 WO2017128575 A1 WO 2017128575A1 CN 2016083563 W CN2016083563 W CN 2016083563W WO 2017128575 A1 WO2017128575 A1 WO 2017128575A1
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layer
polysilicon layer
polysilicon
array substrate
photoresist
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French (fr)
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贺超
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to US15/115,692 priority Critical patent/US9935137B2/en
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    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
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    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H10D86/0223—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies comprising crystallisation of amorphous, microcrystalline or polycrystalline semiconductor materials
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    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
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    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
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    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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    • G02F1/136236—Active matrix addressed cells for reducing the number of lithographic steps using a grey or half tone lithographic process

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating an LTPS array substrate.
  • LCDs liquid crystal displays
  • Various consumer electronic products such as digital assistants, digital cameras, notebook computers, and desktop computers have become mainstream in display devices.
  • liquid crystal display devices which include a liquid crystal display panel and a backlight module.
  • a liquid crystal display panel comprises a CF (Color Filter) substrate, a thin film transistor (TFT) substrate, a liquid crystal (LC) sandwiched between the color filter substrate and the thin film transistor substrate, and a sealant frame ( Sealant) composition.
  • CF Color Filter
  • TFT thin film transistor
  • LC liquid crystal
  • Sealant sealant frame
  • Low Temperature Poly Silicon is a liquid crystal display technology widely used in small and medium-sized electronic products.
  • Conventional amorphous silicon materials have an electron mobility of about 0.5-1.0 cm 2 /VS, while low-temperature polysilicon has an electron mobility of 30-300 cm 2 /VS. Therefore, the low-temperature polycrystalline silicon liquid crystal display has many advantages such as high resolution, fast reaction speed, and high aperture ratio.
  • a method for fabricating a conventional CMOS (Complementary Metal Oxide Semiconductor) LTPS array substrate includes the following steps:
  • Step 1 as shown in FIG. 1 , a substrate 100 is provided, and an NMOS (Negative Channel Metal Oxide Semiconductor) region and a PMOS (Positive Channel Metal Oxide Semiconductor) are defined on the substrate 100 .
  • a first semiconductor layer is deposited on the substrate 100, and the first metal layer is patterned by a photolithography process to obtain a light Shield layer 200 located in the NMOS region;
  • Step 2 as shown in FIG. 2, a buffer layer 300 and an amorphous silicon (a-Si) layer are sequentially deposited on the substrate 100, and the amorphous silicon (a-Si) is formed by an excimer laser annealing process (ELA).
  • ELA excimer laser annealing process
  • the layer is converted into a polysilicon (poly-Si) layer, and the polysilicon layer is patterned by a photolithography process to obtain a first polysilicon layer 410 in the NMOS region and a second polysilicon layer in the PMOS region.
  • a buffer layer 300 and an amorphous silicon (a-Si) layer are sequentially deposited on the substrate 100, and the amorphous silicon (a-Si) is formed by an excimer laser annealing process (ELA).
  • ELA excimer laser annealing process
  • the layer is converted into a polysilicon (poly-Si) layer, and the polysilicon layer is patterned by
  • Step 3 as shown in FIG. 3, applying a first photoresist layer 510 on the first polysilicon layer 410, the second polysilicon layer 420, and the buffer layer 300, and using the photomask to the first photoresist After the layer 510 is exposed and developed, the first polysilicon layer 410 of the NMOS region is doped with a channel;
  • Step 4 as shown in FIG. 4, coating a second photoresist layer 520 on the first polysilicon layer 410, the second polysilicon layer 420, and the buffer layer 300, and using the photomask to the second photoresist After the layer 520 is exposed and developed, N-type heavily doping is performed on both ends of the first polysilicon layer 410 of the NMOS region;
  • Step 5 sequentially depositing a gate insulating layer 600 and a second metal layer on the first polysilicon layer 410, the second polysilicon layer 420, and the buffer layer 300, The two metal layers are patterned to obtain a first gate 710 and a second gate 720 respectively corresponding to the first polysilicon layer 410 and the second polysilicon layer 420; the first gate 710 is used as a mask Performing N-type light doping on the first polysilicon layer 410;
  • Step 6 as shown in FIG. 6 , applying a third photoresist layer 800 on the first gate 710 , the second gate 720 , and the gate insulating layer 600 , and using the photomask to the third photoresist layer 800 After performing exposure and development, P-type heavily doping is performed on both sides of the second polysilicon layer 420;
  • Step 7 sequentially forming an interlayer insulating layer, a source/drain layer, a planarization layer, a common electrode layer, a passivation protective layer, and the like on the first gate 710, the second gate 720, and the gate insulating layer 600. And a structure such as a pixel electrode layer.
  • the channel doping and the N-type heavily doping of the first polysilicon layer 410 of the NMOS region and the P-type heavily doping of the second polysilicon layer 420 of the PMOS region are performed.
  • the galvanic process is required for doping.
  • a total of three masks are required, which is cumbersome in process and high in production cost. Therefore, it is necessary to provide a method for fabricating an LTPS array substrate to solve the technical problem.
  • An object of the present invention is to provide a method for fabricating an LTPS array substrate, which can effectively reduce the fabrication cost of the LTPS array substrate, and the obtained LTPS array substrate has good electrical properties.
  • the present invention provides a method for fabricating an LTPS array substrate, comprising the following steps:
  • Step 1 Providing a substrate, defining an NMOS region and a PMOS region on the substrate, depositing a first metal layer on the substrate, and patterning the first metal layer to obtain a light shielding layer located in the NMOS region ;
  • Step 2 forming a buffer layer on the light shielding layer and the substrate, depositing an amorphous silicon layer on the buffer layer, and converting the amorphous silicon layer into a polysilicon layer by a low temperature crystallization process, and the polycrystalline layer
  • the silicon layer is patterned to obtain a first polysilicon layer in the NMOS region and a second polysilicon layer in the PMOS region;
  • Step 3 applying a photoresist layer on the first polysilicon layer, the second polysilicon layer, and the buffer layer, and exposing and developing the photoresist layer by using a halftone mask.
  • the photoresist layer is ashed by a dry etching process, and the thickness of the photoresist layer is thinned, so that the first recess is converted into a second via hole to expose both ends of the first polysilicon layer.
  • N-type heavily doping is performed on both ends of the first polysilicon layer to obtain two N-type heavily doped regions;
  • the remaining photoresist layer is completely stripped by a photoresist stripping process to expose the first polysilicon layer and the second polysilicon layer, and the first polysilicon layer and the second polysilicon layer are P-type Lightly doped to achieve channel doping of the first polysilicon layer.
  • the manufacturing method of the LTPS array substrate further includes the following steps:
  • Step 4 depositing a gate insulating layer on the first polysilicon layer, the second polysilicon layer, and the buffer layer, and depositing a second metal layer on the gate insulating layer, the second metal
  • the layer is patterned to obtain first gates and second gates respectively corresponding to the first polysilicon layer and the second polysilicon layer;
  • the first plurality Forming a first channel region on a region of the crystalline silicon layer between the two N-type lightly doped regions;
  • Step 5 depositing an interlayer insulating layer on the first gate, the second gate, and the gate insulating layer, and patterning the interlayer insulating layer and the gate insulating layer to obtain the N a first via above the heavily doped region and a second via above the heavily doped region;
  • Step 6 Depositing a third metal layer on the interlayer insulating layer, and patterning the third metal layer to obtain a first source, a first drain, a second source, and a second drain.
  • the first source and the first drain are respectively in contact with the N-type heavily doped region through the first via, and the second source and the second drain are heavily doped with the P-type through the second via, respectively Area contact
  • Step 7 forming a flat layer on the first source, the first drain, the second source, the second drain, and the interlayer insulating layer, and patterning the flat layer to obtain the a third via above the first drain;
  • Step 8 depositing a first transparent conductive oxide layer on the flat layer, and patterning the first transparent conductive oxide layer to obtain a common electrode;
  • Step 9 Depositing a passivation protective layer on the common electrode and the flat layer, the passivation protective layer coating a third via on the flat layer, and then patterning the passivation protective layer Obtaining a fourth via hole on the passivation protective layer at the bottom of the third via hole;
  • Step 10 depositing a second transparent conductive oxide layer on the passivation protective layer, and patterning the second transparent conductive oxide layer to obtain a pixel electrode, wherein the pixel electrode passes through the fourth via and the A drain contacts.
  • the low temperature crystallization process is an excimer laser annealing method or a metal induced lateral crystallization method.
  • the implanted ions in the P-type heavily doped process are boron ions, and the implant dose is 1*10 15 /cm 2 ;
  • the ions implanted in the N-type heavily doped process are Phosphorus ions were implanted at a dose of 4*10 14 /cm 2 ;
  • the ions implanted in the P-type light doping process were boron ions, and the implantation dose was 2*10 12 /cm 2 .
  • the ions implanted in the N-type light doping process are phosphorus ions, and the implantation dose is 1.5*10 13 /cm 2 .
  • the step 5 further includes: performing dehydrogenation and activation treatment on the interlayer insulating layer.
  • the interlayer insulating layer is subjected to dehydrogenation and activation treatment using a rapid thermal annealing process.
  • the substrate is a glass substrate; the material of the first metal layer, the second metal layer and the third metal layer is a stack combination of one or more of molybdenum, titanium, aluminum, copper; the buffer layer and the gate
  • the pole insulating layer, the interlayer insulating layer, and the passivation protective layer are a silicon oxide layer, a silicon nitride layer, or a composite layer composed of a silicon oxide layer and a silicon nitride layer; the flat layer is an organic photoresist material.
  • the material of the first transparent conductive oxide layer and the second transparent conductive oxide layer is a metal oxide.
  • the metal oxide is indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, or indium antimony zinc oxide.
  • the invention also provides a method for manufacturing an LTPS array substrate, comprising the following steps:
  • Step 1 Providing a substrate, defining an NMOS region and a PMOS region on the substrate, depositing a first metal layer on the substrate, and patterning the first metal layer to obtain a light shielding layer located in the NMOS region ;
  • Step 2 forming a buffer layer on the light shielding layer and the substrate, depositing an amorphous silicon layer on the buffer layer, converting the amorphous silicon layer into a polysilicon layer by a low temperature crystallization process, and performing the polysilicon layer on the polysilicon layer Graphic processing to obtain a first polysilicon layer in the NMOS region and a second polysilicon layer in the PMOS region;
  • Step 3 applying a photoresist layer on the first polysilicon layer, the second polysilicon layer, and the buffer layer, and exposing and developing the photoresist layer by using a halftone mask.
  • the photoresist layer is ashed by a dry etching process, and the thickness of the photoresist layer is thinned, so that the first recess is converted into a second via hole to expose both ends of the first polysilicon layer.
  • N-type heavily doping is performed on both ends of the first polysilicon layer to obtain two N-type heavily doped regions;
  • the remaining photoresist layer is completely stripped by a photoresist stripping process to expose the first polysilicon layer and the second polysilicon layer, and the first polysilicon layer and the second polysilicon layer are P-type Lightly doping to achieve channel doping of the first polysilicon layer;
  • Step 4 depositing a gate insulating layer on the first polysilicon layer, the second polysilicon layer, and the buffer layer, and depositing a second metal layer on the gate insulating layer, the second metal
  • the layer is patterned to obtain first gates and second gates respectively corresponding to the first polysilicon layer and the second polysilicon layer;
  • the first plurality Forming a first channel region on a region of the crystalline silicon layer between the two N-type lightly doped regions;
  • Step 5 depositing an interlayer insulating layer on the first gate, the second gate, and the gate insulating layer, and patterning the interlayer insulating layer and the gate insulating layer to obtain the N a first via above the heavily doped region and a second via above the heavily doped region;
  • Step 6 Depositing a third metal layer on the interlayer insulating layer, and patterning the third metal layer to obtain a first source, a first drain, a second source, and a second drain.
  • the first source and the first drain are respectively in contact with the N-type heavily doped region through the first via, and the second source and the second drain are heavily doped with the P-type through the second via, respectively Area contact
  • Step 7 forming a flat layer on the first source, the first drain, the second source, the second drain, and the interlayer insulating layer, and patterning the flat layer to obtain the a third via above the first drain;
  • Step 8 depositing a first transparent conductive oxide layer on the flat layer, and patterning the first transparent conductive oxide layer to obtain a common electrode;
  • Step 9 depositing a passivation protective layer on the common electrode and the flat layer, the passivation protection Laminating a third via on the planar layer, and then patterning the passivation protective layer to obtain a fourth via located on the passivation protective layer at the bottom of the third via;
  • Step 10 depositing a second transparent conductive oxide layer on the passivation protective layer, and patterning the second transparent conductive oxide layer to obtain a pixel electrode, wherein the pixel electrode passes through the fourth via and the a drain contact;
  • the low temperature crystallization process is an excimer laser annealing method or a metal induced lateral crystallization method
  • the ions implanted in the P-type heavily doping process are boron ions, and the implantation dose is 1*10 15 /cm 2 ; the implanted in the N-type heavily doped process The ions are phosphorus ions, and the implantation dose is 4*10 14 /cm 2 ; the ions implanted in the P-type light doping process are boron ions, and the implantation dose is 2*10 12 /cm 2 .
  • the present invention provides a method for fabricating an LTPS array substrate by using a halftone mask to N-type heavily doped and channel doped the first polysilicon layer of the NMOS region, and PMOS
  • the P-type heavily doping of the second polysilicon layer of the zone originally required three reticle processes to be integrated into a reticle process, saving two exposure processes, greatly increasing the exposure capacity, and saving two masks.
  • the manufacturing cost can effectively reduce the manufacturing cost of the LTPS array substrate, and the obtained LTPS array substrate has good electrical properties.
  • step 1 is a schematic diagram of step 1 of a method for fabricating a conventional LTPS array substrate
  • step 2 is a schematic diagram of step 2 of a method for fabricating a conventional LTPS array substrate
  • step 3 is a schematic diagram of step 3 of a method for fabricating a conventional LTPS array substrate
  • step 4 is a schematic diagram of step 4 of a method for fabricating a conventional LTPS array substrate
  • step 5 is a schematic diagram of step 5 of a method for fabricating a conventional LTPS array substrate
  • step 6 is a schematic diagram of step 6 of a method for fabricating a conventional LTPS array substrate
  • step 1 is a schematic diagram of step 1 of a method for fabricating an LTPS array substrate of the present invention
  • step 2 is a schematic diagram of step 2 of a method for fabricating an LTPS array substrate of the present invention
  • 9A-9C are schematic diagrams showing the third step of the method for fabricating the LTPS array substrate of the present invention.
  • step 4 is a schematic diagram of step 4 of a method for fabricating an LTPS array substrate of the present invention
  • step 5 is a schematic diagram of step 5 of a method for fabricating an LTPS array substrate of the present invention.
  • step 6 is a schematic diagram of step 6 of a method for fabricating an LTPS array substrate of the present invention.
  • step 8 is a schematic diagram of step 8 of a method for fabricating an LTPS array substrate of the present invention.
  • step 9 is a schematic diagram of step 9 of a method for fabricating an LTPS array substrate of the present invention.
  • 16 is a schematic view showing the step 10 of the method for fabricating the LTPS array substrate of the present invention.
  • the present invention provides a method for fabricating an LTPS array substrate, including the following steps:
  • Step 1 as shown in FIG. 7, a substrate 10 is provided, an NMOS region and a PMOS region are defined on the substrate 10, a first metal layer is deposited on the substrate 10, and the first metal layer is patterned. Processing results in a light shielding layer 20 located in the NMOS region.
  • Step 2 as shown in FIG. 8, a buffer layer 30 is formed on the light shielding layer 20 and the substrate 10, an amorphous silicon layer is deposited on the buffer layer 30, and the amorphous silicon layer is transformed by a low temperature crystallization process.
  • the polysilicon layer is patterned to obtain a first polysilicon layer 40 in the NMOS region and a second polysilicon layer 90 in the PMOS region.
  • the low temperature crystallization process may be Excimer Laser Annealing (ELA) or Metal Induced Lateral Crystallization (MILC).
  • ELA Excimer Laser Annealing
  • MILC Metal Induced Lateral Crystallization
  • Step 3 as shown in FIG. 9A, applying a photoresist layer 33 on the first polysilicon layer 40, the second polysilicon layer 90, and the buffer layer 30, and using a halftone mask to the light After the resist layer 33 is exposed and developed, a first via hole 331 corresponding to both ends of the second polysilicon layer 90 is formed on the photoresist layer 33, and two of the second polysilicon layer 90 are exposed.
  • first recess 333 corresponding to the two ends of the first polysilicon layer 40 on the photoresist layer 33; using the photoresist layer 33 as a mask, the second polysilicon P-type heavily doped at both ends of layer 90 to obtain two P-type heavily doped regions 91, and a region between the two P-type heavily doped regions 91 on the second polysilicon layer 90 forms a second channel District 92;
  • the photoresist layer 33 is ashed by a dry etching process, and the thickness of the photoresist layer 33 is thinned, so that the first recess 333 is converted into the second via 335, exposing the Both ends of the first polysilicon layer 40, the photoresist layer 33 is used as a mask, and the first polysilicon layer 40 is N-type heavily doped at both ends to obtain two N-type heavily doped regions 41;
  • the remaining photoresist layer 33 is completely stripped by a photoresist stripping process to expose the first polysilicon layer 40 and the second polysilicon layer 90, to the first polysilicon layer 40, And the second polysilicon layer 90 is P-type lightly doped to achieve channel doping of the first polysilicon layer 40.
  • the implanted ions in the P-type heavily doped process are boron (B) ions, and the implant dose is 1*10 15 /cm 2 ;
  • the N-type heavily doped process The implanted ions are phosphorus (P) ions with an implant dose of 4*10 14 /cm 2 ;
  • the ions implanted in the P-type light doping process are boron (B) ions, and the implant dose is 2 *10 12 / cm 2 .
  • the implant dose is sequentially reduced according to the order of implantation, and the implant dose is the first to be doped first, which can reduce the influence of the doping element on the previously doped region.
  • the step 3 is to dope the N-type heavily doped and channel doping of the first polysilicon layer 40 of the NMOS region and the second polysilicon layer of the PMOS region by using a halftone mask.
  • 90 P-type heavily doped three original three-mask process required to integrate into a mask process saving two exposure processes, greatly improving the exposure capacity, while saving the cost of two masks, effective Reduce the manufacturing cost of the LTPS array substrate.
  • Step 4 depositing a gate insulating layer 51 on the first polysilicon layer 40, the second polysilicon layer 90, and the buffer layer 30, depositing on the gate insulating layer 51 a second metal layer, the second metal layer is patterned to obtain a first gate 52 and a second gate 93 respectively corresponding to the first polysilicon layer 40 and the second polysilicon layer 90;
  • the first polysilicon layer 40 is lightly doped N-type by using the first gate 52 as a photomask, and two N-type lightly doped regions 43 respectively located inside the two N-type heavily doped regions 41 are obtained. A region of the first polysilicon layer 40 between the two N-type lightly doped regions 43 forms a first channel region 42.
  • the ions implanted in the N-type light doping process are phosphorus (P) ions, and the implantation dose is 1.5*10 13 /cm 2 .
  • Step 5 as shown in FIG. 11, an interlayer insulating layer 53 is deposited on the first gate 52, the second gate 93, and the gate insulating layer 51, and the interlayer insulating layer 53 and the gate are insulated.
  • the layer 51 is patterned to obtain a first via 55 located above the N-type heavily doped region 41 and a second via 95 above the P-type heavily doped region 91, and then to the interlayer
  • the insulating layer 53 is subjected to dehydrogenation and activation treatment.
  • the interlayer insulating layer 53 is subjected to dehydrogenation and activation treatment using a Rapid Thermal Annealing (RTA) process.
  • RTA Rapid Thermal Annealing
  • Step 6 depositing a third metal layer on the interlayer insulating layer 53, and patterning the third metal layer to obtain a first source 61, a first drain 62, and a first Two source 96, the second drain 97, the first source 61 and the first drain 62 are respectively in contact with the N-type heavily doped region 41 through the first via 55, the second source 96 and the second drain
  • the poles 97 are in contact with the P-type heavily doped region 91 through the second via 95, respectively.
  • Step 7 as shown in FIG. 13, forming a flat layer 70 on the first source 61, the first drain 62, the second source 96, the second drain 97, and the interlayer insulating layer 53.
  • the flat layer 70 is patterned to obtain a third via 71 above the first drain 62.
  • Step 8 As shown in FIG. 14, a first transparent conductive oxide layer is deposited on the flat layer 70, and the first transparent conductive oxide layer is patterned to obtain a common electrode 80.
  • Step 9 As shown in FIG. 15, a passivation protective layer 81 is deposited on the common electrode 80 and the flat layer 70, and the passivation protective layer 81 covers the third via 71 on the flat layer 70. Then, the passivation protective layer 81 is patterned to obtain a fourth via 85 on the passivation protective layer 81 at the bottom of the third via 71.
  • Step 10 depositing a second transparent conductive oxide layer on the passivation protective layer 81, and patterning the second transparent conductive oxide layer to obtain a pixel electrode 82.
  • the electrode 82 is in contact with the first drain 62 through the fourth via 85.
  • the substrate 10 is a transparent substrate, preferably a glass substrate.
  • the material of the first metal layer, the second metal layer, and the third metal layer is a stack of one or more of molybdenum (Mo), titanium (Ti), aluminum (Al), and copper (Cu). combination.
  • the flat layer 70 is an organic photoresist material.
  • the material of the first transparent conductive oxide layer and the second transparent conductive oxide layer is a metal oxide such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium. Zinc oxide, or other suitable oxide.
  • the present invention provides a method for fabricating an LTPS array substrate by using a halftone mask to N-type heavily doped and channel doped the first polysilicon layer of the NMOS region, and the PMOS region.
  • the P-type heavily doped of the second polysilicon layer originally required three reticle processes to be integrated into a reticle process, saving two exposure processes, greatly increasing the exposure capacity, and saving two masks.
  • the manufacturing cost can effectively reduce the manufacturing cost of the LTPS array substrate, and the obtained LTPS array substrate has good electrical properties.

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Abstract

一种LTPS阵列基板的制作方法，通过采用一道半色调光罩将NMOS区的第一多晶硅层（40）的N型重掺杂与沟道掺杂、及PMOS区的第二多晶硅层（90）的P型重掺杂这三道原本需要三道光罩的制程整合到一道光罩制程中，节省两道曝光制程，大大提升曝光产能，同时节省了两张光罩的制作成本，可有效降低LTPS阵列基板的制作成本，制得的LTPS阵列基板具有良好的电学性能。

Description

LTPS阵列基板的制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种LTPS阵列基板的制作方法。
背景技术
随着显示技术的发展，液晶显示器(Liquid Crystal Display，LCD)等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
现有市场上的液晶显示装置大部分为背光型液晶显示器，其包括液晶显示面板及背光模组(backlight module)。通常液晶显示面板由彩膜(CF，Color Filter)基板、薄膜晶体管(TFT，Thin Film Transistor)基板、夹于彩膜基板与薄膜晶体管基板之间的液晶(LC，Liquid Crystal)及密封胶框(Sealant)组成。
低温多晶硅(Low Temperature Poly Silicon，LTPS)是广泛用于中小电子产品中的一种液晶显示技术。传统的非晶硅材料的电子迁移率约0.5-1.0cm2/V.S，而低温多晶硅的电子迁移率可达30-300cm2/V.S。因此，低温多晶硅液晶显示器具有高解析度、反应速度快、高开口率等诸多优点。
但是另一方面，由于LTPS半导体器件的体积小、集成度高，所以整个LTPS阵列基板的制备工艺复杂，生产成本较高。
如图1-6所示，为现有的CMOS(Complementary Metal Oxide Semiconductor，互补金属氧化物半导体)LTPS阵列基板的制作方法，包括如下步骤：
步骤1、如图1所示，提供一基板100，在所述基板100上定义出NMOS(Negative channel Metal Oxide Semiconductor，N型金属氧化物半导体)区与PMOS(Positive channel Metal Oxide Semiconductor，P型金属氧化物半导体)区；在所述基板100上沉积第一金属层，采用光刻制程对所述第一金属层进行图形化处理，得到位于NMOS区的遮光(Light Shield)层200；
步骤2、如图2所示，在所述基板100上依次沉积缓冲层300与非晶硅(a-Si)层，通过准分子激光退火工艺(ELA)将所述非晶硅(a-Si)层转化为多晶硅(poly-Si)层，采用光刻制程对所述多晶硅层进行图形化处理，得到位于NMOS区的第一多晶硅层410、及位于PMOS区的第二多晶硅层 420；
步骤3、如图3所示，在所述第一多晶硅层410、第二多晶硅层420、及缓冲层300上涂布第一光阻层510，利用光罩对第一光阻层510进行曝光、显影后，对NMOS区的第一多晶硅层410进行沟道(Channel)掺杂；
步骤4、如图4所示，在所述第一多晶硅层410、第二多晶硅层420、及缓冲层300上涂布第二光阻层520，利用光罩对第二光阻层520进行曝光、显影后，对NMOS区的第一多晶硅层410的两端进行N型重掺杂；
步骤5、如图5所示，在所述第一多晶硅层410、第二多晶硅层420、及缓冲层300上依次沉积栅极绝缘层600和第二金属层，对所述第二金属层进行图形化处理，得到分别对应于第一多晶硅层410与第二多晶硅层420上方的第一栅极710与第二栅极720；以第一栅极710为掩模对所述第一多晶硅层410进行N型轻掺杂；
步骤6、如图6所示，在所述第一栅极710、第二栅极720、及栅极绝缘层600上涂布第三光阻层800，利用光罩对第三光阻层800进行曝光、显影后，对所述第二多晶硅层420的两侧进行P型重掺杂；
步骤7、在所述第一栅极710、第二栅极720、及栅极绝缘层600上依次制作层间绝缘层、源漏极层、平坦化层、公共电极层、钝化保护层、及像素电极层等结构。
上述LTPS阵列基板的制作方法中，NMOS区的第一多晶硅层410的沟道掺杂与N型重掺杂、及PMOS区的第二多晶硅层420的P型重掺杂这三道制程均需要使用光刻工艺进行掺杂，共需要三道光罩，制程繁琐且生产成本高，因此，有必要提供一种LTPS阵列基板的制作方法，以解决该技术问题。
发明内容
本发明的目的在于提供一种LTPS阵列基板的制作方法，可有效降低LTPS阵列基板的制作成本，且制得的LTPS阵列基板具有良好的电学性能。
为实现上述目的，本发明提供一种LTPS阵列基板的制作方法，包括如下步骤：
步骤1、提供一基板，在所述基板上定义出NMOS区与PMOS区，在所述基板上沉积第一金属层，对所述第一金属层进行图形化处理，得到位于NMOS区的遮光层；
步骤2、在所述遮光层、及基板上形成缓冲层，在所述缓冲层上沉积非晶硅层，采用低温结晶工艺将所述非晶硅层转化为多晶硅层，对所述多晶 硅层进行图形化处理，得到位于NMOS区的第一多晶硅层、及位于PMOS区的第二多晶硅层；
步骤3、在所述第一多晶硅层、第二多晶硅层、及缓冲层上涂布光阻层，采用一道半色调光罩对所述光阻层进行曝光、显影后，在所述光阻层上形成对应于所述第二多晶硅层两端的第一通孔，暴露出所述第二多晶硅层的两端，同时在所述光阻层上形成对应于所述第一多晶硅层两端的第一凹槽；以所述光阻层为掩模，对所述第二多晶硅层的两端进行P型重掺杂，得到两P型重掺杂区，所述第二多晶硅层上位于两P型重掺杂区之间的区域形成第二沟道区；
采用干蚀刻制程对所述光阻层进行灰化，减薄所述光阻层的厚度，使得第一凹槽转化为第二通孔，暴露出所述第一多晶硅层的两端，以所述光阻层为掩模，对所述第一多晶硅层的两端进行N型重掺杂，得到两N型重掺杂区；
采用光阻剥离制程将剩余的光阻层完全剥离，暴露出第一多晶硅层与第二多晶硅层，对所述第一多晶硅层、及第二多晶硅层进行P型轻掺杂，以实现对所述第一多晶硅层的沟道掺杂。
所述LTPS阵列基板的制作方法还包括如下步骤：
步骤4、在所述第一多晶硅层、第二多晶硅层、及缓冲层上沉积栅极绝缘层，在所述栅极绝缘层上沉积第二金属层，对所述第二金属层进行图形化处理，得到分别对应于第一多晶硅层与第二多晶硅层上方的第一栅极与第二栅极；
以所述第一栅极为光罩对所述第一多晶硅层进行N型轻掺杂，得到分别位于两N型重掺杂区内侧的两N型轻掺杂区，所述第一多晶硅层上位于两N型轻掺杂区之间的区域形成第一沟道区；
步骤5、在所述第一栅极、第二栅极、及栅极绝缘层上沉积层间绝缘层，对所述层间绝缘层及栅极绝缘层进行图形化处理，得到位于所述N型重掺杂区上方的第一过孔及位于所述P型重掺杂区上方的第二过孔；
步骤6、在所述层间绝缘层上沉积第三金属层，对所述第三金属层进行图形化处理，得到第一源极、第一漏极、第二源极、第二漏极，所述第一源极、第一漏极分别通过第一过孔与N型重掺杂区相接触，所述第二源极、第二漏极分别通过第二过孔与P型重掺杂区相接触；
步骤7、在所述第一源极、第一漏极、第二源极、第二漏极、及层间绝缘层上形成平坦层，对所述平坦层进行图形化处理，得到位于所述第一漏极上方的第三过孔；
步骤8、在所述平坦层上沉积第一透明导电氧化物层，对所述第一透明导电氧化物层进行图形化处理，得到公共电极；
步骤9、在所述公共电极、及平坦层上沉积钝化保护层，所述钝化保护层包覆所述平坦层上的第三过孔，之后对所述钝化保护层进行图形化处理，得到位于所述第三过孔底部的钝化保护层上的第四过孔；
步骤10、在所述钝化保护层上沉积第二透明导电氧化物层，对所述第二透明导电氧化物层进行图形化处理，得到像素电极，所述像素电极通过第四过孔与第一漏极相接触。
所述步骤2中，所述低温结晶工艺为准分子激光退火法或金属诱导横向晶化法。
所述步骤3中，所述P型重掺杂制程中植入的离子为硼离子，植入剂量为1*1015个/cm2；所述N型重掺杂制程中植入的离子为磷离子，植入剂量为4*1014个/cm2；所述P型轻掺杂制程中植入的离子为硼离子，植入剂量为2*1012个/cm2。
所述步骤4中，所述N型轻掺杂制程中植入的离子为磷离子，植入剂量为1.5*1013个/cm2。
所述步骤5还包括：对所述层间绝缘层进行去氢和活化处理。
采用快速热退火工艺对所述层间绝缘层进行去氢和活化处理。
所述基板为玻璃基板；所述第一金属层、第二金属层、第三金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合；所述缓冲层、栅极绝缘层、层间绝缘层、及钝化保护层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层；所述平坦层为有机光阻材料。
所述第一透明导电氧化物层、第二透明导电氧化物层的材料为金属氧化物。
所述金属氧化物为铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、或铟锗锌氧化物。
本发明还提供一种LTPS阵列基板的制作方法，包括如下步骤：
步骤1、提供一基板，在所述基板上定义出NMOS区与PMOS区，在所述基板上沉积第一金属层，对所述第一金属层进行图形化处理，得到位于NMOS区的遮光层；
步骤2、在所述遮光层、及基板上形成缓冲层，在所述缓冲层上沉积非晶硅层，采用低温结晶工艺将所述非晶硅层转化为多晶硅层，对所述多晶硅层进行图形化处理，得到位于NMOS区的第一多晶硅层、及位于PMOS区的第二多晶硅层；
步骤3、在所述第一多晶硅层、第二多晶硅层、及缓冲层上涂布光阻层，采用一道半色调光罩对所述光阻层进行曝光、显影后，在所述光阻层上形成对应于所述第二多晶硅层两端的第一通孔，暴露出所述第二多晶硅层的两端，同时在所述光阻层上形成对应于所述第一多晶硅层两端的第一凹槽；以所述光阻层为掩模，对所述第二多晶硅层的两端进行P型重掺杂，得到两P型重掺杂区，所述第二多晶硅层上位于两P型重掺杂区之间的区域形成第二沟道区；
采用干蚀刻制程对所述光阻层进行灰化，减薄所述光阻层的厚度，使得第一凹槽转化为第二通孔，暴露出所述第一多晶硅层的两端，以所述光阻层为掩模，对所述第一多晶硅层的两端进行N型重掺杂，得到两N型重掺杂区；
采用光阻剥离制程将剩余的光阻层完全剥离，暴露出第一多晶硅层与第二多晶硅层，对所述第一多晶硅层、及第二多晶硅层进行P型轻掺杂，以实现对所述第一多晶硅层的沟道掺杂；
步骤4、在所述第一多晶硅层、第二多晶硅层、及缓冲层上沉积栅极绝缘层，在所述栅极绝缘层上沉积第二金属层，对所述第二金属层进行图形化处理，得到分别对应于第一多晶硅层与第二多晶硅层上方的第一栅极与第二栅极；
以所述第一栅极为光罩对所述第一多晶硅层进行N型轻掺杂，得到分别位于两N型重掺杂区内侧的两N型轻掺杂区，所述第一多晶硅层上位于两N型轻掺杂区之间的区域形成第一沟道区；
步骤5、在所述第一栅极、第二栅极、及栅极绝缘层上沉积层间绝缘层，对所述层间绝缘层及栅极绝缘层进行图形化处理，得到位于所述N型重掺杂区上方的第一过孔及位于所述P型重掺杂区上方的第二过孔；
步骤6、在所述层间绝缘层上沉积第三金属层，对所述第三金属层进行图形化处理，得到第一源极、第一漏极、第二源极、第二漏极，所述第一源极、第一漏极分别通过第一过孔与N型重掺杂区相接触，所述第二源极、第二漏极分别通过第二过孔与P型重掺杂区相接触；
步骤7、在所述第一源极、第一漏极、第二源极、第二漏极、及层间绝缘层上形成平坦层，对所述平坦层进行图形化处理，得到位于所述第一漏极上方的第三过孔；
步骤8、在所述平坦层上沉积第一透明导电氧化物层，对所述第一透明导电氧化物层进行图形化处理，得到公共电极；
步骤9、在所述公共电极、及平坦层上沉积钝化保护层，所述钝化保护 层包覆所述平坦层上的第三过孔，之后对所述钝化保护层进行图形化处理，得到位于所述第三过孔底部的钝化保护层上的第四过孔；
步骤10、在所述钝化保护层上沉积第二透明导电氧化物层，对所述第二透明导电氧化物层进行图形化处理，得到像素电极，所述像素电极通过第四过孔与第一漏极相接触；
其中，所述步骤2中，所述低温结晶工艺为准分子激光退火法或金属诱导横向晶化法；
其中，所述步骤3中，所述P型重掺杂制程中植入的离子为硼离子，植入剂量为1*1015个/cm2；所述N型重掺杂制程中植入的离子为磷离子，植入剂量为4*1014个/cm2；所述P型轻掺杂制程中植入的离子为硼离子，植入剂量为2*1012个/cm2。
本发明的有益效果：本发明提供的一种LTPS阵列基板的制作方法，通过采用一道半色调光罩将NMOS区的第一多晶硅层的N型重掺杂与沟道掺杂、及PMOS区的第二多晶硅层的P型重掺杂这三道原本需要三道光罩的制程整合到一道光罩制程中，节省两道曝光制程，大大提升曝光产能，同时节省了两张光罩的制作成本，可有效降低LTPS阵列基板的制作成本，制得的LTPS阵列基板具有良好的电学性能。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为现有的LTPS阵列基板的制作方法的步骤1的示意图；
图2为现有的LTPS阵列基板的制作方法的步骤2的示意图；
图3为现有的LTPS阵列基板的制作方法的步骤3的示意图；
图4为现有的LTPS阵列基板的制作方法的步骤4的示意图；
图5为现有的LTPS阵列基板的制作方法的步骤5的示意图；
图6为现有的LTPS阵列基板的制作方法的步骤6的示意图；
图7为本发明的LTPS阵列基板的制作方法的步骤1的示意图；
图8为本发明的LTPS阵列基板的制作方法的步骤2的示意图；
图9A-9C为本发明的LTPS阵列基板的制作方法的步骤3的示意图；
图10为本发明的LTPS阵列基板的制作方法的步骤4的示意图；
图11为本发明的LTPS阵列基板的制作方法的步骤5的示意图；
图12为本发明的LTPS阵列基板的制作方法的步骤6的示意图；
图13为本发明的LTPS阵列基板的制作方法的步骤7的示意图；
图14为本发明的LTPS阵列基板的制作方法的步骤8的示意图；
图15为本发明的LTPS阵列基板的制作方法的步骤9的示意图；
图16为本发明的LTPS阵列基板的制作方法的步骤10的示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图7-16，本发明提供一种LTPS阵列基板的制作方法，包括如下步骤：
步骤1、如图7所示，提供一基板10，在所述基板10上定义出NMOS区与PMOS区，在所述基板10上沉积第一金属层，对所述第一金属层进行图形化处理，得到位于NMOS区的遮光层20。
步骤2、如图8所示，在所述遮光层20、及基板10上形成缓冲层30，在所述缓冲层30上沉积非晶硅层，采用低温结晶工艺将所述非晶硅层转化为多晶硅层，对所述多晶硅层进行图形化处理，得到位于NMOS区的第一多晶硅层40、及位于PMOS区的第二多晶硅层90。
具体的，所述低温结晶工艺可以为准分子激光退火法(Excimer Laser Annealing,ELA)或金属诱导横向晶化法(Metal Induced lateral Crystallization,MILC)等。
步骤3、如图9A所示，在所述第一多晶硅层40、第二多晶硅层90、及缓冲层30上涂布光阻层33，采用一道半色调光罩对所述光阻层33进行曝光、显影后，在所述光阻层33上形成对应于所述第二多晶硅层90两端的第一通孔331，暴露出所述第二多晶硅层90的两端，同时在所述光阻层33上形成对应于所述第一多晶硅层40两端的第一凹槽333；以所述光阻层33为掩模，对所述第二多晶硅层90的两端进行P型重掺杂，得到两P型重掺杂区91，所述第二多晶硅层90上位于两P型重掺杂区91之间的区域形成第二沟道区92；
如图9B所示，采用干蚀刻制程对所述光阻层33进行灰化，减薄所述光阻层33的厚度，使得第一凹槽333转化为第二通孔335，暴露出所述第一多晶硅层40的两端，以所述光阻层33为掩模，对所述第一多晶硅层40 的两端进行N型重掺杂，得到两N型重掺杂区41；
如图9C所示，采用光阻剥离制程将剩余的光阻层33完全剥离，暴露出第一多晶硅层40与第二多晶硅层90，对所述第一多晶硅层40、及第二多晶硅层90进行P型轻掺杂，以实现对所述第一多晶硅层40的沟道掺杂。
具体的，所述步骤3中，所述P型重掺杂制程中植入的离子为硼(B)离子，植入剂量为1*1015个/cm2；所述N型重掺杂制程中植入的离子为磷(P)离子，植入剂量为4*1014个/cm2；所述P型轻掺杂制程中植入的离子为硼(B)离子，植入剂量为2*1012个/cm2。
以上三次掺杂制程，按照植入的先后顺序植入剂量依次减少，植入剂量最大的最先进行掺杂，这样可以减小后面掺杂元素对前面已掺杂区域的影响。
值得一提的是，所述步骤3通过采用一道半色调光罩将NMOS区的第一多晶硅层40的N型重掺杂与沟道掺杂、及PMOS区的第二多晶硅层90的P型重掺杂这三道原本需要三道光罩的制程整合到一道光罩制程中，节省了两道曝光制程，大大提升曝光产能，同时节省了两张光罩的制作成本，可有效降低LTPS阵列基板的制作成本。
步骤4、如图10所示，在所述第一多晶硅层40、第二多晶硅层90、及缓冲层30上沉积栅极绝缘层51，在所述栅极绝缘层51上沉积第二金属层，对所述第二金属层进行图形化处理，得到分别对应于第一多晶硅层40与第二多晶硅层90上方的第一栅极52与第二栅极93；
以所述第一栅极52为光罩对所述第一多晶硅层40进行N型轻掺杂，得到分别位于两N型重掺杂区41内侧的两N型轻掺杂区43，所述第一多晶硅层40上位于两N型轻掺杂区43之间的区域形成第一沟道区42。
具体的，所述步骤4中，所述N型轻掺杂制程中植入的离子为磷(P)离子，植入剂量为1.5*1013个/cm2。
步骤5、如图11所示，在所述第一栅极52、第二栅极93、及栅极绝缘层51上沉积层间绝缘层53，对所述层间绝缘层53及栅极绝缘层51进行图形化处理，得到位于所述N型重掺杂区41上方的第一过孔55及位于所述P型重掺杂区91上方的第二过孔95，之后对所述层间绝缘层53进行去氢和活化处理。
具体的，采用快速热退火工艺(RTA，Rapid Thermal Annealing)对所述层间绝缘层53进行去氢和活化处理。
步骤6、如图12所示，在所述层间绝缘层53上沉积第三金属层，对所述第三金属层进行图形化处理，得到第一源极61、第一漏极62、第二源极 96、第二漏极97，所述第一源极61、第一漏极62分别通过第一过孔55与N型重掺杂区41相接触，所述第二源极96、第二漏极97分别通过第二过孔95与P型重掺杂区91相接触。
步骤7、如图13所示，在所述第一源极61、第一漏极62、第二源极96、第二漏极97、及层间绝缘层53上形成平坦层70，对所述平坦层70进行图形化处理，得到位于所述第一漏极62上方的第三过孔71。
步骤8、如图14所示，在所述平坦层70上沉积第一透明导电氧化物层，对所述第一透明导电氧化物层进行图形化处理，得到公共电极80。
步骤9、如图15所示，在所述公共电极80、及平坦层70上沉积钝化保护层81，所述钝化保护层81包覆所述平坦层70上的第三过孔71，之后对所述钝化保护层81进行图形化处理，得到位于所述第三过孔71底部的钝化保护层81上的第四过孔85。
步骤10、如图16所示，在所述钝化保护层81上沉积第二透明导电氧化物层，对所述第二透明导电氧化物层进行图形化处理，得到像素电极82，所述像素电极82通过第四过孔85与第一漏极62相接触。
具体的，所述基板10为透明基板，优选为玻璃基板。
具体的，所述第一金属层、第二金属层、第三金属层的材料为钼(Mo)、钛(Ti)、铝(Al)、铜(Cu)中的一种或多种的堆栈组合。
具体的，所述缓冲层30、栅极绝缘层51、层间绝缘层53、及钝化保护层81为氧化硅(SiOx)层、氮化硅(SiNx)层、或者由氧化硅层与氮化硅层叠加构成的复合层。
具体的，所述平坦层70为有机光阻材料。
具体的，所述第一透明导电氧化物层、第二透明导电氧化物层的材料为金属氧化物，如铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟锗锌氧化物、或其它合适的氧化物。
综上所述，本发明提供的一种LTPS阵列基板的制作方法，通过采用一道半色调光罩将NMOS区的第一多晶硅层的N型重掺杂与沟道掺杂、及PMOS区的第二多晶硅层的P型重掺杂这三道原本需要三道光罩的制程整合到一道光罩制程中，节省两道曝光制程，大大提升曝光产能，同时节省了两张光罩的制作成本，可有效降低LTPS阵列基板的制作成本，制得的LTPS阵列基板具有良好的电学性能。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (17)

  1. 一种LTPS阵列基板的制作方法，包括如下步骤：
    步骤1、提供一基板，在所述基板上定义出NMOS区与PMOS区，在所述基板上沉积第一金属层，对所述第一金属层进行图形化处理，得到位于NMOS区的遮光层；
    步骤2、在所述遮光层、及基板上形成缓冲层，在所述缓冲层上沉积非晶硅层，采用低温结晶工艺将所述非晶硅层转化为多晶硅层，对所述多晶硅层进行图形化处理，得到位于NMOS区的第一多晶硅层、及位于PMOS区的第二多晶硅层；
    步骤3、在所述第一多晶硅层、第二多晶硅层、及缓冲层上涂布光阻层，采用一道半色调光罩对所述光阻层进行曝光、显影后，在所述光阻层上形成对应于所述第二多晶硅层两端的第一通孔，暴露出所述第二多晶硅层的两端，同时在所述光阻层上形成对应于所述第一多晶硅层两端的第一凹槽；以所述光阻层为掩模，对所述第二多晶硅层的两端进行P型重掺杂，得到两P型重掺杂区，所述第二多晶硅层上位于两P型重掺杂区之间的区域形成第二沟道区；
    采用干蚀刻制程对所述光阻层进行灰化，减薄所述光阻层的厚度，使得第一凹槽转化为第二通孔，暴露出所述第一多晶硅层的两端，以所述光阻层为掩模，对所述第一多晶硅层的两端进行N型重掺杂，得到两N型重掺杂区；
    采用光阻剥离制程将剩余的光阻层完全剥离，暴露出第一多晶硅层与第二多晶硅层，对所述第一多晶硅层、及第二多晶硅层进行P型轻掺杂，以实现对所述第一多晶硅层的沟道掺杂。
  2. 如权利要求1所述的LTPS阵列基板的制作方法，还包括如下步骤：
    步骤4、在所述第一多晶硅层、第二多晶硅层、及缓冲层上沉积栅极绝缘层，在所述栅极绝缘层上沉积第二金属层，对所述第二金属层进行图形化处理，得到分别对应于第一多晶硅层与第二多晶硅层上方的第一栅极与第二栅极；
    以所述第一栅极为光罩对所述第一多晶硅层进行N型轻掺杂，得到分别位于两N型重掺杂区内侧的两N型轻掺杂区，所述第一多晶硅层上位于两N型轻掺杂区之间的区域形成第一沟道区；
    步骤5、在所述第一栅极、第二栅极、及栅极绝缘层上沉积层间绝缘层， 对所述层间绝缘层及栅极绝缘层进行图形化处理，得到位于所述N型重掺杂区上方的第一过孔及位于所述P型重掺杂区上方的第二过孔；
    步骤6、在所述层间绝缘层上沉积第三金属层，对所述第三金属层进行图形化处理，得到第一源极、第一漏极、第二源极、第二漏极，所述第一源极、第一漏极分别通过第一过孔与N型重掺杂区相接触，所述第二源极、第二漏极分别通过第二过孔与P型重掺杂区相接触；
    步骤7、在所述第一源极、第一漏极、第二源极、第二漏极、及层间绝缘层上形成平坦层，对所述平坦层进行图形化处理，得到位于所述第一漏极上方的第三过孔；
    步骤8、在所述平坦层上沉积第一透明导电氧化物层，对所述第一透明导电氧化物层进行图形化处理，得到公共电极；
    步骤9、在所述公共电极、及平坦层上沉积钝化保护层，所述钝化保护层包覆所述平坦层上的第三过孔，之后对所述钝化保护层进行图形化处理，得到位于所述第三过孔底部的钝化保护层上的第四过孔；
    步骤10、在所述钝化保护层上沉积第二透明导电氧化物层，对所述第二透明导电氧化物层进行图形化处理，得到像素电极，所述像素电极通过第四过孔与第一漏极相接触。
  3. 如权利要求1所述的LTPS阵列基板的制作方法，其中，所述步骤2中，所述低温结晶工艺为准分子激光退火法或金属诱导横向晶化法。
  4. 如权利要求1所述的LTPS阵列基板的制作方法，其中，所述步骤3中，所述P型重掺杂制程中植入的离子为硼离子，植入剂量为1*1015个/cm2；所述N型重掺杂制程中植入的离子为磷离子，植入剂量为4*1014个/cm2；所述P型轻掺杂制程中植入的离子为硼离子，植入剂量为2*1012个/cm2。
  5. 如权利要求2所述的LTPS阵列基板的制作方法，其中，所述步骤4中，所述N型轻掺杂制程中植入的离子为磷离子，植入剂量为1.5*1013个/cm2。
  6. 如权利要求2所述的LTPS阵列基板的制作方法，其中，所述步骤5还包括：对所述层间绝缘层进行去氢和活化处理。
  7. 如权利要求6所述的LTPS阵列基板的制作方法，其中，采用快速热退火工艺对所述层间绝缘层进行去氢和活化处理。
  8. 如权利要求2所述的LTPS阵列基板的制作方法，其中，所述基板为玻璃基板；所述第一金属层、第二金属层、第三金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合；所述缓冲层、栅极绝缘层、层间绝缘 层、及钝化保护层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层；所述平坦层为有机光阻材料。
  9. 如权利要求2所述的LTPS阵列基板的制作方法，其中，所述第一透明导电氧化物层、第二透明导电氧化物层的材料为金属氧化物。
  10. 如权利要求9所述的LTPS阵列基板的制作方法，其中，所述金属氧化物为铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、或铟锗锌氧化物。
  11. 一种LTPS阵列基板的制作方法，包括如下步骤：
    步骤1、提供一基板，在所述基板上定义出NMOS区与PMOS区，在所述基板上沉积第一金属层，对所述第一金属层进行图形化处理，得到位于NMOS区的遮光层；
    步骤2、在所述遮光层、及基板上形成缓冲层，在所述缓冲层上沉积非晶硅层，采用低温结晶工艺将所述非晶硅层转化为多晶硅层，对所述多晶硅层进行图形化处理，得到位于NMOS区的第一多晶硅层、及位于PMOS区的第二多晶硅层；
    步骤3、在所述第一多晶硅层、第二多晶硅层、及缓冲层上涂布光阻层，采用一道半色调光罩对所述光阻层进行曝光、显影后，在所述光阻层上形成对应于所述第二多晶硅层两端的第一通孔，暴露出所述第二多晶硅层的两端，同时在所述光阻层上形成对应于所述第一多晶硅层两端的第一凹槽；以所述光阻层为掩模，对所述第二多晶硅层的两端进行P型重掺杂，得到两P型重掺杂区，所述第二多晶硅层上位于两P型重掺杂区之间的区域形成第二沟道区；
    采用干蚀刻制程对所述光阻层进行灰化，减薄所述光阻层的厚度，使得第一凹槽转化为第二通孔，暴露出所述第一多晶硅层的两端，以所述光阻层为掩模，对所述第一多晶硅层的两端进行N型重掺杂，得到两N型重掺杂区；
    采用光阻剥离制程将剩余的光阻层完全剥离，暴露出第一多晶硅层与第二多晶硅层，对所述第一多晶硅层、及第二多晶硅层进行P型轻掺杂，以实现对所述第一多晶硅层的沟道掺杂；
    步骤4、在所述第一多晶硅层、第二多晶硅层、及缓冲层上沉积栅极绝缘层，在所述栅极绝缘层上沉积第二金属层，对所述第二金属层进行图形化处理，得到分别对应于第一多晶硅层与第二多晶硅层上方的第一栅极与第二栅极；
    以所述第一栅极为光罩对所述第一多晶硅层进行N型轻掺杂，得到分 别位于两N型重掺杂区内侧的两N型轻掺杂区，所述第一多晶硅层上位于两N型轻掺杂区之间的区域形成第一沟道区；
    步骤5、在所述第一栅极、第二栅极、及栅极绝缘层上沉积层间绝缘层，对所述层间绝缘层及栅极绝缘层进行图形化处理，得到位于所述N型重掺杂区上方的第一过孔及位于所述P型重掺杂区上方的第二过孔；
    步骤6、在所述层间绝缘层上沉积第三金属层，对所述第三金属层进行图形化处理，得到第一源极、第一漏极、第二源极、第二漏极，所述第一源极、第一漏极分别通过第一过孔与N型重掺杂区相接触，所述第二源极、第二漏极分别通过第二过孔与P型重掺杂区相接触；
    步骤7、在所述第一源极、第一漏极、第二源极、第二漏极、及层间绝缘层上形成平坦层，对所述平坦层进行图形化处理，得到位于所述第一漏极上方的第三过孔；
    步骤8、在所述平坦层上沉积第一透明导电氧化物层，对所述第一透明导电氧化物层进行图形化处理，得到公共电极；
    步骤9、在所述公共电极、及平坦层上沉积钝化保护层，所述钝化保护层包覆所述平坦层上的第三过孔，之后对所述钝化保护层进行图形化处理，得到位于所述第三过孔底部的钝化保护层上的第四过孔；
    步骤10、在所述钝化保护层上沉积第二透明导电氧化物层，对所述第二透明导电氧化物层进行图形化处理，得到像素电极，所述像素电极通过第四过孔与第一漏极相接触；
    其中，所述步骤2中，所述低温结晶工艺为准分子激光退火法或金属诱导横向晶化法；
    其中，所述步骤3中，所述P型重掺杂制程中植入的离子为硼离子，植入剂量为1*1015个/cm2；所述N型重掺杂制程中植入的离子为磷离子，植入剂量为4*1014个/cm2；所述P型轻掺杂制程中植入的离子为硼离子，植入剂量为2*1012个/cm2。
  12. 如权利要求11所述的LTPS阵列基板的制作方法，其中，所述步骤4中，所述N型轻掺杂制程中植入的离子为磷离子，植入剂量为1.5*1013个/cm2。
  13. 如权利要求11所述的LTPS阵列基板的制作方法，其中，所述步骤5还包括：对所述层间绝缘层进行去氢和活化处理。
  14. 如权利要求13所述的LTPS阵列基板的制作方法，其中，采用快速热退火工艺对所述层间绝缘层进行去氢和活化处理。
  15. 如权利要求11所述的LTPS阵列基板的制作方法，其中，所述基 板为玻璃基板；所述第一金属层、第二金属层、第三金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合；所述缓冲层、栅极绝缘层、层间绝缘层、及钝化保护层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层；所述平坦层为有机光阻材料。
  16. 如权利要求11所述的LTPS阵列基板的制作方法，其中，所述第一透明导电氧化物层、第二透明导电氧化物层的材料为金属氧化物。
  17. 如权利要求16所述的LTPS阵列基板的制作方法，其中，所述金属氧化物为铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、或铟锗锌氧化物。
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