CN104409346A - 低温多晶硅薄膜晶体管及制作方法、阵列基板、显示装置 - Google Patents

低温多晶硅薄膜晶体管及制作方法、阵列基板、显示装置 Download PDF

Info

Publication number
CN104409346A
CN104409346A CN201410553299.3A CN201410553299A CN104409346A CN 104409346 A CN104409346 A CN 104409346A CN 201410553299 A CN201410553299 A CN 201410553299A CN 104409346 A CN104409346 A CN 104409346A
Authority
CN
China
Prior art keywords
layer
film transistor
active layer
low
temperature polysilicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201410553299.3A
Other languages
English (en)
Inventor
陆小勇
刘政
孙亮
李小龙
龙春平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN201410553299.3A priority Critical patent/CN104409346A/zh
Publication of CN104409346A publication Critical patent/CN104409346A/zh
Priority to PCT/CN2015/074489 priority patent/WO2016058324A1/zh
Priority to US14/768,349 priority patent/US9768308B2/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • H01L29/6675Amorphous silicon or polysilicon transistors
    • H01L29/66757Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28568Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising transition metals
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/127Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45Ohmic electrodes
    • H01L29/456Ohmic electrodes on silicon
    • H01L29/458Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651Silicon transistors
    • H01L29/7866Non-monocrystalline silicon transistors
    • H01L29/78672Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本发明提供了一种低温多晶硅薄膜晶体管及制作方法、阵列基板、显示装置,该低温多晶硅薄膜晶体管的制作方法包括:S1:在衬底基板上依次形成有源层、栅极绝缘层、栅极以及层间绝缘层;S2:形成第一金属薄膜层;S3:对所述有源层和栅极绝缘层进行氢化处理;S4:形成第二金属薄膜层,所述第二金属薄膜层用于形成源漏极的图形。本发明通过在对有源层和栅极绝缘层进行氢化处理之前在层间绝缘层上方形成第一金属薄膜层,在氢化工艺之后,再制作用于形成源漏极的第二金属薄膜层,不但能够避免氢化工艺对源漏极电阻的不良影响,且不会改变形成的薄膜晶体管的特性,从而减小氢化工艺对形成的薄膜晶体管的不良影响。

Description

低温多晶硅薄膜晶体管及制作方法、阵列基板、显示装置
技术领域
本发明涉及显示领域,尤其涉及一种低温多晶硅薄膜晶体管及制作方法、阵列基板、显示装置。
背景技术
低温多晶硅薄膜晶体管(Low Temperature Poly-silicon ThinFilmTransistor,简称LTPS TFT)由于具有较高的迁移率和稳定性等优点,已普遍应用于显示器制造领域。
低温多晶硅薄膜晶体管的制备过程一般是在衬底基板1’上形成缓冲层2’和多晶硅薄膜,并对多晶硅薄膜图案化形成薄膜晶体管的有源层3’;在有源层3’上形成栅绝缘层4’;在栅绝缘层4’上形成栅极5’;再在有源层3’内注入离子分别形成源漏极区域(源极区域和漏极区域);沉积覆盖栅极5’以及栅绝缘层4’的层间绝缘层(ILD)6’;形成直达源极区域和漏极区域的接触孔;再形成金属层7’并图案化形成源极和漏极,源极和漏极通过接触孔分别连接源极区域和漏极区域。在上述TFT的制备过程中,多晶硅薄膜与栅绝缘层之间的界面会产生具有未成键轨道的悬挂键,这是多晶硅晶界的界面态密度增加的很重要的因素,由于悬挂键的影响从而导致薄膜晶体管的载流子迁移率下降,阈值电压升高等显示器件的性能退化问题。
现有技术通常采用氢化工艺向悬挂键供氢从而钝化多晶硅薄膜与栅极绝缘层界面处的悬挂键,然而,由于源漏(S/D)工艺采用钛铝钛(TiAlTi)低电阻率薄膜,其采用的氢化工艺会导致Ti与Al发生反应生成高电阻率TiAl3合金,造成最终的共用接地端电压(VSS Rs)较大,对最后形成的TFT造成不良影响。
发明内容
(一)要解决的技术问题
本发明要解决的技术问题是如何减小氢化工艺对形成的薄膜晶体管的不良影响。
(二)技术方案
为解决上述技术问题,本发明的技术方案提供了一种低温多晶硅薄膜晶体管的制作方法,包括:
S1:在衬底基板上依次形成有源层、栅极绝缘层、栅极以及层间绝缘层;
S2:形成第一金属薄膜层;
S3:对所述有源层和栅极绝缘层进行氢化处理;
S4:形成第二金属薄膜层,所述第二金属薄膜层用于形成源漏极的图形。
进一步地,在步骤S1中形成有源层包括:
在所述衬底基板上形成非晶硅薄膜;
对所述非晶硅薄膜进行晶化处理形成多晶硅薄膜;
对所述多晶硅薄膜图案化形成有源层。
进一步地,步骤S2之前还包括:在所述有源层的源漏区域上方形成过孔,以使在步骤S2中第一金属薄膜层与所述有源层在所述源漏区域相接触;
步骤S2之后还包括:进行第一热处理以使所述第一金属薄膜层与所述有源层在相接触的区域发生反应生成金属硅化物。
进一步地,步骤S3之后还包括:
去除所述第一金属薄膜层中所述相接触区域之外的金属薄膜材料。
进一步地,步骤S3之后还包括:对所述生成的金属硅化物进行第二热处理。
进一步地,所述氢化处理的温度为250~500摄氏度,时间为0.5~3小时。
进一步地,所述第一金属薄膜层的材料为钨、钛、钴、镍中的一种或多种。
为解决上述技术问题,本发明还提供了一种上述方法制作的低温多晶硅薄膜晶体管。
为解决上述技术问题,本发明还提供了一种阵列基板,包括上述的低温多晶硅薄膜晶体管。
为解决上述技术问题,本发明还提供了一种显示装置,包括上述的阵列基板。
(三)有益效果
本发明通过在对有源层和栅极绝缘层进行氢化处理之前在层间绝缘层上方形成第一金属薄膜层,在氢化工艺之后,再制作用于形成源漏极的第二金属薄膜层,不但能够避免氢化工艺对源漏极电阻的不良影响,且不会改变形成的薄膜晶体管的特性,从而减小氢化工艺对形成的薄膜晶体管的不良影响。
附图说明
图1是现有技术中对有源层和栅极绝缘层进行氢化处理的示意图;
图2是本发明实施方式提供的一种低温多晶硅薄膜晶体管的制作方法的流程图;
图3是本发明实施方式提供的另一种低温多晶硅薄膜晶体管的制作方法的流程图;
图4-9是本发明实施方式提供的制作低温多晶硅薄膜晶体管的示意图。
具体实施方式
下面结合附图和实施例,对本发明的具体实施方式作进一步详细描述。以下实施例用于说明本发明,但不用来限制本发明的范围。
图2是本发明实施方式提供的一种低温多晶硅薄膜晶体管的制作方法的流程图,包括:
S1:在衬底基板上依次形成有源层、栅极绝缘层、栅极以及层间绝缘层;
S2:形成第一金属薄膜层;
S3:对所述有源层和栅极绝缘层进行氢化处理;
S4:形成第二金属薄膜层,所述第二金属薄膜层用于形成源漏极的图形。
其中,第一金属薄膜层的材料可与形成第二金属薄膜的材料相同,通过溅射的方式形成在层间绝缘层上,氢化处理的温度可以为250~500摄氏度,例如可以为350摄氏度、400摄氏度等,时间为0.5~3小时,例如可以为1小时、2小时等。对于步骤S2形成的第一金属薄膜层,可在步骤S3对有源层和栅极绝缘层进行氢化处理之后将该第一金属薄膜层去除,也可不将其去除,而在步骤S4形成第二金属薄膜层之后,将第一薄膜层与第二薄膜层作为一层结构进行刻蚀,从而形成源漏极的图形。
本发明实施方式提供的低温多晶硅薄膜晶体管的制作方法,通过在对有源层和栅极绝缘层进行氢化处理之前在层间绝缘层上方形成第一金属薄膜层,在氢化工艺之后,再制作用于形成源漏极的第二金属薄膜层,不但能够避免氢化工艺对源漏极电阻的不良影响,且不会改变形成的薄膜晶体管的特性,从而减小氢化工艺对形成的薄膜晶体管的不良影响。
图3是本发明实施方式提供的另一种低温多晶硅薄膜晶体管的制作方法的流程图,包括:
S21:在衬底基板上依次形成有源层、栅极绝缘层、栅极以及层间绝缘层;具体地,如图4所示,首先在衬底基板1上形成缓冲层2和有源层3,其中,有源层3的形成步骤为在衬底基板上形成非晶硅薄膜;对非晶硅薄膜进行晶化处理形成多晶硅薄膜;对多晶硅薄膜图案化形成有源层3,而后在有源层3上形成栅极绝缘层4;在栅极绝缘层4上形成栅极5;再在有源层3内注入离子分别形成源漏区域31(源极区域和漏极区域);沉积覆盖栅极5以及栅绝缘层4的层间绝缘层6;
S22:在所述有源层的源漏区域上方形成过孔,参见图4,可对层间绝缘层6和栅极绝缘层4进行刻蚀,在有源层的源漏区域31上方形成过孔;
S23:形成第一金属薄膜层8,参见图5,通过步骤S22中的过孔可使第一金属薄膜8与所述有源层3在所述源漏区域31相接触,其中,该第一金属薄膜层8可以是一层或多层金属薄膜,其采用的材料可以为钨、钛、钴、镍中的一种或多种;
S24:进行第一热处理以使所述第一金属薄膜层与所述有源层在相接触的区域发生反应生成金属硅化物,参见图6,具体,可采用RTP(快速热处理)工艺对上述的结构进行热处理,使第一金属薄膜层8与所述有源层3在相接触的区域发生反应生成金属硅化物81,从而在有源层3上方形成自对准硅化物;
S25:对所述有源层3和栅极绝缘层4进行氢化处理;具体地,参见图7,氢化处理的温度可以为250~500摄氏度,例如可以为350摄氏度、400摄氏度等,时间为0.5~3小时,例如可以为1小时、2小时等,通过步骤S23和步骤S24得到的结构对层间绝缘层形成阻挡层,而后再进行氢化工艺,能够有效的将氢原子从供氢薄膜传输到多晶层,从而钝化多晶硅薄膜与栅绝缘层界面处的悬挂键,此外,步骤S25与步骤S24也可互换,即先进行氢化处理,再进行第一热处理;
S26:去除所述第一金属薄膜层中所述相接触区域之外的金属薄膜材料;参见图8,可通过刻蚀工艺将第一金属薄膜层中未发生反应的金属薄膜层去除,而只保留第一金属薄膜层与有源层相接触区域生成的金属硅化物,用作有源层与后续形成的源漏极之间的欧姆接触层,具体地,由于生成的金属硅化物不溶于刻蚀液,因此,在上述刻蚀工艺中,不需要掩膜工艺,通过刻蚀液直接对第一金属薄膜层进行刻蚀,即可去除掉第一金属薄膜层中未发生反应的金属薄膜,而只保留源漏区域上方的金属硅化物。
S27:对所述生成的金属硅化物进行第二热处理;由于步骤S24中生成的金属硅化物的电阻率较高,因此,在氢化工艺之后可采用RTP(快速热处理)工艺对生成的金属硅化物进行第二热处理,从而降低生成的金属硅化物的电阻率,有助于源漏极与有源层之间形成良好的欧姆接触;
S28:形成第二金属薄膜层7,所述第二金属薄膜层7用于形成源漏极的图形,具体地,参见图9,可采用钛铝钛(TiAlTi)或者铝钛(AlTi)等低电阻率薄膜,通过溅射工艺形成在上述的结构上,而后通过刻蚀工艺对第二金属薄膜层7刻蚀形成源漏极。
本发明实施方式提供的低温多晶硅薄膜晶体管的制作方法,通过在层间绝缘层上方形成第一金属薄膜层,并通过过孔使第一金属薄膜与有源层在源漏区域相接触,对该第一金属薄膜进行热处理以在接触的区域形成自对准硅化物,而后进行氢化工艺,再形成源漏极的图形,不但能够避免氢化工艺对源漏极电阻的不良影响,获得较好的TFT特性,且形成的自对准硅化物有助于源漏极与有源层形成良好的欧姆接触,此外,该制作方法不影响源漏极掺杂工艺,能够提高工艺稳定性与可靠性。
此外,本发明实施方式还提供了一种上述方法制作的低温多晶硅薄膜晶体管。
另一方面,本发明实施方式还提供了一种阵列基板,包括上述方法制作的低温多晶硅薄膜晶体管。
本发明实施方式还提供了一种显示装置,包括上述的阵列基板。本发明实施方式提供的显示装置可以是笔记本电脑显示屏、液晶显示器、液晶电视、数码相框、手机、平板电脑等任何具有显示功能的产品或部件。
以上实施方式仅用于说明本发明,而并非对本发明的限制,有关技术领域的普通技术人员,在不脱离本发明的精神和范围的情况下,还可以做出各种变化和变型,因此所有等同的技术方案也属于本发明的范畴,本发明的专利保护范围应由权利要求限定。

Claims (10)

1.一种低温多晶硅薄膜晶体管的制作方法,其特征在于,包括:
S1:在衬底基板上依次形成有源层、栅极绝缘层、栅极以及层间绝缘层;
S2:形成第一金属薄膜层;
S3:对所述有源层和栅极绝缘层进行氢化处理;
S4:形成第二金属薄膜层,所述第二金属薄膜层用于形成源漏极的图形。
2.根据权利要求1所述的低温多晶硅薄膜晶体管的制作方法,其特征在于,在步骤S1中形成有源层包括:
在所述衬底基板上形成非晶硅薄膜;
对所述非晶硅薄膜进行晶化处理形成多晶硅薄膜;
对所述多晶硅薄膜图案化形成有源层。
3.根据权利要求2所述的低温多晶硅薄膜晶体管的制作方法,其特征在于,步骤S2之前还包括:在所述有源层的源漏区域上方形成过孔,以使在步骤S2中第一金属薄膜层与所述有源层在所述源漏区域相接触;
步骤S2之后还包括:进行第一热处理以使所述第一金属薄膜层与所述有源层在相接触的区域发生反应生成金属硅化物。
4.根据权利要求3所述的低温多晶硅薄膜晶体管的制作方法,其特征在于,步骤S3之后还包括:
去除所述第一金属薄膜层中所述相接触区域之外的金属薄膜材料。
5.根据权利要求3所述的低温多晶硅薄膜晶体管的制作方法,其特征在于,步骤S3之后还包括:对所述生成的金属硅化物进行第二热处理。
6.根据权利要求1~5任一所述的低温多晶硅薄膜晶体管的制作方法,其特征在于,所述氢化处理的温度为250~500摄氏度,时间为0.5~3小时。
7.根据权利要求1~5任一所述的低温多晶硅薄膜晶体管的制作方法,其特征在于,所述第一金属薄膜层的材料为钨、钛、钴、镍中的一种或多种。
8.一种如权利要求1~7中任一项所述方法制作的低温多晶硅薄膜晶体管。
9.一种阵列基板,其特征在于,包括如权利要求8所述的低温多晶硅薄膜晶体管。
10.一种显示装置,其特征在于,包括如权利要求9所述的阵列基板。
CN201410553299.3A 2014-10-17 2014-10-17 低温多晶硅薄膜晶体管及制作方法、阵列基板、显示装置 Pending CN104409346A (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201410553299.3A CN104409346A (zh) 2014-10-17 2014-10-17 低温多晶硅薄膜晶体管及制作方法、阵列基板、显示装置
PCT/CN2015/074489 WO2016058324A1 (zh) 2014-10-17 2015-03-18 低温多晶硅薄膜晶体管及制作方法、阵列基板、显示装置
US14/768,349 US9768308B2 (en) 2014-10-17 2015-03-18 Low temperature poly-silicon thin film transistor and fabrication method thereof, array substrate and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410553299.3A CN104409346A (zh) 2014-10-17 2014-10-17 低温多晶硅薄膜晶体管及制作方法、阵列基板、显示装置

Publications (1)

Publication Number Publication Date
CN104409346A true CN104409346A (zh) 2015-03-11

Family

ID=52646963

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410553299.3A Pending CN104409346A (zh) 2014-10-17 2014-10-17 低温多晶硅薄膜晶体管及制作方法、阵列基板、显示装置

Country Status (3)

Country Link
US (1) US9768308B2 (zh)
CN (1) CN104409346A (zh)
WO (1) WO2016058324A1 (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016058324A1 (zh) * 2014-10-17 2016-04-21 京东方科技集团股份有限公司 低温多晶硅薄膜晶体管及制作方法、阵列基板、显示装置
CN105655404A (zh) * 2015-12-31 2016-06-08 武汉华星光电技术有限公司 低温多晶硅薄膜晶体管及其制作方法
CN107819005A (zh) * 2016-08-31 2018-03-20 乐金显示有限公司 包含多种类型薄膜晶体管的有机发光显示装置及其制造方法
WO2020244404A1 (zh) * 2019-06-04 2020-12-10 京东方科技集团股份有限公司 薄膜晶体管、薄膜晶体管的制作方法、阵列基板、显示面板、显示装置
CN114167654A (zh) * 2021-12-08 2022-03-11 武汉华星光电技术有限公司 一种阵列基板及液晶显示面板

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105489552B (zh) * 2016-01-28 2018-08-14 武汉华星光电技术有限公司 Ltps阵列基板的制作方法
WO2017154303A1 (ja) * 2016-03-11 2017-09-14 株式会社リコー 非常停止用感圧センサ、安全装置及び安全システム
US10090415B1 (en) 2017-11-29 2018-10-02 International Business Machines Corporation Thin film transistors with epitaxial source/drain contact regions
CN112074956B (zh) 2020-07-30 2024-01-05 长江存储科技有限责任公司 具有富氢半导体沟道的三维存储器件

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1567550A (zh) * 2003-07-04 2005-01-19 统宝光电股份有限公司 低温多晶硅薄膜晶体管的制作方法
CN1588645A (zh) * 2004-07-14 2005-03-02 友达光电股份有限公司 半导体元件与其中的多晶硅薄膜晶体管及其制造方法
US20060001092A1 (en) * 2004-06-30 2006-01-05 Tae-Seong Kim Thin film transistor (TFT) and flat panel display including TFT
CN1855399A (zh) * 2005-04-28 2006-11-01 株式会社半导体能源研究所 半导体器件和制造半导体器件的方法
US20140308812A1 (en) * 2013-04-12 2014-10-16 Reza Arghavani Cvd based metal/semiconductor ohmic contact for high volume manufacturing applications

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2677167B2 (ja) * 1993-07-08 1997-11-17 日本電気株式会社 駆動回路内蔵型液晶表示装置の製造方法
TW589474B (en) * 2003-04-29 2004-06-01 Au Optronics Corp Display panel with the integrated driver circuit
TW200530717A (en) * 2004-03-05 2005-09-16 Innolux Display Corp Thin film transistor and method for manufacturing it
JP2006310741A (ja) * 2005-03-30 2006-11-09 Seiko Epson Corp 半導体装置の製造方法及び半導体装置
JP5548351B2 (ja) * 2007-11-01 2014-07-16 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP2009212504A (ja) * 2008-02-08 2009-09-17 Advanced Lcd Technologies Development Center Co Ltd 薄膜半導体装置およびその製造方法
JP5878797B2 (ja) * 2012-03-13 2016-03-08 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
CN104409346A (zh) 2014-10-17 2015-03-11 京东方科技集团股份有限公司 低温多晶硅薄膜晶体管及制作方法、阵列基板、显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1567550A (zh) * 2003-07-04 2005-01-19 统宝光电股份有限公司 低温多晶硅薄膜晶体管的制作方法
US20060001092A1 (en) * 2004-06-30 2006-01-05 Tae-Seong Kim Thin film transistor (TFT) and flat panel display including TFT
CN1588645A (zh) * 2004-07-14 2005-03-02 友达光电股份有限公司 半导体元件与其中的多晶硅薄膜晶体管及其制造方法
CN1855399A (zh) * 2005-04-28 2006-11-01 株式会社半导体能源研究所 半导体器件和制造半导体器件的方法
US20140308812A1 (en) * 2013-04-12 2014-10-16 Reza Arghavani Cvd based metal/semiconductor ohmic contact for high volume manufacturing applications

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2016058324A1 (zh) * 2014-10-17 2016-04-21 京东方科技集团股份有限公司 低温多晶硅薄膜晶体管及制作方法、阵列基板、显示装置
US9768308B2 (en) 2014-10-17 2017-09-19 Boe Technology Group Co., Ltd. Low temperature poly-silicon thin film transistor and fabrication method thereof, array substrate and display device
CN105655404A (zh) * 2015-12-31 2016-06-08 武汉华星光电技术有限公司 低温多晶硅薄膜晶体管及其制作方法
CN105655404B (zh) * 2015-12-31 2019-07-26 武汉华星光电技术有限公司 低温多晶硅薄膜晶体管及其制作方法
CN107819005A (zh) * 2016-08-31 2018-03-20 乐金显示有限公司 包含多种类型薄膜晶体管的有机发光显示装置及其制造方法
WO2020244404A1 (zh) * 2019-06-04 2020-12-10 京东方科技集团股份有限公司 薄膜晶体管、薄膜晶体管的制作方法、阵列基板、显示面板、显示装置
US11563100B2 (en) 2019-06-04 2023-01-24 Chengdu Boe Optoelectronics Technology Co., Ltd. Thin film transistor and method for manufacturing the same, array substrate, display panel, and display device
CN114167654A (zh) * 2021-12-08 2022-03-11 武汉华星光电技术有限公司 一种阵列基板及液晶显示面板

Also Published As

Publication number Publication date
US20160254389A1 (en) 2016-09-01
US9768308B2 (en) 2017-09-19
WO2016058324A1 (zh) 2016-04-21

Similar Documents

Publication Publication Date Title
CN104409346A (zh) 低温多晶硅薄膜晶体管及制作方法、阵列基板、显示装置
CN103700706B (zh) 薄膜晶体管制备方法和阵列基板制备方法
CN102636927B (zh) 阵列基板及其制造方法
WO2015165164A1 (zh) 低温多晶硅薄膜晶体管及其制作方法、阵列基板和显示装置
US9923075B2 (en) Low temperature poly-silicon thin film transistor and manufacturing method thereof
US10192975B2 (en) Low temperature polycrystalline silicon thin film transistor
CN107316874B (zh) 阵列基板及其制作方法、显示装置
US20150295094A1 (en) Thin film transistor, manufacturing method thereof, array substrate and display device
CN102881657A (zh) 一种cmos晶体管及其制造方法
CN103700629A (zh) 一种阵列基板及其制备方法、显示装置
CN105304500A (zh) N型tft的制作方法
CN105514120A (zh) 一种双栅tft阵列基板及其制造方法和显示装置
CN105655404B (zh) 低温多晶硅薄膜晶体管及其制作方法
US9899425B2 (en) Array substrate and manufacturing method thereof
CN105321825A (zh) 低温多晶硅薄膜晶体管及其制作方法
CN104617151A (zh) 低温多晶硅薄膜晶体管及制作方法、阵列基板及显示装置
CN104851894A (zh) 阵列基板及其制备方法、显示装置
CN107170835B (zh) 薄膜晶体管及其制备方法和阵列基板
CN101728436A (zh) 薄膜晶体管元件及其制作方法
JPH0432267A (ja) 薄膜トランジスタ
WO2015196627A1 (zh) 薄膜晶体管制作方法及阵列基板制作方法
KR100977538B1 (ko) 폴리실리콘 박막의 제조방법
KR100593267B1 (ko) 결정질 실리콘 박막트랜지스터의 제조 방법
US20180130826A1 (en) Method of manufacturing top-gate thin film transistor and top-gate thin film transistor thereof
KR101018271B1 (ko) 다결정 실리콘 박막트랜지스터 제조방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20150311