WO2017121007A1 - 薄膜晶体管结构的制造方法 - Google Patents

薄膜晶体管结构的制造方法 Download PDF

Info

Publication number
WO2017121007A1
WO2017121007A1 PCT/CN2016/074501 CN2016074501W WO2017121007A1 WO 2017121007 A1 WO2017121007 A1 WO 2017121007A1 CN 2016074501 W CN2016074501 W CN 2016074501W WO 2017121007 A1 WO2017121007 A1 WO 2017121007A1
Authority
WO
WIPO (PCT)
Prior art keywords
pattern layer
layer
film transistor
degrees
transistor structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2016/074501
Other languages
English (en)
French (fr)
Inventor
史文
李文辉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to US15/029,253 priority Critical patent/US20180047763A1/en
Publication of WO2017121007A1 publication Critical patent/WO2017121007A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/20—Changing the shape of the active layer in the devices, e.g. patterning
    • H10K71/231—Changing the shape of the active layer in the devices, e.g. patterning by etching of existing layers
    • H10K71/233—Changing the shape of the active layer in the devices, e.g. patterning by etching of existing layers by photolithographic etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/621—Providing a shape to conductive layers, e.g. patterning or selective deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/202—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials for lift-off processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H10P76/2041—Photolithographic processes
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/14—Metallic material, boron or silicon
    • C23C14/18—Metallic material, boron or silicon on other inorganic substrates
    • C23C14/185—Metallic material, boron or silicon on other inorganic substrates by cathodic sputtering
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34—Sputtering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/20—Changing the shape of the active layer in the devices, e.g. patterning
    • H10K71/221—Changing the shape of the active layer in the devices, e.g. patterning by lift-off techniques
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H10W72/01951—Changing the shapes of bond pads
    • H10W72/01955—Changing the shapes of bond pads by using masks

Definitions

  • the present invention relates to a method of fabricating a semiconductor structure, and more particularly to a method of fabricating a thin film transistor structure.
  • an etching stopper layer is usually formed on the oxide semiconductor layer (etching stop) Layer; ESL), which adds a masking procedure that increases the complexity of the thin film transistor fabrication process.
  • ESL oxide semiconductor layer
  • the etching stopper layer is difficult to implement in a display device having a higher resolution than limiting the length of the channel.
  • a masking process is required to increase the complexity of the thin film transistor manufacturing process.
  • the present invention provides a method of fabricating a thin film transistor structure to solve the high complexity problem of the manufacturing process existing in the prior art and the problems caused by using an etch barrier.
  • an embodiment of the present invention provides a method of fabricating a thin film transistor structure, including the steps of: providing a substrate; forming a gate pattern layer on the substrate; covering a gate insulating layer On the gate pattern layer and the substrate; forming an active pattern layer on the gate insulating layer, wherein a position of the active pattern layer corresponds to a position of the gate pattern layer; forming a photoresist a pattern layer on the active pattern layer and a portion of the gate insulating layer to expose a source predetermined position and a drain predetermined position of the gate insulating layer, wherein the photoresist pattern layer comprises a plurality of inverted trapezoidal blocks; using the photoresist pattern layer as a mask, depositing a metal layer on the photoresist pattern layer, the source predetermined position and the drain predetermined position; and removing the The photoresist pattern layer simultaneously removes the metal layer on the photoresist pattern layer to pattern the metal layer into a source
  • the material of the gate pattern layer comprises aluminum, molybdenum or copper.
  • the gate pattern layer is formed by a photolithography mask method.
  • the active pattern layer is formed by a photolithography mask method.
  • the gate insulating layer in the step of covering the gate insulating layer on the gate pattern layer and the substrate, is formed by a physical vapor deposition method.
  • each of the plurality of inverted trapezoidal blocks includes a lower bottom surface and an upper bottom surface, wherein the lower bottom surface contacts the active pattern layer or the gate insulating layer, and The area of the lower bottom surface is smaller than the area of the upper bottom surface.
  • each of the plurality of inverted trapezoidal blocks includes a left side surface and a right side surface extending from both sides of the lower bottom surface and connecting the two sides of the upper bottom surface a first angle between the left side surface and the upper bottom surface is greater than 0 degrees and less than 90 degrees; and a second angle between the right side surface and the upper bottom surface is greater than 0 degrees And less than 90 degrees.
  • the first angle is greater than or equal to 30 degrees and less than 90 degrees; and the second angle is greater than or equal to 30 degrees and less than 90 degrees.
  • another embodiment of the present invention provides a method of fabricating a thin film transistor structure, including the steps of: providing a substrate; forming a gate pattern layer on the substrate; covering a gate insulating layer On the gate pattern layer and the substrate; forming an active pattern layer on the gate insulating layer, wherein a position of the active pattern layer corresponds to a position of the gate pattern layer; forming a light And a resist pattern layer on the active pattern layer and a portion of the gate insulating layer to expose a source predetermined position and a drain predetermined position of the gate insulating layer, wherein the photoresist pattern layer Having a plurality of inverted trapezoidal blocks; depositing a metal layer on the photoresist pattern layer, the source predetermined position, and the drain predetermined position with the photoresist pattern layer as a mask; The photoresist pattern layer is simultaneously removed to remove the metal layer on the photoresist pattern layer to pattern the metal layer into a source and
  • the method further comprises: covering a passivation layer to the source, the drain, the active On the pattern layer and the gate pattern layer.
  • the photoresist pattern layer in the step of depositing the metal layer, is used as a photomask, and the metal layer is formed on the photoresist pattern layer by sputtering. And the predetermined position of the source and the predetermined position of the drain.
  • the material of the gate pattern layer comprises aluminum, molybdenum or copper.
  • the gate pattern layer is formed by a photolithography mask method.
  • the active pattern layer is formed by a photolithography mask method.
  • the gate insulating layer in the step of covering the gate insulating layer on the gate pattern layer and the substrate, is formed by a physical vapor deposition method.
  • each of the plurality of inverted trapezoidal blocks includes a lower bottom surface and an upper bottom surface, wherein the lower bottom surface contacts the active pattern layer or the gate insulating layer, and The area of the lower bottom surface is smaller than the area of the upper bottom surface.
  • each of the plurality of inverted trapezoidal blocks includes a left side surface and a right side surface extending from both sides of the lower bottom surface and connecting the two sides of the upper bottom surface a first angle between the left side surface and the upper bottom surface is greater than 0 degrees and less than 90 degrees; and a second angle between the right side surface and the upper bottom surface is greater than 0 degrees And less than 90 degrees.
  • the first angle is greater than or equal to 30 degrees and less than 90 degrees; and the second angle is greater than or equal to 30 degrees and less than 90 degrees.
  • the method of fabricating the thin film transistor structure of the present invention not only simplifies the fabrication process, but also forms an etch stop layer for protecting the back channel.
  • FIG. 1 is a flow chart showing a method of fabricating a thin film transistor structure in accordance with an embodiment of the invention.
  • FIGS. 2A to 2G are schematic cross-sectional views showing a method of fabricating a thin film transistor structure in various stages of fabrication, in accordance with an embodiment of the invention.
  • FIG. 1 is a flow chart showing a manufacturing method 10 of a thin film transistor structure according to an embodiment of the invention.
  • a manufacturing method 10 for a thin film transistor structure according to an embodiment of the present invention includes: providing a substrate (step 11); forming a gate pattern layer on the substrate (step 12); covering a gate insulating layer on the gate a pattern layer and the substrate (step 13); forming an active pattern layer on the gate insulating layer, wherein a position of the active pattern layer corresponds to a position of the gate pattern layer (step 14 Forming a photoresist pattern layer on the active pattern layer and a portion of the gate insulating layer to expose a source predetermined position and a drain predetermined position of the gate insulating layer, wherein
  • the photoresist pattern layer includes a plurality of inverted trapezoidal blocks (step 15); using the photoresist pattern layer as a mask, depositing a metal layer on the photoresist pattern layer, the source predetermined position, and the drain a predetermined position (
  • FIGS. 2A to 2G are schematic cross-sectional views showing a manufacturing method 10 of a thin film transistor structure in various stages of fabrication according to an embodiment of the invention. Please refer to Figures 1 and 2A together.
  • a substrate 21 is provided.
  • the substrate 21 may be a transparent substrate.
  • a gate pattern layer 22 is formed on the substrate 21.
  • the gate pattern layer 22 is formed by a photolithography mask method.
  • the material of the gate pattern layer 22 comprises aluminum, molybdenum or copper.
  • a gate insulating layer 23 is overlaid on the gate pattern layer 22 and the substrate 21.
  • the gate insulating layer 23 is deposited on the gate pattern layer 22 and the substrate 21 by a physical vapor deposition method.
  • the gate insulating layer 23 is formed without using a mask.
  • an active pattern layer 24 is formed on the gate insulating layer 23, wherein the position of the active pattern layer 24 corresponds to the position of the gate pattern layer 22.
  • the active pattern layer 24 is located above the gate pattern layer 22.
  • the material of the active pattern layer 24 is an oxide semiconductor such as indium gallium zinc oxide.
  • the active pattern layer 24 is formed by a photolithographic masking process.
  • a photoresist pattern layer 25 is formed on the active pattern layer 24 and a portion of the gate insulating layer 23 to expose a source predetermined position 231 of the gate insulating layer 23 and A drain predetermined position 232, wherein the photoresist pattern layer 25 includes a plurality of inverted trapezoidal blocks 251.
  • the effect of the plurality of inverted trapezoidal blocks 251 will be explained in step 16.
  • each of the plurality of inverted trapezoidal blocks 251 includes a lower bottom surface 251A and an upper bottom surface 251B, wherein the lower bottom surface 251A contacts the active pattern layer 24 or the gate insulating layer 23, The area of the lower bottom surface 251A is smaller than the area of the upper bottom surface 251B.
  • each of the plurality of inverted trapezoidal blocks 251 includes a left side surface 251C and a right side surface 251D extending from both sides of the lower bottom surface 251A and connecting the upper bottom surface.
  • a first angle An1 between the left side surface 251C and the upper bottom surface 251B is greater than 0 degrees and less than 90 degrees; and between the right side surface 251D and the upper bottom surface 251B
  • a second angle A2 is greater than 0 degrees and less than 90 degrees.
  • the photoresist pattern layer 25 is used as a mask, and a metal layer 26 is deposited (for example, by sputtering) on the photoresist pattern layer 25, the source predetermined position 231, and the drain. Extremely predetermined position 232. It is worth mentioning that the metal layer 26 located at the source predetermined position 231 and the drain predetermined position 232 may be distinct from the metal layer 26 located on the photoresist pattern layer 25. The boundary is due to the shape of the plurality of inverted trapezoidal blocks 251.
  • the photoresist pattern layer 25 is a plurality of rectangular blocks or a plurality of positive trapezoidal blocks
  • the flexibility of the metal layer itself may cause the position at the source to be predetermined and leaked.
  • the metal layer at the extreme predetermined position does not have a significant boundary with the metal layer located on the photoresist pattern layer, and even the metal layer maintains a complete undulating structure without a cross section. Since the metal layer has no significant cross section, the metal layer located at a predetermined position of the source and at a predetermined position of the drain is easily taken away together when the step 17 is performed. It can be seen that the photoresist pattern layer 25 including the plurality of inverted trapezoidal blocks 251 can assist the patterning of the metal layer 26 when performing step 17 in addition to the effect as a mask.
  • the plurality of inverted trapezoidal blocks 251 may have a relatively stable structure, but Relatively reducing the cross-sectional effect of the metal layer 26; when the first angle A1 and the second angle A2 are closer to 0 degrees, the cross-sectional effect of the metal layer 26 is better, but the plurality of The inverted trapezoidal block 251 has a less stable structure.
  • the first angle A1 may be greater than or equal to 30 degrees and less than 90 degrees, for example, 45 degrees, 60 degrees, 65 degrees, 70 degrees, 75 degrees, 80 degrees, or 85 degrees, etc.
  • the second included angle A2 may be 30 degrees or more and less than 90 degrees, for example, 45 degrees, 60 degrees, 65 degrees, 70 degrees, 75 degrees, 80 degrees, or 85 degrees. It should be noted that the first angle A1 may also be selected to be unequal to the second angle A2. For example, the first angle A1 is 30 degrees and the second angle A2 is 45. degree.
  • step 17 the photoresist pattern layer 25 is removed to simultaneously remove the metal layer 26 on the photoresist pattern layer 25, so that the metal layer 26 is patterned into a source 261 and a drain 262. To produce the thin film transistor structure 20 of the embodiment of the present invention.
  • the method 10 of manufacturing the thin film transistor structure of the embodiment of the present invention may include: covering a passivation layer 27
  • the source 261, the drain 262, the active pattern layer 24, and the gate pattern layer 22 are disposed to prevent the source 261 and the drain 262 from being oxidized or corroded.
  • the method for fabricating the thin film transistor structure of the embodiment of the present invention can reduce the two mask processes (the mask used for the etch stop layer and the mask used for the etch source/drain) to simplify the manufacturing process.
  • An etch stop layer for protecting the back channel is also not formed to avoid the problems caused by the formation of the etch stop layer.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

一种薄膜晶体管结构的制造方法，形成一光阻图案层（25）于一有源图案层（24）上及一部分的栅极绝缘层（23）上以暴露出栅极绝缘层（23）的一源极预定位置（231）及一漏极预定位置（232）。光阻图案层（25）包含多个倒梯形块（251），并可作为一掩膜，以便沉积一金属层（26）于光阻图案层（25）、源极预定位置（231）及漏极预定位置上（232）；在移除光阻图案层（25）及其上的金属层（26）后，使剩余的金属层（26）图案化成一源极（261）及一漏极（262）。该薄膜晶体管结构的制造方法不但可简化制造过程，也不需要形成用来保护背沟道的蚀刻阻挡层。

Description

薄膜晶体管结构的制造方法 技术领域
本发明是有关于一种半导体结构的制造方法，特别是有关于一种薄膜晶体管结构的制造方法。
 背景技术
在传统的氧化物半导体薄膜晶体管的制造过程中，例如氧化铟镓锌薄膜晶体管(IGZO TFT)，为了在进行源极与漏极的蚀刻过程中保护背沟道不受蚀刻损伤，通常会在氧化物半导体层上形成一个蚀刻阻挡层(etching stop layer；ESL)，从而增加了一次掩膜程序，增加薄膜晶体管制造过程的复杂度。另外，蚀刻阻挡层除了限制沟道的长度之外，在具有更高分辨率的显示装置中难以实行。再者，在传统薄膜晶体管的制造过程中，为了形成源极及漏极，需要一次掩膜程序，增加薄膜晶体管制造过程的复杂度。
故，有必要提供一种薄膜晶体管结构的制造方法，以解决现有技术所存在的问题。
 技术问题
有鉴于此，本发明提供一种薄膜晶体管结构的制造方法，以解决现有技术所存在的制造过程的高复杂度问题，以及使用蚀刻阻挡层所产生的问题。
 技术解决方案
本发明的主要目的在于提供一种薄膜晶体管结构的制造方法，其可以简化制造过程，并且不使用蚀刻阻挡层来形成源级及漏极。
为达成本发明的前述目的，本发明一实施例提供一种薄膜晶体管结构的制造方法，包含步骤：提供一基板；形成一栅极图案层于所述基板上；覆盖一栅极绝缘层于所述栅极图案层及所述基板上；形成一有源图案层于所述栅极绝缘层上，其中所述有源图案层的位置对应于所述栅极图案层的位置；形成一光阻图案层于所述有源图案层上及一部分的所述栅极绝缘层上以暴露出所述栅极绝缘层的一源极预定位置及一漏极预定位置，其中所述光阻图案层包含多个倒梯形块；以所述光阻图案层作为一掩膜，沉积一金属层于所述光阻图案层、所述源极预定位置及所述漏极预定位置上；及移除所述光阻图案层以同时移除位于所述光阻图案层上的金属层，以使所述金属层图案化成一源极及一漏极，其中在所述移除所述光阻图案层的步骤之后，更包含：覆盖一钝化层于所述源极、所述漏极、所述有源图案层及所述栅极图案层上；及其中在所述沉积所述金属层的步骤中，以所述光阻图案层为一光掩膜，以溅镀方式形成所述金属层于所述光阻图案层、所述源极预定位置及所述漏极预定位置上。
在本发明的一实施例中，所述栅极图案层的材质包含铝、钼或铜。
在本发明的一实施例中，所述栅极图案层是通过一光刻掩膜法形成。
在本发明的一实施例中，所述有源图案层是通过一光刻掩膜法形成。
在本发明的一实施例中，在所述覆盖所述栅极绝缘层于所述栅极图案层及所述基板上的步骤中，以一物理气相沉积法形成所述栅极绝缘层。
在本发明的一实施例中，所述多个倒梯形块的每一个包含一下底面及一上底面，其中所述下底面接触所述有源图案层或所述栅极绝缘层，及所述下底面的面积小于所述上底面的面积。
在本发明的一实施例中，所述多个倒梯形块的每一个包含一左侧面及一右侧面，分别从所述下底面的两侧延伸朝向并连接所述上底面的两侧，其中所述左侧面与所述上底面之间的一第一夹角大于0度且小于90度；及所述右侧面与所述上底面之间的一第二夹角大于0度且小于90度。
在本发明的一实施例中，所述第一夹角大于等于30度且小于90度；及所述第二夹角大于等于30度且小于90度。
为达成本发明的前述目的，本发明另一实施例提供一种薄膜晶体管结构的制造方法，包含步骤：提供一基板；形成一栅极图案层于所述基板上；覆盖一栅极绝缘层于所述栅极图案层及所述基板上；形成一有源图案层于所述栅极绝缘层上，其中所述有源图案层的位置对应于所述栅极图案层的位置；形成一光阻图案层于所述有源图案层上及一部分的所述栅极绝缘层上以暴露出所述栅极绝缘层的一源极预定位置及一漏极预定位置，其中所述光阻图案层包含多个倒梯形块；以所述光阻图案层作为一掩膜，沉积一金属层于所述光阻图案层、所述源极预定位置及所述漏极预定位置上；及移除所述光阻图案层以同时移除位于所述光阻图案层上的金属层，以使所述金属层图案化成一源极及一漏极。
在本发明的一实施例中，在所述移除所述光阻图案层的步骤之后，所述方法更包含：覆盖一钝化层于所述源极、所述漏极、所述有源图案层及所述栅极图案层上。
在本发明的一实施例中，在所述沉积所述金属层的步骤中，以所述光阻图案层为一光掩膜，以溅镀方式形成所述金属层于所述光阻图案层、所述源极预定位置及所述漏极预定位置上。
在本发明的一实施例中，所述栅极图案层的材质包含铝、钼或铜。
在本发明的一实施例中，所述栅极图案层是通过一光刻掩膜法形成。
在本发明的一实施例中，所述有源图案层是通过一光刻掩膜法形成。
在本发明的一实施例中，在所述覆盖所述栅极绝缘层于所述栅极图案层及所述基板上的步骤中，以一物理气相沉积法形成所述栅极绝缘层。
在本发明的一实施例中，所述多个倒梯形块的每一个包含一下底面及一上底面，其中所述下底面接触所述有源图案层或所述栅极绝缘层，及所述下底面的面积小于所述上底面的面积。
在本发明的一实施例中，所述多个倒梯形块的每一个包含一左侧面及一右侧面，分别从所述下底面的两侧延伸朝向并连接所述上底面的两侧，其中所述左侧面与所述上底面之间的一第一夹角大于0度且小于90度；及所述右侧面与所述上底面之间的一第二夹角大于0度且小于90度。
在本发明的一实施例中，所述第一夹角大于等于30度且小于90度；及所述第二夹角大于等于30度且小于90度。
 有益效果
与现有技术相比较，本发明的薄膜晶体管结构的制造方法不但可简化制造过程，也不形成用来保护背沟道的蚀刻阻挡层。
 附图说明
图1是根据本发明实施例绘示一种薄膜晶体管结构的制造方法的流程图。
图2A至2G是根据本发明实施例绘示一种薄膜晶体管结构的制造方法在各个制作阶段中的剖面示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。再者，本发明所提到的方向用语，例如上、下、顶、底、前、后、左、右、内、外、侧面、周围、中央、水平、横向、垂直、纵向、轴向、径向、最上层或最下层等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
请参照图1所示，图1是根据本发明实施例绘示一种薄膜晶体管结构的制造方法10的流程图。本发明实施例的一种薄膜晶体管结构的制造方法10包含：提供一基板(步骤11)；形成一栅极图案层于所述基板上(步骤12)；覆盖一栅极绝缘层于所述栅极图案层及所述基板上(步骤13)；形成一有源图案层于所述栅极绝缘层上，其中所述有源图案层的位置对应于所述栅极图案层的位置(步骤14)；形成一光阻图案层于所述有源图案层上及一部分的所述栅极绝缘层上以暴露出所述栅极绝缘层的一源极预定位置及一漏极预定位置，其中所述光阻图案层包含多个倒梯形块(步骤15)；以所述光阻图案层作为一掩膜，沉积一金属层于所述光阻图案层、所述源极预定位置及所述漏极预定位置上(步骤16)；及移除所述光阻图案层以同时移除位于所述光阻图案层上的金属层，以使所述金属层图案化成一源极及一漏极(步骤17)。
请一并参照图1至2G，图2A至2G是根据本发明实施例绘示一种薄膜晶体管结构的制造方法10在各个制作阶段中的剖面示意图。请一并参照图1及2A。在步骤11中，提供一基板21。在一实施例中，所述基板21可以是一透明基板。在步骤12中，形成一栅极图案层22于所述基板21上。在一实施例中，所述栅极图案层22是通过一光刻掩膜法形成。在另一实施例中，所述栅极图案层22的材质包含铝、钼或铜。
请一并参照图1及2B。在步骤13中，覆盖一栅极绝缘层23于所述栅极图案层22及所述基板21上。在一实施例中，所述栅极绝缘层23是利用一物理气相沉积法来沉积在所述栅极图案层22及所述基板21上。在步骤13中，不需使用掩膜形成所述栅极绝缘层23。
请一并参照图1及2C。在步骤14中，形成一有源图案层24于所述栅极绝缘层23上，其中所述有源图案层24的位置对应于所述栅极图案层22的位置。在一实施例中，所述有源图案层24位于所述栅极图案层22的上方。在另一实施例中，所述有源图案层24的材质是氧化物半导体，例如氧化铟镓锌。在又一实施例中，所述有源图案层24是通过一光刻掩膜法形成。
请一并参照图1及2D。在步骤15中，形成一光阻图案层25于所述有源图案层24上及一部分的所述栅极绝缘层23上以暴露出所述栅极绝缘层23的一源极预定位置231及一漏极预定位置232，其中所述光阻图案层25包含多个倒梯形块251。所述多个倒梯形块251的效果将在步骤16中说明。在一实施例中，所述多个倒梯形块251的每一个包含一下底面251A及一上底面251B，其中所述下底面251A接触所述有源图案层24或所述栅极绝缘层23，及所述下底面251A的面积小于所述上底面251B的面积。在另一实施例中，所述多个倒梯形块251的每一个皆包含一左侧面251C及一右侧面251D，分别从所述下底面251A的两侧延伸朝向并连接所述上底面251B的两侧，其中所述左侧面251C与所述上底面251B之间的一第一夹角A1大于0度且小于90度;及所述右侧面251D与所述上底面251B之间的一第二夹角A2大于0度且小于90度。
请一并参照图1及2E。在步骤16中，以所述光阻图案层25作为一掩膜，沉积(例如使用溅镀方式)一金属层26于所述光阻图案层25、所述源极预定位置231及所述漏极预定位置232上。值得一提的是，位在所述源极预定位置231及所述漏极预定位置232上的所述金属层26会与位在所述光阻图案层25上的所述金属层26具有明显的分界，这是因为所述多个倒梯形块251的形状所导致。详言之，若所述光阻图案层25是多个矩型块或多个正梯形块，进行步骤16时，金属层本身所具备的可挠性可能会使得位在源极预定位置及漏极预定位置上的金属层与位在光阻图案层上的金属层不具有明显的分界，甚至金属层会保持一层完整无断面的起伏结构。由于此种金属层没有明显的断面，所以在进行步骤17时，位于源极预定位置及漏极预定位置上的金属层容易被一并带走。由此可见，包含多个倒梯形块251的所述光阻图案层25除了具有作为一掩膜的效果外，还可以协助所述金属层26在进行步骤17时的图案化。
在一实施例中，如图2D所示，所述第一夹角A1及所述第二夹角A2越接近90度时，所述多个倒梯形块251可具有相对稳固的结构，但是也相对减少所述金属层26的断面效果；所述第一夹角A1及所述第二夹角A2越接近0度时，具有较好的所述金属层26的断面效果，但是所述多个倒梯形块251具有较不稳固的结构。为了取得两者的平横点，所述第一夹角A1可以是大于等于30度且小于90度，例如为45度、60度、65度、70度、75度、80度或85度等；及所述第二夹角A2可以是大于等于30度且小于90度，例如为45度、60度、65度、70度、75度、80度或85度等。值得一提的是，所述第一夹角A1也可以选择为不相等于所述第二夹角A2，例如，所述第一夹角A1是30度及所述第二夹角A2是45度。
请一并参照图1及2F。在步骤17中，移除所述光阻图案层25以同时移除位于所述光阻图案层25上的金属层26，以使所述金属层26图案化成一源极261及一漏极262，以制得本发明实施例的薄膜晶体管结构20。
在一实施例中，请参照图2G，在所述移除所述光阻图案层25的步骤17之后，本发明实施例的薄膜晶体管结构的制造方法10可包含:覆盖一钝化层27于所述源极261、所述漏极262、所述有源图案层24及所述栅极图案层22上，从而避免所述源极261及所述漏极262被氧化或腐蚀。
综上所述，本发明实施例的薄膜晶体管结构的制造方法不但可以减少二道掩膜程序(蚀刻停止层所使用的掩膜及蚀刻源/漏极所使用的掩膜)以简化制造过程，也不形成用来保护背沟道的蚀刻阻挡层，以避免形成蚀刻阻挡层所产生的问题。
本发明已由上述相关实施例加以描述，然而上述实施例仅为实施本发明的范例。必需指出的是，已公开的实施例并未限制本发明的范围。相反地，包含于权利要求书的精神及范围的修改及均等设置均包括于本发明的范围内。

Claims (18)

  1. 一种薄膜晶体管结构的制造方法，其包含步骤:
    提供一基板；
    形成一栅极图案层于所述基板上;
    覆盖一栅极绝缘层于所述栅极图案层及所述基板上;
    形成一有源图案层于所述栅极绝缘层上，其中所述有源图案层的位置对应于所述栅极图案层的位置;
    形成一光阻图案层于所述有源图案层上及一部分的所述栅极绝缘层上以暴露出所述栅极绝缘层的一源极预定位置及一漏极预定位置，其中所述光阻图案层包含多个倒梯形块;
    以所述光阻图案层作为一掩膜，沉积一金属层于所述光阻图案层、所述源极预定位置及所述漏极预定位置上;及
    移除所述光阻图案层以同时移除位于所述光阻图案层上的金属层，以使所述金属层图案化成一源极及一漏极;
    其中在所述移除所述光阻图案层的步骤之后，更包含:覆盖一钝化层于所述源极、所述漏极、所述有源图案层及所述栅极图案层上;及
    其中在所述沉积所述金属层的步骤中，以所述光阻图案层为一光掩膜，以溅镀方式形成所述金属层于所述光阻图案层、所述源极预定位置及所述漏极预定位置上。
  2. 如权利要求1所述的薄膜晶体管结构的制造方法，其中所述栅极图案层的材质包含铝、钼或铜。
  3. 如权利要求1所述的薄膜晶体管结构的制造方法，其中所述栅极图案层是通过一光刻掩膜法形成。
  4. 如权利要求1所述的薄膜晶体管结构的制造方法，其中所述有源图案层是通过一光刻掩膜法形成。
  5. 如权利要求1所述的薄膜晶体管结构的制造方法，其中在所述覆盖所述栅极绝缘层于所述栅极图案层及所述基板上的步骤中，以一物理气相沉积法形成所述栅极绝缘层。
  6. 如权利要求1所述的薄膜晶体管结构的制造方法，其中所述多个倒梯形块的每一个包含一下底面及一上底面，其中所述下底面接触所述有源图案层或所述栅极绝缘层，及所述下底面的面积小于所述上底面的面积。
  7. 如权利要求6所述的薄膜晶体管结构的制造方法，其中所述多个倒梯形块的每一个包含一左侧面及一右侧面，分别从所述下底面的两侧延伸朝向并连接所述上底面的两侧，其中所述左侧面与所述上底面之间的一第一夹角大于0度且小于90度；及所述右侧面与所述上底面之间的一第二夹角大于0度且小于90度。
  8. 如权利要求7所述的薄膜晶体管结构的制造方法，其中所述第一夹角大于等于30度且小于90度;及所述第二夹角大于等于30度且小于90度。
  9. 一种薄膜晶体管结构的制造方法，其包含步骤:
    提供一基板;
    形成一栅极图案层于所述基板上;
    覆盖一栅极绝缘层于所述栅极图案层及所述基板上;
    形成一有源图案层于所述栅极绝缘层上，其中所述有源图案层的位置对应于所述栅极图案层的位置;
    形成一光阻图案层于所述有源图案层上及一部分的所述栅极绝缘层上以暴露出所述栅极绝缘层的一源极预定位置及一漏极预定位置，其中所述光阻图案层包含多个倒梯形块;
    以所述光阻图案层作为一掩膜，沉积一金属层于所述光阻图案层、所述源极预定位置及所述漏极预定位置上;及
    移除所述光阻图案层以同时移除位于所述光阻图案层上的金属层，以使所述金属层图案化成一源极及一漏极。
  10. 如权利要求9所述的薄膜晶体管结构的制造方法，其中在所述移除所述光阻图案层的步骤之后，更包含:覆盖一钝化层于所述源极、所述漏极、所述有源图案层及所述栅极图案层上。
  11. 如权利要求9所述的薄膜晶体管结构的制造方法，其中在所述沉积所述金属层的步骤中，以所述光阻图案层为一光掩膜，以溅镀方式形成所述金属层于所述光阻图案层、所述源极预定位置及所述漏极预定位置上。
  12. 如权利要求9所述的薄膜晶体管结构的制造方法，其中所述栅极图案层的材质包含铝、钼或铜。
  13. 如权利要求9所述的薄膜晶体管结构的制造方法，其中所述栅极图案层是通过一光刻掩膜法形成。
  14. 如权利要求9所述的薄膜晶体管结构的制造方法，其中所述有源图案层是通过一光刻掩膜法形成。
  15. 如权利要求9所述的薄膜晶体管结构的制造方法，其中在所述覆盖所述栅极绝缘层于所述栅极图案层及所述基板上的步骤中，以一物理气相沉积法形成所述栅极绝缘层。
  16. 如权利要求9所述的薄膜晶体管结构的制造方法，其中所述多个倒梯形块的每一个包含一下底面及一上底面，其中所述下底面接触所述有源图案层或所述栅极绝缘层，及所述下底面的面积小于所述上底面的面积。
  17. 如权利要求16所述的薄膜晶体管结构的制造方法，其中所述多个倒梯形块的每一个包含一左侧面及一右侧面，分别从所述下底面的两侧延伸朝向并连接所述上底面的两侧，其中所述左侧面与所述上底面之间的一第一夹角大于0度且小于90度；及所述右侧面与所述上底面之间的一第二夹角大于0度且小于90度。
  18. 如权利要求17所述的薄膜晶体管结构的制造方法，其中所述第一夹角大于等于30度且小于90度；及所述第二夹角大于等于30度且小于90度。
PCT/CN2016/074501 2016-01-13 2016-02-25 薄膜晶体管结构的制造方法 Ceased WO2017121007A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/029,253 US20180047763A1 (en) 2016-01-13 2016-02-25 Method of fabricating thin film transistor structure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201610022135.7 2016-01-13
CN201610022135.7A CN105655257A (zh) 2016-01-13 2016-01-13 薄膜晶体管结构的制造方法

Publications (1)

Publication Number Publication Date
WO2017121007A1 true WO2017121007A1 (zh) 2017-07-20

Family

ID=56487495

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2016/074501 Ceased WO2017121007A1 (zh) 2016-01-13 2016-02-25 薄膜晶体管结构的制造方法

Country Status (3)

Country Link
US (1) US20180047763A1 (zh)
CN (1) CN105655257A (zh)
WO (1) WO2017121007A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106229297B (zh) * 2016-09-18 2019-04-02 深圳市华星光电技术有限公司 Amoled像素驱动电路的制作方法
CN107706115A (zh) * 2017-10-09 2018-02-16 深圳市华星光电半导体显示技术有限公司 一种薄膜晶体管及其制作方法
CN108179378A (zh) * 2017-12-21 2018-06-19 武汉华星光电半导体显示技术有限公司 金属光掩膜的制作方法以及金属光掩膜
US11825661B2 (en) * 2020-09-23 2023-11-21 Taiwan Semiconductor Manufacturing Company Limited Mobility enhancement by source and drain stress layer of implantation in thin film transistors
CN115440666B (zh) * 2022-11-10 2023-01-24 广州粤芯半导体技术有限公司 具有双应力衬垫结构的cmos器件的制造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6034015A (ja) * 1983-08-05 1985-02-21 Canon Inc パタ−ン形成方法
US4933303A (en) * 1989-07-25 1990-06-12 Standard Microsystems Corporation Method of making self-aligned tungsten interconnection in an integrated circuit
JPH02215134A (ja) * 1989-02-15 1990-08-28 Fujitsu Ltd 薄膜トランジスタの製造方法
CN1056187A (zh) * 1990-04-17 1991-11-13 通用电气公司 用背面曝光和非镜面反射层光刻形成自对准掩模的方法
CN101013240A (zh) * 2007-01-31 2007-08-08 友达光电股份有限公司 阵列基板的制作方法

Family Cites Families (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4745045A (en) * 1985-03-11 1988-05-17 International Business Machines Corporation Method for improving resolution in microelectronic circuits using photoresist overlayer by using thermally processed polyimide underlayer formed from positive photoresist and polyamic acid
US5360698A (en) * 1992-09-21 1994-11-01 Eastman Kodak Company Deep UV lift-off resist process
US5391507A (en) * 1993-09-03 1995-02-21 General Electric Company Lift-off fabrication method for self-aligned thin film transistors
JP3448838B2 (ja) * 1995-06-30 2003-09-22 富士通株式会社 磁気抵抗効果型ヘッドの製造方法
JPH10116964A (ja) * 1996-10-09 1998-05-06 Oki Electric Ind Co Ltd 半導体装置とその製造方法およびスパッタリング装置
KR100490575B1 (ko) * 2001-08-03 2005-05-17 야마하 가부시키가이샤 귀금속 박막 패턴 형성방법
JP3627705B2 (ja) * 2002-01-04 2005-03-09 株式会社村田製作所 電極の形成方法
JP2004200209A (ja) * 2002-12-16 2004-07-15 Fuji Xerox Co Ltd 電極等の導電パターンの形成方法およびこれを用いた面発光型半導体レーザ並びにその製造方法
TWI220770B (en) * 2003-06-11 2004-09-01 Ind Tech Res Inst Method for forming a conductive layer
JP2005320590A (ja) * 2004-05-10 2005-11-17 National Institute For Materials Science コンビナトリアル成膜方法とその装置
CN101047145A (zh) * 2006-03-30 2007-10-03 京东方科技集团股份有限公司 一种制备有源驱动tft矩阵中金属连线的方法
WO2008117362A1 (ja) * 2007-03-23 2008-10-02 Pioneer Corporation 有機トランジスタ及びその製造方法
JP2009021477A (ja) * 2007-07-13 2009-01-29 Sony Corp 半導体装置およびその製造方法、ならびに表示装置およびその製造方法
US7989146B2 (en) * 2007-10-09 2011-08-02 Eastman Kodak Company Component fabrication using thermal resist materials
US7960097B2 (en) * 2007-10-30 2011-06-14 Triquint Semiconductor, Inc. Methods of minimizing etch undercut and providing clean metal liftoff
CN102203956A (zh) * 2008-08-12 2011-09-28 戴索有限公司 用于柔性光电和显示设备中的集电器系统和制造方法
WO2010085507A1 (en) * 2009-01-20 2010-07-29 President And Fellows Of Harvard College Electrodes for fuel cells
JP5724157B2 (ja) * 2009-04-13 2015-05-27 日立金属株式会社 酸化物半導体ターゲット及びそれを用いた酸化物半導体装置の製造方法
JP2011100831A (ja) * 2009-11-05 2011-05-19 Sony Corp 半導体装置及び半導体装置を用いた表示装置
KR101602635B1 (ko) * 2009-11-30 2016-03-22 삼성디스플레이 주식회사 표시 장치, 박막 트랜지스터 기판 및 이의 제조 방법
KR20110093113A (ko) * 2010-02-11 2011-08-18 삼성전자주식회사 박막 트랜지스터 기판 및 이의 제조 방법
TW201203652A (en) * 2010-04-27 2012-01-16 Orthogonal Inc Method for forming an organic device
JP6151888B2 (ja) * 2011-05-27 2017-06-21 株式会社半導体エネルギー研究所 発光装置の作製方法
US8455312B2 (en) * 2011-09-12 2013-06-04 Cindy X. Qiu Fabrication methods for T-gate and inverted L-gate structure for high frequency devices and circuits
JP2013115098A (ja) * 2011-11-25 2013-06-10 Sony Corp トランジスタ、トランジスタの製造方法、表示装置および電子機器
CN104040693B (zh) * 2012-12-04 2017-12-12 深圳市柔宇科技有限公司 一种金属氧化物tft器件及制造方法
US9679995B2 (en) * 2013-03-22 2017-06-13 Shenzhen Royole Technologies Co., Ltd. Method for manufacturing thin film transistor and pixel unit thereof
CN103295970B (zh) * 2013-06-05 2015-04-29 京东方科技集团股份有限公司 阵列基板、其制造方法及显示装置
JP6227396B2 (ja) * 2013-12-20 2017-11-08 株式会社ジャパンディスプレイ 薄膜トランジスタ及びそれを用いた表示装置
CN103730510B (zh) * 2013-12-24 2016-12-14 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板、显示装置
US9312276B2 (en) * 2014-03-28 2016-04-12 Shenzhen China Star Optoelectronics Technology Co., Ltd Method for manufacturing array substrate
KR20170039306A (ko) * 2014-08-14 2017-04-10 광주과학기술원 직교 패터닝 방법
TWI546850B (zh) * 2014-11-14 2016-08-21 群創光電股份有限公司 顯示面板之製備方法
CN104392928A (zh) * 2014-11-20 2015-03-04 深圳市华星光电技术有限公司 薄膜晶体管的制造方法
CN104952792B (zh) * 2015-07-13 2017-12-29 深圳市华星光电技术有限公司 Tft基板结构的制作方法
CN105140271B (zh) * 2015-07-16 2019-03-26 深圳市华星光电技术有限公司 薄膜晶体管、薄膜晶体管的制造方法及显示装置
CN105206678A (zh) * 2015-10-29 2015-12-30 京东方科技集团股份有限公司 薄膜晶体管及阵列基板的制作方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6034015A (ja) * 1983-08-05 1985-02-21 Canon Inc パタ−ン形成方法
JPH02215134A (ja) * 1989-02-15 1990-08-28 Fujitsu Ltd 薄膜トランジスタの製造方法
US4933303A (en) * 1989-07-25 1990-06-12 Standard Microsystems Corporation Method of making self-aligned tungsten interconnection in an integrated circuit
CN1056187A (zh) * 1990-04-17 1991-11-13 通用电气公司 用背面曝光和非镜面反射层光刻形成自对准掩模的方法
CN101013240A (zh) * 2007-01-31 2007-08-08 友达光电股份有限公司 阵列基板的制作方法

Also Published As

Publication number Publication date
US20180047763A1 (en) 2018-02-15
CN105655257A (zh) 2016-06-08

Similar Documents

Publication Publication Date Title
JP6092260B2 (ja) アレイ基板の製造方法及びアレイ基板、ディスプレー
WO2017121007A1 (zh) 薄膜晶体管结构的制造方法
US8728861B2 (en) Fabrication method for ZnO thin film transistors using etch-stop layer
JPH09181014A (ja) 薄膜トランジスタ基板およびその製造方法
CN105336746B (zh) 一种双栅极薄膜晶体管及其制作方法、以及阵列基板
WO2016106799A1 (zh) Tft-lcd像素结构及其制作方法
WO2016029541A1 (zh) 薄膜晶体管及其的制备方法、阵列基板和显示装置
WO2015067054A1 (zh) 互补式薄膜晶体管及其制备方法、阵列基板和显示装置
CN105762195A (zh) 金属氧化物薄膜晶体管及其制备方法
CN109494257B (zh) 一种薄膜晶体管及其制造方法、阵列基板、显示装置
WO2021026990A1 (zh) 一种阵列基板及其制作方法
CN106229298B (zh) 一种阵列基板及其制作方法
US20170373165A1 (en) Dual-gate tft array substrate and manufacturing method thereof
JP5679397B2 (ja) 薄膜トランジスタ基板の製造方法
KR20160101211A (ko) 박막 트랜지스터 어레이 기판 및 그의 제조 방법
CN109037241A (zh) Ltps阵列基板及其制造方法、显示面板
WO2017124690A1 (zh) 薄膜晶体管结构的制造方法
CN108886042B (zh) 阵列基板及其制造方法、显示面板和显示设备
WO2019095562A1 (zh) Tft基板的制作方法
WO2016197400A1 (zh) Ltps阵列基板及其制造方法
CN101320712A (zh) 半导体器件的制造方法
CN113206144B (zh) 薄膜晶体管的制备方法、薄膜晶体管及显示面板
CN104617112B (zh) 阵列基板及其制作方法、显示装置
CN102830531B (zh) Tft阵列基板、制造方法及液晶显示装置
CN108064414A (zh) 阵列基板的制造方法

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15029253

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16884569

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16884569

Country of ref document: EP

Kind code of ref document: A1