WO2017094644A1 - 半導体基板及び表示装置 - Google Patents

半導体基板及び表示装置 Download PDF

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Publication number
WO2017094644A1
WO2017094644A1 PCT/JP2016/085117 JP2016085117W WO2017094644A1 WO 2017094644 A1 WO2017094644 A1 WO 2017094644A1 JP 2016085117 W JP2016085117 W JP 2016085117W WO 2017094644 A1 WO2017094644 A1 WO 2017094644A1
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Prior art keywords
film
semiconductor
insulating film
substrate
electrode
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PCT/JP2016/085117
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English (en)
French (fr)
Inventor
今井　元
徹 大東
久雄 越智
藤田　哲生
北川　英樹
菊池　哲郎
鈴木　正彦
輝幸 上田
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シャープ株式会社
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Priority to US15/779,655 priority Critical patent/US10243010B2/en
Publication of WO2017094644A1 publication Critical patent/WO2017094644A1/ja

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    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G02F1/13685—Top gates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel

Definitions

  • the present invention relates to a semiconductor substrate and a display device, and more particularly to a semiconductor substrate used for a display device including a touch sensor.
  • a touch panel attached type that attaches the touch panel to the display device after the display device and the touch panel are separately manufactured, or a touch sensor on the surface of the upper glass substrate of the display device.
  • an upper plate integrated type on-cell type
  • the display device integrated with the upper plate is thinner than the display device with the upper plate, but a display device integrated with a touch sensor has been developed as a display device of a thinner type.
  • Patent Document 1 a plurality of gate lines and a plurality of data lines intersecting each other, a plurality of pixel electrodes formed in an area defined by the intersection of the plurality of gate lines and the plurality of data lines, and a plurality of There is disclosed a touch sensor integrated display device including a plurality of common electrodes formed so as to overlap with the pixel electrode.
  • the plurality of common electrodes also serve as the common electrode of the display, the touch drive electrode that constitutes the touch sensor, and the touch sensing electrode.
  • the TFT has a bottom gate structure as described above. Therefore, the gate electrode and the source electrode are necessarily arranged so as to overlap each other in the plan view. When the gate electrode and the source electrode overlap with each other in plan view, a parasitic capacitance is generated between the gate electrode and the source electrode, which may cause signal dullness during signal writing.
  • An object of the present invention is to provide a display device that suppresses the generation of parasitic capacitance and has a short writing time.
  • the semiconductor substrate of the present invention includes a substrate, a light shielding film provided on the substrate, a first insulating film provided on the substrate so as to cover the light shielding film, and a light shielding film and a planar surface on the first insulating film.
  • the source electrode, the drain electrode, and the gate electrode are provided so as not to overlap with each other in plan view. Therefore, by suppressing the generation of parasitic capacitance, a semiconductor substrate and a display device with a short writing time can be obtained. Obtainable.
  • FIG. 1 is an explanatory diagram schematically showing a cross-sectional configuration of a liquid crystal display device.
  • FIG. 2 is a plan view of the liquid crystal panel of the first embodiment.
  • FIG. 3 is a plan view of the liquid crystal panel showing in detail the layout of the TFT array substrate of the first embodiment.
  • 4 is a cross-sectional view taken along line AA of the liquid crystal display panel of FIG.
  • FIG. 5 is a cross-sectional view of the substrate showing the manufacturing process of the TFT array substrate.
  • FIG. 6 is a plan view of the substrate showing the manufacturing process of the TFT array substrate.
  • FIG. 7 is a sectional view taken along line BB in FIG.
  • FIG. 8 is a cross-sectional view of the substrate showing the manufacturing process of the TFT array substrate.
  • FIG. 1 is an explanatory diagram schematically showing a cross-sectional configuration of a liquid crystal display device.
  • FIG. 2 is a plan view of the liquid crystal panel of the first embodiment.
  • FIG. 3
  • FIG. 9 is a plan view of the substrate showing the manufacturing process of the TFT array substrate.
  • 10 is a cross-sectional view taken along the line CC of FIG.
  • FIG. 11 is a plan view of the substrate showing the manufacturing process of the TFT array substrate.
  • 12 is a cross-sectional view taken along the line DD of FIG.
  • FIG. 13 is a cross-sectional view of the substrate illustrating the manufacturing process of the TFT array substrate.
  • FIG. 14 is a cross-sectional view of the substrate illustrating the manufacturing process of the TFT array substrate.
  • FIG. 15 is a cross-sectional view of the substrate illustrating the manufacturing process of the TFT array substrate.
  • FIG. 16 is a cross-sectional view of the substrate illustrating the manufacturing process of the TFT array substrate.
  • FIG. 17 is a plan view of the substrate showing the manufacturing process of the TFT array substrate.
  • 18 is a cross-sectional view taken along line EE in FIG.
  • FIG. 19 is a cross-sectional view
  • the semiconductor substrate of the present invention includes a substrate, a light shielding film provided on the substrate, a first insulating film provided on the substrate so as to cover the light shielding film, and a light shielding film and a planar surface on the first insulating film.
  • a gate electrode provided so as not to overlap with each other in plan view, a third insulating film covering the gate electrode and in contact with the source electrode and the drain electrode through the contact hole on the second insulating film; With ( 1 configuration).
  • the semiconductor substrate includes the semiconductor film, the source electrode, and the drain electrode on the first insulating film, the second insulating film on the first insulating film, and the second insulating film.
  • a gate electrode is provided on the insulating film. That is, the semiconductor substrate includes a top gate type semiconductor. Therefore, a structure in which the gate electrode does not overlap with either the source electrode or the drain electrode in plan view can be obtained. Therefore, generation of parasitic capacitance between the gate electrode and the source and drain electrodes can be suppressed, and as a result, a semiconductor substrate with a short writing time can be obtained. Note that since the semiconductor film is provided so as to overlap with the light-shielding film in plan view, the semiconductor film can be prevented from being exposed to light and being deteriorated.
  • the third insulating film is in contact with the semiconductor film in addition to the source electrode and the drain electrode through the contact hole, and the hydrogen of the third insulating film
  • the concentration is 1 ⁇ 10 22 cm ⁇ 3 or more (second configuration).
  • the third insulating film having a hydrogen concentration of 1 ⁇ 10 22 cm ⁇ 3 or more is in contact with the semiconductor film, hydrogen easily enters the semiconductor film from the third insulating film.
  • oxygen in the semiconductor film is extracted and the resistance of the oxide semiconductor becomes low.
  • the electron transfer efficiency of the semiconductor in the semiconductor substrate can be improved.
  • the semiconductor film in the first or second configuration, is formed of an oxide film semiconductor (third configuration).
  • the semiconductor film is an In—Ga—Zn—O-based oxide semiconductor (fourth configuration).
  • the semiconductor film is a crystalline oxide semiconductor (fifth configuration).
  • the display device of the present invention includes a semiconductor substrate having any one of the first to fifth configurations.
  • FIG. 1 is an explanatory diagram schematically illustrating a cross-sectional configuration of the liquid crystal display device 100 according to the first embodiment.
  • the liquid crystal display device 100 includes a liquid crystal display panel 200 that displays an image on a display surface 200a, a backlight device 300 that supplies light to the liquid crystal display panel 200, a casing 400 that houses the liquid crystal display panel 200, the backlight device 300, and the like. Is provided.
  • the liquid crystal display panel 200 includes a TFT array substrate 210, a counter substrate 220, a liquid crystal layer 230, and a sealing material 240.
  • the TFT array substrate 210 and the counter substrate 220 are arranged to face each other.
  • the TFT array substrate 210 and the counter substrate 220 are bonded together with a frame-shaped sealing material 240.
  • a liquid crystal layer 230 is sealed in a space surrounded by the sealing material 240 between the TFT array substrate 210 and the counter substrate 220.
  • the liquid crystal display panel 200 operates in an FFS (Fringe Field Switching) mode.
  • FFS Frringe Field Switching
  • the backlight device 300 is a device that irradiates light toward the liquid crystal display panel 200 while using an LED (Light Emitting Diode) as a light source. As shown in FIG. 1, the backlight device 300 is disposed on the TFT array substrate 210 side of the liquid crystal display panel 200 and irradiates light toward the TFT array substrate 210. The liquid crystal display panel 200 displays an image on the display surface 200 a using light supplied from the backlight device 300.
  • LED Light Emitting Diode
  • the liquid crystal display device 100 of the present embodiment is used in various electronic devices such as a mobile phone, a smartphone, a laptop computer, a tablet terminal, a portable information terminal, a digital photo frame, a portable game machine, and electronic ink paper. .
  • FIG. 2 is a plan view of the liquid crystal display panel 200.
  • the liquid crystal display panel 200 includes the TFT array substrate 210, the counter substrate 220, and the liquid crystal layer 230 as described above.
  • the TFT array substrate 210 is slightly larger than the counter substrate 220.
  • a gate driver 211, a source driver / touch panel controller 212, and the like are formed in a region of the TFT array substrate 210 that is larger than the counter substrate 220.
  • a plurality of gate wirings 42 are provided from the gate driver 211 so as to extend in parallel with each other.
  • a plurality of source wirings 24 and touch panel wirings 12 are provided from the source driver / touch panel control unit 212 so as to extend in parallel with each other.
  • the touch panel wiring 12 is electrically connected to a common electrode 51 described later.
  • FIG. 3 is a plan view showing a layout of the TFT array substrate 210 in the liquid crystal display panel 200.
  • FIG. 4 is a cross-sectional view of the liquid crystal display panel 200 taken along line AA in FIG.
  • the TFT array substrate 210 is a semiconductor substrate. The configuration of the TFT array substrate 210 will be described later. A polarizing plate (not shown) is provided on the surface of the TFT array substrate 210 opposite to the liquid crystal layer 230.
  • the counter substrate 220 has a predetermined arrangement of colored portions such as a transparent glass substrate (transparent substrate) 221, a black matrix 222, R (red), G (green), and B (blue). And a color filter 223, an alignment film (not shown), and the like are arranged.
  • a polarizing plate (not shown) is provided on the surface of the counter substrate 220 opposite to the liquid crystal layer 230.
  • the TFT array substrate 210 includes a top gate type TFT 250.
  • the TFT array substrate 210 has a configuration in which a plurality of TFTs 250 as switching elements and pixel electrodes 43 connected thereto are arranged in a matrix on the transparent substrate 10.
  • a source wiring 24 and a gate wiring 42 are arranged on the TFT array substrate 210 so as to partition the TFT 250 and the like.
  • the TFT array substrate 210 includes a transparent substrate 10, a light shielding film 11, a first insulating film 20, a semiconductor film 21, a source electrode 22, a drain electrode 23, and a source wiring 24.
  • the transparent substrate 10 is made of a glass plate material.
  • the transparent substrate 10 is not limited to glass, and various substrates can be used.
  • a substrate such as a single crystal semiconductor substrate, an oxide single crystal substrate, a metal substrate, a glass substrate, a quartz substrate, or a resin substrate can be used.
  • a conductive substrate such as a single crystal semiconductor substrate or a metal substrate, it is preferably used by providing an insulating film or the like thereon.
  • the light shielding film 11 is formed on the transparent substrate 10.
  • the light shielding film 11 is formed in a floating island shape that is not electrically connected to other components.
  • the light shielding film 11 is provided below the semiconductor film 21 and shields the semiconductor film 21 from light.
  • the light shielding film 11 is formed of, for example, a metal film.
  • the first insulating film 20 is provided on the transparent substrate 10 so as to cover the light shielding film 11.
  • the first insulating film 20 is made of, for example, a SiN x film or a SiO 2 film.
  • the semiconductor film 21 is formed on the first insulating film 20.
  • the semiconductor film 21 is formed so as to overlap the region where the light shielding film 11 is formed in a plan view.
  • the region where the semiconductor film 21 is formed is preferably slightly smaller than the region where the light shielding film 11 is formed, as shown in FIG.
  • the semiconductor film 21 is formed of an oxide semiconductor.
  • the oxide semiconductor contained in the semiconductor film 21 may be an amorphous oxide semiconductor or a crystalline oxide semiconductor having a crystalline portion.
  • the crystalline oxide semiconductor include a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, and a crystalline oxide semiconductor in which the c-axis is oriented substantially perpendicular to the layer surface.
  • the semiconductor film 21 may have a laminated structure of two or more layers.
  • the semiconductor film 21 may include an amorphous oxide semiconductor layer and a crystalline oxide semiconductor layer.
  • a plurality of crystalline oxide semiconductor layers having different crystal structures may be included.
  • a plurality of amorphous oxide semiconductor layers may be included.
  • the energy gap of the oxide semiconductor included in the upper layer is preferably larger than the energy gap of the oxide semiconductor included in the lower layer.
  • the energy gap of the lower oxide semiconductor may be larger than the energy gap of the upper oxide semiconductor.
  • the semiconductor film 21 may contain at least one metal element of In, Ga, and Zn, for example.
  • the semiconductor film 21 includes, for example, an In—Ga—Zn—O-based semiconductor (for example, indium gallium zinc oxide).
  • Such a semiconductor film 21 can be formed of an oxide semiconductor film containing an In—Ga—Zn—O-based semiconductor.
  • the In—Ga—Zn—O-based oxide semiconductor may be amorphous or crystalline.
  • a crystalline In—Ga—Zn—O-based semiconductor in which the c-axis is oriented substantially perpendicular to the layer surface is preferable.
  • a TFT having an In—Ga—Zn—O-based semiconductor layer has high mobility (more than 20 times that of an a-Si TFT) and low leakage current (less than one hundredth of that of an a-Si TFT).
  • the TFT is suitably used as a driving TFT (for example, a TFT included in a driving circuit provided on the same substrate as the display area around a display area including a plurality of pixels) and a pixel TFT (a TFT provided in the pixel).
  • a driving TFT for example, a TFT included in a driving circuit provided on the same substrate as the display area around a display area including a plurality of pixels
  • a pixel TFT a TFT provided in the pixel
  • the semiconductor film 21 may include another oxide semiconductor instead of the In—Ga—Zn—O-based semiconductor.
  • an In—Sn—Zn—O-based semiconductor eg, In 2 O 3 —SnO 2 —ZnO; InSnZnO
  • the In—Sn—Zn—O-based semiconductor is a ternary oxide of In (indium), Sn (tin), and Zn (zinc).
  • the semiconductor film 21 may be an In—Al—Zn—O based semiconductor, an In—Al—Sn—Zn—O based semiconductor, a Zn—O based semiconductor, an In—Zn—O based semiconductor, or a Zn—Ti—O based semiconductor.
  • An oxide semiconductor such as an —In—Zn—O-based semiconductor or an Hf—In—Zn—O-based semiconductor may be included.
  • the source electrode 22, the drain electrode 23, and the source wiring 24 are formed on the first insulating film 20. Part of the source electrode 22 and the drain electrode 23 is formed so as to cover the semiconductor film 21. In the semiconductor film 21, a region between the source electrode 22 and the drain electrode 23 forms a channel region 21c.
  • the gate insulating film 30 is formed on the first insulating film 20 so as to cover the semiconductor film 21, the source electrode 22, the drain electrode 23, the source wiring 24, and the like.
  • the gate insulating film 30 is formed of, for example, a SiN x film or a SiO 2 film.
  • the photosensitive resin film 40 is formed on the gate insulating film 30.
  • the photosensitive resin film 40 is made of, for example, an organic photosensitive resin such as acrylic.
  • Contact holes CH1 and CH2 are formed in the gate insulating film 30 and the photosensitive resin film 40.
  • the contact hole CH1 is formed in the region where the semiconductor film 21 is formed.
  • both the gate insulating film 30 and the photosensitive resin film 40 are removed, and the semiconductor film 21 is exposed on the surface of the contact hole CH1.
  • the region overlapping with the channel region 21c only the photosensitive resin film 40 is removed, and the gate insulating film 30 remains.
  • the contact hole CH2 is formed in a region where the drain electrode 23 is formed.
  • the drain electrode 23 is exposed on the surface of the contact hole CH2.
  • the gate electrode 41 is formed on the gate insulating film 30 as shown in FIG.
  • the gate electrode 41 is formed so as to overlap the channel region 21c of the semiconductor film 21 in plan view.
  • the gate wiring 42 is disposed so as to be orthogonal to the source wiring 24.
  • the gate electrode 41 and the gate wiring 42 are formed of a transparent conductive film 41a common to the pixel electrode 43 and a metal film 41b covering the transparent conductive film 41a.
  • the pixel electrode 43 is electrically connected to the drain electrode 23 through a contact hole CH2 formed in the gate insulating film 30 and the photosensitive resin film 40.
  • the pixel electrode 43 is formed of a transparent conductive film.
  • the passivation film 50 is formed on the photosensitive resin film 40 so as to cover the gate electrode 41, the pixel electrode 43, and the like.
  • the passivation film 50 is in contact with the semiconductor film 21 in the contact hole CH1.
  • the passivation film 50 is formed of, for example, a SiN x film.
  • the hydrogen concentration of the passivation film 50 is preferably 1 ⁇ 10 22 cm ⁇ 3 or more. Since the passivation film 50 having a hydrogen concentration of 1 ⁇ 10 22 cm ⁇ 3 or more is in contact with the semiconductor film 21, oxygen is extracted from a region adjacent to the channel region 21c in the semiconductor film 21, thereby reducing the resistance of the region. can do.
  • the common electrode 51 is formed so as to cover the passivation film 50.
  • the common electrode 51 is formed in the upper layer of the pixel electrode 43. As shown in FIG. 3, the common electrode 51 is a comb-like electrode.
  • the common electrode 51 is formed of a transparent conductive film such as ITO, for example.
  • the pattern shape of the TFT array substrate 210 can be confirmed after disassembling the TFT array substrate 210, and then using an optical microscope, STEM (Scanning Transmission Electron Microscope), SEM (Scanning Electron Microscope). ) Or the like.
  • TFT array substrate manufacturing method Next, a manufacturing method of the TFT array substrate 210 will be described with reference to FIGS.
  • the transparent substrate 10 is prepared. Then, for example, a light shielding film is formed by laminating a copper (Cu) film and a titanium (Ti) film. Specifically, for example, after forming a copper (Cu) film and a titanium (Ti) film by sputtering, photolithography by wet etching is performed, as shown in FIG. A film 11 is formed.
  • a light shielding film is formed by laminating a copper (Cu) film and a titanium (Ti) film. Specifically, for example, after forming a copper (Cu) film and a titanium (Ti) film by sputtering, photolithography by wet etching is performed, as shown in FIG. A film 11 is formed.
  • an SiO 2 film and an SiN film are formed by using, for example, a CVD method, and an insulating film covering the transparent substrate 10 and the light shielding film 11 is formed as shown in FIG.
  • the first insulating film 20 is formed by performing photolithography by dry etching on the insulating film.
  • the first insulating film 20 may be formed by forming a transparent SOG film by using, for example, a spin coating method.
  • an oxide semiconductor film is formed on the first insulating film 20 by using, for example, a sputtering method. Then, the oxide semiconductor film is patterned using photolithography by wet etching to form an island-shaped semiconductor film 21 as shown in FIG. At this time, the region where the semiconductor film 21 is formed is a region overlapping the light shielding film 11 in plan view.
  • a copper (Cu) film and a titanium (Ti) film are laminated to form a conductive film.
  • the metal film is patterned by photolithography using wet etching or dry etching, and the source electrode 22, A conductive film constituting the drain electrode 23, the source wiring 24, and the like is formed.
  • the conductive film constituting the source electrode 22 and the like may have the structure of the other metal film exemplified above or may have a single layer structure. However, this conductive film preferably has a two-layer structure.
  • a low resistance metal for example, aluminum (Al) or copper (Cu) is suitable as the material constituting the lower layer.
  • a metal for example, titanium (Ti), molybdenum (Mo) film, titanium nitride (TiN), which is difficult to be etched at the time of overetching due to in-plane distribution in the subsequent dry etching process, Molybdenum nitride (MoN) or the like is preferable.
  • a SiN x film and a SiO 2 film are sequentially formed on the first insulating film 20 by using, for example, PECVD so as to cover the conductive film such as the source electrode 22. Then, the insulating film 30p is formed.
  • the insulating film 30 p formed here is a film constituting the gate insulating film 30.
  • a photosensitive resin film 40 such as an acrylic resin is formed on the SiO 2 film.
  • the photosensitive resin film 40 is patterned by photolithography to form a contact hole CH1a that overlaps the semiconductor film 21 and a contact hole CH2a that overlaps the drain electrode 23, as shown in FIGS. Then, an annealing process is performed on the photosensitive resin film 40.
  • patterning is performed by photolithography of the insulating film 30p to form a contact hole CH2 reaching the drain electrode 23 from the surface of the photosensitive resin film 40.
  • a transparent conductive film is formed on the photosensitive resin film 40 by using, for example, a sputtering method, and the conductive film is further laminated. Then, patterning is performed by photolithography using wet etching, the gate electrode 41 made of the transparent conductive film 41a and the conductive film 41b, the gate wiring 42 made of the transparent conductive film and the conductive film (see FIG. 11), and transparent.
  • a pixel electrode 43 made of a conductive film is formed. The conductive film 43b having the same pattern as the pixel electrode 43 remains in the upper layer of the pixel electrode 43.
  • a resist R is formed in a region overlapping with the gate electrode 41 and the gate wiring 42. Then, as shown in FIG. 14, the conductive film 43b on the pixel electrode 43 is removed by wet etching.
  • the gate insulating film 30 in the region where the gate electrode 41 does not exist in the region overlapping the contact hole CH1a formed in the photosensitive resin film 40 is removed by dry etching. Thereby, the contact hole CH1 is formed. Then, as shown in FIG. 16, the resist R formed on the gate electrode 41 is removed.
  • a SiN film is formed so as to cover the photosensitive resin film 40, the pixel electrode 43, and the like, and the SiN film is etched by photolithography using dry etching.
  • a passivation film 50 is formed.
  • the passivation film 50 is formed at 250 ° C. using a mixed gas of SiH 4 , NH 3 and N 2 by a plasma CVD apparatus, the concentration of hydrogen contained in the passivation film 50 is set to 1 ⁇ 10 22 cm ⁇ 3. This can be done.
  • a transparent conductive film is formed on the passivation film 50 using a sputtering method or the like.
  • the common electrode 51 is formed by annealing the transparent conductive film.
  • an alignment film (not shown) is formed so as to cover the passivation film 50 and the common electrode 51.
  • the TFT array substrate 210 of this embodiment has a structure in which the gate electrode 41 does not overlap with either the source electrode 22 or the drain electrode 23 in plan view. Therefore, it is possible to suppress the generation of parasitic capacitance between the gate electrode 41 and the source electrode 22 and the drain electrode 23. As a result, the TFT array substrate 210 with a short writing time can be obtained.
  • the writing time of the TFT array substrate 210 is shortened, the time required for raising the voltage of each pixel to a desired magnitude can be shortened. Therefore, the occurrence of signal delay can be suppressed.
  • the writing time of the TFT array substrate 210 is shortened, the time for driving the touch panel during the display driving suspension period can be lengthened. Since the influence of the noise of the display signal on the signal of the touch panel is suppressed, as a result, the accuracy of the touch panel can be improved.
  • the TFT array substrate 210 of this embodiment is a top gate type semiconductor substrate. However, since the semiconductor film 21 is provided so as to overlap the light shielding film 11 in plan view, the semiconductor film 21 is exposed to light and the semiconductor film It can suppress that 21 deteriorates.
  • the passivation film 50 having a hydrogen concentration of 1 ⁇ 10 22 cm ⁇ 3 or more is in contact with the semiconductor film 21, hydrogen easily enters the semiconductor film 21 from the passivation film 50. .
  • oxygen in the semiconductor film 21 is extracted, and the resistance of the oxide semiconductor becomes low. As a result, the electron transfer efficiency of the semiconductor 21 of the TFT array substrate 210 can be improved. .
  • the configuration in which the semiconductor film 21 and the passivation film 50 are in direct contact with each other has been described.
  • the channel region 21c of the semiconductor film 21 is formed in the TFT array substrate 210A of the liquid crystal display panel 200A.
  • the other region may be covered with the source electrode 22A or the drain electrode 23A. Even in this case, since the source electrode 22A or the drain electrode 23A and the gate electrode 41 are arranged so as not to overlap in plan view, it is possible to suppress the occurrence of parasitic capacitance between them.
  • the semiconductor film is described as being formed of an oxide semiconductor film, but the material of the semiconductor film is not limited to this.
  • the semiconductor film may be formed of polysilicon.
  • Each TFT array substrate of the above embodiment may further include an auxiliary capacitance wiring that forms an auxiliary capacitance used to hold a voltage applied to the liquid crystal.
  • the operation mode of the liquid crystal display panel 200 is the FFS mode, but the display device of the present invention is not particularly limited to this.
  • the liquid crystal display panel of the present invention may be, for example, a TN mode.
  • the display device of the present invention may be a display device other than the liquid crystal display device.
  • the present invention may be applied to a display device such as an organic EL display device.
  • the present invention can be used for semiconductor substrates and display devices.
  • CH1 ... contact hole 100 ... liquid crystal display device (display device), 210 ... TFT array substrate (semiconductor substrate), 10 ... transparent substrate (substrate), 11 ... light shielding film, 20 ... first insulating film, 21 ... semiconductor film 22 ... Source electrode, 23 ... Drain electrode, 30 ... Gate insulating film (second insulating film), 40 ... Passivation film (third insulating film), 41 ... Gate electrode

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Abstract

寄生容量の発生を抑制し、書き込み時間の短い半導体基板及び表示装置を提供する。半導体膜２１は、遮光膜１１と平面視で重なるように設けられている。第２の絶縁膜３０は、ソース電極２２及びドレイン電極２３に達するコンタクトホールＣＨ１を有する。ゲート電極４１は、第２の絶縁膜３０上に、半導体膜２１と平面視で重なると共にソース電極２２及びドレイン電極２３のいずれとも平面視で重ならないように設けられている。第３の絶縁膜５０は、ゲート電極４１を覆うと共にコンタクトホールＣＨ１を介してソース電極２２及びドレイン電極２３と接触するように第２の絶縁膜３０上に設けられている。

Description

半導体基板及び表示装置
　本発明は、半導体基板及び表示装置に関し、特に、タッチセンサーを備えた表示装置に用いる半導体基板に関する。
　近年、タッチセンサーを備える表示装置として、表示装置とタッチパネルとを個別に作製した後に表示装置にタッチパネルを取り付ける上板付型（アドオンタイプ）のものや、表示装置の上部ガラス基板の表面にタッチセンサーを直接形成する上板一体型（オンセルタイプ）のものがある。上板一体型の表示装置は上板付型のものに比べて厚さが薄くなっているが、さらに薄型化したタイプの表示装置として、タッチセンサー一体型の表示装置が開発されている。
　例えば、特許文献１には、互いに交差する複数のゲートライン及び複数のデータラインと、複数のゲートライン及び複数のデータラインの交差によって定義される領域内に形成される複数の画素電極と、複数の画素電極と重なるように形成される複数の共通電極と、を含むタッチセンサー一体型の表示装置が開示されている。この表示装置では、複数の共通電極が、ディスプレイの共通電極、タッチセンサーを構成するタッチ駆動電極及びタッチセンシング電極の機能を兼ねている。
特開２０１５－１０６４１１号公報
　特許文献１に記載の表示装置は、上述のように、ＴＦＴがボトムゲート構造となっている。そのため、平面視において、ゲート電極とソース電極は、平面視において必ず重なるように配置されることとなる。ゲート電極とソース電極とが平面視で重なることにより、ゲート電極とソース電極との間に寄生容量が発生し、信号書き込み時に信号の鈍りが生じる原因となり得る。
　本発明の目的は、寄生容量の発生を抑制し、書き込み時間の短い表示装置を提供することである。
　本発明の半導体基板は、基板と、基板上に設けられた遮光膜と、基板上に遮光膜を覆って設けられた第１の絶縁膜と、第１の絶縁膜上に、遮光膜と平面視で重なるように設けられた半導体膜と、第１の絶縁膜上に、一部が半導体膜を覆うように設けられたソース電極及びドレイン電極と、第１の絶縁膜上に、半導体膜、ソース電極及びドレイン電極を覆って設けられ、ソース電極及びドレイン電極に達するコンタクトホールを有する第２の絶縁膜と、第２の絶縁膜上に、半導体膜と平面視で重なると共にソース電極及びドレイン電極のいずれとも平面視で重ならないように設けられたゲート電極と、第２の絶縁膜上に、ゲート電極を覆うと共にコンタクトホールを介してソース電極及びドレイン電極と接触するように設けられた第３の絶縁膜と、を備える。
　本発明によれば、ソース電極及びドレイン電極と、ゲート電極とが平面視で重ならないように設けられているので、寄生容量の発生を抑制することにより、書き込み時間の短い半導体基板及び表示装置を得ることができる。
図１は、液晶表示装置の断面構成を模式的に表した説明図である。 図２は、実施形態１の液晶パネルの平面図である。 図３は、実施形態１のＴＦＴアレイ基板のレイアウトを詳しく示した液晶パネルの平面図である。 図４は、図３の液晶表示パネルのＡ－Ａ線における断面図である。 図５は、ＴＦＴアレイ基板の製造工程を示す基板の断面図である。 図６は、ＴＦＴアレイ基板の製造工程を示す基板の平面図である。 図７は、図６のＢ－Ｂ線における断面図である。 図８は、ＴＦＴアレイ基板の製造工程を示す基板の断面図である。 図９は、ＴＦＴアレイ基板の製造工程を示す基板の平面図である。 図１０は、図９のＣ－Ｃ線における断面図である。 図１１は、ＴＦＴアレイ基板の製造工程を示す基板の平面図である。 図１２は、図１１のＤ－Ｄ線における断面図である。 図１３は、ＴＦＴアレイ基板の製造工程を示す基板の断面図である。 図１４は、ＴＦＴアレイ基板の製造工程を示す基板の断面図である。 図１５は、ＴＦＴアレイ基板の製造工程を示す基板の断面図である。 図１６は、ＴＦＴアレイ基板の製造工程を示す基板の断面図である。 図１７は、ＴＦＴアレイ基板の製造工程を示す基板の平面図である。 図１８は、図１７のＥ－Ｅ線における断面図である。 図１９は、変形例のＴＦＴアレイ基板の断面図である。
　本発明の半導体基板は、基板と、基板上に設けられた遮光膜と、基板上に遮光膜を覆って設けられた第１の絶縁膜と、第１の絶縁膜上に、遮光膜と平面視で重なるように設けられた半導体膜と、第１の絶縁膜上に、一部が半導体膜を覆うように設けられたソース電極及びドレイン電極と、第１の絶縁膜上に、半導体膜、ソース電極及びドレイン電極を覆って設けられ、ソース電極及びドレイン電極に達するコンタクトホールを有する第２の絶縁膜と、第２の絶縁膜上に、半導体膜と平面視で重なると共にソース電極及びドレイン電極のいずれとも平面視で重ならないように設けられたゲート電極と、第２の絶縁膜上に、ゲート電極を覆うと共にコンタクトホールを介してソース電極及びドレイン電極と接触した第３の絶縁膜と、を備える（第１の構成）。
　第１の構成によれば、半導体基板は、第１の絶縁膜上に半導体膜並びにソース電極及びドレイン電極を備え、第１の絶縁膜上に第２の絶縁膜を備え、さらに、第２の絶縁膜上にゲート電極を備える。つまり、半導体基板は、トップゲート型の半導体を備える。そのため、ゲート電極がソース電極及びドレイン電極のいずれとも平面視で重ならない構造とすることができる。したがって、ゲート電極と、ソース電極及びドレイン電極との間に寄生容量が発生するのを抑制することができ、結果として、書き込み時間の短い半導体基板を得ることができる。なお、半導体膜は遮光膜と平面視で重なるように設けられているので、半導体膜に光があたって半導体膜が劣化するのを抑制することができる。
　本発明の半導体基板は、第１の構成において、第３絶縁膜は、コンタクトホールを介して、ソース電極及びドレイン電極に加え、さらに、半導体膜に接触しており、第３の絶縁膜の水素濃度は、１×１０２２ｃｍ－３以上である（第２の構成）。
　第２の構成によれば、水素濃度が１×１０２２ｃｍ－３以上の第３の絶縁膜が半導体膜に接触しているので、第３の絶縁膜から半導体膜に水素が進入しやすくなる。半導体膜に水素が進入すると、半導体膜中の酸素が抜き取られて、酸化物半導体が低抵抗になり、結果として、半導体基板の半導体の電子の移動効率を向上させることができる。
　本発明の半導体基板は、第１または第２の構成において、半導体膜が、酸化膜半導体で形成されている（第３の構成）。
　本発明の半導体基板は、第３の構成において、半導体膜が、Ｉｎ－Ｇａ－Ｚｎ－Ｏ系の酸化物半導体である（第４の構成）。
　本発明の半導体基板は、第３または第４の構成において、半導体膜が、結晶質の酸化物半導体である（第５の構成）。
　本発明の表示装置は、第１～第５の構成のいずれかの半導体基板を備える。
　以下、図面を参照しつつ、本発明の好適な実施の形態について詳細に説明する。以下の説明において参照する各図は、説明の便宜上、本発明の実施形態の構成部材のうち、本発明を説明するために必要な主要部材のみを簡略化して示したものである。従って、本発明は以下の各図に示されていない任意の構成部材を備え得る。また、以下の各図中の部材の寸法は、実際の寸法および各部材の寸法比率等を忠実に表したものではない。
　　＜実施形態１＞
　実施形態１では、表示装置の一例として、バックライト装置を備えた液晶表示装置について説明する。図１は、実施形態１の液晶表示装置１００の断面構成を模式的に示した説明図である。
　液晶表示装置１００は、表示面２００ａに画像を表示する液晶表示パネル２００、液晶表示パネル２００に光を供給するバックライト装置３００、液晶表示パネル２００やバックライト装置３００等を収容する筐体４００等を備える。
　液晶表示パネル２００は、ＴＦＴアレイ基板２１０と、対向基板２２０と、液晶層２３０と、シール材２４０とを備える。ＴＦＴアレイ基板２１０及び対向基板２２０は、互いに対向して配置されている。ＴＦＴアレイ基板２１０及び対向基板２２０は、枠状のシール材２４０で貼り合わされている。ＴＦＴアレイ基板２１０及び対向基板２２０間のシール材２４０で囲まれた空間には、液晶層２３０が封入されている。液晶表示パネル２００は、ＦＦＳ（Ｆｒｉｎｇｅ　Ｆｉｅｌｄ　Ｓｗｉｔｃｈｉｎｇ）モードで動作する。
　バックライト装置３００は、ＬＥＤ（Ｌｉｇｈｔ　Ｅｍｉｔｔｉｎｇ　Ｄｉｏｄｅ）を光源としつつ、液晶表示パネル２００に向かって光を照射する装置である。バックライト装置３００は、図１に示されるように、液晶表示パネル２００のＴＦＴアレイ基板２１０側に配され、ＴＦＴアレイ基板２１０に向かって光を照射する。液晶表示パネル２００は、バックライト装置３００から供給される光を利用して、表示面２００ａに画像が表示される。
　本実施形態の液晶表示装置１００は、例えば、携帯電話、スマートフォン、ラップトップ型パソコン、タブレット端末、携帯型情報端末、デジタルフォトフレーム、携帯型ゲーム機、電子インクペーパ等の各種電子機器に用いられる。
　　（液晶表示パネル）
　図２は、液晶表示パネル２００の平面図である。液晶表示パネル２００は、上述のように、ＴＦＴアレイ基板２１０，対向基板２２０及び液晶層２３０を含む。ＴＦＴアレイ基板２１０は、図２に示すように、対向基板２２０よりも一回り大きくなっている。ＴＦＴアレイ基板２１０のうち、対向基板２２０よりも大きくなった領域には、図２に示すように、ゲートドライバ２１１、ソースドライバ兼タッチパネル制御部２１２等が形成されている。ゲートドライバ２１１からは、図２に示すように、複数のゲート配線４２が互いに並行して延びるように設けられている。ソースドライバ兼タッチパネル制御部２１２からは、複数のソース配線２４及びタッチパネル配線１２が、互いに並行して延びるように設けられている。タッチパネル配線１２は、後述する共通電極５１と電気的に接続されている。
　図３は、液晶表示パネル２００のうちＴＦＴアレイ基板２１０のレイアウトを示した平面図である。図４は、図３のＡ－Ａ線における液晶表示パネル２００の断面図である。
　ＴＦＴアレイ基板２１０は、半導体基板である。ＴＦＴアレイ基板２１０の構成については後述する。ＴＦＴアレイ基板２１０の液晶層２３０とは反対側の表面には、偏光板（不図示）が設けられている。
　対向基板２２０は、図４に示すように、透明なガラス製の基板（透明基板）２２１、ブラックマトリクス２２２，Ｒ（赤色），Ｇ（緑色），Ｂ（青色）等の各着色部が所定配列で配置されたカラーフィルタ２２３、配向膜（不図示）等が配設された構成を有する。対向基板２２０の液晶層２３０とは反対側の表面には、偏光板（不図示）が設けられている。
　　（ＴＦＴアレイ基板）
　次に、ＴＦＴアレイ基板２１０について説明する。本実施形態のＴＦＴアレイ基板２１０は、トップゲート型のＴＦＴ２５０を備えている。
　ＴＦＴアレイ基板２１０は、図３に示すように、透明基板１０上に、スイッチング素子としてのＴＦＴ２５０やそれに接続する画素電極４３がマトリクス状に複数個配設された構成を有する。ＴＦＴアレイ基板２１０には、ＴＦＴ２５０等を区画するようにソース配線２４やゲート配線４２が配設されている。具体的には、ＴＦＴアレイ基板２１０は、図３及び図４に示すように、透明基板１０、遮光膜１１，第１絶縁膜２０，半導体膜２１，ソース電極２２，ドレイン電極２３，ソース配線２４，ゲート絶縁膜３０，感光性樹脂膜４０，ゲート電極４１，ゲート配線４２、画素電極４３，パッシベーション膜５０，共通電極５１、配向膜（不図示）等を備える。
　透明基板１０は、上述したように、ガラス製の板材からなる。なお、透明基板１０としては、ガラス製に限定されず、種々の基板を用いることができる。例えば、単結晶半導体基板、酸化物単結晶基板、金属基板、ガラス基板、石英基板、樹脂基板等の基板を用いることができる。例えば、単結晶半導体基板や金属基板等の導電性基板である場合には、その上に絶縁膜等を設けることによって用いることが好ましい。
　遮光膜１１は、透明基板１０上に形成されている。遮光膜１１は、他の構成と電気的に接続されない浮島状に形成されている。遮光膜１１は、半導体膜２１の下層に設けられ、半導体膜２１を遮光している。遮光膜１１は、例えば、金属膜で形成されている。
　第１絶縁膜２０は、透明基板１０上に、遮光膜１１を覆って設けられている。第１絶縁膜２０は、例えば、ＳｉＮｘ膜やＳｉＯ２膜で形成されている。
　半導体膜２１は、第１絶縁膜２０上に形成されている。半導体膜２１は、遮光膜１１が形成された領域に平面視で重なるように形成されている。半導体膜２１をより確実に遮光するためには、図２に示すように、半導体膜２１が形成された領域は、遮光膜１１が形成された領域よりも一回り小さくなっていることが好ましい。半導体膜２１は、酸化物半導体で形成されている。
　半導体膜２１に含まれる酸化物半導体は、アモルファス酸化物半導体であってもよいし、結晶質部分を有する結晶質酸化物半導体であってもよい。結晶質酸化物半導体としては、多結晶酸化物半導体、微結晶酸化物半導体、ｃ軸が層面に概ね垂直に配向した結晶質酸化物半導体などが挙げられる。
　半導体膜２１は、２層以上の積層構造を有していてもよい。半導体膜２１が積層構造を有する場合には、半導体膜２１は、非晶質酸化物半導体層と結晶質酸化物半導体層とを含んでいてもよい。あるいは、結晶構造の異なる複数の結晶質酸化物半導体層を含んでいてもよい。また、複数の非晶質酸化物半導体層を含んでいてもよい。半導体膜２１が上層と下層とを含む２層構造を有する場合、上層に含まれる酸化物半導体のエネルギーギャップは、下層に含まれる酸化物半導体のエネルギーギャップよりも大きいことが好ましい。ただし、これらの層のエネルギーギャップの差が比較的小さい場合には、下層の酸化物半導体のエネルギーギャップが上層の酸化物半導体のエネルギーギャップよりも大きくてもよい。
　非晶質酸化物半導体および上記の各結晶質酸化物半導体の材料、構造、成膜方法、積層構造を有する酸化物半導体層の構成などは、例えば特開２０１４－００７３９９号公報に記載されている。
　半導体膜２１は、例えば、Ｉｎ、ＧａおよびＺｎのうち少なくとも１種の金属元素を含んでもよい。本実施形態では、半導体膜２１は、例えば、Ｉｎ－Ｇａ－Ｚｎ－Ｏ系の半導体（例えば酸化インジウムガリウム亜鉛）を含む。ここで、Ｉｎ－Ｇａ－Ｚｎ－Ｏ系の半導体は、Ｉｎ（インジウム）、Ｇａ（ガリウム）、Ｚｎ（亜鉛）の三元系酸化物であって、Ｉｎ、ＧａおよびＺｎの割合（組成比）は特に限定されず、例えばＩｎ：Ｇａ：Ｚｎ＝２：２：１、Ｉｎ：Ｇａ：Ｚｎ＝１：１：１、Ｉｎ：Ｇａ：Ｚｎ＝１：１：２等を含む。このような半導体膜２１は、Ｉｎ－Ｇａ－Ｚｎ－Ｏ系の半導体を含む酸化物半導体膜から形成され得る。
　Ｉｎ－Ｇａ－Ｚｎ－Ｏ系の酸化物半導体は、アモルファスでもよいし、結晶質でもよい。結晶質Ｉｎ－Ｇａ－Ｚｎ－Ｏ系の半導体としては、ｃ軸が層面に概ね垂直に配向した結晶質Ｉｎ－Ｇａ－Ｚｎ－Ｏ系の半導体が好ましい。
　なお、結晶質Ｉｎ－Ｇａ－Ｚｎ－Ｏ系の酸化物半導体の結晶構造は、例えば、上述した特開２０１４－００７３９９号公報、特開２０１２－１３４４７５号公報、特開２０１４－２０９７２７号公報などに開示されている。Ｉｎ－Ｇａ－Ｚｎ－Ｏ系半導体層を有するＴＦＴは、高い移動度（ａ－ＳｉＴＦＴに比べ２０倍超）および低いリーク電流（ａ－ＳｉＴＦＴに比べ１００分の１未満）を有しているので、駆動ＴＦＴ（例えば、複数の画素を含む表示領域の周辺に、表示領域と同じ基板上に設けられる駆動回路に含まれるＴＦＴ）および画素ＴＦＴ（画素に設けられるＴＦＴ）として好適に用いられる。
　半導体膜２１は、Ｉｎ－Ｇａ－Ｚｎ－Ｏ系半導体の代わりに、他の酸化物半導体を含んでいてもよい。例えばＩｎ－Ｓｎ－Ｚｎ－Ｏ系半導体（例えばＩｎ２Ｏ３－ＳｎＯ２－ＺｎＯ；ＩｎＳｎＺｎＯ）を含んでもよい。Ｉｎ－Ｓｎ－Ｚｎ－Ｏ系半導体は、Ｉｎ（インジウム）、Ｓｎ（スズ）およびＺｎ（亜鉛）の三元系酸化物である。あるいは、半導体膜２１は、Ｉｎ－Ａｌ－Ｚｎ－Ｏ系半導体、Ｉｎ－Ａｌ－Ｓｎ－Ｚｎ－Ｏ系半導体、Ｚｎ－Ｏ系半導体、Ｉｎ－Ｚｎ－Ｏ系半導体、Ｚｎ－Ｔｉ－Ｏ系半導体、Ｃｄ－Ｇｅ－Ｏ系半導体、Ｃｄ－Ｐｂ－Ｏ系半導体、ＣｄＯ（酸化カドミウム）、Ｍｇ－Ｚｎ－Ｏ系半導体、Ｉｎ－Ｇａ－Ｓｎ－Ｏ系半導体、Ｉｎ－Ｇａ－Ｏ系半導体、Ｚｒ－Ｉｎ－Ｚｎ－Ｏ系半導体、Ｈｆ－Ｉｎ－Ｚｎ－Ｏ系半導体等の酸化物半導体を含んでいてもよい。
　ソース電極２２，ドレイン電極２３，及びソース配線２４は、第１絶縁膜２０上に形成されている。ソース電極２２及びドレイン電極２３の一部は、半導体膜２１を覆って形成されている。なお、半導体膜２１のうち、ソース電極２２とドレイン電極２３の間となる領域は、チャネル領域２１ｃを構成している。
　ゲート絶縁膜３０は、第１絶縁膜２０上に、半導体膜２１，ソース電極２２，ドレイン電極２３，ソース配線２４等を覆って形成されている。ゲート絶縁膜３０は、例えば、ＳｉＮｘ膜やＳｉＯ２膜で形成されている。
　感光性樹脂膜４０は、ゲート絶縁膜３０上に形成されている。感光性樹脂膜４０は、例えば、アクリル等の有機感光性樹脂で形成されている。
　ゲート絶縁膜３０及び感光性樹脂膜４０には、コンタクトホールＣＨ１，ＣＨ２が形成されている。コンタクトホールＣＨ１は、半導体膜２１が形成された領域に形成されている。なお、コンタクトホールＣＨ１においては、チャネル領域２１ｃと重ならない領域では、ゲート絶縁膜３０と感光性樹脂膜４０の両方が除去されて、コンタクトホールＣＨ１の表面に半導体膜２１が露出している。チャネル領域２１ｃと重なる領域では、感光性樹脂膜４０のみが除去され、ゲート絶縁膜３０は残った状態となっている。
　コンタクトホールＣＨ２は、ドレイン電極２３が形成された領域に形成されている。コンタクトホールＣＨ２の表面には、ドレイン電極２３が露出している。
　ゲート電極４１は、図４に示すように、ゲート絶縁膜３０上に形成されている。ゲート電極４１は、半導体膜２１のチャネル領域２１ｃと平面視で重なるように形成されている。ゲート配線４２は、図３に示すように、ソース配線２４と直交するように配置されている。ゲート電極４１及びゲート配線４２は、画素電極４３と共通の透明導電膜４１ａ、及びそれを覆う金属膜４１ｂで形成されている。
　画素電極４３は、ゲート絶縁膜３０及び感光性樹脂膜４０に形成されたコンタクトホールＣＨ２を介して、ドレイン電極２３と電気的に接続されている。画素電極４３は、透明導電膜で形成されている。
　パッシベーション膜５０は、感光性樹脂膜４０上に、ゲート電極４１，画素電極４３等を覆って形成されている。パッシベーション膜５０は、コンタクトホールＣＨ１において、半導体膜２１と接触している。パッシベーション膜５０は、例えば、ＳｉＮｘ膜で形成されている。パッシベーション膜５０の水素濃度は、１×１０２２ｃｍ－３以上であることが好ましい。水素濃度が１×１０２２ｃｍ－３以上のパッシベーション膜５０が半導体膜２１と接触しているので、半導体膜２１のうちチャネル領域２１ｃに隣接する領域から酸素が引き抜かれ、当該領域を低抵抗化することができる。
　共通電極５１は、パッシベーション膜５０を覆って形成されている。共通電極５１は、画素電極４３の上層に形成されている。共通電極５１は、図３に示すように、櫛状の電極となっている。共通電極５１は、例えば、ＩＴＯ等の透明導電膜で形成されている。
　なお、ＴＦＴアレイ基板２１０のパターン形状等の確認は、ＴＦＴアレイ基板２１０を分解した後、光学顕微鏡、ＳＴＥＭ（Ｓｃａｎｎｉｎｇ　Ｔｒａｎｓｍｉｓｓｉｏｎ　Ｅｌｅｃｔｒｏｎ　Ｍｉｃｒｏｓｃｏｐｅ：走査型透過電子顕微鏡）、ＳＥＭ（Ｓｃａｎｎｉｎｇ　Ｅｌｅｃｔｒｏｎ　Ｍｉｃｒｏｓｃｏｐｅ：走査型電子顕微鏡）等の顕微鏡を用いて観察することにより行うことができる。
　　（ＴＦＴアレイ基板の製造方法）
　次に、図５～図１８を用いて、ＴＦＴアレイ基板２１０の製造方法について説明する。
　まず、透明基板１０を準備する。そして、例えば、銅（Ｃｕ）膜及びチタン（Ｔｉ）膜を積層して、遮光膜を成膜する。具体的には、例えば、スパッタ法を用いて銅（Ｃｕ）膜及びチタン（Ｔｉ）膜を成膜した後、ウェットエッチングによるフォトリソグラフィを行うことにより、図５に示すように、島状の遮光膜１１を形成する。
　次に、たとえばＣＶＤ法を用いてＳｉＯ２膜及びＳｉＮ膜を成膜して、図５に示すように、透明基板１０及び遮光膜１１を覆う絶縁膜を成膜する。そして、この絶縁膜にドライエッチングによるフォトグラフィを行って、第１絶縁膜２０を形成する。なお、ＳｉＯ２膜及びＳｉＮ膜によって第１絶縁膜２０を形成する他、例えば、スピンコート法を用いて透明ＳＯＧ膜を成膜することによって、第１絶縁膜２０を形成してもよい。
　次に、例えばスパッタ法を用いて、第１絶縁膜２０上に酸化物半導体の膜を成膜する。そして、ウェットエッチングによるフォトリソグラフィを用いて酸化物半導体の膜をパターンニングして、図５に示すように、島状の半導体膜２１を形成する。このとき半導体膜２１が形成される領域は、平面視で遮光膜１１と重なる領域である。
　次に、図６及び図７に示すように、例えば、銅（Ｃｕ）膜及びチタン（Ｔｉ）膜を積層して、導電膜を成膜する。具体的には、例えば、スパッタ法を用いて銅（Ｃｕ）膜及びチタン（Ｔｉ）膜を成膜した後、ウェットエッチングまたはドライエッチングによるフォトリソグラフィにより金属膜をパターンニングして、ソース電極２２、ドレイン電極２３、ソース配線２４等を構成する導電膜を形成する。
　なお、ソース電極２２等を構成する導電膜は、上記で例示した他の金属膜の構成であってもよく、単層構造であってもよい。ただし、好ましくは、この導電膜は２層構造である。ソース電極２２等を構成する導電膜が２層構造の場合、下層を構成する材料としては、低抵抗の金属（例えば、アルミニウム（Ａｌ）や銅（Ｃｕ）等）が好適である。上層を構成する材料としては、後工程のドライエッチングの工程において、面内分布のためのオーバーエッチ時にエッチングされにくい金属（例えば、チタン（Ｔｉ）、モリブデン（Ｍｏ）膜、窒化チタン（ＴｉＮ）、窒化モリブデン（ＭｏＮ）等）が好適である。
　次に、図７に示すように、ソース電極２２等の導電膜を覆うように、第１絶縁膜２０上に、例えばＰＥＣＶＤ法を用いてＳｉＮｘ膜及びＳｉＯ２膜を順に成膜することにより、絶縁膜３０ｐを形成する。ここで形成する絶縁膜３０ｐは、ゲート絶縁膜３０を構成する膜である。
　次に、図８に示すように、ＳｉＯ２膜上に、アクリル樹脂等の感光性樹脂膜４０を成膜する。この感光性樹脂膜４０にフォトリソグラフィによってパターンニングを行って、図８及び図９に示すように、半導体膜２１と重なるコンタクトホールＣＨ１ａ、及びドレイン電極２３と重なるコンタクトホールＣＨ２ａを形成する。そして、感光性樹脂膜４０に対してアニール処理を行う。
　続いて、図９及び図１０に示すように、絶縁膜３０ｐのフォトリソグラフィによってパターンニングを行って、感光性樹脂膜４０の表面からドレイン電極２３に達するコンタクトホールＣＨ２を形成する。
　次に、図１１及び図１２に示すように、感光性樹脂膜４０上に、例えばスパッタ法を用いて透明導電膜を成膜し、さらに、導電膜を積層する。そして、ウェットエッチングを用いたフォトリソグラフィによってパターンニングを行い、透明導電膜４１ａ及び導電膜４１ｂからなるゲート電極４１、透明導電膜及び導電膜からなるゲート配線４２（図１１を参照。）、並びに透明導電膜からなる画素電極４３を形成する。画素電極４３の上層には、画素電極４３と同一のパターンの導電膜４３ｂが残った状態となっている。
　続いて、図１３に示すように、ゲート電極４１及びゲート配線４２と重なる領域に、レジストＲを形成する。そして、図１４に示すように、ウェットエッチングによって、画素電極４３の上の導電膜４３ｂを除去する。
　次いで、図１５に示すように、感光性樹脂膜４０に形成されたコンタクトホールＣＨ１ａと重なる領域のうち、ゲート電極４１が存在しない領域のゲート絶縁膜３０を、ドライエッチングにより除去する。これにより、コンタクトホールＣＨ１が形成される。そして、図１６に示すように、ゲート電極４１の上に形成されたレジストＲを除去する。
　次に、図１７及び図１８に示すように、感光性樹脂膜４０、画素電極４３等を覆うようにＳｉＮ膜を成膜し、ドライエッチングを用いたフォトリソグラフィによってＳｉＮ膜をエッチングすることによって、パッシベーション膜５０を形成する。このとき、プラズマＣＶＤ装置により、ＳｉＨ４、ＮＨ３及びＮ２の混合ガスを用いて２５０℃でパッシベーション膜５０を成膜するので、パッシベーション膜５０に含まれる水素濃度を１×１０２２ｃｍ－３以上とすることができる。
　続いて、パッシベーション膜５０上に、スパッタ法等を用いて透明導電膜を形成する。透明導電膜に対してウェットエッチングを用いたフォトリソグラフィによってパターンニングを行った後、透明導電膜にアニール処理をすることによって、共通電極５１を形成する。
　最後に、パッシベーション膜５０及び共通電極５１を覆うように、図示しない配向膜を形成する。以上の工程を経ることにより、ＴＦＴアレイ基板２１０が作製される。
　　（実施形態１の効果）
　本実施形態のＴＦＴアレイ基板２１０は、ゲート電極４１がソース電極２２及びドレイン電極２３のいずれとも平面視で重ならない構造を有する。そのため、ゲート電極４１と、ソース電極２２及びドレイン電極２３との間に寄生容量が発生するのを抑制することができ、結果として、書き込み時間の短いＴＦＴアレイ基板２１０とすることができる。
　ＴＦＴアレイ基板２１０の書き込み時間が短くなることにより、各画素の電圧を所望の大きさにまで上げるのに要する時間を短縮することができる。そのため、信号の遅延が発生するのを抑制することができる。
　また、ＴＦＴアレイ基板２１０の書き込み時間が短くなることにより、表示の駆動休止期間中のタッチパネル駆動のための時間を長くすることができる。タッチパネルの信号に表示信号のノイズが影響を及ぼすのが抑制されるので、結果として、タッチパネルの精度を向上させることができる。
　本実施形態のＴＦＴアレイ基板２１０は、トップゲート型の半導体基板であるが、半導体膜２１は遮光膜１１と平面視で重なるように設けられているので、半導体膜２１に光があたって半導体膜２１が劣化するのを抑制することができる。
　本実施形態のＴＦＴアレイ基板２１０では、水素濃度が１×１０２２ｃｍ－３以上のパッシベーション膜５０が半導体膜２１に接触しているので、パッシベーション膜５０から半導体膜２１に水素が進入しやすくなる。半導体膜２１に水素が進入すると、半導体膜２１中の酸素が抜き取られて、酸化物半導体が低抵抗になり、結果として、ＴＦＴアレイ基板２１０の半導体２１の電子の移動効率を向上させることができる。
　　＜その他の実施形態＞
　本発明は上記記述及び図面によって説明した実施形態に限定されるものではなく、例えば次のような実施形態も本発明の技術的範囲に含まれる。
　実施形態１では、半導体膜２１とパッシベーション膜５０とが直接接触している構成について説明したが、図１９に示すように、液晶表示パネル２００ＡのＴＦＴアレイ基板２１０Ａにおいて、半導体膜２１のチャネル領域２１ｃ以外の領域が、ソース電極２２Ａまたはドレイン電極２３Ａで覆われていてもよい。この場合でも、ソース電極２２Ａまたはドレイン電極２３Ａと、ゲート電極４１とが、平面視で重ならないように配置されているので、両者間の寄生容量が発生するのを抑制することができる。
　上記の実施形態では、半導体膜が酸化物半導体膜で形成されていると説明したが、半導体膜の材料はこれに限定されない。例えば、半導体膜がポリシリコンで形成されていてもよい。
　上記の実施形態の各ＴＦＴアレイ基板は、液晶に印加した電圧を保持するために用いられる補助容量を形成する補助容量配線を更に備えてもよい。
　上記の実施形態では、液晶表示パネル２００の動作モードがＦＦＳモードであると説明したが、本発明の表示装置は特にこれに限定されない。本発明の液晶表示パネルは、例えば、ＴＮモード等であってもよい。
　上記の実施形態では、表示装置が液晶表示装置の場合について説明したが、本発明の表示装置は、液晶表示装置以外の表示装置であってもよい。例えば、本発明を、有機ＥＬ表示装置等の表示装置に適用してもよい。
　以上、上述した実施の形態は本発明を実施するための例示に過ぎない。よって、本発明は上述した実施の形態に限定されることなく、その趣旨を逸脱しない範囲内で上述した実施の形態を適宜変形して実施することが可能である。
　本発明は、半導体基板及び表示装置について利用可能である。
ＣＨ１…コンタクトホール、１００…液晶表示装置（表示装置）、２１０…ＴＦＴアレイ基板（半導体基板）、１０…透明基板（基板）、１１…遮光膜、２０…第１の絶縁膜、２１…半導体膜、２２…ソース電極、２３…ドレイン電極、３０…ゲート絶縁膜（第２の絶縁膜）、４０…パッシベーション膜（第３の絶縁膜）、４１…ゲート電極

Claims (6)

  1. 　基板と、
    　前記基板上に設けられた遮光膜と、
    　前記基板上に前記遮光膜を覆って設けられた第１の絶縁膜と、
    　前記第１の絶縁膜上に、前記遮光膜と平面視で重なるように設けられた半導体膜と、
    　前記第１の絶縁膜上に、一部が前記半導体膜を覆うように設けられたソース電極及びドレイン電極と、
    　前記第１の絶縁膜上に、前記半導体膜、前記ソース電極及び前記ドレイン電極を覆って設けられ、前記ソース電極及び前記ドレイン電極に達するコンタクトホールを有する第２の絶縁膜と、
    　前記第２の絶縁膜上に、前記半導体膜と平面視で重なると共に前記ソース電極及び前記ドレイン電極のいずれとも平面視で重ならないように設けられたゲート電極と、
    　前記第２の絶縁膜上に、前記ゲート電極を覆うと共に前記コンタクトホールを介して前記ソース電極及び前記ドレイン電極と接触するように設けられた第３の絶縁膜と、
    を備えた、半導体基板。
  2. 　請求項１に記載の半導体基板において、
    　前記第３絶縁膜は、前記コンタクトホールを介して、前記ソース電極及び前記ドレイン電極に加え、さらに、前記半導体膜に接触しており、
    　前記第３の絶縁膜の水素濃度は、１×１０２２ｃｍ－３以上である、半導体基板。
  3. 　請求項１または請求項２に記載の半導体基板において、
    　前記半導体膜が、酸化膜半導体で形成されている、半導体基板。
  4. 　請求項３に記載の半導体基板において、
    　前記半導体膜は、Ｉｎ－Ｇａ－Ｚｎ－Ｏ系の酸化物半導体である、半導体基板。
  5. 　請求項３または請求項４に記載の半導体基板において、
    　前記半導体膜は、結晶質の酸化物半導体である、半導体基板。
  6. 　請求項１～請求項５のいずれか一項に記載の半導体基板を備えた表示装置。
PCT/JP2016/085117 2015-11-30 2016-11-28 半導体基板及び表示装置 WO2017094644A1 (ja)

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