WO2017071378A1 - 半导体器件耐压结构 - Google Patents

半导体器件耐压结构 Download PDF

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Publication number
WO2017071378A1
WO2017071378A1 PCT/CN2016/095903 CN2016095903W WO2017071378A1 WO 2017071378 A1 WO2017071378 A1 WO 2017071378A1 CN 2016095903 W CN2016095903 W CN 2016095903W WO 2017071378 A1 WO2017071378 A1 WO 2017071378A1
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semi
conductor
field plate
semiconductor device
insulating
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PCT/CN2016/095903
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English (en)
French (fr)
Inventor
顾炎
宋华
张森
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无锡华润上华半导体有限公司
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Publication of WO2017071378A1 publication Critical patent/WO2017071378A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/405—Resistive arrangements, e.g. resistive or semi-insulating field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes

Definitions

  • the present invention relates to the field of semiconductor device technology, and in particular to a semiconductor device withstand voltage structure.
  • a part of the electrode needs to be connected to the peripheral high voltage bus through a high voltage interconnection line.
  • the high voltage interconnection line includes an active region under the area covered by the surface of the semiconductor device, when the high voltage interconnection line is connected to the high voltage bus line, the high voltage is transmitted to the active area through the contact layer through the dielectric layer and the field oxide layer, thereby The breakdown of the active region eventually causes the entire semiconductor device to fail. Therefore, for a semiconductor device that needs to operate at a higher voltage, a region dedicated to arranging the above-described high voltage interconnection line is provided in the layout.
  • the underside of the high-voltage interconnect line (hereinafter referred to as the semiconductor device withstand voltage structure) cannot contain the active region, but only the drift region.
  • the part of the drift region can induce a corresponding high voltage through the field oxide layer and the dielectric layer. If the breakdown voltage of the drift region is greater than the induced high voltage, the high voltage can be depleted through the drift region, thereby making the semiconductor device No longer affected by high pressure. Therefore, the key to the high voltage interconnection is to increase the breakdown voltage of the withstand voltage structure of the semiconductor device, and to make the breakdown voltage of the semiconductor device withstand voltage structure greater than the withstand voltage of the semiconductor device.
  • a voltage resistance structure of a semiconductor device comprising: a metal layer comprising a high voltage interconnection region for arranging a high voltage interconnection line; a dielectric layer, a field oxide layer, a drift region sequentially under the high voltage interconnection region; and a plurality of semi-insulating resistance fields a plate, each of the semi-insulating resistive field plates is adjacent to the field oxide layer; a plurality of conductor field plates, each of the conductor field plates being located above the semi-insulating resistive field plate, and the conductor field plate is at In the dielectric layer; the conductor field plate and the semi-insulating resistance field plate constitute a plurality of capacitors, and each two adjacent capacitors share one of the conductor field plates or the semi-insulating resistance field plates, so that each A capacitor can transfer energy with another capacitor.
  • a voltage resistance structure of a semiconductor device comprising: a metal layer comprising a high voltage interconnection region for arranging a high voltage interconnection line; a dielectric layer, a field oxide layer, a drift region sequentially under the high voltage interconnection region; and a plurality of semi-insulating resistance fields a plate, each of the semi-insulating resistive field plates adjacent to the field oxide layer; and a plurality of conductor field plates in the dielectric layer; the conductor field plate being located above the semi-insulating resistive field plate;
  • the semi-insulating resistive field plate and the conductor field plate are both located between two electrodes of the semiconductor device, and at least one of the two electrodes is used to connect the high voltage interconnecting wire; the closest is used to connect the high voltage interconnecting wire
  • the conductor field plate of the electrode is connected to the electrode conductor; in the two of the conductor field plates closest to each of the semi-insulating resistance field plates, the conductor adjacent to the electrode for connecting the high voltage interconnection line
  • a voltage resistance structure of a semiconductor device comprising: a metal layer comprising a high voltage interconnection region for arranging a high voltage interconnection line; a dielectric layer, a field oxide layer, a drift region sequentially under the high voltage interconnection region; and a plurality of semi-insulating resistance fields a plate, each of the semi-insulating resistive field plates adjacent to the field oxide layer; and a plurality of conductor field plates in the dielectric layer and above the semi-insulating resistive field plate; the plurality of conductor fields The plates are arranged in two upper and lower layers; each of the conductor field plates and another conductor field plate arranged in different layers form a capacitor; each of the semi-insulated resistance field plates and the conductor field plate are located in two of the semiconductor devices Between the electrodes, and at least one of the two electrodes is used to connect the high voltage interconnecting wires; in the two of the conductor field plates closest to each of the semi-insulating resistive field plates, close to The conductor field plate of the electrode connected to the high voltage inter
  • the conductor field plate is located above the semi-insulating resistance field plate, and the conductor field plate is in the dielectric layer, and the conductor field plate and the semi-insulating resistance field plate constitute a plurality of capacitors, and each two adjacent capacitors One conductor field plate or semi-insulated resistance field plate is shared so that each capacitor can transfer energy to another capacitor.
  • the conductor field plate senses high voltage and is transmitted through the capacitive effect, since each capacitor can transfer energy to another capacitor, the final high voltage is dispersed in each capacitor. Due to the energy consumption in the transfer process, the voltage dispersed in each capacitor is weakened, so that a weak electric field is formed under the semi-insulating resistance field plate.
  • the semi-insulating resistance field plate is adjacent to the field oxide layer, that is, the semi-insulating resistance field plate has a modulation effect on the electric field on the surface of the drift region, so that a weak electric field is formed under the semi-insulating resistance field plate, Due to the modulation effect of the semi-insulating resistance field plate, the electric field on the surface of the drift region is also weak, thereby reducing the high voltage on the surface of the drift region as a whole, and improving the breakdown voltage of the semiconductor device, so that the semiconductor device can Work at higher voltages.
  • Figure 1 is a cross-sectional view showing a pressure-resistant structure of a semiconductor device of an embodiment.
  • FIG. 2 is a cross-sectional view showing a withstand voltage structure of a semiconductor device according to another embodiment.
  • FIG. 3 is a diagram showing an electric field distribution formed by a withstand voltage structure of a conventional semiconductor device.
  • FIG. 4 is a view showing an electric field distribution formed by a withstand voltage structure of the semiconductor device of the embodiment shown in FIG. 2.
  • Fig. 5 is a breakdown voltage test curve of a conventional semiconductor device withstand voltage structure.
  • Fig. 6 is a breakdown voltage test curve of the withstand voltage structure of the semiconductor device of the embodiment shown in Fig. 2.
  • Fig. 7 is a cross-sectional view showing a pressure-resistant structure of a semiconductor device of another embodiment.
  • the withstand voltage structure of the semiconductor device is provided in the semiconductor device for improving the breakdown voltage of the semiconductor device, and the lateral diffusion metal oxide semiconductor is taken as an example for description.
  • the semiconductor device withstand voltage structure provided by an embodiment includes a P-type substrate 101 , a buried oxide layer 109 , a drift region 102 , a P well 103 , an N well 104 , a plurality of semi-insulating resistance field plates 105 , and more The conductor field plate 106, the metal layer 107, the dielectric layer 108a, and the field oxide layer 108b.
  • the metal layer 107 includes a high voltage interconnection region 107a for arranging the high voltage interconnection lines, and the dielectric layer 108a, the field oxide layer 108b, and the drift region 102 are sequentially under the high voltage interconnection region 107a.
  • the buried oxide layer 109 serves as an isolation.
  • the P-type substrate 101 can be heavily doped, and since the P-type substrate 101 is separated from the remaining portion by the buried oxide layer 109, the influence on the breakdown characteristics of the semiconductor device is small.
  • the drift region 102 is an N-type top layer silicon, and the breakdown voltage of the entire semiconductor device device can be increased by adjusting the concentration.
  • P well 103 is the source substrate.
  • the N well 104 is a buffer layer for the drain.
  • the dielectric layer 108a and the field oxide layer 108b are both insulating materials.
  • the drain is used to connect the high voltage interconnection line, and the dielectric layer 108a is thickened to increase the breakdown voltage. It should be noted that, since a plurality of semi-insulating resistance field plates 105 and a plurality of conductor field plates 106 are disposed in the dielectric layer 108a in this embodiment, the dielectric layer 108a itself is thickened to accommodate multiple The semi-insulating resistive field plate 105 and the plurality of conductor field plates 106. The thickness of the field oxide layer 108b is lower than the thickness of the dielectric layer 108a.
  • the field oxide layer 108 is in contact with the surface of the drift region 102, and the surface of the drift region 102 refers to a surface region of the drift region 102 between the P well 103 and the N well 104.
  • the breakdown structure of the semiconductor device provided by this embodiment is based on the thickened dielectric layer 108a, and a multilayer field plate is introduced to further increase the breakdown voltage of the semiconductor device.
  • the specific principle is as follows.
  • each of the semi-insulating resistive field plates 105 is adjacent to the field oxide layer 108b. Since each of the semi-insulating resistive field plates 105 is adjacent to the field oxide layer 108b, the semi-insulating resistive field plate 105 modulates the electric field on the surface of the drift region 102.
  • each conductor field plate 106 is located within the dielectric layer 108a and is located within the dielectric layer 108a adjacent to the metal layer 107. At the same time, each conductor field plate 106 is over each of the semi-insulating resistive field plates 105.
  • the conductor field plate 106 and the semi-insulating resistance field plate 105 constitute a plurality of capacitors, and each two adjacent capacitors share a conductor field plate 106 or a semi-insulating resistance field plate 105 so that each capacitor can transmit energy to another capacitor. .
  • two adjacent capacitors share one conductor field plate 106, and the left and right portions of the common conductor field plate 106 respectively form two capacitors with the adjacent two semi-insulating resistance field plates 105 located below. Therefore, energy can be transferred between the two adjacent capacitors through the common conductor field plate 106 and the capacitive effect.
  • each two adjacent capacitors share a semi-insulating resistance field plate 105, and the left and right two-part structures of the shared semi-insulating resistance field plate 105 respectively form two capacitors with the adjacent two conductor field plates 106 located above. . Therefore, energy can be transferred between the two adjacent capacitors through the shared semi-insulating resistance field plate 105 and the capacitive effect.
  • the conductor field plate 106 senses a high voltage and transmits it through a capacitive effect, since each capacitor can transfer energy with another capacitor, the final high voltage is dispersed in each capacitor. in. However, due to the energy consumption in the transfer process, the voltage dispersed in each capacitor is weakened, so that a weak electric field is formed under the semi-insulating resistance field plate 105.
  • the semi-insulating resistance field plate 105 is adjacent to the field oxide layer 108b, that is, the semi-insulating resistance field plate 105 has a modulation effect on the electric field on the surface of the drift region 102, a weaker formation is formed under the semi-insulating resistance field plate 105.
  • the electric field on the surface of the drift region 102 is also weak, thereby reducing the high voltage on the surface of the drift region 102 as a whole, and improving the impact of the semiconductor device.
  • the voltage is applied so that the semiconductor device can operate at a higher voltage.
  • each of the semi-insulating resistive field plates 105 and the conductor field plates 106 are located between the two electrodes of the semiconductor device, and at least one of the two electrodes is used to connect the high voltage interconnecting wires.
  • the conductor field plate 106 adjacent to the electrodes for connecting the high voltage interconnection lines and the semi-insulating resistance field plate 105 are connected by conductors, away from A conductor field plate 106 for connecting the electrodes of the high voltage interconnection line and the semi-insulating resistance field plate 105 constitute a capacitor.
  • the electrode on the right side is a drain, and the drain is used to connect the high voltage interconnection line.
  • each of the semi-insulating resistance field plates 105 is vertically connected to the conductor field plate 106 located at the upper right side thereof, and is located at the same
  • the conductor field plate 106 at the upper left constitutes a capacitor, that is, an overlapping capacitance is formed.
  • any semi-insulating resistor field plate 105 disposed in this embodiment is perpendicularly connected to the conductor field plate 106 located at the upper right thereof, so that any one of the semi-insulating resistance field plates 105 There is only one type of capacitor on the top, which enhances the stability of the operation of each capacitor.
  • FIG. 2 is a cross-sectional view showing a withstand voltage structure of a semiconductor device of another embodiment.
  • the voltage-resistant structure of the semiconductor device includes: a P-type substrate 201, a buried oxide layer 209, a drift region 202, a P-well 203, an N-well 204, a plurality of semi-insulating resistance field plates 205, a plurality of conductor field plates 206, and a metal layer 207.
  • the dielectric layer 208a and the field oxide layer 208b is the dielectric layer 208a and the field oxide layer 208b.
  • the buried oxide layer 209 acts as an isolation.
  • the P-type substrate 201 can be heavily doped, and since the P-type substrate 201 is separated from the remaining portion by the buried oxide layer 209, the breakdown characteristics of the semiconductor device are less affected.
  • the drift region 202 is an N-type top layer silicon which can be adjusted to increase the breakdown voltage of the entire semiconductor device device.
  • P well 203 is the source substrate.
  • N-well 204 is the buffer layer of the drain.
  • the dielectric layer 208a and the field oxide layer 208b are both insulating materials.
  • the drain is used to connect the high voltage interconnection line, and the dielectric layer 208a is thickened to increase the breakdown voltage.
  • the dielectric layer 208a itself is thickened to accommodate the above-mentioned The semi-insulating resistive field plate 205 and the conductor field plate 206.
  • the thickness of the field oxide layer 208b is lower than the thickness of the dielectric layer 208a.
  • the metal layer 207 includes a high voltage interconnect region 207a for arranging high voltage interconnect lines, and the dielectric layer 208a, the field oxide layer 208b, and the drift region 202 are sequentially under the high voltage interconnect region 207a.
  • the field oxide layer 208 is in contact with the surface of the drift region 202, and the surface of the drift region 202 refers to a surface region between the P well 203 and the N well 204.
  • the breakdown structure of the semiconductor device provided by this embodiment is based on the thickened dielectric layer 208a, and a multilayer field plate is introduced to further increase the breakdown voltage of the semiconductor device.
  • Each of the semi-insulating resistive field plates 205 is adjacent to the field oxide layer 208b. Since each of the semi-insulating resistive field plates 205 is adjacent to the field oxide layer 208b, the semi-insulating resistive field plate 205 modulates the electric field on the surface of the drift region 202.
  • each of the conductor field plates 206 is located in the dielectric layer 208a adjacent to the metal layer 207 and is located above each of the semi-insulating resistance field plates 205.
  • each of the semi-insulating resistive field plates 205 and the conductor field plates 206 are located between the two electrodes of the semiconductor device, and at least one of the two electrodes is used to connect the high voltage interconnecting wires.
  • the conductor field plate 206 closest to the electrode for connecting the high voltage interconnection line is connected to the electrode conductor, as shown in Fig. 2, that is, the rightmost conductor field plate 206 is connected to the drain.
  • each of the semi-insulating resistive field plates 205 is vertically connected to the conductor field plate 206 at the upper right thereof, and forms a capacitor with the conductor field plate 206 at the upper left thereof to form an overlapping capacitance.
  • any semi-insulating resistance field plate 205 disposed in this embodiment is perpendicularly connected to the conductor field plate 206 located at the upper right side thereof, so that any one of the semi-insulating resistance fields There is only one type of capacitor on the board 205, which enhances the stability of the operation of each capacitor.
  • a portion of the voltage is again transferred to the other conductor field plate 206 at the upper left by a capacitive effect, and so on, eventually the high voltage will be dispersed in each of the conductor field plates 206 and the semi-insulating resistance field plate 205, and due to energy consumption, A weak electric field is finally formed under the semi-insulating resistance field plate 205, and the electric field on the surface of the drift region 202 is also weakly distributed under the action of the electric field modulation of the surface of the drift region 202 by the semi-insulating resistance field plate 205, effectively weakening The effect of high voltage on the internal drift region 202 of the semiconductor device.
  • the conductor field plate 206 connected to the drain first forms a potential field plate through the drain, and causes the semi-insulating resistance field plate 205 connected thereto to have the same potential. Then, the conductor field plate 206 at the upper left of the semi-insulating resistance field plate 205 also has a certain potential due to the capacitive effect. By analogy, eventually all of the conductor field plate 206 and the semi-insulating resistance field plate 205 will become potential field plates.
  • the potential of each of the semi-insulating resistance field plates 205 is gradually decreased, and under the modulation of the semi-insulating resistance field plate 205, The electric field corresponding to the surface of the drift region 202 near any one of the semi-insulating resistance field plates 205 is evenly distributed, thereby reducing the possibility of breakdown due to the occurrence of an electric field dense region.
  • the size of the semi-insulating resistance field plates 205 and the spacing between them, the size of each conductor field plate 206, and the spacing between the two can be adjusted.
  • the size of the stacked capacitors allows the entire electric field distribution to be optimal.
  • each of the semi-insulating resistive field plates 205 has the same size and is sequentially arranged at the same interval.
  • the semi-insulating resistive field plate 205 induces a relatively evenly distributed electric field. Then, under the modulation of the semi-insulating resistance field plate 205, the phenomenon that breakdown occurs on the surface of the drift region 202 due to the occurrence of an electric field dense region can be avoided.
  • the voltage-resistant structure of the semiconductor device sequentially transfers a voltage between the semi-insulating resistance field plate 205 and the conductor field plate 206, so that the surface of the drift region 202 forms a gradually decreasing potential distribution; Since the semi-insulating resistance field plate 205 can uniformly distribute the electric field, the electric field on the surface of the drift region 202 is finally uniformly distributed on the basis of gradually decreasing, which not only weakens the influence of the high voltage on the drift region 202, but also avoids the surface of the drift region 202. The breakdown occurs due to the occurrence of an electric field dense region, thereby further increasing the breakdown voltage of the semiconductor device.
  • the distance between the semi-insulating resistance field plates 205 the more uniform the electric field generated by all the semi-insulating resistance field plates 205.
  • the distance between any two adjacent semi-insulating resistive field plates 205 is between 0.3 and 0.8 microns.
  • all of the semi-insulating resistance field plates 205 constitute an area equal to the area of the surface area of the drift region.
  • the region of the surface of the drift region 202 is the surface region of the drift region 202 between the P well 203 and the N well 204.
  • This has the advantage that the larger the region of the drift region 202 that is subjected to high voltage, the greater the high voltage value that the semiconductor device can withstand, thereby further increasing the breakdown voltage of the entire semiconductor device.
  • all of the areas of the semi-insulating resistance field plate 205 are not covered on the active area, so that the active area is not affected by the high voltage.
  • the entire area composed of all the semi-insulating resistance field plates 205 may be smaller than the area of the surface of the drift region 202 as long as the semiconductor device is not broken down.
  • the conductor field plate 206 is a metal field plate
  • the semi-insulated resistance field plate 205 is a polysilicon field plate.
  • the conductor field plate 206 can also be made from other types of conductors, such as an electrically conductive alloy.
  • the semi-insulating resistive field plate 205 can also be made of other semi-insulating materials as long as a uniform electric field can be ensured.
  • the two electrodes include a first electrode and a second electrode, and the first electrode is used to connect the high voltage interconnection line, and the second electrode is used to ground.
  • the first electrode is located on the right side and is the drain, and the corresponding active area is the N well 204.
  • the second electrode is used for grounding and is located on the left side, and its corresponding active region is the P well 203.
  • the conductor field plate 206 closest to the second electrode is electrically connected to the second electrode and the semi-insulating resistance field plate 205 closest to the second electrode. Meanwhile, an end of the semi-insulating resistive field plate 205 closest to the second electrode adjacent to the second electrode is located above the active region corresponding to the second electrode.
  • the conductive field plates 206 located at the leftmost side are electrically connected to the second electrode and the semi-insulating resistance field plate 205 located at the leftmost side. Since the second electrode is grounded, the potentials of the conductive field plate 206 on the leftmost side and the semi-insulating resistance field plate 205 on the leftmost side are both at zero potential, so that the influence of the boundary peak electric field on the performance of the semiconductor device can be attenuated.
  • the semiconductor device withstand voltage structure provided by the embodiment is applicable not only to a laterally diffused metal oxide semiconductor but also to other types of semiconductor devices, such as a semiconductor device using bulk silicon or silicon carbide as a substrate material. Or a fast recovery diode, an insulated gate bipolar transistor, or the like, as long as the conductor field plate 206 and the semi-insulating resistance field plate 205 are provided in the lower insulating layer corresponding to the high voltage interconnection line in each semiconductor device in the same principle as the present embodiment. The breakdown voltage of each semiconductor device is increased.
  • FIG. 3 shows an electric field distribution diagram formed by a withstand voltage structure of a conventional semiconductor device
  • FIG. 4 shows an electric field distribution diagram formed by a withstand voltage structure of a semiconductor device of an embodiment.
  • the conventional semiconductor device withstand voltage structure, electric field lines are concentrated on the left side, and thus breakdown phenomenon is likely to occur in this region.
  • the line density of the electric field from the drain to the source gradually becomes smaller, that is, the potential gradually becomes smaller, and the electric field line distribution tends to have a uniform transition as a whole. The change is smooth and there is no case where the electric field lines are concentrated. Therefore, in the case of electric field line distribution, the withstand voltage structure of the semiconductor device provided by the present invention is greatly improved compared with the conventional method.
  • Fig. 5 is a breakdown voltage test curve of a conventional semiconductor device withstand voltage structure.
  • Fig. 6 is a breakdown voltage test curve of the withstand voltage structure of the semiconductor device of the embodiment shown in Fig. 2.
  • the breakdown voltage of the conventional semiconductor device withstand voltage structure is about 170V
  • the breakdown voltage of the semiconductor device withstand voltage structure of the embodiment shown in FIG. 2 is about 650V
  • the inventors also measure The breakdown voltage of the semiconductor device using the withstand voltage structure of the semiconductor device provided in the embodiment shown in Fig. 2 was 580V.
  • the present embodiment uses the conductor field plate 206 and the semi-insulating resistance field plate 205 to make the breakdown voltage of the semiconductor device with a high breakdown voltage while satisfying the breakdown voltage of the semiconductor device with a breakdown voltage greater than that of the semiconductor.
  • the breakdown voltage of the device Therefore, in terms of withstand voltage, the withstand voltage structure of the conventional semiconductor device is greatly improved, and thus the breakdown voltage of the semiconductor device withstand voltage structure provided by the embodiment has a high breakdown voltage, thereby improving the semiconductor device. Breakdown voltage.
  • FIG. 7 is a cross-sectional view showing a voltage-resistant structure of a semiconductor device including a P-type substrate 301, a buried oxide layer 307, a drift region 302, a P-well 303, an N-well 304, and a plurality of other embodiments.
  • the buried oxide layer 307 acts as an isolation.
  • the P-type substrate 301 can be heavily doped, and since the P-type substrate 301 is separated from the remaining portion by the buried oxide layer 307, the breakdown characteristics of the semiconductor device are less affected.
  • the drifter 302 is an N-type top layer silicon which can increase the breakdown voltage of the entire semiconductor device by adjusting the concentration.
  • P well 303 is the source substrate.
  • N-well 304 is the buffer layer of the drain.
  • the dielectric layer 308b and the field oxide layer 308a are both insulating materials.
  • the drain is used to connect the high voltage interconnection line, and the dielectric layer 308b is thickened to increase the breakdown voltage.
  • the dielectric layer 308b itself is thickened to accommodate the above The semi-insulating resistive field plate 305 and the conductor field plate 306.
  • the thickness of the field oxide layer 308a is lower than the thickness of the dielectric layer 308b.
  • the metal layer 309 includes a high voltage interconnection region 309a for arranging the high voltage interconnection lines, and the dielectric layer 308b, the field oxide layer 308a, and the drift region 302 are sequentially under the high voltage interconnection region 309a.
  • the field oxide layer 308a is in contact with the surface of the drift region 302, and the surface of the drift region 302 refers to a surface region of the drift region 302 between the P well 303 and the N well 304.
  • the breakdown structure of the semiconductor device provided in this embodiment is based on the thickened dielectric layer 308b, and a multilayer composite field plate is introduced to further increase the breakdown voltage of the semiconductor device.
  • Each of the semi-insulating resistive field plates 305 is adjacent to the surface of the field oxide layer 308a. Since the field oxide layer 308a is only below the semi-insulating resistive field plate 305, each of the semi-insulating resistive field plates 305 modulates the electric field on the surface of the drift region 302.
  • Each of the conductor field plates 306 is located in the dielectric layer 308b, and is sequentially arranged from below the metal layer 309 to form a multi-layer structure, and each of the lowermost conductor field plates 306 is located above each of the semi-insulating resistance field plates 305. It should be noted that although all of the conductor field plates 306 in FIG. 7 are arranged in two upper and lower layers, in other embodiments, all of the conductor field plates 306 may be arranged in three or more layers.
  • any of the conductor field plates 306 and the other conductor field plates 306 arranged in different layers constitute a capacitor. Since the capacitor can be formed, the two conductor field plates 306 constituting the capacitor are located in the upper and lower layers, respectively. Wherein, the conductor field plate 306 may form a capacitor with one conductor field plate 306, or at the same time, two adjacent capacitor field plates 306, respectively, as long as one conductor field plate 306 can be combined with another conductor field plate. 306 can constitute a capacitor. Since the performance of each conductor field plate 306 is the same, when the conductor field plate 306 and the two adjacent conductor field plates 306 respectively form two capacitors, the capacitance on the conductor field plate 306 is two capacitors connected in series. And, therefore, the two capacitors do not cancel each other out, so that the effect of enhancing the breakdown voltage is not affected.
  • each of the semi-insulating resistive field plates 305 and the conductor field plates 306 are located between the two electrodes of the semiconductor device, and at least one of the two electrodes is used to connect the high voltage interconnecting wires.
  • the conductor field plate 306 adjacent to the electrodes for connecting the high voltage interconnection wires is connected to the semi-insulating resistance field plate 305 through the conductors, away from A conductor field plate 306 for connecting the electrodes of the high voltage interconnection line and the semi-insulating field plate 305 constitute a capacitor.
  • each of the semi-insulating resistive field plates 305 is vertically connected to the conductor field plate 306 located at the upper right thereof, and forms a capacitor with the conductor field plate 306 at the upper left thereof to form an overlapping capacitance.
  • the conductor field plate 306 located at the lowermost layer ie, closest to the semi-insulating resistance field plate 305 forms both a capacitor with the other conductor field plate 306 located above and a semi-insulating field plate 305 located below.
  • a capacitor is arranged in the lowermost layer (ie, closest to the semi-insulating resistance field plate 305)
  • any semi-insulating resistance field plate 305 disposed in this embodiment is perpendicularly connected to the conductor field plate 306 located at the upper right thereof, so that any one of the semi-insulating resistance fields There is only one type of capacitor on the board 305, which enhances the stability of the operation of each capacitor.
  • the induced voltage is gradually transferred to the conductor field plate 306 of the lower adjacent layer due to the capacitive effect, and finally transferred to the semi-insulating resistance field plate 305. . Since the voltage is consumed during the downward transfer, the voltage value of the induced voltage finally transmitted to the semi-insulating resistance field plate 305 is low. At the same time, since the semi-insulating resistance field plate 305 modulates the electric field on the surface of the drift region 302, the entire electric field potential of the surface of the drift region 302 is finally low, thereby effectively weakening the influence of the high voltage on the drift region 302, and improving the semiconductor device.
  • the breakdown voltage in turn, enables semiconductor devices to operate at higher voltages, while also making it easier to interconnect high and low voltage devices.
  • the surface of the drift region 302 can be evenly distributed corresponding to the electric field near each semi-insulating resistance field plate 305 under the modulation of the semi-insulating resistance field plates 305. Distribution, thereby reducing the possibility of occurrence of dense areas of the circuit, further increasing the breakdown voltage of the semiconductor device.
  • each of the conductor field plates 306 arranged in the same layer has the same size and is sequentially arranged at the same interval
  • each of the semi-insulating resistance field plates 305 has the same size and is sequentially arranged at the same interval.
  • the electric fields formed by the respective conductor field plates 306 in each layer are uniformly distributed, and the electric fields formed by all of the semi-insulating resistance field plates 305 of the first layer are also uniformly distributed.
  • the electric field formed in the vicinity of the semi-insulating resistance field plate 305 is not only low in potential but also uniformly distributed.
  • the withstand voltage structure of the semiconductor device can both weaken the influence of the high voltage on the drift region 302 and avoid the occurrence of the electric field dense region on the surface of the drift region 302. The phenomenon of breakdown occurs, thereby further increasing the breakdown voltage of the semiconductor device.
  • the formed projection pattern can cover the surface of the drift region 302. That is to say, the gap between any two adjacent field plates in each layer always has a field plate of the other layer located opposite to the gap, thereby completely isolating the drift region 302 from the dielectric layer 308b.
  • the metal layer 309 and the dielectric layer 308b When the semiconductor device is in operation, the metal layer 309 and the dielectric layer 308b generate a lot of movable ions, and these movable ions have a certain potential, and at the same time, since the semiconductor device generates self-heating effect during operation, these movable ions will Diffusion to the drift region 302 under the action of the self-heating effect, when these movable ions are excessive to some extent, causes failure of the semiconductor device, thereby seriously affecting the reliability of the semiconductor device. Therefore, in the present embodiment, by providing a multi-layer composite field plate, the drift region 302 is completely isolated from the dielectric layer 308b, shielding the movement of the movable ions, thereby improving the reliability of the operation of the semiconductor device.
  • the size and spacing of the semi-insulating resistance field plates 305, the size of each conductor field plate 306, and the spacing between the layers, and the layers are adjusted.
  • the interval between the two can adjust the size of each capacitor, so that the entire electric field distribution is optimal.
  • the distance between each of the semi-insulating resistive field plates 305 is between 0.3 and 0.8 microns.
  • each of the semi-insulating resistance field plates 305 the greater the thickness of each of the semi-insulating resistance field plates 305, the more uniform the internal electric field, but the thickness of each semi-insulating resistance field plate 305 needs to be ensured between the semi-insulating resistance field plates 305 and the corresponding conductor field plates 306.
  • the spacing maintains the capacitive effect.
  • the thinner the thickness of the field oxide layer 308a the more obvious the effect of the semi-insulating resistance field plate 305 on the surface electric field of the drift region 302, but the thickness of the field oxide layer 308a needs to ensure that the semi-insulating resistance field plate 305 does not have a direct current flow.
  • the area of the area formed by all of the semi-insulating resistance field plates 305 is equal to the area of the surface area of the drift area 302.
  • the region of the surface of the drift region 302 is the surface region of the drift region 302 between the P well 303 and the N well 304.
  • This has the advantage that the larger the region of the drift region 302 that is subjected to high voltage, the greater the high voltage value that the drift region 302 can withstand, thereby further increasing the breakdown voltage of the entire semiconductor device.
  • all of the regions of the semi-insulating resistive field plate 305 are not overlaid on the active region, thereby ensuring that the active region is not affected by the high voltage.
  • the entire area of all of the semi-insulating resistive field plates 305 may also be smaller than the area of the surface area of the drift region 302 as long as the semiconductor device is not broken down.
  • the conductor field plate 306 is a metal field plate
  • the semi-insulated resistance field plate 305 is a polysilicon field plate.
  • the conductor field plate 306 can also be made from other types of conductors, such as an electrically conductive alloy.
  • the semi-insulating resistive field plate 305 can also be made of other semi-insulating materials as long as a uniform electric field is ensured.
  • the two electrodes comprise a first electrode and a second electrode, and the first electrode is for connecting a high voltage interconnecting wire and the second electrode is for grounding.
  • Each of the conductor field plates 306 arranged in the respective layers and closest to the second electrode is electrically connected to the second electrode, and is arranged on a layer adjacent to the semi-insulating resistance field plate 305 and closest to the second electrode.
  • the conductor field plate 306 is also electrically coupled to a semi-insulating resistive field plate 305 that is closest to the second electrode.
  • an end of the semi-insulating resistive field plate 305 closest to the second electrode adjacent to the second electrode is located above the active region corresponding to the second electrode.
  • the first electrode is located on the right side and the second electrode is located on the left side. Since the second electrode is grounded, the conductive field plate 306 located at the leftmost side of each layer and the semi-insulated resistance field plate 305 located at the leftmost side are disposed. The potentials are all zero potential, thereby being able to attenuate the influence of the boundary peak electric field on the performance of the semiconductor device.
  • the high voltage semiconductor withstand voltage structure provided by the embodiment is applicable not only to a laterally diffused metal oxide semiconductor but also to other types of semiconductor devices, such as a semiconductor device using bulk silicon or silicon carbide as a substrate material. Or a fast recovery diode, an insulated gate bipolar transistor, or the like, as long as the conductor field plate 306 and the semi-insulating resistance field plate 305 are provided in the lower insulating layer corresponding to the high voltage interconnection line in each semiconductor device in the same principle as the present embodiment. The breakdown voltage of each semiconductor device is increased.

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Abstract

一种半导体器件耐压结构，包括：金属层（107），包括用于布置高压互联线的高压互联区域（107a）；依次位于高压互联区域（107a）下方的介质层（108a）、场氧化层（108b）、漂移区（102）；多个半绝缘电阻场板（105），每一半绝缘电阻场板（105）均与场氧化层（108b）相邻；及多个导体场板（106），每一导体场板（106）位于半绝缘电阻场板（105）上方，且导体场板（106）处于介质层（108a）中；导体场板（106）与半绝缘电阻场板（105）构成多个电容器，且每两个相邻的电容器共用一个导体场板（106）或半绝缘电阻场板（105），以使每一电容器能与另一电容器传送能量。

Description

半导体器件耐压结构
【技术领域】
本发明涉及半导体器件技术领域，特别是涉及一种半导体器件耐压结构。
【背景技术】
在半导体器件中，若需要在较高电压下工作时，需将一部分电极通过高压互联线与外围的高压母线连接。若高压互联线在半导体器件表面覆盖的区域下方包含有源区，则当高压互联线与高压母线连接后，高压会通过接触孔经过介质层、场氧化层而传递到有源区中，从而可能导致有源区发生击穿最终使得整个半导体器件失效。因此，对于需要在较高电压下工作的半导体器件来说，版图中会设置一片专用于布置上述高压互联线的区域。
为防止半导体器件击穿，高压互联线覆盖区域的下方（以下简称半导体器件耐压结构）不能包含有源区，而只能包含漂移区。这部分漂移区则能通过场氧化层和介质层而感应出相应的高压，若这部分漂移区的击穿电压大于所感应出的高压，即可通过漂移区来耗尽高压，从而使半导体器件不再受到高压的影响。因此，高压互联的关键在于提高此半导体器件耐压结构的击穿电压，并使得半导体器件耐压结构的击穿电压大于半导体器件的耐压。
【发明内容】
基于此，有必要提供一种能够使半导体器件在更高的电压下工作的半导体器件耐压结构。
一种半导体器件耐压结构，包括：金属层，包括用于布置高压互联线的高压互联区域；依次位于所述高压互联区域下方的介质层、场氧化层、漂移区；多个半绝缘电阻场板，每一所述半绝缘电阻场板均与所述场氧化层相邻；多个导体场板，每一导体场板位于所述半绝缘电阻场板上方，且所述导体场板处于所述介质层中；所述导体场板与所述半绝缘电阻场板构成多个电容器，且每两个相邻的电容器共用一个所述导体场板或所述半绝缘电阻场板，以使每一电容器能与另一电容器传送能量。
一种半导体器件耐压结构，包括：金属层，包括用于布置高压互联线的高压互联区域；依次位于所述高压互联区域下方的介质层、场氧化层、漂移区；多个半绝缘电阻场板，每一所述半绝缘电阻场板与所述场氧化层相邻；及多个导体场板，处于所述介质层中；所述导体场板位于所述半绝缘电阻场板上方；各所述半绝缘电阻场板及导体场板均位于半导体器件的两个电极之间，且所述两个电极中至少有一个电极用于连接所述高压互联线；最接近用于连接高压互联线的电极的导体场板与所述电极用导体连接；在与每一所述半绝缘电阻场板最接近的两个所述导体场板中，靠近用于接高压互联线的电极的所述导体场板与所述半绝缘电阻场板通过导体连接，而远离用于接高压互联线的电极的所述导体场板与所述半绝缘场板构成电容器。
一种半导体器件耐压结构，包括：金属层，包括用于布置高压互联线的高压互联区域；依次位于所述高压互联区域下方的介质层、场氧化层、漂移区；多个半绝缘电阻场板，每一所述半绝缘电阻场板与所述场氧化层相邻；及多个导体场板，处于所述介质层中并位于所述半绝缘电阻场板上方；所述多个导体场板排列成上、下两层；每一所述导体场板与排列在不同层的另一所述导体场板构成电容器；各所述半绝缘电阻场板及导体场板均位于半导体器件的两个电极之间，且所述两个电极中至少有一个电极用于连接所述高压互联线；在与每一所述半绝缘电阻场板最接近的两个所述导体场板中，靠近用于接高压互联线的电极的所述导体场板与所述半绝缘电阻场板通过导体连接，而远离用于接高压互联线的电极的所述导体场板与所述半绝缘场板构成电容器。
上述半导体器件耐压结构中，导体场板位于半绝缘电阻场板上方，且导体场板处于介质层中，导体场板与半绝缘电阻场板构成多个电容器，且每两个相邻的电容器共用一个导体场板或半绝缘电阻场板，以使每一电容器能与另一电容器传送能量。当导体场板感应到高压并通过电容效应传递时，由于每一电容器能与另一电容器传送能量，因此最终高压会分散于各电容器中。而由于传递过程中存在能量消耗，因此分散于各电容器中的电压即会减弱，从而使得半绝缘电阻场板下方形成较弱的电场。同时，由于半绝缘电阻场板均与场氧化层相邻，即半绝缘电阻场板对漂移区表面的电场具有的调制作用，因此在半绝缘电阻场板下方形成较弱的电场的情况下，由于半绝缘电阻场板的调制作用，即使得漂移区表面的电场也会较弱，从而在整体上减小了漂移区表面承受的高压，提高了半导体器件的击穿电压，使得半导体器件能够在更高的电压下工作。
【附图说明】
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的附图。
图1为一实施例的半导体器件耐压结构的剖视图。
图2为另一实施例提供的半导体器件耐压结构的剖视图。
图3为传统半导体器件耐压结构形成的电场分布图。
图4为图2所示实施例的半导体器件耐压结构形成的电场分布图。
图5为传统半导体器件耐压结构的击穿电压测试曲线。
图6为图2所示实施例的半导体器件耐压结构的击穿电压测试曲线。
图7为另一实施例的半导体器件耐压结构的剖视图。
【具体实施方式】
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的较佳实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容的理解更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于发明的技术领域的技术人员通常理解的含义相同。本文中在发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在限制本发明。本文所使用的术语“和／或”包括一个或多个相关的所列项目的任意的和所有的组合。
为了更清楚的解释本发明提供的半导体器件耐压结构，以下结合实施例作具体的说明。在以下实施例中，半导体器件耐压结构设置于半导体器件中，用于提高半导体器件的击穿电压，且以横向扩散金属氧化物半导体为例进行说明。
如图1所示，一实施例提供的半导体器件耐压结构包括P型衬底101、埋氧化层109、漂移区102、P阱103、N阱104、多个半绝缘电阻场板105、多个导体场板106、金属层107、介质层108a、场氧化层108b。
其中，金属层107包括用于布置高压互联线的高压互联区域107a，且高压互联区域107a下方依次为介质层108a、场氧化层108b、漂移区102。其中，埋氧化层109起隔离作用。P型衬底101可以使用重掺杂，同时由于P型衬底101被埋氧化层109与其余部分隔离开，所以对半导体器件的击穿特性影响较小。漂移区102为N型顶层硅，可通过调节浓度来提高整个半导体器件器件的击穿电压。P阱103，是源极的衬底。N阱104，是漏极的缓冲层。介质层108a、场氧化层108b均为绝缘材料。
其中，漏极用于接高压互联线，介质层108a采取加厚的方式以提高击穿电压。需要说明的是，由于本实施例中在介质层108a中设置了多个半绝缘电阻场板105、多个导体场板106，因此介质层108a本身就是采用了加厚的方式，以便容纳多个半绝缘电阻场板105及多个导体场板106。场氧化层108b的厚度低于介质层108a的厚度。需要说明的是，本实施例中场氧化层108与漂移区102表面相接，且该漂移区102表面是指漂移区102上位于P阱103和N阱104之间的表面区域。
本实施例提供的半导体器件耐压结构，是在加厚介质层108a的基础上，引入多层场板来进一步提高半导体器件的击穿电压。具体原理如下。
其中，每一半绝缘电阻场板105均与场氧化层108b相邻。由于各半绝缘电阻场板105与场氧化层108b相邻，所以半绝缘电阻场板105对漂移区102表面的电场有调制作用。
另外，每一导体场板106均位于介质层108a内，并处于介质层108a内靠近金属层107的位置。同时，每一导体场板106在各半绝缘电阻场板105之上。导体场板106与半绝缘电阻场板105构成多个电容器，且每两个相邻的电容器共用一个导体场板106或半绝缘电阻场板105，以使每一电容器能与另一电容器传送能量。
其中，每两个相邻的电容器共用一个导体场板106，则该共用的导体场板106的左右两部分结构分别与位于下方的相邻两个半绝缘电阻场板105构成两个电容器。因此，这两个相邻的电容器之间即可通过该共用的导体场板106及电容效应来传递能量。
另外，每两个相邻的电容器共用一个半绝缘电阻场板105，则该共用的半绝缘电阻场板105的左右两部分结构分别与位于上方的相邻两个导体场板106构成两个电容器。因此，这两个相邻的电容器之间即可通过该共用的半绝缘电阻场板105及电容效应来传递能量。
因此，对于本实施例提供的上述半导体器件耐压结构，当导体场板106感应到高压并通过电容效应传递时，由于每一电容器能与另一电容器传送能量，因此最终高压会分散于各电容器中。而由于传递过程中存在能量消耗，因此分散于各电容器中的电压即会减弱，从而使得半绝缘电阻场板105下方形成较弱的电场。同时，由于半绝缘电阻场板105均与场氧化层108b相邻，即半绝缘电阻场板105对漂流区102表面的电场具有的调制作用，因此在半绝缘电阻场板105下方形成较弱的电场的情况下，由于半绝缘电阻场板105的调制作用，即使得漂移区102表面的电场也会较弱，从而在整体上减小了漂移区102表面承受的高压，提高了半导体器件的击穿电压，使得半导体器件能够在更高的电压下工作。
在其他实施例中，各半绝缘电阻场板105及导体场板106均位于半导体器件的两个电极之间，且该两个电极中至少有一个电极用于连接高压互联线。另外，在与每一半绝缘电阻场板105最接近的两个导体场板106中，靠近用于接高压互联线的电极的导体场板106与该半绝缘电阻场板105通过导体连接，而远离用于接高压互联线的电极的导体场板106与该半绝缘电阻场板105构成电容器。例如，位于右侧的电极为漏极，且该漏极用于连接高压互连线，因此，每一半绝缘电阻场板105均与位于其右上方的导体场板106垂直相连，而与位于其左上方的导体场板106构成电容器，即形成交叠电容。
由于绝缘电阻场板105与导体场板106的材料性质不同，因此本实施例设置任一半绝缘电阻场板105均与位于其右上方的导体场板106垂直相连，使得任一半绝缘电阻场板105上只存在一种电容，从而增强了各电容工作的稳定性。
进一步的，图2示出了另一实施例的半导体器件耐压结构的剖视图。其中，该半导体器件耐压结构包括：P型衬底201、埋氧化层209、漂移区202、P阱203、N阱204、若干半绝缘电阻场板205、若干导体场板206、金属层207、介质层208a、场氧化层208b。
其中，埋氧化层209起隔离作用。P型衬底201可以使用重掺杂，同时由于P型衬底201被埋氧化层209与其余部分隔离开，所以对半导体器件的击穿特性影响较小。漂移区202为N型顶层硅，可通过调节浓度来提高整个半导体器件器件的击穿电压。P阱203，是源极的衬底。N阱204，是漏极的缓冲层。介质层208a、场氧化层208b均为绝缘材料。
其中，漏极用于接高压互联线，介质层208a采取加厚的方式以提高击穿电压。需要说明的是，由于本实施例中在介质层208a中设置了多个半绝缘电阻场板205、多个导体场板206，因此介质层208a本身就是采用了加厚的方式，以便容纳上述各半绝缘电阻场板205、导体场板206。场氧化层208b的厚度低于介质层208a的厚度。如图2所示，金属层207包括用于布置高压互联线的高压互联区域207a，且高压互联区域207a下方依次为介质层208a、场氧化层208b、漂移区202。需要说明的是，本实施例中场氧化层208与漂移区202表面相接，且该漂移区202表面是指位于P阱203和N阱204之间的表面区域。
本实施例提供的半导体器件耐压结构，是在加厚介质层208a的基础上，引入多层场板来进一步提高半导体器件的击穿电压。
其中，各半绝缘电阻场板205均与场氧化层208b相邻。由于各半绝缘电阻场板205与场氧化层208b相邻，所以半绝缘电阻场板205对漂移区202表面的电场有调制作用。
另外，各导体场板206均位于介质层208a中接近金属层207的位置，并位于各半绝缘电阻场板205之上。同时，各半绝缘电阻场板205及导体场板206均位于半导体器件的两个电极之间，且这两个电极中至少有一个电极用于连接高压互联线。在所有导体场板206中，最接近用于接高压互联线的电极的导体场板206与该电极用导体连接，如图2所示，即最右端的导体场板206与漏极相连。
同时在与每一半绝缘电阻场板205最接近的两个导体场板206中，靠近上述电极的导体场板206与该半绝缘电阻场板205通过导体连接，而远离用于接高压互联线的电极的导体场板206与该半绝缘场板205构成电容器。在本实施例中，每一半绝缘电阻场板205均与位于其右上方的导体场板206垂直相连，而与位于其左上方的导体场板206构成电容器，即形成交叠电容。
其中，由于绝缘电阻场板205与导体场板206的材料性质不同，因此本实施例设置任一半绝缘电阻场板205均与位于其右上方的导体场板206垂直相连，使得任一半绝缘电阻场板205上只存在一种电容，增强了各电容工作的稳定性。
因此，对于本实施例提供的半导体器件耐压结构，一方面，当导体场板206感应到高压后，即会将电压传递至与其相连的半绝缘电阻场板205，之后半绝缘电阻场板205又会通过电容效应将一部分电压传递至左上方的另一导体场板206，以此类推，最终高压将会分散于各导体场板206和半绝缘电阻场板205中，且由于存在能量消耗，半绝缘电阻场板205下方最终形成较弱的电场，进而在半绝缘电阻场板205对漂移区202表面电场调制的作用下，使得漂移区202表面的电场也呈较弱的电场分布，有效削弱了高压对半导体器件内部漂移区202的影响。
另一方面，当漏极连接高压互联线后，与漏极相连的导体场板206即会通过漏极首先形成带电位场板，并使得与其相连的半绝缘电阻场板205带有同样电位，之后该半绝缘电阻场板205左上方的导体场板206也会由于电容效应，随之带有一定的电位。依次类推，最终所有的导体场板206和半绝缘电阻场板205都会成为带电位场板。而由于在各级场板中传递电压时存在能量消耗，因此，最终在半绝缘电阻场板205的下方形成逐渐递减的电势分布，进而在半绝缘电阻场板205对漂移区202表面电场调制的作用下，使得漂移区202表面的电场也呈逐渐递减的电势分布，有效削弱了高压对半导体器件内部漂移区202的影响，在整体上减小了漂移区202表面承受的高压，提高了半导体器件的击穿电压，从而使得半导体器件能够在更高的电压下工作，同时更有益于实现高低压器件的互联。
另外，由于各半绝缘电阻场板205内部电场是均匀分布的，因此，在各半绝缘电阻场板205附近的电势逐渐下降的基础上，在半绝缘电阻场板205的调制作用下，还可以使得对应任一半绝缘电阻场板205附近漂移区202表面的电场均匀分布，从而减小因出现电场密集区域而发生击穿的可能性。
需要说明的是，在不同的工作电压或其他情况下，通过调整半绝缘电阻场板205的大小及相互之间的间隔、各导体场板206的大小及相互之间的间隔，即可调整交叠电容的大小，进而使得整个电场分布达到最佳的状态。
同时，各半绝缘电阻场板205的厚度越大，其内部的电场越均匀，但半绝缘电阻场板205的厚度需保证半绝缘电阻场板205与相应的导体场板206之间的间隔能够保持电容效应。另外，场氧化层208b的厚度越薄，半绝缘电阻场板205对漂移区202表面电场的调制作用越明显，但场氧化层208b的厚度需保证半绝缘电阻场板205中不会有电流直接流向漂移区202。
具体的，各半绝缘电阻场板205的大小相同，且按相同的间隔依次排列，如此，半绝缘电阻场板205则会感应出相对均匀分布的电场。那么在半绝缘电阻场板205的调制作用下，就能够避免漂移区202表面因出现电场密集区域而发生击穿的现象。在上述情况下，该半导体器件耐压结构，一方面在半绝缘电阻场板205与导体场板206之间依次传递电压的情况下，使得漂移区202表面形成逐渐递减的电势分布；另一方面，由于半绝缘电阻场板205能够均匀分布电场，因此最终使得漂移区202表面的电场在逐渐递减的基础上又均匀分布，既削弱了高压对漂移区202的影响，又能避免漂移区202表面因出现电场密集区域而发生击穿的现象，从而进一步提高了半导体器件的击穿电压。
需要说明的是，半绝缘电阻场板205之间的距离越小，由所有半绝缘电阻场板205产生的电场就越均匀。在本实施例中，任意相邻的两个半绝缘电阻场板205之间的距离介于0.3至0.8微米之间。
具体的，所有半绝缘电阻场板205构成的区域面积等于漂移区表面区域的面积。如图2所示，漂移区202表面的区域即为漂移区202上位于P阱203和N阱204之间的表面区域。这样做的好处是，漂移区202上承受高压的区域越大，则半导体器件能够承受的高压值就越大，从而进一步提高整个半导体器件的击穿电压。另外，所有半绝缘电阻场板205构成的区域没有覆盖在有源区上，从而可以保证有源区不会受到高压的影响。
另外，在其他情况下，例如电压较低，由所有半绝缘电阻场板205构成的整个区域也可小于漂移区202表面的区域，只要保证半导体器件不会击穿即可。
具体的，导体场板206为金属场板，半绝缘电阻场板205为多晶硅场板。
在其他情况下，导体场板206也可由其他类型的导体制成，例如可导电的合金。半绝缘电阻场板205也可由其他半绝缘的材料制成，只要能够保证产生均匀的电场即可。
具体的，上述两个电极包括第一电极和第二电极，且第一电极用于连接高压互联线，第二电极用于接地。本实施例中，如图2所示，第一电极位于右侧且为漏极，其对应的有源区为N阱204。第二电极用于接地且位于左侧，其对应的有源区为P阱203。
其中，最靠近第二电极的导体场板206分别与该第二电极、最靠近该第二电极的半绝缘电阻场板205电连接。同时，最靠近该第二电极的半绝缘电阻场板205的靠近该第二电极的一端位于与该第二电极对应的有源区上方。
如图2所示，本实施例中，位于最左侧的导电场板206分别与第二电极、位于最左侧的半绝缘电阻场板205电连接。由于第二电极接地，因此使得位于最左侧的导电场板206及位于最左侧的半绝缘电阻场板205的电位均为零电位，从而能够减弱边界峰值电场对半导体器件性能的影响。
需要说明的，本实施例提供的半导体器件耐压结构不仅适用于横向扩散金属氧化物半导体中，还适用于其他类型的半导体器件中，例如以体硅或碳化硅作为衬底材料的半导体器件，或者快恢复二极管、绝缘栅双极晶体管等，只要在各半导体器件中对应高压互联线的下方绝缘层中按与本实施例相同的原理设置导体场板206和半绝缘电阻场板205，就同样会提高各半导体器件的击穿电压。
为了验证本实施例提供的半导体器件耐压结构的击穿电压，发明人通过模拟仿真软件在将高压互联线连接高压后，对传统和本实施例提供的半导体器件耐压结构分别进行二维模拟仿真，图3示出了传统半导体器件耐压结构形成的电场分布图，图4示出了一实施例的半导体器件耐压结构形成的电场分布图。
由图3、图4可以看出，传统的半导体器件耐压结构中在左侧出现电场线聚集的情况，因此在这一区域容易发生击穿的现象。而在本实施例提供的半导体器件耐压结构中，从漏极到源极之间的电场线密度逐渐变小，也就是电势逐渐变小，同时电场线分布在整体上呈现均匀过渡的趋势，变化平滑，没有出现电场线聚集的情况。因此，在电场线分布情况中，本发明提供的半导体器件耐压结构较传统方法有了较大程度的提升。
同时，为了进一步验证本实施例提供的半导体器件耐压结构的耐压性能，发明人还对传统方法和本实施例提供的高压半导体耐压结构的击穿电压进行了验证。图5为传统半导体器件耐压结构的击穿电压测试曲线。图6为图2所示实施例的半导体器件耐压结构的击穿电压测试曲线。
由图5、图6所示，传统的半导体器件耐压结构的击穿电压为170V左右，而图2所示实施例的半导体器件耐压结构的击穿电压为650V左右，并且发明人还测出使用图2所示实施例提供的半导体器件耐压结构的半导体器件的击穿电压为580V。由此可以得出，本实施例通过采用导体场板206和半绝缘电阻场板205，使得半导体器件耐压结构具有较高的击穿电压，同时满足半导体器件耐压结构的击穿电压大于半导体器件的击穿电压。因此在耐压性方面，较传统的半导体器件耐压结构有了较大的提升，由此可得出本实施例提供的半导体器件耐压结构具有较高的击穿电压，进而提高了半导体器件的击穿电压。
图7示出了另一实施例的半导体器件耐压结构的剖视图，该半导体器件耐压结构包括：P型衬底301、埋氧化层307、漂移区302、P阱303、N阱304、多个半绝缘电阻场板305、多个导体场板306、金属层309、介质层308b、场氧化层308a。
其中，埋氧化层307起隔离作用。P型衬底301可以使用重掺杂，同时由于P型衬底301被埋氧化层307与其余部分隔离开，所以对半导体器件的击穿特性影响较小。漂移器302为N型顶层硅，可通过调节浓度来提高整个半导体器件器件的击穿电压。P阱303，是源极的衬底。N阱304，是漏极的缓冲层。介质层308b、场氧化层308a均为绝缘材料。
其中，漏极用于接高压互联线，介质层308b采取加厚的方式以提高击穿电压。需要说明的是，由于本实施例中在介质层308b中设置了多个半绝缘电阻场板305、多个导体场板306，因此介质层308b本身就是采用了加厚的方式，以便容纳上述各半绝缘电阻场板305、导体场板306。场氧化层308a的厚度低于介质层308b的厚度。如图7所示，金属层309包括用于布置高压互联线的高压互联区域309a，且高压互联区域309a下方依次为介质层308b、场氧化层308a、漂移区302。需要说明的是，本实施例中场氧化层308a与漂移区302表面相接，且该漂移区302表面是指漂移区302上位于P阱303和N阱304之间的表面区域。
本实施例提供的半导体器件耐压结构，是在加厚介质层308b的基础上，引入多层复合型场板来进一步提高半导体器件的击穿电压。
其中，各半绝缘电阻场板305均与场氧化层308a表面相邻。由于半绝缘电阻场板305的下方仅有场氧化层308a，因此各半绝缘电阻场板305对漂移区302表面的电场有调制作用。
各导体场板306位于介质层308b中，且从金属层309下方开始，依次排列形成多层结构，最下层的各导体场板306均位于各半绝缘电阻场板305之上。需要说明的是，虽然图7中的所有导体场板306共排列为上、下两层，但在其他实施例中，所有导体场板306还可以排列为三层或三层以上结构。
同时，任一导体场板306与排列在不同层的另一导体场板306构成电容器。由于能够构成电容器，因此构成电容器的这两个导体场板306分别位于上、下层。其中，导体场板306可以与一个导体场板306构成电容器，或者同时与相邻的两个导体场板306分别构成两个电容器，只要保证任一导体场板306均能够与另一个导体场板306构成电容器即可。由于各导体场板306的性能相同，所以当导体场板306同时与相邻的两个导体场板306分别构成两个电容器时，该导体场板306上的电容即为两个串联的电容之和，因此两个电容不会存在相互抵消的情况，从而不会影响增强击穿电压的效果。
另外，各半绝缘电阻场板305及导体场板306均位于半导体器件的两个电极之间，且这两个电极中至少有一个电极用于连接高压互联线。其中，在与每一半绝缘电阻场板305最接近的两个导体场板306中，靠近用于连接高压互联线的电极的导体场板306与该半绝缘电阻场板305通过导体连接，而远离用于连接高压互联线的电极的导体场板306与该半绝缘场板305构成电容器。在本实施例中，每一半绝缘电阻场板305均与位于其右上方的导体场板306垂直相连，而与位于其左上方的导体场板306构成电容器，即形成交叠电容。需注意的是，位于最下层（即最接近半绝缘电阻场板305）的导体场板306既与位于上方的另一个导体场板306构成电容器，又与位于下方的半绝缘场板305构成另一电容器。
其中，由于绝缘电阻场板305与导体场板306的材料性质不同，因此本实施例设置任一半绝缘电阻场板305均与位于其右上方的导体场板306垂直相连，使得任一半绝缘电阻场板305上只存在一种电容，增强了各电容工作的稳定性。
当高压互联线连接高压后，从最接近金属层309的导体场板306开始，由于电容效应会逐渐向下面相邻层的导体场板306传递感应电压，并最终传递至半绝缘电阻场板305。由于电压在向下传递的过程中，会消耗能量，所以最终传递至半绝缘电阻场板305上的感应电压的电压值较低。同时由于半绝缘电阻场板305对漂移区302表面的电场有调制作用，因此，最终使得漂移区302表面的整个电场电势较低，从而有效削弱了高压对漂移区302的影响，提高了半导体器件的击穿电压，进而使得半导体器件能够在更高的电压下工作，同时也更易于实现高低压器件的互联。
另外，由于各半绝缘电阻场板305内部电场是均匀分布的，因此在各半绝缘电阻场板305调制的作用下，还可以使得漂移区302表面对应每一半绝缘电阻场板305附近的电场均匀分布，从而降低电路密集区域的出现的可能性，进一步提高半导体器件的击穿电压。
具体的，排列在同一层中的各导体场板306大小相同，且按相同的间隔依次排列，且各半绝缘电阻场板305的大小相同，且按相同的间隔依次排列。在这种情况下，在每一层中由各导体场板306形成的电场都是均匀分布，而且位于第一层的所有半绝缘电阻场板305形成的电场也呈均匀分布。那么，在高压从最上层的导体场板306开始逐渐向下传递至最底层的半绝缘电阻场板305后，在半绝缘电阻场板305附近形成的电场不仅电势较低而且均匀分布。由于电场均匀分布能够避免因出现电场密集区域而容易击穿的现象，因此，该半导体器件耐压结构既能削弱高压对漂移区302的影响，又能避免漂移区302表面因出现电场密集区域而发生击穿的现象，从而进一步提高了半导体器件的击穿电压。
具体的，将所有导体场板306、半绝缘电阻场板305投影至漂移区302表面后，形成的投影图形能够将漂移区302表面覆盖。也就是说，各层中任意相邻两个场板之间的空隙，总会有其它层的场板位于与该空隙相对的位置上，从而将漂移区302与介质层308b完全隔离开。
当半导体器件在工作时，金属层309和介质层308b会产生很多可动离子，这些可动离子均带有一定的电位，同时由于半导体器件在工作时会产生自热效应，而这些可动离子会在自热效应的作用下向漂移区302进行扩散，当这些可动离子多到一定程度时，会导致半导体器件的失效，从而严重影响半导体器件的可靠性。因此，在本实施例中，通过设置多层复合型场板，将漂移区302与介质层308b完全隔离开，屏蔽了可动离子的运动，从而可以提高半导体器件工作的可靠性。
需要说明的是，在不同的工作电压或其他情况下，通过调整各半绝缘电阻场板305的大小及相互之间的间隔、各导体场板306的大小及相互之间的间隔、各层之间的间隔，均可调整各电容的大小，进而使得整个电场分布达到最佳的状态。另外，各半绝缘电阻场板305之间的距离越小，由所有半绝缘电阻场板305产生的电场越均匀。在本实施例中，各半绝缘电阻场板305之间的距离介于0.3至0.8微米之间。
同时，各半绝缘电阻场板305的厚度越大，其内部的电场越均匀，但各半绝缘电阻场板305的厚度需保证各半绝缘电阻场板305与相应的导体场板306之间的间隔能够保持电容效应。另外，场氧化层308a的厚度越薄，半绝缘电阻场板305对漂移区302表面电场的调制作用越明显，但场氧化层308a的厚度需保证半绝缘电阻场板305不会有电流直接流向漂移区302。
具体的，由所有半绝缘电阻场板305构成的区域面积等于漂移区302表面区域的面积。如图7所示，漂移区302表面的区域即为漂移区302上位于P阱303和N阱304之间的表面区域。这样做的好处是，漂移区302上承受高压的区域越大，则漂移区302能够承受的高压值就越大，从而进一步提高整个半导体器件的击穿电压。另外，所有半绝缘电阻场板305构成的区域没有覆盖在有源区上，从而保证有源区不会受到高压的影响。
在其他情况下，例如电压较低，由所有半绝缘电阻场板305构成的整个区域的面积也可小于漂移区302表面区域的面积，只要保证半导体器件不会击穿即可。
具体的，导体场板306为金属场板，半绝缘电阻场板305为多晶硅场板。
在其他情况下，导体场板306也可由其他类型的导体制成，例如可导电的合金。半绝缘电阻场板305也可由其他半绝缘的材料制成，只要能够保证产生均匀的电场即可。
在其他实施例中，上述两个电极包括第一电极和第二电极，且第一电极用于连接高压互联线，第二电极用于接地。
其中，排列于各层且最靠近第二电极的各导体场板306均与该第二电极电连接，同时，排列于与半绝缘电阻场板305相邻的一层且最靠近第二电极的导体场板306，还与最靠近该第二电极的半绝缘电阻场板305电连接。另外，最靠近该第二电极的半绝缘电阻场板305的靠近该第二电极的一端位于与该第二电极对应的有源区上方。
故以第一电极位于右侧，第二电极位于左侧为例，由于第二电极接地，因此使得各层中位于最左侧的导电场板306及位于最左侧的半绝缘电阻场板305的电位均为零电位，从而能够减弱边界峰值电场对半导体器件性能的影响。
需要说明的，本实施例提供的高压半导体耐压结构不仅适用于横向扩散金属氧化物半导体中，还适用于其他类型的半导体器件中，例如以体硅或碳化硅作为衬底材料的半导体器件，或者快恢复二极管、绝缘栅双极晶体管等，只要在各半导体器件中对应高压互联线的下方绝缘层中按与本实施例相同的原理设置导体场板306和半绝缘电阻场板305，就同样会提高各半导体器件的击穿电压。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种半导体器件耐压结构，包括：
    金属层，包括用于布置高压互联线的高压互联区域；
    依次位于所述高压互联区域下方的介质层、场氧化层、漂移区；
    多个半绝缘电阻场板，每一所述半绝缘电阻场板均与所述场氧化层相邻；及
    多个导体场板，每一导体场板位于所述半绝缘电阻场板上方，且所述导体场板处于所述介质层中；所述导体场板与所述半绝缘电阻场板构成多个电容器，且每两个相邻的电容器共用一个所述导体场板或所述半绝缘电阻场板，以使每一电容器能与另一电容器传送能量。
  2. 根据权利要求1所述的半导体器件耐压结构，其特征在于，各所述半绝缘电阻场板及导体场板均位于半导体器件的两个电极之间，且所述两个电极中至少有一个电极用于连接所述高压互联线；在与每一所述半绝缘电阻场板最接近的两个所述导体场板中，靠近用于接高压互联线的电极的所述导体场板与所述半绝缘电阻场板通过导体连接，而远离用于接高压互联线的电极的所述导体场板与所述半绝缘电阻场板构成电容器。
  3. 根据权利要求2所述的半导体器件耐压结构，其特征在于，最接近用于连接高压互联线的电极的导体场板与所述电极用导体连接。
  4. 根据权利要求2所述的半导体器件耐压结构，其特征在于，所述多个导体场板排列成上、下两层；每一所述导体场板与排列在不同层的另一所述导体场板构成电容器。
  5. 根据权利要求4所述的半导体器件耐压结构，其特征在于，同一层中的各所述导体场板大小相同且按相同的间隔依次排列。
  6. 根据权利要求4所述的半导体器件耐压结构，其特征在于，将所有所述导体场板、半绝缘电阻场板投影至所述漂移区表面后，形成的投影图形能够将所述漂移区表面覆盖。
  7. 根据权利要求1所述的半导体器件耐压结构，其特征在于，各所述半绝缘电阻场板大小相同并按相同的间隔依次排列。
  8. 根据权利要求1所述的半导体器件耐压结构，其特征在于，所有所述半绝缘电阻场板构成的区域面积等于所述漂移区表面区域的面积。
  9. 根据权利要求1所述的半导体器件耐压结构，其特征在于，任意相邻的两个所述半绝缘电阻场板之间的距离均介于0.3至0.8微米之间。
  10. 根据权利要求1所述的半导体器件耐压结构，其特征在于，所述导体场板为金属场板。
  11. 根据权利要求1所述的半导体器件耐压结构，其特征在于，所述半绝缘电阻场板为多晶硅场板。
  12. 根据权利要求2所述的半导体器件耐压结构，其特征在于，所述两个电极包括第一电极和第二电极；其中，所述第一电极用于连接所述高压互联线；所述第二电极用于接地；
    最靠近所述第二电极的所述导体场板分别与所述第二电极、最靠近所述第二电极的所述半绝缘电阻场板电连接；另外，最靠近所述第二电极的所述半绝缘电阻场板的靠近所述第二电极的一端位于与所述第二电极对应的有源区上方。
  13. 一种半导体器件耐压结构，包括：
    金属层，包括用于布置高压互联线的高压互联区域；
    依次位于所述高压互联区域下方的介质层、场氧化层、漂移区；
    多个半绝缘电阻场板，每一所述半绝缘电阻场板与所述场氧化层相邻；及
    多个导体场板，处于所述介质层中；所述导体场板位于所述半绝缘电阻场板上方；各所述半绝缘电阻场板及导体场板均位于半导体器件的两个电极之间，且所述两个电极中至少有一个电极用于连接所述高压互联线；最接近用于连接高压互联线的电极的导体场板与所述电极用导体连接；在与每一所述半绝缘电阻场板最接近的两个所述导体场板中，靠近用于接高压互联线的电极的所述导体场板与所述半绝缘电阻场板通过导体连接，而远离用于接高压互联线的电极的所述导体场板与所述半绝缘场板构成电容器。
  14. 根据权利要求13所述的半导体器件耐压结构，其特征在于，各所述半绝缘电阻场板大小相同并按相同的间隔依次排列。
  15. 根据权利要求13所述的半导体器件耐压结构，其特征在于，所有所述半绝缘电阻场板构成的区域面积等于所述漂移区表面区域的面积。
  16. 根据权利要求13所述的半导体器件耐压结构，其特征在于，任意相邻的两个所述半绝缘电阻场板之间的距离均介于0.3至0.8微米之间。
  17. 根据权利要求13所述的半导体器件耐压结构，其特征在于，所述两个电极包括第一电极和第二电极；其中，所述第一电极用于连接所述高压互联线；所述第二电极用于接地；
    最靠近所述第二电极的所述导体场板分别与所述第二电极、最靠近所述第二电极的所述半绝缘电阻场板电连接；另外，最靠近所述第二电极的所述半绝缘电阻场板的靠近所述第二电极的一端位于与所述第二电极对应的有源区上方。
  18. 一种半导体器件耐压结构，包括：
    金属层，包括用于布置高压互联线的高压互联区域；
    依次位于所述高压互联区域下方的介质层、场氧化层、漂移区；
    多个半绝缘电阻场板，每一所述半绝缘电阻场板与所述场氧化层相邻；及
    多个导体场板，处于所述介质层中并位于所述半绝缘电阻场板上方；所述多个导体场板排列成上、下两层；每一所述导体场板与排列在不同层的另一所述导体场板构成电容器；各所述半绝缘电阻场板及导体场板均位于半导体器件的两个电极之间，且所述两个电极中至少有一个电极用于连接所述高压互联线；在与每一所述半绝缘电阻场板最接近的两个所述导体场板中，靠近用于接高压互联线的电极的所述导体场板与所述半绝缘电阻场板通过导体连接，而远离用于接高压互联线的电极的所述导体场板与所述半绝缘场板构成电容器。
  19. 根据权利要求18所述的半导体器件耐压结构，其特征在于，排列在同一层中的各所述导体场板大小相同且按相同的间隔依次排列。
  20. 根据权利要求18所述的半导体器件耐压结构，其特征在于，将所有所述导体场板、半绝缘电阻场板投影至所述漂移区表面后，形成的投影图形能够将所述漂移区表面覆盖。
PCT/CN2016/095903 2015-10-28 2016-08-18 半导体器件耐压结构 WO2017071378A1 (zh)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110620147A (zh) * 2018-09-14 2019-12-27 电子科技大学 超高速大电流纵向绝缘栅双极型晶体管
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CN113948571A (zh) * 2021-10-18 2022-01-18 上海华虹宏力半导体制造有限公司 半导体结构及其形成方法

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6729487B2 (ja) * 2017-05-15 2020-07-22 三菱電機株式会社 半導体装置、半導体装置の製造方法、および電力変換装置
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CN115241281A (zh) * 2022-09-15 2022-10-25 北京芯可鉴科技有限公司 功率半导体器件终端及制造方法
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CN117558746B (zh) * 2024-01-09 2024-04-16 润新微电子(大连)有限公司 一种含可变电势多场板结构的器件及其制备方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1649168A (zh) * 2004-01-26 2005-08-03 三菱电机株式会社 半导体器件
CN101859769A (zh) * 2009-04-06 2010-10-13 三菱电机株式会社 半导体装置及其制造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0175277B1 (ko) * 1996-02-29 1999-02-01 김광호 중첩된 필드플레이트구조를 갖는 전력반도체장치 및 그의 제조방법
JP3958404B2 (ja) * 1997-06-06 2007-08-15 三菱電機株式会社 横型高耐圧素子を有する半導体装置
JP2005005443A (ja) * 2003-06-11 2005-01-06 Toshiba Corp 高耐圧半導体装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1649168A (zh) * 2004-01-26 2005-08-03 三菱电机株式会社 半导体器件
CN101859769A (zh) * 2009-04-06 2010-10-13 三菱电机株式会社 半导体装置及其制造方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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CN110620147B (zh) * 2018-09-14 2023-05-23 电子科技大学 超高速大电流纵向绝缘栅双极型晶体管
CN112420681A (zh) * 2019-08-20 2021-02-26 苏州捷芯威半导体有限公司 一种芯片封装结构
CN112420681B (zh) * 2019-08-20 2024-02-27 苏州捷芯威半导体有限公司 一种芯片封装结构
CN113948571A (zh) * 2021-10-18 2022-01-18 上海华虹宏力半导体制造有限公司 半导体结构及其形成方法
CN113948571B (zh) * 2021-10-18 2023-08-25 上海华虹宏力半导体制造有限公司 半导体结构及其形成方法

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