WO2017045334A1 - 阵列基板、显示面板、显示装置以及阵列基板的制作方法 - Google Patents

阵列基板、显示面板、显示装置以及阵列基板的制作方法 Download PDF

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Publication number
WO2017045334A1
WO2017045334A1 PCT/CN2016/072672 CN2016072672W WO2017045334A1 WO 2017045334 A1 WO2017045334 A1 WO 2017045334A1 CN 2016072672 W CN2016072672 W CN 2016072672W WO 2017045334 A1 WO2017045334 A1 WO 2017045334A1
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Prior art keywords
data line
segment
electrical connection
disposed
layer
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PCT/CN2016/072672
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English (en)
French (fr)
Inventor
王守坤
郭会斌
冯玉春
李梁梁
郭总杰
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US15/324,053 priority Critical patent/US10101626B2/en
Publication of WO2017045334A1 publication Critical patent/WO2017045334A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate, a display panel, a display device, and a method of fabricating an array substrate.
  • the display panel of the liquid crystal display device includes an array substrate 1'.
  • the array substrate 1' includes gate lines 20' and data lines that cross each other on a base substrate (not shown) and define a plurality of sub-pixel units 30'.
  • a thin film transistor 40' and a pixel electrode 50' are formed in each of the sub-pixel units 30'.
  • the thin film transistor 40' includes a gate electrode 40a', a source electrode 40b', and a drain electrode 40c'.
  • the data line includes a first data line 61' and a second data line 62' disposed side by side between each two columns of adjacent sub-pixel units 50'. As shown, the first data line 61' and the second data line 62' are disposed in the same layer as the source electrode 40b' and the drain electrode 40c' of the thin film transistor 40'.
  • a double data line short circuit (DDS) easily occurs between the first data line 61' and the second data line 62' disposed side by side. Especially when the interval between the first data line 61' and the second data line 62' is too small, the DDS problem is more serious, which causes a sharp drop in product yield.
  • DDS double data line short circuit
  • the array substrate, the display panel, the display device, and the method of fabricating the array substrate of the present disclosure have at least a portion of the first data line and the adjacent second data line disposed on different layers without increasing the patterning process.
  • the DDS problem was solved in the case.
  • an array substrate in a first aspect, includes gate lines and data lines insulated from each other and intersecting to define a plurality of sub-pixel units on a base substrate, each of which is formed with a thin film transistor and a pixel electrode
  • the data line includes a first data line and a second data line disposed side by side between each two columns of adjacent sub-pixel units, wherein in each two columns of adjacent sub-pixel units, the odd-numbered sub-pixel units are connected to the first a data line, and the even row of sub-pixel units are connected to the second data line, wherein between each two adjacent sub-pixel units, at least part
  • the first data line and the adjacent second data line are disposed in different layers.
  • the first data line and the adjacent second data line are disposed on different layers.
  • the DDS can be effectively prevented, thereby improving the product yield; the crosstalk between the double data lines arranged side by side can be significantly eliminated, thereby improving the display quality of the product; and the small pitch design between the double data lines can be realized and improved.
  • the aperture ratio and wiring density of the array substrate are disposed on different layers.
  • the first data line may include a plurality of first segments and second segments that are alternately disposed, each of the first segments and each of the second segments and the film a gate electrode of the transistor is disposed in the same layer, and each of the first segment and the adjacent second segment are electrically connected to each other by a first electrical connection;
  • the second data line is disposed in the same layer as the source/drain electrodes of the thin film transistor.
  • the first data line segment is arranged, the first segment and the second segment of the first data line are disposed in the same layer as the gate electrode, and each of the first segment and the adjacent second segment They are electrically connected to each other by a first electrical connection.
  • the second data line is a conventional data line, that is, a data line disposed in the same layer as the source/drain electrodes and continuous.
  • each of the first segments of the first data line may be provided with a gate insulating through the thin film transistor at both ends thereof along the extending direction of the first data line. a first via of the layer and the passivation layer;
  • Each of the second segments of the first data line may be provided with a through-the-gate insulating layer and the passivation layer at both ends thereof along the extending direction of the first data line Two vias;
  • a third via penetrating through the passivation layer may be disposed over the source/drain electrodes of the thin film transistor
  • the first electrical connector may electrically connect the source/drain electrodes and each of the first data lines through the first via, the second via, and the third via a segment and a second segment adjacent to the first segment.
  • the first electrical connector passes through the first and second adjacent vias of the first and second segments of the first data line and the third via above the corresponding source/drain electrodes
  • the first segment of the first data line and the adjacent second segment are simultaneously electrically connected to the source/drain electrodes of the respective thin film transistors, thereby forming a complete first data line.
  • First via, second The vias and the third vias can be formed in the same patterning process, which facilitates simplification of the process steps.
  • a planarization layer may be disposed above the passivation layer in the thin film transistor. In this case, the first via, the second via, and the third via also correspondingly penetrate the planarization layer.
  • the first data line may include a plurality of first segments and second segments that are alternately disposed, the first segments being disposed in the same layer as the source/drain electrodes of the thin film transistor.
  • the second segment is disposed in the same layer as the gate electrode of the thin film transistor, and each of the first segment and the adjacent second segment are electrically connected to each other by a second electrical connection.
  • the first segment and the second segment of the first data line are alternately arranged, the first segment is disposed in the same layer as the source/drain electrodes, and the second segment is disposed in the same layer as the gate electrode.
  • the first segment and the second segment of the first data line are disposed in a staggered manner, thereby facilitating at least partial dislocation setting of the first data line and the second data line, thereby preventing the double data lines disposed side by side. Short circuit and crosstalk between.
  • the second data line may be disposed in the same layer as the source/drain electrodes of the thin film transistor.
  • the first segment and the second segment of the first data line are alternately arranged, the first segment being in the same layer as the source/drain electrodes and the second segment being disposed in the same layer as the gate electrode.
  • the second data line is disposed in the same layer as the source/drain electrodes.
  • each of the first segments of the first data line may be provided with a passivation layer penetrating the thin film transistor at both ends thereof along the extending direction of the first data line.
  • Each of the second segments of the first data line may be provided with a through-the-gate insulating layer and the passivation layer at both ends thereof along the extending direction of the first data line Five vias;
  • the second electrical connector may electrically connect each of the first segments of the first data line and adjacent to the first segment through the fourth via and the fifth via The second section.
  • the second electrical connector passes each of the first segment and the adjacent second of the first data line through the adjacent fourth via and fifth via of the first segment and the second segment
  • the segments are electrically connected to one another, thereby forming a complete first data line.
  • the fourth via and the fifth via can be formed in the same patterning process, which facilitates simplification of the process steps.
  • the second The electrical connector may form a complete first data line through a fourth via on the first segment of the first data line and a fifth via on the second segment of the first data.
  • the number of via holes is reduced.
  • a planarization layer may be disposed over the passivation layer in the thin film transistor, the fourth via hole and the fifth via hole respectively penetrate the planarization layer.
  • the second data line may include a plurality of first segments and second segments that are alternately arranged
  • the first segment of the second data line may be disposed side by side with the first segment of the first data line and disposed in the same layer as a gate electrode of the thin film transistor;
  • the second segment of the second data line may be disposed side by side with the second segment of the first data line and disposed in the same layer as the source/drain electrodes of the thin film transistor;
  • the first segment and the second segment of the second data line may be electrically connected to each other by a third electrical connection.
  • the second data line is also segmented based on the first data line segmentation setting.
  • the first data line includes a first segment disposed in the same layer as the source/drain electrodes and a second segment disposed in the same layer as the gate electrode, and the second data line includes a first segment disposed in the same layer as the gate electrode and The source/drain electrodes are in the same segment as the second segment.
  • the first segment of the second data line is disposed side by side with the first segment of the first data line, and the second segment of the second data line is disposed side by side with the second segment of the first data line.
  • the first segment of the first data line and the first segment of the second data line are layered, and the second segment of the first data line and the second segment of the second data line are layered.
  • any segments of the first data line and the second data line arranged side by side are always arranged in a staggered manner, thereby effectively preventing short circuits and crosstalk between the double data lines arranged side by side.
  • each of the first segments of the second data line may be provided with a gate insulating through the thin film transistor at both ends thereof along the extending direction of the second data line.
  • Each of the second segments of the second data line may be provided with a seventh via extending through the passivation layer at both ends thereof along the extending direction of the second data line;
  • the third electrical connector may electrically connect each of the first segment of the second data line and adjacent to the first segment through the sixth via and the seventh via The second section.
  • the third electrical connector passes each of the first segment of the second data line through the first segment of the second data line and the adjacent sixth via and seventh via of the second segment And the second segment adjacent to the first segment are electrically connected to each other, thereby forming a complete second data line.
  • the sixth via and the seventh via can be formed in the same patterning process, which facilitates simplification of the process steps.
  • a planarization layer may be disposed over the passivation layer in the thin film transistor, the sixth via hole and the seventh via hole respectively penetrate the planarization layer.
  • the first data line may include a plurality of segments arranged alternately, at least some of the segments being disposed in the same layer as a gate electrode of the thin film transistor; and a second data line The portions of the first data line in which the segments are arranged side by side are disposed in the same layer as the source/drain electrodes of the thin film transistor.
  • some segments of the first data line are formed when the gate electrode/gate line is formed, and corresponding portions of the second data lines disposed side by side with the segments are formed in a conventional manner, thereby implementing the first data line
  • the second data line is at least partially layered to prevent short circuit and crosstalk between the parallel data lines.
  • mutually adjacent segments of the first data line may be electrically connected to each other by electrical connectors, and the electrical connectors may include a first electrical connection formed by a conductive material forming the pixel electrodes Floor.
  • the first electrical connector, the second electrical connector, and the third electrical connector may be disposed in the same layer as the pixel electrode of each sub-pixel unit.
  • the first/second/three electrical connectors are disposed in the same layer as the pixel electrodes of each sub-pixel unit.
  • the first/second/third electrical connectors and the pixel electrodes can be simultaneously formed by the same patterning process, which is advantageous for controlling the number of patterning processes, thereby facilitating cost control.
  • the first electrical connection layer may be formed of ITO (Indium Tin Oxide).
  • the first electrical connection layer of each of the electrical connectors is composed of a conductive material ITO forming a pixel electrode. Therefore, the first electrical connection layer of each of the electrical connectors can be simultaneously formed in the patterning process of forming the pixel electrodes. Thereby, the patterning process in the existing manufacturing process will not be increased, and thus the cost will not be increased.
  • the first electrical connector, the second electrical connector, and the third electrical connector may further include a second electrical connection layer formed on the first electrical connection layer, and
  • the second electrical connection layer may comprise a metal.
  • the second electrical connection layer comprising a metal can improve the electrical conductivity of the electrical connector, facilitating electrical connection between adjacent segments of the first data line or the second data line.
  • the pattern of the first and second electrical connection layers of the electrical connector and the pattern of the pixel electrode may be formed in a single patterning process, and then the second electrical connection layer above the pixel electrode is removed to form a pixel electrode . Thereby, the patterning process in the existing manufacturing process will not be increased, and thus the cost will not be increased.
  • the second electrical connection layer may comprise a metal monolayer or a metal stack.
  • the second electrical connection layer is formed of a metal monolayer or a laminate of low resistivity, whereby the electrical conductivity of each of the electrical connectors can be improved. Thereby, a good electrical connection between the mutually adjacent segments of the first data line and the mutually adjacent segments of the second data line is facilitated.
  • the second electrical connection layer may be formed of a Mo monolayer or a Mo/Al/Mo laminate.
  • the second electrical connection layer when the second electrical connection layer is formed of a single layer or a laminate not containing Al, the second electrical connection layer over the pixel electrode region ITO may be removed by a dry etching process, thereby forming a pixel electrode . Further, according to this embodiment, when the second electrical connection layer is formed of a single layer or a laminate containing Al, the ITO may be annealed first, and then the second electrical connection above the pixel electrode region ITO may be removed by a wet etching process. A layer, thereby forming a pixel electrode.
  • the electrical connector may at least partially overlap the gate line.
  • the electrical connectors overlap the gate lines or are disposed across the gate lines, and the vias on both ends of the respective segments of the first data line and/or the second data line are disposed adjacent to the gate lines.
  • the segments of the first data line and/or the second data line may be disposed between the adjacent two gate lines, and the mutually adjacent segments may be electrically connected to each other by electrical connections across the gate lines. Connected to form a complete first data line and/or second data line.
  • the present disclosure provides a display panel comprising an array substrate as described above.
  • the present disclosure provides a display device comprising a display panel as described above.
  • the present disclosure provides a method of fabricating an array substrate including gate lines and data lines insulated from each other on a base substrate and intersecting to define a plurality of sub-pixel units, each sub-pixel unit Forming a thin film transistor and a pixel electrode therein,
  • the data line includes a first data line and a second data line disposed side by side between each two columns of adjacent sub-pixel units, wherein in each two columns of adjacent sub-pixel units, the odd-numbered sub-pixel units are connected to the first data line, And the even row of sub-pixel units are connected to the second data line, wherein the method comprises the following steps:
  • a pattern comprising an electrical connector is formed by a fourth patterning process, wherein the electrical connector electrically connects the second segment of the first data line to a first segment of the adjacent first data line.
  • the segment is such that the second segment of the first data line and the second segment of the second data line are layered, that is, the first data line and the second data line are at least partially layered.
  • the gate electrode including the thin film transistor and the gate line, the second segment of the first data line, and the a graphic of the first segment of the first data line;
  • a pattern including the source/drain electrodes of the thin film transistor and a continuous second data line may be formed.
  • a pattern including a first via, a second via, and a third via may be formed, wherein the first via is disposed in the first data Each of the first segments of the line is at both ends thereof along the extending direction of the first data line and penetrates a gate insulating layer and a passivation layer of the thin film transistor, the second via setting Each of the second segments of the first data line is at both ends thereof along the extending direction of the first data line and penetrates the gate insulating layer and the passivation layer, and a third via disposed over the source/drain electrodes of the thin film transistor and penetrating the passivation layer;
  • a pattern including a first electrical connection may be formed, wherein the first electrical connection passes through the first via, the second via, and the third via And electrically connecting the source/drain electrodes, each first segment of the first data line, and a second segment adjacent to the first segment.
  • the source/drain electrodes including the thin film transistor, the second segment of the second data line, and the first data may be formed The graph of the first segment of the line.
  • the source/drain electrodes including the thin film transistor, the continuous second data line, and the first segment of the first data line may be formed Graphics.
  • a pattern including a fourth via and a fifth via may be formed, wherein the fourth via is disposed at each of the first data lines
  • the first segment is at both ends thereof along the extending direction of the first data line and penetrates the passivation layer of the thin film transistor
  • the fifth via is disposed at each of the first data lines
  • the second segment is at both ends thereof along the extending direction of the first data line and penetrates the gate insulating layer and the passivation layer;
  • a pattern including a second electrical connection may be formed, wherein the second electrical connection electrically connects the first through the fourth via and the fifth via Each of the first segment of the data line and the second segment adjacent to the first segment.
  • the gate electrode including the thin film transistor and the gate line, the second segment of the first data line, and the A graph of the first segment of the second data.
  • a pattern including a sixth via and a seventh via may be formed, wherein the sixth via is disposed in each of the second data lines
  • the first segment is at both ends thereof along the extending direction of the second data line and penetrates the gate insulating layer and the passivation layer of the thin film transistor
  • the seventh via is disposed at the Each of the second segments of the two data lines is at both ends thereof along the extending direction of the second data line and penetrates the passivation layer;
  • a pattern including a third electrical connection may be formed, wherein the third electrical connection electrically connects the second through the sixth via and the seventh via Each of the first segment of the data line and the second segment adjacent to the first segment segment.
  • a pattern including the electrical connector and the pixel electrode of each sub-pixel unit may be formed.
  • the step of forming a pattern including the electrical connector and the pixel electrode of each sub-pixel unit may include:
  • first electrical connection layer on the substrate substrate completing the third patterning process, wherein the first electrical connection layer comprises a conductive material for forming the pixel electrode;
  • the photoresist that will form the regions of the pixel electrode and the electrical connector is stripped to form an electrical connector and the pixel electrode.
  • the step of forming a pattern including the electrical connector by the fourth patterning process may include:
  • first electrical connection layer comprises a conductive material for forming the pixel electrode
  • second electrical connection layer does not contain Al
  • Exposure is performed using a semi-transparent mask, leaving a photoresist that will form the area of the electrical connector, partially removing the photoresist that will form the area of the pixel electrode, and removing all of the photo-resistance of the remaining area Corrosion agent
  • Dry etching to remove the second electrical connection layer of a region where the pixel electrode is to be formed, thereby forming a pixel electrode composed of the first electrical connection layer;
  • the photoresist that will form the area of the electrical connector is stripped to form an electrical connection formed by the first electrical connection layer and the second electrical connection layer.
  • the step of forming a pattern including the electrical connector by the fourth patterning process may include:
  • first electrical connection layer includes a surface for forming the image a conductive material of the element electrode, and the second electrical connection layer comprises Al;
  • Exposure is performed using a semi-transparent mask, leaving a photoresist that will form the area of the electrical connector, partially removing the photoresist that will form the area of the pixel electrode, and removing all of the photo-resistance of the remaining area Corrosion agent
  • the photoresist that will form the area of the electrical connector is stripped to form an electrical connection formed by the first electrical connection layer and the second electrical connection layer.
  • the step of depositing the second electrical connection layer can include depositing a metal monolayer or a metal stack.
  • the display panel, the display device, and the method of fabricating the array substrate according to the present disclosure have the same or similar benefits as the array substrate described above, and are not described herein again.
  • the first data line and the adjacent second data line are disposed on different layers.
  • the DDS can be effectively prevented, thereby improving the product yield; the crosstalk between the double data lines arranged side by side can be significantly eliminated, thereby improving the display quality of the product; and the small pitch design between the double data lines can be realized and improved.
  • the aperture ratio and wiring density of the array substrate are disposed on different layers.
  • some segments of the first data line are disposed in the same layer as the gate electrode of the thin film transistor, and corresponding portions of the second data lines disposed side by side with the segments are disposed in the same layer as the source/drain electrodes of the thin film transistor, such that The segments of the first data line and the corresponding portions of the second data line are disposed on different layers, thereby achieving at least partial layering of the first data line and the second data line, thereby preventing parallel arrangement between the double data lines Short circuit and crosstalk.
  • the technical solution of the present disclosure does not increase the patterning process in the existing manufacturing process, and thus does not cause an increase in cost.
  • 1 is a schematic plan view of an array substrate of a conventional display panel
  • FIG. 2 is a schematic plan view of an array substrate according to a first embodiment of the present disclosure
  • FIG. 3a and 3b are schematic cross-sectional views of an array substrate according to a first embodiment of the present disclosure, wherein FIG. 3a is a schematic cross-sectional view of the array substrate along line AB of FIG. 2, and FIG. 3b is a schematic cross-sectional view of the array substrate A schematic cross-sectional view along the CD line of FIG. 2;
  • FIG. 4 is a schematic plan view of an array substrate in accordance with a second embodiment of the present disclosure.
  • FIG. 5a and 5b are schematic cross-sectional views of an array substrate according to a second embodiment of the present disclosure, wherein FIG. 5a is a schematic cross-sectional view of the array substrate along line AB of FIG. 4, and FIG. 5b is the array substrate A schematic cross-sectional view along the CD line of FIG. 4;
  • FIG. 6 is a schematic plan view of an array substrate according to a third embodiment of the present disclosure.
  • FIG. 7a, 7b, 7c, and 7d are schematic cross-sectional views of an array substrate according to a third embodiment of the present disclosure, wherein FIG. 7a is a schematic cross-sectional view of the array substrate taken along line AB of FIG. 7b is a schematic cross-sectional view of the array substrate along the GH line of FIG. 6, FIG. 7c is a schematic cross-sectional view of the array substrate along the CD line of FIG. 6, and FIG. 7d is the EF of the array substrate along FIG. a schematic cross-sectional view of the line;
  • 8a, 8b, 8c, and 8d are schematic cross-sectional views of an array substrate in respective fabrication steps in accordance with a fourth embodiment of the present disclosure
  • 9a, 9b, 9c, 9d, and 9e are schematic cross-sectional views of an array substrate in respective fabrication steps in accordance with a fifth embodiment of the present disclosure
  • 10a, 10b, 10c, 10d, 10e, 10f, and 10g are schematic cross-sectional views of the array substrate in each fabrication step according to a sixth embodiment of the present disclosure
  • 11a, 11b, and 11c are schematic cross-sectional views of an array substrate in respective fabrication steps in accordance with a seventh embodiment of the present disclosure.
  • FIGS. 2, 3a, and 3b are schematic plan view of the array substrate 1 according to the first embodiment
  • FIG. 3a is a schematic cross-sectional view of the array substrate 1 taken along line AB of FIG. 2
  • FIG. 3b is a CD line of the array substrate 1 taken along line 2 of FIG. Schematic cross-sectional view.
  • the array substrate 1 of the display panel includes gate lines 20 and data lines which are insulated from each other on the base substrate 10 and intersect to define a plurality of sub-pixel units 30.
  • a thin film transistor 40 and a pixel electrode 50 are formed in each sub-pixel unit 30.
  • the thin film transistor 40 includes a gate electrode 40a, a source electrode 40b, and a drain electrode 40c.
  • the data line includes a first data line 61 and a second data line 62 disposed side by side between each two columns of adjacent sub-pixel units 50. In each of the two adjacent sub-pixel units 30, the odd-line sub-pixel units 30 are connected to the first data line 61, and the even-numbered sub-pixel units are connected to the second data line 62.
  • the first data line 61 includes a plurality of first segments 611 and second segments 612 that are alternately disposed.
  • the first segment 611 is provided with a first via 701 at both ends, and the second segment 612 is respectively provided with a second via 702 at both ends.
  • the first electrical connector 801 electrically connects each first segment 611 of the first data line 61 and the adjacent second segment 612 to each other through the first via 701 and the second via 702.
  • a third via 703 is further disposed above the source electrode 40b of the thin film transistor 40.
  • the first electrical connector 801 simultaneously electrically connects the first segment 611 and the second segment 612 of the first data line 61 to the source electrode 40b of the thin film transistor 40 through the third via 703, thereby forming a complete first data.
  • the second data line 62 is disposed in the same layer as the source electrode 40b and the drain electrode 40c of the thin film transistor 40, and is electrically connected to the source electrode 40b.
  • Fig. 3a is a schematic cross-sectional view of the array substrate 1 taken along line A-B of Fig. 2.
  • the AB line starts from point A on the pixel electrode 50 of one sub-pixel unit 30, extends through a portion of the first segment 611 of the first data line 61, the first electrical connector 801, and the first data line 61.
  • Fig. 3b is a schematic cross-sectional view of the array substrate 1 taken along line C-D of Fig. 2.
  • the CD line starts from a point C on the pixel electrode 50 of one sub-pixel unit 30, extends through the second data line 62 and the second segment 612 of the first data line 61 in a direction perpendicular to the data line, and
  • the point D on the pixel electrode 50 of another sub-pixel unit 30 adjacent to the same line is the end point.
  • the first segment 611 and the second segment 612 of the first data line 61, the gate electrode 40a (not shown in FIG. 3a), and the gate line 20 are disposed on the base substrate 10.
  • the first segment 611 of the first data line 61 is provided with a first via 701 at both ends, and the first via 701 penetrates the gate insulating layer 42 and the passivation layer 44 of the thin film transistor 40.
  • the second segment 612 of the first data line 61 is provided with a second via 702 at both ends, and the second via 702 penetrates the gate insulating layer 42 and the passivation layer 44 of the thin film transistor 40.
  • the third via 703 is disposed over the source electrode 40b of the thin film transistor 40 and penetrates the passivation layer 44.
  • the first electrical connector 801 is disposed on the passivation layer 44 and passes the first segment 611, the adjacent second segment 612, and the source electrode through the first via 701, the second via 702, and the third via 703
  • the 40b are electrically connected to each other, thereby forming a complete first data line 61.
  • the second segment 612 of the first data line 61 is disposed under the gate insulating layer 42 and disposed in the same layer as the gate electrode 40a (not shown in FIG. 3b), and the second data line 62 is disposed on the gate.
  • the pole insulating layer 42 is disposed in the same layer as the source electrode 40b and the drain electrode 40c (not shown in Fig. 3b). Therefore, the second segment 612 of the first data line 61 is disposed in a layered manner with the second data line 62.
  • the first segment 611 of the first data line 61 is also layered with the second data line 62.
  • each of the first segment 611 and the second segment 612 of the first data line 61 is disposed in a layered manner with the second data line 62, whereby the DDS problem can be effectively solved. Even in the case where the spacing between the first data line 61 and the second data line 62 is small, the first data line and the second data line thus designed can effectively solve the DDS problem, so that the yield of the product is not negative. influences.
  • a dielectric layer such as a planarization layer may also be disposed over the passivation layer 44 in the thin film transistor 40.
  • the first via 701, the second The via 702 and the third via 703 also correspondingly penetrate the planarization layer.
  • FIGS. 4, 5a, and 5b are schematic plan view of the array substrate 2 according to the second embodiment
  • FIG. 5a is a schematic cross-sectional view of the array substrate 2 taken along line AB of FIG. 4
  • FIG. 5b is a CD line of the array substrate 2 taken along line 4 of FIG. Schematic cross-sectional view.
  • the second embodiment is different from the first embodiment in that the first segment of the first data line is disposed in the same layer as the source/drain electrodes of the thin film transistor, instead of being the same as the gate electrode of the thin film transistor as in the first embodiment. Layer settings.
  • the first data line 61 includes a plurality of first segments 613 and second segments 614 that are alternately disposed.
  • the first segment 613 is respectively provided with a fourth through hole 704 at both ends
  • the second segment 614 is respectively provided with a fifth through hole 705 at both ends.
  • the second electrical connector 802 electrically connects each first segment 613 of the first data line 61 and the adjacent second segment 614 to each other through the fourth via 704 and the fifth via 705, thereby forming a complete A data line 61. Since the first segment 613 is disposed in the same layer as the source electrode 40b and the drain electrode 40c of the thin film transistor 40, the third via hole 703 disposed above the source electrode 40b in the first embodiment can be omitted herein.
  • the second data line 62 is disposed in the same layer as the source electrode 40b and the drain electrode 40c of the thin film transistor 40, and is electrically connected to the source electrode 40b.
  • the first data line 61 and the second data line 62 are described in more detail with reference to FIGS. 5a and 5b.
  • the second segment 614 of the first data line 61, the gate electrode 40a (not shown in FIG. 5a), and the gate line 20 are disposed on the base substrate 10.
  • the first segment 613 of the first data line 61 and the source electrode 40b and the drain electrode 40c (not shown in FIG. 5a) of the thin film transistor 40 are disposed on the gate insulating layer 42.
  • the first segment 613 of the first data line 61 is provided with a fourth via 704 at both ends, and the fourth via 704 extends through the passivation layer 44 of the thin film transistor 40.
  • the second segment 614 of the first data line 61 is provided with a fifth via 705 at both ends, and the fifth via 705 penetrates the gate insulating layer 42 and the passivation layer 44 of the thin film transistor 40.
  • a second electrical connector 802 is disposed over the passivation layer 44 and electrically interconnects the first segment 613 and the adjacent second segment 614 through the fourth via 704 and the fifth via 705, thereby forming a complete The first data line 61.
  • the second segment 614 of the first data line 61 is disposed under the gate insulating layer 42 and disposed in the same layer as the gate electrode 40a (not shown in FIG. 5b), and the second data line 62 is disposed. It is disposed on the gate insulating layer 42 and in the same layer as the source electrode 40b and the drain electrode 40c (not shown in FIG. 5b). Therefore, the second segment 614 of the first data line 61 and the second data line 62 are layered.
  • the second segment 614 of the first data line 61 is disposed in a layered manner with the second data line 62, whereby the DDS problem can be effectively solved.
  • FIGS. 6, 7a, 7b, 7c, and 7d are schematic plan views of the array substrate 3 according to the third embodiment
  • FIG. 7a is a schematic cross-sectional view of the array substrate 3 taken along line AB of FIG. 6
  • FIG. 7b is a line of the array substrate 3 along the GH line of FIG.
  • FIG. 7c is a schematic cross-sectional view of the array substrate 3 taken along line CD of FIG. 6
  • FIG. 7d is a schematic cross-sectional view of the array substrate 3 taken along line EF of FIG.
  • the third embodiment is different from the second embodiment in that the second data line includes staggered segments, each segment being disposed in a staggered manner with a corresponding segment of the first data line.
  • the first data line 61 includes a plurality of first segments 613 and second segments 614 that are alternately disposed.
  • the first segment 613 is respectively provided with a fourth through hole 704 at both ends
  • the second segment 614 is respectively provided with a fifth through hole 705 at both ends.
  • the second electrical connector 802 electrically connects each first segment 613 of the first data line 61 and the adjacent second segment 614 to each other through the fourth via 704 and the fifth via 705, thereby forming a complete A data line 61.
  • the second data line 62 includes a plurality of first segments 621 and second segments 622 that are alternately disposed.
  • the first segment 621 is respectively provided with a sixth through hole 706 at both ends
  • the second segment 622 is respectively provided with a seventh through hole 707 at both ends.
  • the third electrical connector 803 electrically connects each first segment 621 of the second data line 62 and the adjacent second segment 622 to each other through the sixth via 706 and the seventh via 707, thereby forming a complete Two data lines 62.
  • the first data line 61 and the second data line 62 are described in more detail with reference to FIGS. 7a, 7b, 7c, and 7d.
  • the second segment 614 of the first data line 61, the gate electrode 40a (not shown in FIG. 7a), and the gate line 20 are disposed on the base substrate 10.
  • the first segment 613 of the first data line 61 and the source electrode 40b and the drain electrode 40c of the thin film transistor 40 (not shown in FIG. 7a) are disposed at On the gate insulating layer 42.
  • the fourth via 704 penetrates the passivation layer 44 and the fifth via 705 penetrates the gate insulating layer 42 and the passivation layer 44.
  • a second electrical connector 802 is disposed over the passivation layer 44 and electrically interconnects the first segment 613 and the adjacent second segment 614 through the fourth via 704 and the fifth via 705, thereby forming a complete The first data line 61.
  • Fig. 7b is a schematic cross-sectional view of the array substrate 3 taken along the line G-H of Fig. 6.
  • the GH line starts from the G point on the pixel electrode 50 of one sub-pixel unit 30, extends through a portion of the second segment 622 of the second data line 62, and the third electrical connector 803 and the second data line 62 A portion of the segment 621 is terminated with an H point on the pixel electrode 50 of another sub-pixel unit 30 adjacent to the same column.
  • the first segment 621 of the second data line 62, the gate electrode 40a (not shown in FIG. 7b), and the gate line 20 are disposed on the base substrate 10.
  • the second segment 622 of the second data line 62 and the source electrode 40b and the drain electrode 40c (not shown in FIG. 7b) of the thin film transistor 40 are disposed on the gate insulating layer 42.
  • the seventh via 707 penetrates the passivation layer 44 and the sixth via 706 penetrates the gate insulating layer 42 and the passivation layer 44.
  • the third electrical connector 803 is disposed on the passivation layer 44 and electrically connects the first segment 621 and the adjacent second segment 622 to each other through the sixth via 706 and the seventh via 707, thereby forming a complete The second data line 62.
  • the second segment 614 of the first data line 61 is disposed under the gate insulating layer 42 and is disposed in the same layer as the gate electrode 40a (not shown in FIG. 7c), and the second of the second data line 62.
  • the segment 622 is disposed on the gate insulating layer 42 and disposed in the same layer as the source electrode 40b and the drain electrode 40c (not shown in Fig. 7c). Therefore, the second segment 614 of the first data line 61 and the second segment 622 of the second data line 62 are layered.
  • Fig. 7d is a schematic cross-sectional view of the array substrate 3 taken along line E-F of Fig. 6.
  • the EF line starts from the E point on the pixel electrode 50 of one sub-pixel unit 30, and extends through the first segment 612 of the second data line 62 and the first of the first data line 61 in a direction perpendicular to the data line.
  • the segment 613 is terminated with an F point on the pixel electrode 50 of another sub-pixel unit 30 adjacent to the same row.
  • the first segment 621 of the second data line 62 is disposed under the gate insulating layer 42 and disposed in the same layer as the gate electrode 40a (not shown in FIG.
  • the segment 613 is disposed on the gate insulating layer 42 and disposed in the same layer as the source electrode 40b and the drain electrode 40c (not shown in Fig. 7d). Therefore, the first segment 613 of the first data line 61 and the first segment 621 of the second data line 62 are layered.
  • the first segment 613 of the first data line 61 and the first segment 621 of the second data line 62 are layered, and the second segment 614 of the first data line 61
  • the second segment 622 of the second data line 62 is layered. That is, any two of the first data lines 61 and the second data lines 62 are arranged side by side in a staggered arrangement, whereby the DDS problem can be effectively solved. Even in the case where the spacing between the first data line 61 and the second data line 62 is small, the first data line and the second data line thus designed can effectively solve the DDS problem, so that the yield of the product is not negative. influences.
  • FIGS. 8a, 8b, 8c, and 8d are schematic cross-sectional views of the array substrate in each fabrication step according to the fourth embodiment.
  • FIG. 6 the method for fabricating the array substrate of the present disclosure will be described by taking the array substrate 3 in the third embodiment shown in FIG. 6 and FIGS. 7a-7d as an example.
  • FIGS. 7a-7d the respective cross-sectional views of Figs. 8a-8d correspond to the structures along the line A-B in Fig. 6. That is, Figures 8a-8d only show the various fabrication steps of the first data line 61.
  • a second segment 614 of the first data line 61 (FIG. 8a), and a second data line 62 are formed on the base substrate 10 by a first patterning process.
  • a gate insulating layer 42 is deposited on the base substrate 10 on which the foregoing steps are completed, and the source electrode 40b and the drain electrode 40c including the thin film transistor 40 and the first segment 613 of the first data line 61 are formed by a second patterning process. (Fig. 8b) and the pattern of the second segment 622 of the second data line 62 (Fig. 7c).
  • a passivation layer 44 is deposited on the base substrate 10 completing the foregoing steps, and the fourth via hole 704 and the fifth via hole 705 (FIGS. 8c and 7a) and the sixth via hole 706 are formed by a third patterning process. And the pattern of the seventh via 707 (Fig. 7b).
  • the fourth via 704 is disposed at both ends of the first segment 613 of the first data line 61 and penetrates the passivation layer 44 to expose a portion of the first segment 613.
  • a fifth via 705 is disposed at both ends of the second segment 614 of the first data line 61 and penetrates the gate insulating layer 42 and the passivation layer 44 to expose a portion of the second segment 614.
  • the sixth via 706 is disposed at both ends of the first segment 621 of the second data line 62 and penetrates the gate insulating layer 42 and the passivation layer 44 to expose a portion of the first segment 621.
  • a seventh via 707 is disposed at both ends of the second segment 622 of the second data line 62 and extends through the passivation layer 44 to expose a portion of the second segment 622.
  • a pattern including a second electrical connector 802 (Fig. 8d) and a third electrical connector 803 (Fig. 7b) is formed.
  • the second electrical connector 802 electrically connects each first segment 613 of the first data line 61 and the adjacent second segment 614 to each other through the fourth via 704 and the fifth via 705, thereby forming a complete A data line 61.
  • the third electrical connector 803 electrically connects each first segment 621 of the second data line 62 and the adjacent second segment 622 to each other through the sixth via 706 and the seventh via 707, thereby forming a complete Two data lines 62.
  • the fabrication of the first data line 61 and the second data line 62 is completed, and the array substrate 3 of FIGS. 6 and 7a-7d is obtained.
  • the pixel electrodes 50 in each sub-pixel unit 30 are simultaneously formed. Graphics.
  • the gate electrode 40a including the thin film transistor 40 and the gate line 20, the first segment 611 of the first data line 61, and the second section of the first data line 61 are formed on the base substrate 10 by the first patterning process.
  • the graph of segment 612 (Fig. 3a).
  • a gate insulating layer 42 is deposited on the base substrate 10 on which the foregoing steps are completed, and a pattern including the source electrode 40b and the drain electrode 40c of the thin film transistor 40 and the second data line 62 is formed by a second patterning process (FIG. 3b) .
  • a passivation layer 44 is deposited on the base substrate 10 on which the foregoing steps are completed, and a pattern including the first via 701, the second via 703, and the third via 703 is formed by a third patterning process (FIG. 3a).
  • the first via 701 is disposed at both ends of the first segment 611 of the first data line 61 and penetrates the gate insulating layer 42 and the passivation layer 44 to expose a portion of the first segment 611.
  • the second via 702 is disposed at both ends of the second segment 612 of the first data line 61 and penetrates the gate insulating layer 42 and the passivation layer 44 to expose a portion of the first segment 612.
  • the third via 703 is disposed over the source electrode 40b of the thin film transistor 40 and penetrates the passivation layer 44 to expose a portion of the source electrode 40b.
  • a pattern including the first electrical connector 801 is formed by a fourth patterning process (Fig. 3a).
  • the first electrical connector 801 electrically connects the first segment 611, the adjacent second segment 612, and the source electrode 40b to each other through the first via 701, the second via 702, and the third via 703, thereby forming a complete The first data line 61.
  • the first data line 61 and the second data line 62 are completed. Go to the array substrate 1 of Figures 2, 3a-3b.
  • a pattern including the gate electrode 40a of the thin film transistor 40 and the gate line 20 and the second segment 614 of the first data line 61 is formed on the base substrate 10 by the first patterning process (FIG. 5a).
  • a gate insulating layer 42 is deposited on the base substrate 10 on which the foregoing steps are completed, and the source electrode 40b and the drain electrode 40c including the thin film transistor 40 and the first segment 613 of the first data line 61 are formed by a second patterning process. And a pattern of the second data line 62 (Fig. 5b).
  • a passivation layer 44 is deposited on the base substrate 10 on which the foregoing steps are completed, and a pattern including the fourth via 704 and the fifth via 705 is formed by a third patterning process (FIG. 5a).
  • the fourth via 704 is disposed at both ends of the first segment 613 of the first data line 61 and penetrates the passivation layer 44 to expose a portion of the first segment 613.
  • a fifth via 705 is disposed at both ends of the second segment 614 of the first data line 61 and penetrates the gate insulating layer 42 and the passivation layer 44 to expose a portion of the first segment 614.
  • a pattern including the second electrical connection member 802 is formed by a fourth patterning process (Fig. 5a).
  • the second electrical connector 802 electrically connects the first segment 613 of the first data line 61 and the adjacent second segment 614 to each other through the fourth via 704 and the fifth via 705, thereby forming a complete first data. Line 61.
  • the fabrication of the first data line 61 and the second data line 62 is completed, and the array substrate 2 of FIGS. 4 and 5a-5b is obtained.
  • FIGS. 9a-9e are schematic cross-sectional views of an array substrate according to a fifth embodiment at each fabrication step.
  • the fourth patterning process shown in FIG. 8d is described in detail in the fifth embodiment.
  • a pattern including the electrical connection and the pixel electrode of each sub-pixel unit is formed, and the electrical connection and the pixel electrode are composed of the same material.
  • the steps of forming the second electrical connector 802 and the pixel electrode 50 in the fourth patterning process are described by taking the embodiment shown in FIGS. 6 and 7a as an example.
  • the first electrical connection layer 8021 may be formed of a conductive material for forming the pixel electrode 50.
  • the electrically conductive material may be ITO.
  • the conductive material may also be other transparent conductive oxide such as IZO (indium zinc oxide), IGZO (indium gallium zinc oxide), InGaSnO (indium gallium oxide).
  • the pixel electrode 50 can also be formed of other suitable conductive materials.
  • a photoresist 90 is applied on the base substrate 10.
  • the exposure process is performed using the mask 91.
  • the mask 91 includes a light transmitting region 911 and an opaque region 912.
  • the opaque region 912 corresponds to a region on the base substrate 10 where the pixel electrode 50 and the second electrical connector 802 are to be formed, and the light-transmitting region 911 corresponds to the remaining region on the base substrate 10.
  • the photoresist 90 forming the regions of the pixel electrode 50 and the second electrical connector 802 is retained, and the photoresist 90 of the remaining regions is removed to expose the first electrical connection layer 8021, As shown in Figure 9c.
  • the first electrical connection layer 8021 is removed by etching.
  • the photoresist 90 that will form the regions of the pixel electrode 50 and the second electrical connector 802 is stripped, thereby forming the second electrical connector 802 and the pixel electrode 50.
  • the second electrical connector 802 and the pixel electrode 50 composed of the first electrical connection layer 8021 are formed.
  • the first electrical connection layer 8021 is formed of ITO.
  • the second electrical connection 802 is simultaneously formed. Therefore, the patterning process in the existing manufacturing process will not be increased, and thus the cost will not be increased.
  • FIGS. 10a, 10b, 10c, 10d, 10e, 10f, and 10g are schematic cross-sectional views of the array substrate according to the sixth embodiment at each fabrication step.
  • the sixth embodiment is different from the fifth embodiment in that the electrical connector further includes a metal layer in addition to the same material as the pixel electrode. That is, the electrical connector includes a stack of a first electrical connection layer and a second electrical connection layer, wherein the first electrical connection layer is ITO and the second electrical connection layer is metal.
  • the steps of forming the second electrical connector 802 and the pixel electrode 50 in the fourth patterning process are still described by taking the embodiment shown in FIGS. 6 and 7a as an example.
  • a first electrical connection layer 8021 and a second electrical connection layer 8022 are sequentially deposited.
  • the electrical connection layer 8021 may be formed of a conductive material for forming the pixel electrode 50.
  • the conductive material may be ITO (Indium Tin Oxide).
  • the second electrical connection layer 8022 can include a metal.
  • a photoresist 92 is coated on the base substrate 10.
  • the exposure process is performed using the mask 93.
  • the reticle 93 is a semi-transparent reticle such as a half-tone mask and a gray-tone mask.
  • the mask plate 93 includes a light transmitting region 931, a partially light transmitting region 932, and an opaque region 933.
  • the opaque region 933 corresponds to a region on the base substrate 10 where the second electrical connector 802 is to be formed
  • the partial light-transmitting region 932 corresponds to a region on the base substrate 10 where the pixel electrode 50 is to be formed
  • the light-transmitting region 931 corresponds to The remaining area on the base substrate 10.
  • the photoresist 92 forming the region of the second electrical connection 802 is completely retained, the photoresist 92 portion of the region forming the pixel electrode 50 is partially retained, and The remaining area of photoresist 92 is completely removed. In the remaining regions, the second electrical connection layer 8022 is exposed as the photoresist 92 is removed.
  • the second electrical connection layer 8022 is removed by dry etching to expose the first electrical connection layer 8021, and the first electrical connection layer 8021 is removed by etching.
  • the photoresist 92 that will form the region of the pixel electrode 50 is removed by ashing, thereby exposing the second electrical connection layer 8022. During this ashing process, the photoresist 92 that forms the area of the second electrical connection 802 is thinned.
  • the second electrical connection layer 8022 of the region where the pixel electrode 50 is to be formed is removed by dry etching, leaving the first electrical connection layer 8021 to form the pixel electrode 50.
  • the photoresist 92 of the region where the second electrical connection member 802 is to be formed is peeled off, thereby forming a second electrical connection composed of the first electrical connection layer 8021 and the second electrical connection layer 8022.
  • the pixel electrode 50 composed of the first electrical connection layer 8021 is formed, and the second electrical connection member 802 composed of the first electrical connection layer 8021 and the second electrical connection layer 8022 is formed.
  • the first electrical connection layer 8021 may be formed of ITO.
  • the second electrical connection layer 8022 may be formed of a metal such as Mo, Cu, Mg, Ca, Cr, W, Ti, Ta, or the like.
  • the second electrical connection member 802 is composed of a laminate of the first electrical connection layer 8021 and the second electrical connection layer 8022, a halftone mask and a gray tone mask are employed in the exposure step.
  • the second electrical connection layer 8022 of the region where the pixel electrode 50 is to be formed is removed by dry etching. Therefore, the method of this embodiment is particularly applicable to the case where the second electrical connection layer 8022 of the second electrical connector 802 does not contain Al.
  • FIGS. 11a, 11b, and 11c are schematic cross-sectional views of the array substrate in each fabrication step according to the seventh embodiment.
  • the seventh embodiment is different from the sixth embodiment in that the second electrical connection layer 8022 of the second electrical connector 802 comprises Al.
  • the steps of forming the second electrical connector 802 and the pixel electrode 50 in the fourth patterning process are still described by taking the embodiment shown in FIGS. 6 and 7a as an example.
  • the second electrical connection layer 8022 includes the metal Al
  • the second electricity which will form the region where the pixel electrode 50 is to be formed is preferably removed by wet etching.
  • Connection layer 8022 That is, the seventh embodiment is different from the sixth embodiment in the step of removing the Al-containing second electrical connection layer 8022 which will form the region of the pixel electrode 50.
  • the first electrical connection layer 8021 in the base substrate 10 shown in Fig. 10e is annealed to improve the crystal quality of the conductive material such as ITO, thereby improving the etching resistance thereof.
  • the second electrical connection layer 8022 of the region where the pixel electrode 50 is to be formed is removed by wet etching.
  • the ITO of the first electrical connection layer 8021 is resistant to the etching of the etching liquid used in the wet etching due to the annealing treatment in advance. This is advantageous for ensuring the performance of the subsequently formed pixel electrode 50.
  • the photoresist 92 of the region where the second electrical connection member 802 is to be formed is peeled off, thereby forming a second electrical connection composed of the first electrical connection layer 8021 and the second electrical connection layer 8022.
  • the pixel electrode 50 composed of the first electrical connection layer 8021 is formed, and the second electrical connection member 802 composed of the first electrical connection layer 8021 and the second electrical connection layer 8022 is formed.
  • the first electrical connection layer 8021 may be formed of ITO.
  • the second electrical connection layer 8022 includes Al.
  • the first electrical connection layer 8021 may not be annealed in advance, but by selecting an appropriate etching solution and etching time, The adverse effect of the etching solution on the ITO of the first electrical connection layer 8021 is minimized.
  • the second electrical connection layer 8022 preferably includes a metal stack. That is, the second electrical connection layer 8022 can include a metal monolayer or laminate of low resistivity to increase the conductivity of the second electrical connector 802. Thereby, a good electrical connection between the first segment 613 and the second segment 614 of the first data line 61 is facilitated.
  • the second electrical connection layer 8022 can comprise a Mo single layer or a Mo/Al/Mo stack.
  • the second electrical connection layer may comprise two, four or more layers of metal.
  • the electrical connector of the present disclosure is described by taking the second electrical connector 802 as an example. It should be noted that the above description applies equally to the first electrical connector 801 and the third electrical connector 803.
  • an eighth embodiment of the present disclosure provides a display panel.
  • the display panel includes the array substrate described in the above embodiments of the present disclosure.
  • the display panel also includes other indispensable components, which are known to those of ordinary skill in the art, and are not described herein, and should not be construed as limiting the disclosure.
  • the eighth embodiment also provides a display device.
  • the display device includes the display panel described above.
  • the display device can be any product or component having a display function, such as a cell phone, a tablet, a television, a display, a notebook computer, a digital photo frame, and a navigator.
  • a portion of the second data line is disposed in the same layer as the source/drain electrodes, and a corresponding portion of the first data line disposed side by side is disposed in the same layer as the gate electrode, thereby implementing the first data line and the first
  • the two data lines are at least partially layered to reduce or eliminate DDS.
  • the present disclosure does not limit the layer in which the first data line and the second data line portion are disposed in the wrong layer.
  • the corresponding portion of the first data line may also be disposed in other conductive layers in the array substrate, and the conductive layer may be in the array substrate.
  • the existing conductive layer may also be an intentionally added additional conductive layer.
  • the vias of the segments of the data line are disposed adjacent to the gate lines of the thin film transistor, and the electrical connectors cross the gate lines to electrically connect the adjacent segments to each other to form a complete first data line and/or Or the second data line.
  • the present disclosure does not limit the position of the electrical connectors and the locations of the vias of the segments.
  • the segments of the first data line and/or the second data line may be disposed across the gate line and the electrical connectors may be disposed between adjacent two gate lines as long as the segments are electrically connected to each other by electrical connectors Form a complete data line.
  • the scope of protection of the disclosure is defined by the appended claims.

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Abstract

一种阵列基板（1）、显示面板、显示装置以及阵列基板（1）的制作方法。阵列基板（1）包括在衬底基板（10）上相互绝缘并且交叉以限定多个亚像素单元（30）的栅线（20）和数据线，每个亚像素单元（30）内形成有薄膜晶体管（40）和像素电极（50），数据线包括并排设置在每两列相邻亚像素单元（30）之间的第一数据线（61）和第二数据线（62），其中在每两列相邻的亚像素单元（30）中，奇数行亚像素单元（30）连接第一数据线（61），且偶数行亚像素单元（30）连接第二数据线（62），其中在每两个相邻亚像素单元（30）之间，至少部分的第一数据线（61）和相邻的第二数据线（62）不同层设置。因此，解决了双数据线（61，62）间短路的问题。

Description

阵列基板、显示面板、显示装置以及阵列基板的制作方法 技术领域
本公开涉及显示技术领域，具体地涉及一种阵列基板、显示面板、显示装置以及阵列基板的制作方法。
背景技术
目前在各种薄膜晶体管-液晶显示装置(thin film transistor-liquid crystal display TFT-LCD)产品中，数据线需要采用双数据线设计以提高信号输出频率。如图1所示，液晶显示装置的显示面板包括阵列基板1′。阵列基板1′包括在衬底基板(未图示)上相互交叉并且限定多个亚像素单元30′的栅线20′和数据线。每个亚像素单元30′内形成有薄膜晶体管40′和像素电极50′。薄膜晶体管40′包括栅电极40a′、源电极40b′和漏电极40c′。数据线包括并排设置在每两列相邻亚像素单元50′之间的第一数据线61′和第二数据线62′。如所示，第一数据线61′和第二数据线62′与薄膜晶体管40′的源电极40b′和漏电极40c′同层设置。并排设置的第一数据线61′和第二数据线62′之间容易出现双数据线间短路(DDS)。特别是当第一数据线61′和第二数据线62′之间的间距过小时，DDS问题更加严重，这会导致产品良率急剧下降。
因此，本领域中存在对防止DDS的显示面板的需求。
发明内容
本公开的目的在于减轻或解决前文所提到的问题的一个或多个。具体而言，本公开的阵列基板、显示面板、显示装置以及阵列基板的制作方法将至少部分的第一数据线和相邻的第二数据线设置在不同层上，在不增加图案化工艺的情况下解决了DDS问题。
在第一方面，提供了一种阵列基板，其包括在衬底基板上相互绝缘并且交叉以限定多个亚像素单元的栅线和数据线，每个亚像素单元内形成有薄膜晶体管和像素电极，所述数据线包括并排设置在每两列相邻亚像素单元之间的第一数据线和第二数据线，其中在每两列相邻亚像素单元中，奇数行亚像素单元连接第一数据线，且偶数行亚像素单元连接第二数据线，其中在每两个相邻亚像素单元之间，至少部分 的所述第一数据线和相邻的所述第二数据线不同层设置。
根据此实施例，至少部分的第一数据线和相邻的第二数据线设置在不同层上。藉此，可以有效地防止DDS，从而提高产品良率；可以显著地消除并排设置的双数据线之间的串扰，从而改善产品显示质量；并且可以实现双数据线之间的小间距设计，提高阵列基板的开口率和布线密度。
在优选实施例中，所述第一数据线可以包括交替设置的多个第一节段和第二节段，每个所述第一节段和每个所述第二节段与所述薄膜晶体管的栅电极同层设置，并且每个所述第一节段和毗邻的第二节段通过第一电连接件相互电连接；以及
所述第二数据线与所述薄膜晶体管的源/漏电极同层设置。
根据此实施例，第一数据线分段设置，第一数据线的各个第一节段和第二节段与栅电极同层设置，并且每个第一节段和毗邻的第二节段之间通过第一电连接件相互电连接。第二数据线为常规数据线，即，与源/漏电极同层设置并且连续的数据线。藉此，第一数据线的各个第一节段和第二节段与第二数据线设置在不同层上，从而有效地防止并排设置的双数据线之间的短路和串扰。
在优选实施例中，所述第一数据线的每个所述第一节段在其沿所述第一数据线的延伸方向的两个端部可以设置有贯穿所述薄膜晶体管的栅极绝缘层和钝化层的第一过孔；
所述第一数据线的每个所述第二节段在其沿所述第一数据线的延伸方向的两个端部可以设置有贯穿所述栅极绝缘层和所述钝化层的第二过孔；
所述薄膜晶体管的源/漏电极上方可以设置有贯穿所述钝化层的第三过孔；以及
所述第一电连接件可以通过所述第一过孔、所述第二过孔和所述第三过孔，电连接所述源/漏电极、所述第一数据线的每个第一节段以及与所述第一节段毗邻的第二节段。
根据此实施例，第一电连接件通过第一数据线的第一节段和第二节段的毗邻的第一过孔和第二过孔以及相应的源/漏电极上方的第三过孔，将第一数据线的第一节段和毗邻的第二节段同时电连接到相应薄膜晶体管的源/漏电极，由此形成完整的第一数据线。第一过孔、第二 过孔和第三过孔可以在同一图案化工艺中形成，有利于简化工艺步骤。备选地，薄膜晶体管中钝化层上方还可以设置有平坦化层。这种情况下，第一过孔、第二过孔和第三过孔相应地还贯穿所述平坦化层。
在优选实施例中，所述第一数据线可以包括交替设置的多个第一节段和第二节段，所述第一节段与所述薄膜晶体管的源/漏电极同层设置，所述第二节段与所述薄膜晶体管的栅电极同层设置，并且每个所述第一节段和毗邻的第二节段通过第二电连接件相互电连接。
根据此实施例，第一数据线的第一节段和第二节段交替设置，第一节段与源/漏电极同层设置，并且第二节段与栅电极同层设置。藉此，第一数据线的第一节段和第二节段错层设置，由此有利于实现第一数据线和第二数据线至少部分错层设置，进而防止并排设置的双数据线之间的短路和串扰。
在优选实施例中，所述第二数据线可以与所述薄膜晶体管的源/漏电极同层设置。
根据此实施例，第一数据线的第一节段和第二节段交替设置，第一节段与源/漏电极同层，而第二节段与栅电极同层设置。第二数据线与源/漏电极同层设置。藉此，第一数据线的第二节段和第二数据线设置在不同层上，从而防止并排设置的双数据线之间的短路和串扰。
在优选实施例中，所述第一数据线的每个所述第一节段在其沿所述第一数据线的延伸方向的两个端部可以设置有贯穿所述薄膜晶体管的钝化层的第四过孔；
所述第一数据线的每个所述第二节段在其沿所述第一数据线的延伸方向的两个端部可以设置有贯穿所述栅极绝缘层和所述钝化层的第五过孔；以及
所述第二电连接件可以通过所述第四过孔和所述第五过孔，电连接所述第一数据线的每个所述第一节段和与所述第一节段毗邻的第二节段。
根据此实施例，第二电连接件通过第一节段和第二节段的毗邻的第四过孔和第五过孔，将第一数据线的每个第一节段和毗邻的第二节段相互电连接，由此形成完整的第一数据线。第四过孔和第五过孔可以在同一图案化工艺中形成，有利于简化工艺步骤。在该实施例中，由于第一数据线的第一节段与薄膜晶体管的源/漏电极同层设置，第二 电连接件通过第一数据线的第一节段上的第四过孔和第一数据的第二节段上的第五过孔，可以形成完整的第一数据线。与上述包括第三过孔的实施例相比，该技术方案中无需形成薄膜晶体管的源/漏电极上方的过孔，即，过孔数目减少。备选地，当薄膜晶体管中钝化层上方还可以设置有平坦化层时，第四过孔和第五过孔相应地还贯穿所述平坦化层。
在优选实施例中，所述第二数据线可以包括交替设置的多个第一节段和第二节段；
所述第二数据线的所述第一节段可以与所述第一数据线的所述第一节段并排设置，并且与所述薄膜晶体管的栅电极同层设置；
所述第二数据线的所述第二节段可以与所述第一数据线的所述第二节段并排设置，并且与所述薄膜晶体管的源/漏电极同层设置；以及
所述第二数据线的所述第一节段和第二节段可以通过第三电连接件相互电连接。
根据此实施例，在第一数据线分段设置的基础上，第二数据线也分段设置。第一数据线包括与源/漏电极同层设置的第一节段和与栅电极同层设置的第二节段，并且第二数据线包括与栅电极同层设置的第一节段和与源/漏电极同层设置的第二节段。第二数据线的第一节段与第一数据线的第一节段并排设置，并且第二数据线的第二节段与第一数据线的第二节段并排设置。因此，第一数据线的第一节段与第二数据线的第一节段错层设置，并且第一数据线的第二节段与第二数据线的第二节段错层设置。藉此，第一数据线和第二数据线的并排设置的任何节段总是错层设置，从而有效地防止并排设置的双数据线之间的短路和串扰。
在优选实施例中，所述第二数据线的每个所述第一节段在其沿所述第二数据线的延伸方向的两个端部可以设置有贯穿所述薄膜晶体管的栅极绝缘层和钝化层的第六过孔；
所述第二数据线的每个所述第二节段在其沿所述第二数据线的延伸方向的两个端部可以设置有贯穿所述钝化层的第七过孔；以及
所述第三电连接件可以通过所述第六过孔和所述第七过孔，电连接所述第二数据线的每个所述第一节段和与所述第一节段毗邻的第二节段。
根据此实施例，第三电连接件通过第二数据线的第一节段和第二节段的毗邻的第六过孔和第七过孔，将第二数据线的每个第一节段和与该第一节段毗邻的第二节段相互电连接，由此形成完整的第二数据线。第六过孔和第七过孔可以在同一图案化工艺中形成，有利于简化工艺步骤。备选地，当薄膜晶体管中钝化层上方还可以设置有平坦化层时，第六过孔和第七过孔相应地还贯穿所述平坦化层。
在优选实施例中，所述第一数据线可以包括交替设置的多个节段，至少一些所述节段与所述薄膜晶体管的栅电极同层设置；以及所述第二数据线的与所述第一数据线的所述节段并排设置的部分与所述薄膜晶体管的源/漏电极同层设置。
根据此实施例，在形成栅电极/栅线时形成第一数据线的一些节段，并且按照常规方式形成与这些节段并排设置的第二数据线的相应部分，由此实现第一数据线和第二数据线至少部分错层设置，进而防止并排设置的双数据线之间的短路和串扰。
在优选实施例中，所述第一数据线的相互毗邻的节段可以通过电连接件相互电连接，且所述电连接件可以包括由形成所述像素电极的导电材料构成的第一电连接层。在优选实施例中，上述第一电连接件、第二电连接件和第三电连接件可以与每个亚像素单元的像素电极同层设置。
根据此实施例，第一/第二/三电连接件与每个亚像素单元的像素电极同层设置。藉此，通过同一图案化工艺即可同时形成第一/第二/第三电连接件和像素电极，这有利于控制图案化工艺的数目，进而有利于控制成本。
在优选实施例中，所述第一电连接层可以由ITO(氧化铟锡)形成。
根据此实施例，各电连接件的第一电连接层由形成像素电极的导电材料ITO构成。因此，可以在形成像素电极的图案化工艺中，同时形成各电连接件的第一电连接层。藉此，将不会增加已有制作工艺中的图案化工艺，因而不会导致成本增加。
在优选实施例中，所述第一电连接件、所述第二电连接件和所述第三电连接件还可以包括形成于所述第一电连接层上的第二电连接层，以及
所述第二电连接层可以包括金属。
根据此实施例，包括金属的第二电连接层可以提高电连接件的导电性，有利于实现第一数据线或第二数据线的各相邻节段之间的电连接。此外，电连接件的第一电连接层和第二电连接层的图形以及像素电极的图形可以在一次图案化工艺中形成，随后像素电极上方的第二电连接层被移除以形成像素电极。藉此，将不会增加已有制作工艺中的图案化工艺，因而不会导致成本增加。
在优选实施例中，所述第二电连接层可以包括金属单层或金属叠层。
根据此实施例，第二电连接层由低电阻率的金属单层或叠层形成，由此可以提高各电连接件的导电性。藉此，有利于实现第一数据线的相互毗邻的各节段之间以及第二数据线的相互毗邻的各节段之间的良好电连接。
在优选实施例中，所述第二电连接层可以由Mo单层或Mo/Al/Mo叠层形成。
根据此实施例，当第二电连接层由不含Al的单层或叠层形成时，可以采用干法刻蚀工艺移除像素电极区域ITO上方的第二电连接层，由此形成像素电极。此外，根据此实施例，当第二电连接层由含Al的单层或叠层形成时，可以先对ITO退火，然后采用湿法刻蚀工艺移除像素电极区域ITO上方的第二电连接层，由此形成像素电极。
在优选实施例中，所述电连接件可以至少部分与所述栅线交叠。
根据此实施例，电连接件与栅线交叠或者跨过栅线设置，并且第一数据线和/或第二数据线的各个节段两个端部上的过孔靠近栅线设置。藉此，第一数据线和/或第二数据线的各节段可以设置在相邻的两条栅线之间，并且相互毗邻的节段可以通过跨过栅线的电连接件而相互电连接，从而形成完整的第一数据线和/或第二数据线。
在第二方面，本公开提供了一种显示面板，其包括如上文所述的阵列基板。
在第三方面，本公开提供了一种显示装置，其包括如上文所述的显示面板。
在第四方面，本公开提供了一种阵列基板的制作方法，所述阵列基板包括在衬底基板上相互绝缘并且交叉以限定多个亚像素单元的栅线和数据线，每个亚像素单元内形成有薄膜晶体管和像素电极，所述 数据线包括并排设置在每两列相邻亚像素单元之间的第一数据线和第二数据线，其中在每两列相邻亚像素单元中，奇数行亚像素单元连接第一数据线，且偶数行亚像素单元连接第二数据线，其中所述方法包括下述步骤：
通过第一图案化工艺，在衬底基板上形成包括所述薄膜晶体管的栅电极和栅线以及所述第一数据线的第二节段的图形；
通过第二图案化工艺形成包括所述薄膜晶体管的源/漏电极和所述第二数据线的第二节段的图形，其中所述第二数据线的所述第二节段与所述第一数据线的所述第二节段并排设置；
通过第三图案化工艺形成包括所述第一数据线的所述第二节段和所述第二数据线的所述第二节段上方的过孔的图形；以及
通过第四图案化工艺形成包括电连接件的图形，其中电连接件将所述第一数据线的所述第二节段电连接到毗邻的所述第一数据线的第一节段。
在第一图案化工艺形成与栅电极同层设置的第一数据线的第二节段，并且在第二图案化工艺中形成与源/漏电极同层设置的第二数据线的第二节段，使得第一数据线的第二节段与第二数据线的第二节段错层设置，即，第一数据线和第二数据线至少部分错层设置。具体技术效果见上文所述的阵列基板的相应实施例。
在优选实施例中，在所述第一图案化工艺中，可以形成包括所述薄膜晶体管的所述栅电极和所述栅线、所述第一数据线的所述第二节段以及所述第一数据线的所述第一节段的图形；以及
在所述第二图案化工艺中，可以形成包括所述薄膜晶体管的所述源/漏电极以及连续第二数据线的图形。
在优选实施例中，在所述第三图案化工艺中，可以形成包括第一过孔、第二过孔和第三过孔的图形，其中所述第一过孔设置在所述第一数据线的每个所述第一节段在其沿所述第一数据线的延伸方向的两个端部并且贯穿所述薄膜晶体管的栅极绝缘层和钝化层，所述第二过孔设置在所述第一数据线的每个所述第二节段在其沿所述第一数据线的延伸方向的两个端部并且贯穿所述栅极绝缘层和所述钝化层，并且所述第三过孔设置在所述薄膜晶体管的源/漏电极上方并且贯穿所述钝化层；以及
在所述第四图案化工艺中，可以形成包括第一电连接件的图形，其中所述第一电连接件通过所述第一过孔、所述第二过孔以及所述第三过孔，电连接所述源/漏电极、所述第一数据线的每个第一节段以及与所述第一节段毗邻的第二节段。
在优选实施例中，在所述第二图案化工艺中，可以形成包括所述薄膜晶体管的所述源/漏电极、所述第二数据线的所述第二节段以及所述第一数据线的第一节段的图形。
在优选实施例中，在所述第二图案化工艺中，可以形成包括所述薄膜晶体管的所述源/漏电极、连续第二数据线以及所述第一数据线的所述第一节段的图形。
在优选实施例中，在所述第三图案化工艺中，可以形成包括第四过孔和第五过孔的图形，其中所述第四过孔设置在所述第一数据线的每个所述第一节段在其沿所述第一数据线的延伸方向的两个端部并且贯穿所述薄膜晶体管的钝化层，并且所述第五过孔设置在所述第一数据线的每个所述第二节段在其沿所述第一数据线的延伸方向的两个端部并且贯穿所述栅极绝缘层和所述钝化层；以及
在所述第四图案化工艺中，可以形成包括第二电连接件的图形，其中所述第二电连接件通过所述第四过孔和所述第五过孔，电连接所述第一数据线的每个所述第一节段和与所述第一节段毗邻的第二节段。
在优选实施例中，在所述第一图案化工艺中，可以形成包括所述薄膜晶体管的所述栅电极和所述栅线、所述第一数据线的所述第二节段以及所述第二数据的第一节段的图形。
在优选实施例中，在所述第三图案化工艺中，可以形成包括第六过孔和第七过孔的图形，其中所述第六过孔设置在所述第二数据线的每个所述第一节段在其沿所述第二数据线的延伸方向的两个端部并且贯穿所述薄膜晶体管的栅极绝缘层和钝化层，并且所述第七过孔设置在所述第二数据线的每个所述第二节段在其沿所述第二数据线的延伸方向的两个端部并且贯穿所述钝化层；以及
在所述第四图案化工艺中，可以形成包括第三电连接件的图形，其中所述第三电连接件通过所述第六过孔和所述第七过孔，电连接所述第二数据线的每个所述第一节段和与所述第一节段毗邻的第二节 段。
在优选实施例中，在所述第四图案化工艺中，可以形成包括电连接件和每个亚像素单元的所述像素电极的图形。
在优选实施例中，形成包括电连接件和每个亚像素单元的所述像素电极的图形的步骤可以包括：
在完成所述第三图案化工艺的所述衬底基板上，沉积第一电连接层，其中所述第一电连接层包括用于形成所述像素电极的导电材料；
通过曝光，保留将形成像素电极和电连接件的区域的光致抗蚀剂并且移除其余区域的光致抗蚀剂；
移除所述其余区域的所述导电材料；以及
剥离将形成像素电极和电连接件的区域的光致抗蚀剂，以形成电连接件和所述像素电极。
在优选实施例中，通过所述第四图案化工艺形成包括电连接件的图形的步骤可以包括：
在完成所述第三图案化工艺的所述衬底基板上，依次沉积第一电连接层和第二电连接层，其中所述第一电连接层包括用于形成所述像素电极的导电材料，并且所述第二电连接层不包含Al；
利用半透式掩模板进行曝光，保留将形成电连接件的区域的光致抗蚀剂，部分移除将形成像素电极的区域的光致抗蚀剂，并且全部移除其余区域的光致抗蚀剂；
干法刻蚀以移除所述其余区域的所述第二电连接层，并且进一步刻蚀以移除所述其余区域的所述第一电连接层；
灰化光致抗蚀剂，以完全移除将形成像素电极的区域的光致抗蚀剂并且减薄将形成电连接件的区域的光致抗蚀剂；
干法刻蚀以移除将形成像素电极的区域的所述第二电连接层，从而形成由所述第一电连接层构成的像素电极；以及
剥离将形成电连接件的区域的光致抗蚀剂，以形成由所述第一电连接层和所述第二电连接层构成的电连接件。
在优选实施例中，通过所述第四图案化工艺形成包括电连接件的图形的步骤可以包括：
在完成所述第三图案化工艺的所述衬底基板上，依次沉积第一电连接层和第二电连接层，其中所述第一电连接层包括用于形成所述像 素电极的导电材料，并且所述第二电连接层包含Al；
利用半透式掩模板进行曝光，保留将形成电连接件的区域的光致抗蚀剂，部分移除将形成像素电极的区域的光致抗蚀剂，并且全部移除其余区域的光致抗蚀剂；
干法刻蚀以移除所述其余区域的所述第二电连接层，并且进一步刻蚀以移除所述其余区域的所述第一电连接层；
灰化光致抗蚀剂，以完全移除将形成像素电极的区域的光致抗蚀剂并且减薄将形成电连接件的区域的光致抗蚀剂；
对所述第一电连接层退火；
湿法刻蚀以移除将形成像素电极的区域的所述第二电连接层，从而形成由所述第一电连接层构成的像素电极；以及
剥离将形成电连接件的区域的光致抗蚀剂，以形成由所述第一电连接层和所述第二电连接层构成的电连接件。
在优选实施例中，沉积所述第二电连接层的步骤可以包括沉积金属单层或金属叠层。
根据本公开的显示面板、显示装置以及阵列基板的制作方法具有与上文所述的阵列基板相同或相似的益处，此处不再赘述。
根据本公开，通过将至少部分的第一数据线和相邻的第二数据线设置在不同层上。藉此，可以有效地防止DDS，从而提高产品良率；可以显著地消除并排设置的双数据线之间的串扰，从而改善产品显示质量；并且可以实现双数据线之间的小间距设计，提高阵列基板的开口率和布线密度。例如，将第一数据线的一些节段与薄膜晶体管的栅电极同层设置，并且将与这些节段并排设置的第二数据线的相应部分与薄膜晶体管的源/漏电极同层设置，使得第一数据线的这些节段和第二数据线的相应部分设置在不同层上，由此实现第一数据线和第二数据线至少部分错层设置，进而防止并排设置的双数据线之间的短路和串扰。本公开的技术方案不会增加已有制作工艺中的图案化工艺，因而不会导致成本增加。
附图说明
图1为已有显示面板的阵列基板的示意性俯视图；
图2为根据本公开第一实施例的阵列基板的示意性俯视图；
图3a和图3b分别为根据本公开第一实施例的阵列基板的示意性剖面图，其中图3a为该阵列基板的沿图2的A-B线的示意性剖面图，图3b为该阵列基板的沿图2的C-D线的示意性剖面图；
图4为根据本公开第二实施例的阵列基板的示意性俯视图；
图5a和图5b分别为根据本公开第二实施例的阵列基板的示意性剖面图，其中图5a为该阵列基板的沿图4的A-B线的示意性剖面图，以及图5b为该阵列基板的沿图4的C-D线的示意性剖面图；
图6为根据本公开第三实施例的阵列基板的示意性俯视图；
图7a、图7b、图7c和图7d分别为根据本公开第三实施例的阵列基板的示意性剖面图，其中图7a为该阵列基板的沿图6的A-B线的示意性剖面图，图7b为该阵列基板的沿图6的G-H线的示意性剖面图，图7c为该阵列基板的沿图6的C-D线的示意性剖面图，以及图7d为该阵列基板的沿图6的E-F线的示意性剖面图；
图8a、图8b、图8c和图8d为根据本公开第四实施例的阵列基板在各制作步骤的示意性剖面图；
图9a、图9b、图9c、图9d和图9e为根据本公开第五实施例的阵列基板在各制作步骤的示意性剖面图；
图10a、图10b、图10c、图10d、图10e、图10f和图10g为根据本公开第六实施例的阵列基板在各制作步骤的示意性剖面图；以及
图11a、图11b和图11c为根据本公开第七实施例的阵列基板在各制作步骤的示意性剖面图。
具体实施方式
下面结合附图，对本公开的阵列基板、显示面板、显示装置以及阵列基板的制作方法的具体实施方式进行详细地说明。本公开的附图示意性地绘示出与发明点有关的结构、部分和/或步骤，而没有绘示或者仅仅部分地绘示与发明点无关的结构、部分和/或步骤。
附图中示出的部件标注如下：
1′ 阵列基板；20′ 栅线；30′ 亚像素单元；40′ 薄膜晶体管；40a′ 栅电极；40b′ 源电极；40c′ 漏电极；50′ 像素电极；61′ 第一数据线；62′第二数据线；1、2、3 阵列基板；20 栅线；30 亚像素单元；40 薄膜晶体管；40a 栅电极；40b 源电极；40c 漏电极；42 栅极绝缘层；44 钝化层；50 像素电极；61 第一数据线；62 第二数据线；611、613 第一数据线的第一节段；612、614 第一数据线的第二节段；621 第二数据线的第一节段；622 第二数据线的第二节段；701 第一过孔；702 第二过孔；703 第三过孔；704 第四过孔；705 第五过孔；706 第六过孔；707 第七过孔；801 第一电连接件；802 第二电连接件；803 第三电连接件；8021 第一电连接层；8022 第二电连接层；90、92 光致抗蚀剂；91、93 掩模板；911、931 透光区域、912、933 不透光区域；932 部分透光区域。
第一实施例
在下文中结合图2、图3a和图3b描述根据本公开第一实施例的阵列基板1。图2为根据第一实施例的阵列基板1的示意性俯视图，图3a为阵列基板1的沿图2的A-B线的示意性剖面图，以及图3b为阵列基板1的沿图2的C-D线的示意性剖面图。
显示面板的阵列基板1包括在衬底基板10上相互绝缘并且交叉以限定多个亚像素单元30的栅线20和数据线。每个亚像素单元30内形成有薄膜晶体管40和像素电极50。薄膜晶体管40包括栅电极40a、源电极40b和漏电极40c。数据线包括并排设置在每两列相邻亚像素单元50之间的第一数据线61和第二数据线62。在每两列相邻亚像素单元30中，奇数行亚像素单元30连接第一数据线61，且偶数行亚像素单元连接第二数据线62。
如图2所示，第一数据线61包括交替设置的多个第一节段611和第二节段612。第一节段611在两个端部分别设置有第一过孔701，并且第二节段612在两个端部分别设置有第二过孔702。第一电连接件801通过第一过孔701和第二过孔702将第一数据线61的每个第一节段611和毗邻的第二节段612相互电连接。薄膜晶体管40的源电极40b上方还设置有第三过孔703。第一电连接件801通过第三过孔703将第一数据线61的第一节段611和第二节段612同时电连接到薄膜晶体管40的源电极40b，由此形成完整的第一数据线61。第二数据线62与薄膜晶体管40的源电极40b和漏电极40c同层设置，并且电连接到源电极40b。
参考图3a和图3b，更详细描述第一数据线61和第二数据线62。 图3a为阵列基板1的沿图2的A-B线的示意性剖面图。该A-B线以一个亚像素单元30的像素电极50上的A点为起点，延伸经过第一数据线61的第一节段611的一部分、第一电连接件801和第一数据线61的第二节段612的一部分，并且以同一列上相邻的另一亚像素单元30的像素电极50上的B点为终点。图3b为阵列基板1的沿图2的C-D线的示意性剖面图。该C-D线以一个亚像素单元30的像素电极50上的C点为起点，在与数据线垂直的方向上延伸经过第二数据线62和第一数据线61的第二节段612，并且以同一行上相邻的另一亚像素单元30的像素电极50上的D点为终点。
如图3a所示，第一数据线61的第一节段611和第二节段612、栅电极40a(未示于图3a)以及栅线20设置在衬底基板10上。第一数据线61的第一节段611在两个端部设置有第一过孔701，并且第一过孔701贯穿薄膜晶体管40的栅极绝缘层42和钝化层44。第一数据线61的第二节段612在两个端部设置有第二过孔702，并且第二过孔702贯穿薄膜晶体管40的栅极绝缘层42和钝化层44。第三过孔703设置在薄膜晶体管40的源电极40b上方并且贯穿钝化层44。第一电连接件801设置在钝化层44上，并且通过第一过孔701、第二过孔702和第三过孔703将第一节段611、毗邻的第二节段612以及源电极40b相互电连接，由此形成完整的第一数据线61。
如图3b所示，第一数据线61的第二节段612设置在栅极绝缘层42下并且与栅电极40a(未示于图3b)同层设置，而第二数据线62设置在栅极绝缘层42上并且与源电极40b和漏电极40c(未示于图3b)同层设置。因此，第一数据线61的第二节段612与第二数据线62错层设置。此外，由图3a可知，第一数据线61的第一节段611也与第二数据线62错层设置。
因此，在第一实施例中，第一数据线61的各个第一节段611和第二节段612都与第二数据线62错层设置，由此可以有效地解决DDS问题。即使在第一数据线61和第二数据线62之间的间距较小的情况下，如此设计的第一数据线和第二数据线可以有效地解决DDS问题，使得产品的良率不受负面影响。
如本领域中所知，薄膜晶体管40中钝化层44上方还可以设置有诸如平坦化层的电介质层(未图示)。这种情况下，第一过孔701、第二 过孔702和第三过孔703相应地还贯穿该平坦化层。
第二实施例
在下文中结合图4、图5a和图5b描述根据本公开第二实施例的阵列基板2。图4为根据第二实施例的阵列基板2的示意性俯视图，图5a为阵列基板2的沿图4的A-B线的示意性剖面图，以及图5b为阵列基板2的沿图4的C-D线的示意性剖面图。
第二实施例与第一实施例不同之处在于，第一数据线的第一节段与薄膜晶体管的源/漏电极同层设置，而不是如第一实施例那样与薄膜晶体管的栅电极同层设置。
如图4所示，第一数据线61包括交替设置的多个第一节段613和第二节段614。第一节段613在两个端部分别设置有第四过孔704，并且第二节段614在两个端部分别设置有第五过孔705。第二电连接件802通过第四过孔704和第五过孔705将第一数据线61的每个第一节段613和毗邻的第二节段614相互电连接，由此形成完整的第一数据线61。由于第一节段613与薄膜晶体管40的源电极40b和漏电极40c同层设置，因此此处可以省略第一实施例中设置在源电极40b上方的第三过孔703。第二数据线62与薄膜晶体管40的源电极40b和漏电极40c同层设置，并且电连接到源电极40b。
参考图5a和图5b以更详细描述第一数据线61和第二数据线62。
如图5a所示，第一数据线61的第二节段614、栅电极40a(未示于图5a)以及栅线20设置在衬底基板10上。第一数据线61的第一节段613以及薄膜晶体管40的源电极40b和漏电极40c(未示于图5a)设置在栅极绝缘层42上。第一数据线61的第一节段613在两个端部设置有第四过孔704，并且第四过孔704贯穿薄膜晶体管40的钝化层44。第一数据线61的第二节段614在两个端部设置有第五过孔705，并且第五过孔705贯穿薄膜晶体管40的栅极绝缘层42和钝化层44。第二电连接件802设置在钝化层44上，并且通过第四过孔704和第五过孔705将第一节段613和毗邻的第二节段614相互电连接，由此形成完整的第一数据线61。
如图5b所示，第一数据线61的第二节段614设置在栅极绝缘层42下并且与栅电极40a(未示于图5b)同层设置，而第二数据线62设置 在栅极绝缘层42上并且与源电极40b和漏电极40c(未示于图5b)同层设置。因此，第一数据线61的第二节段614与第二数据线62错层设置。
因此，在第二实施例中，第一数据线61的第二节段614与第二数据线62错层设置，由此可以有效地解决DDS问题。
第三实施例
在下文中结合图6、图7a、图7b、图7c和图7d描述根据本公开第三实施例的阵列基板3。图6为根据第三实施例的阵列基板3的示意性俯视图，图7a为阵列基板3的沿图6的A-B线的示意性剖面图，图7b为阵列基板3的沿图6的G-H线的示意性剖面图，图7c为阵列基板3的沿图6的C-D线的示意性剖面图，以及图7d为阵列基板3的沿图6的E-F线的示意性剖面图。
第三实施例与第二实施例不同之处在于，第二数据线包括交错设置的节段，每个节段与第一数据线的相应节段错层设置。
如图6所示，第一数据线61包括交替设置的多个第一节段613和第二节段614。第一节段613在两个端部分别设置有第四过孔704，并且第二节段614在两个端部分别设置有第五过孔705。第二电连接件802通过第四过孔704和第五过孔705将第一数据线61的每个第一节段613和毗邻的第二节段614相互电连接，由此形成完整的第一数据线61。
如图6所示，第二数据线62包括交替设置的多个第一节段621和第二节段622。第一节段621在两个端部分别设置有第六过孔706，并且第二节段622在两个端部分别设置有第七过孔707。第三电连接件803通过第六过孔706和第七过孔707将第二数据线62的每个第一节段621和毗邻的第二节段622相互电连接，由此形成完整的第二数据线62。
参考图7a、图7b、图7c和图7d以更详细描述第一数据线61和第二数据线62。
如图7a所示，第一数据线61的第二节段614、栅电极40a(未示于图7a)以及栅线20设置在衬底基板10上。第一数据线61的第一节段613以及薄膜晶体管40的源电极40b和漏电极40c(未示于图7a)设置在 栅极绝缘层42上。第四过孔704贯穿钝化层44，并且第五过孔705贯穿栅极绝缘层42和钝化层44。第二电连接件802设置在钝化层44上，并且通过第四过孔704和第五过孔705将第一节段613和毗邻的第二节段614相互电连接，由此形成完整的第一数据线61。
图7b为阵列基板3的沿图6的G-H线的示意性剖面图。该G-H线以一个亚像素单元30的像素电极50上的G点为起点，延伸经过第二数据线62的第二节段622的一部分、第三电连接件803和第二数据线62的第一节段621的一部分，并且以同一列上相邻的另一亚像素单元30的像素电极50上的H点为终点。如图7b所示，第二数据线62的第一节段621、栅电极40a(未示于图7b)以及栅线20设置在衬底基板10上。第二数据线62的第二节段622以及薄膜晶体管40的源电极40b和漏电极40c(未示于图7b)设置在栅极绝缘层42上。第七过孔707贯穿钝化层44，并且第六过孔706贯穿栅极绝缘层42和钝化层44。第三电连接件803设置在钝化层44上，并且通过第六过孔706和第七过孔707将第一节段621和毗邻的第二节段622相互电连接，由此形成完整的第二数据线62。
如图7c所示，第一数据线61的第二节段614设置在栅极绝缘层42下并且与栅电极40a(未示于图7c)同层设置，而第二数据线62的第二节段622设置在栅极绝缘层42上并且与源电极40b和漏电极40c(未示于图7c)同层设置。因此，第一数据线61的第二节段614与第二数据线62的第二节段622错层设置。
图7d为阵列基板3的沿图6的E-F线的示意性剖面图。该E-F线以一个亚像素单元30的像素电极50上的E点为起点，在与数据线垂直的方向上延伸经过第二数据线62的第一节段612和第一数据线61的第一节段613，并且以同一行上相邻的另一亚像素单元30的像素电极50上的F点为终点。如图7d所示，第二数据线62的第一节段621设置在栅极绝缘层42下并且与栅电极40a(未示于图7d)同层设置，而第一数据线61的第一节段613设置在栅极绝缘层42上并且与源电极40b和漏电极40c(未示于图7d)同层设置。因此，第一数据线61的第一节段613与第二数据线62的第一节段621错层设置。
因此，在第三实施例中，第一数据线61的第一节段613与第二数据线62的第一节段621错层设置，并且第一数据线61的第二节段614 与第二数据线62的第二节段622错层设置。即，第一数据线61和第二数据线62的任何两个并排设置的节段错层设置，由此可以有效地解决DDS问题。即使在第一数据线61和第二数据线62之间的间距较小的情况下，如此设计的第一数据线和第二数据线可以有效地解决DDS问题，使得产品的良率不受负面影响。
第四实施例
在下文中结合图8a、图8b、图8c和图8d描述根据本公开第四实施例的阵列基板的制作方法。图8a-8d为根据第四实施例的阵列基板在各制作步骤的示意性剖面图。
具体而言，以图6、图7a-7d所示第三实施例中的阵列基板3为例，描述本公开的阵列基板的制作方法。应指出，图8a-8d的各剖面图对应于图6中沿A-B线的结构。即，图8a-8d仅仅示出第一数据线61的各制作步骤。
首先，通过第一图案化工艺，在衬底基板10上形成包括薄膜晶体管40的栅电极40a和栅线20、第一数据线61的第二节段614(图8a)以及第二数据线62的第一节段621(图7d)的图形。
接着，在完成前述步骤的衬底基板10上沉积栅极绝缘层42，通过第二图案化工艺形成包括薄膜晶体管40的源电极40b和漏电极40c、第一数据线61的第一节段613(图8b)以及第二数据线62的第二节段622的图形(图7c)。
接着，在完成前述步骤的衬底基板10上沉积钝化层44，通过第三图案化工艺形成包括第四过孔704和第五过孔705(图8c和图7a)以及第六过孔706和第七过孔707(图7b)的图形。第四过孔704设置在第一数据线61的第一节段613的两个端部，并且贯穿钝化层44以露出第一节段613的一部分。第五过孔705设置在第一数据线61的第二节段614的两个端部，并且贯穿栅极绝缘层42和钝化层44以露出第二节段614的一部分。第六过孔706设置在第二数据线62的第一节段621的两个端部，并且贯穿栅极绝缘层42和钝化层44以露出第一节段621的一部分。第七过孔707设置在第二数据线62的第二节段622的两个端部，并且贯穿钝化层44以露出第二节段622的一部分。
最后，在完成前述步骤的衬底基板10上，通过第四图案化工艺， 形成包括第二电连接件802(图8d)和第三电连接件803(图7b)的图形。第二电连接件802通过第四过孔704和第五过孔705将第一数据线61的每个第一节段613和毗邻的第二节段614相互电连接，由此形成完整的第一数据线61。第三电连接件803通过第六过孔706和第七过孔707将第二数据线62的每个第一节段621和毗邻的第二节段622相互电连接，由此形成完整的第二数据线62。
通过上述步骤，第一数据线61和第二数据线62的制作完成，得到图6、图7a-7d的阵列基板3。
在优选实施方式中，如图8d所示，在第四图案化工艺中，在形成第二电连接件802和第三电连接件803时，同时形成各亚像素单元30中的像素电极50的图形。
在下文中，描述图2、图3a-3b所示第一实施例中的阵列基板1的制作方法。
首先，通过第一图案化工艺，在衬底基板10上形成包括薄膜晶体管40的栅电极40a和栅线20、第一数据线61的第一节段611以及第一数据线61的第二节段612的图形(图3a)。
接着，在完成前述步骤的衬底基板10上沉积栅极绝缘层42，通过第二图案化工艺形成包括薄膜晶体管40的源电极40b和漏电极40c以及第二数据线62的图形(图3b)。
接着，在完成前述步骤的衬底基板10上沉积钝化层44，通过第三图案化工艺形成包括第一过孔701、第二过孔703和第三过孔703的图形(图3a)。第一过孔701设置在第一数据线61的第一节段611的两个端部，并且贯穿栅极绝缘层42和钝化层44以露出第一节段611的一部分。第二过孔702设置在第一数据线61的第二节段612的两个端部，并且贯穿栅极绝缘层42和钝化层44以露出第一节段612的一部分。第三过孔703设置在薄膜晶体管40的源电极40b上方，并且贯穿钝化层44以露出源电极40b的一部分。
最后，在完成前述步骤的衬底基板10上，通过第四图案化工艺，形成包括第一电连接件801的图形(图3a)。第一电连接件801通过第一过孔701、第二过孔702和第三过孔703将第一节段611、毗邻的第二节段612以及源电极40b相互电连接，由此形成完整的第一数据线61。
通过上述步骤，第一数据线61和第二数据线62的制作完成，得 到图2、图3a-3b的阵列基板1。
在下文中，描述图4、图5a-5b所示第一实施例中的阵列基板2的制作方法。
首先，通过第一图案化工艺，在衬底基板10上形成包括薄膜晶体管40的栅电极40a和栅线20以及第一数据线61的第二节段614的图形(图5a)。
接着，在完成前述步骤的衬底基板10上沉积栅极绝缘层42，通过第二图案化工艺形成包括薄膜晶体管40的源电极40b和漏电极40c、第一数据线61的第一节段613以及第二数据线62的图形(图5b)。
接着，在完成前述步骤的衬底基板10上沉积钝化层44，通过第三图案化工艺形成包括第四过孔704和第五过孔705的图形(图5a)。第四过孔704设置在第一数据线61的第一节段613的两个端部，并且贯穿钝化层44以露出第一节段613的一部分。第五过孔705设置在第一数据线61的第二节段614的两个端部，并且贯穿栅极绝缘层42和钝化层44以露出第一节段614的一部分。
最后，在完成前述步骤的衬底基板10上，通过第四图案化工艺，形成包括第二电连接件802的图形(图5a)。第二电连接件802通过第四过孔704和第五过孔705将第一数据线61的第一节段613以及毗邻的第二节段614相互电连接，由此形成完整的第一数据线61。
通过上述步骤，第一数据线61和第二数据线62的制作完成，得到图4、图5a-5b的阵列基板2。
第五实施例
在下文中结合图9a-9e描述根据本公开第五实施例的阵列基板的制作方法。图9a-9e为根据第五实施例的阵列基板在各制作步骤的示意性剖面图。
具体而言，在第五实施例中详细描述图8d所示的第四图案化工艺。在该第四图案化工艺中，形成包括电连接件和每个亚像素单元的所述像素电极的图形，并且电连接件和像素电极由相同材料构成。例如，以图6和图7a所示的实施例为例，描述在第四图案化工艺中形成第二电连接件802和像素电极50的步骤。
首先，如图9a所示，在图8c所示的完成第三图案化工艺的衬底基 板10上，沉积第一电连接层8021。第一电连接层8021可以由用于形成像素电极50的导电材料形成。优选地，该导电材料可以为ITO。该导电材料还可以是诸如IZO(氧化铟锌)、IGZO(氧化铟镓锌)、InGaSnO(氧化铟镓锡)的其它透明导电氧化物。当然，像素电极50也可以由其它合适的导电材料形成。
接着，如图9b所示，在衬底基板10上涂布光致抗蚀剂90。采用掩模板91进行曝光工艺。掩模板91包括透光区域911和不透光区域912。不透光区域912对应于衬底基板10上将形成像素电极50和第二电连接件802的区域，而透光区域911对应于衬底基板10上的其余区域。在曝光之后，将形成像素电极50和第二电连接件802的区域的光致抗蚀剂90保留，并且所述其余区域的光致抗蚀剂90移除以露出第一电连接层8021，如图9c所示。
接着，如图9d所示，在所述其余区域，通过刻蚀移除第一电连接层8021。
最后，如图9e所示，剥离将形成像素电极50和第二电连接件802的区域的光致抗蚀剂90，从而形成第二电连接件802和像素电极50。
通过上述步骤，形成了由第一电连接层8021构成的第二电连接件802和像素电极50。该第一电连接层8021由ITO形成。
根据第五实施例，在形成像素电极50的图案化工艺中，同时形成第二电连接件802。藉此，将不会增加已有制作工艺中的图案化工艺，因而不会导致成本增加。
第六实施例
在下文中结合图10a、图10b、图10c、图10d、图10e、图10f和图10g描述根据本公开第六实施例的阵列基板的制作方法。图10a-10g为根据第六实施例的阵列基板在各制作步骤的示意性剖面图。
第六实施例与第五实施例不同之处在于，除了与像素电极相同的材料之外，电连接件还包括金属层。即，电连接件包括第一电连接层和第二电连接层的叠层，其中第一电连接层为ITO，并且第二电连接层为金属。仍然以图6和图7a所示的实施例为例，描述在第四图案化工艺中形成第二电连接件802和像素电极50的步骤。
首先，如图10a所示，在图8c所示的完成第三图案化工艺的衬底基板10上，依次沉积第一电连接层8021和第二电连接层8022。第一 电连接层8021可以由用于形成像素电极50的导电材料形成。优选地，该导电材料可以为ITO(铟锡氧化物)。第二电连接层8022可以包括金属。
如图10b所示，在衬底基板10上涂布光致抗蚀剂92。采用掩模板93进行曝光工艺。掩模板93为半透式掩模板，例如半色调掩模板(half-tone mask)和灰色调掩模(gray-tone mask)。掩模板93包括透光区域931、部分透光区域932和不透光区域933。不透光区域933对应于衬底基板10上将形成第二电连接件802的区域，部分透光区域932对应于衬底基板10上将形成像素电极50的区域，而透光区域931对应于衬底基板10上的其余区域。
如图10c所示，在曝光之后，将形成第二电连接件802的区域的光致抗蚀剂92完全保留，将形成像素电极50的区域的光致抗蚀剂92部分保留，并且所述其余区域的光致抗蚀剂92完全移除。在所述其余区域，由于光致抗蚀剂92被移除，第二电连接层8022露出。
如图10d所示，在所述其余区域，通过干法刻蚀移除第二电连接层8022从而露出第一电连接层8021，并且通过刻蚀移除第一电连接层8021。
如图10e所示，通过灰化(ashing)移除将形成像素电极50的区域的光致抗蚀剂92，从而露出第二电连接层8022。在该灰化过程中，将形成第二电连接件802的区域的光致抗蚀剂92被减薄。
如图10f所示，通过干法刻蚀移除将形成像素电极50的区域的第二电连接层8022，保留第一电连接层8021以形成像素电极50。
最后，如图10g所示，通过剥离将形成第二电连接件802的区域的光致抗蚀剂92，从而形成由第一电连接层8021和第二电连接层8022构成的第二电连接件802。
通过上述步骤，形成了由第一电连接层8021构成的像素电极50，并且形成了由第一电连接层8021和第二电连接层8022构成的第二电连接件802。该第一电连接层8021可以由ITO形成。该第二电连接层8022可以由金属形成，例如Mo、Cu、Mg、Ca、Cr、W、Ti、Ta等。
在第六实施例中，由于第二电连接件802由第一电连接层8021和第二电连接层8022的叠层构成，因此在曝光步骤中采用了诸如半色调掩模板和灰色调掩模的半透式掩模板。
在图10f的剖面图对应的步骤中，采用干法刻蚀移除将形成像素电极50的区域的第二电连接层8022。因此，此实施例的方法尤其适用于第二电连接件802的第二电连接层8022不含Al的情形。
第七实施例
在下文中结合图11a、图11b和图11c描述根据本公开第七实施例的阵列基板的制作方法。图11a-11c为根据第七实施例的阵列基板在各制作步骤的示意性剖面图。
第七实施例与第六实施例不同之处在于，第二电连接件802的第二电连接层8022包含Al。仍然以图6和图7a所示的实施例为例，描述在第四图案化工艺中形成第二电连接件802和像素电极50的步骤。
在第七实施例中，由于第二电连接层8022包含金属Al，因此在图10f的剖面图所对应的步骤中，优选采用湿法刻蚀移除将形成像素电极50的区域的第二电连接层8022。也就是说，第七实施例与第六实施例不同之处在于移除将形成像素电极50的区域的含Al的第二电连接层8022的步骤。
如图11a的空心箭头所示，对图10e所示的衬底基板10中的第一电连接层8021进行退火，提高例如ITO的导电材料的结晶品质，从而提高其刻蚀耐受性。
如图11b所示，通过湿法刻蚀移除将形成像素电极50的区域的第二电连接层8022。在该湿法刻蚀过程中，第一电连接层8021的ITO由于提前进行退火处理而耐受湿法刻蚀中所采用的刻蚀液的腐蚀。这有利于保证后续形成的像素电极50的性能。
最后，如图11c所示，通过剥离将形成第二电连接件802的区域的光致抗蚀剂92，从而形成由第一电连接层8021和第二电连接层8022构成的第二电连接件802。
通过上述步骤，形成了由第一电连接层8021构成的像素电极50，并且形成了由第一电连接层8021和第二电连接层8022构成的第二电连接件802。该第一电连接层8021可以由ITO形成。该第二电连接层8022包含Al。
备选地，当第二电连接层8022包含Al时，可以不提前对第一电连接层8021进行退火处理，而是通过选择适当的刻蚀液和刻蚀时间， 尽可能减小刻蚀液对第一电连接层8021的ITO的不良影响。
如图11a-11c所示，第二电连接层8022优选地包括金属叠层。也就是说，第二电连接层8022可以包括低电阻率的金属单层或叠层，从而提高第二电连接件802的导电性。藉此，有利于实现第一数据线61的第一节段613和第二节段614之间的良好电连接。例如，第二电连接层8022可以包括Mo单层，或者包括Mo/Al/Mo叠层。备选地，第二电连接层可以包括两层、四层或更多层的金属。
在上述的第五实施例、第六实施例和第七实施例中，以第二电连接件802为例描述本公开的电连接件。应指出，上文的描述同样适用于第一电连接件801和第三电连接件803。
第八实施例
基于同一发明构思，本公开第八实施例提供了一种显示面板。该显示面板包括本公开上述实施例中所描述的阵列基板。该显示面板还包括其它必不可少的组成部分，但是这些均为本领域普通技术人员应所知晓，故在此不做赘述，并且这些也不应作为对本公开的限制。
第八实施例还提供了一种显示装置。该显示装置包括上文所述的显示面板。该显示装置可以是任何具有显示功能的产品或部件，例如手机、平板电脑、电视机、显示器、笔记本电脑、数码相框和导航仪。
仅仅是出于图示和说明的目的而给出对本公开实施例的前述描述。它们不是旨在穷举或者限制本公开内容。因此，本领域技术人员将容易想到许多调整和变型。例如，在上述实施例中，第二数据线的一部分与源/漏电极同层设置，与其并排设置的第一数据线的相应部分与栅电极同层设置，由此实现第一数据线和第二数据线至少部分错层设置，从而减轻或消除DDS。然而本公开对错层设置的第一数据线和第二数据线部分所在层不做限定。例如，除了上文所述的源/漏电极所在层以及栅电极所在层之外，第一数据线的相应部分也可以设置在阵列基板中的其它导电层，并且该导电层可以是阵列基板中已有的导电层，也可以是有意增加的额外导电层。此外，在上述实施例中，数据线各节段的过孔靠近薄膜晶体管的栅线设置，电连接件跨过栅线使相互毗邻的节段相互电连接以形成完整的第一数据线和/或第二数据线。然而本公开对电连接件的位置以及各节段的过孔的位置不做限定。例 如，第一数据线和/或第二数据线的节段可以跨过栅线设置并且电连接件可以设置在相邻两条栅线之间，只要各节段通过电连接件相互电连接以形成完整数据线即可。简而言之，本公开的保护范围由所附权利要求定义。

Claims (24)

  1. 一种阵列基板，包括在衬底基板上相互绝缘并且交叉以限定多个亚像素单元的栅线和数据线，每个亚像素单元内形成有薄膜晶体管和像素电极，所述数据线包括并排设置在每两列相邻亚像素单元之间的第一数据线和第二数据线，其中在每两列相邻亚像素单元中，奇数行亚像素单元连接第一数据线，且偶数行亚像素单元连接第二数据线，其特征在于，在每两个列相邻亚像素单元之间，至少部分的所述第一数据线和相邻的所述第二数据线不同层设置。
  2. 根据权利要求1所述的阵列基板，其特征在于，
    所述第一数据线包括交替设置的多个第一节段和第二节段，每个所述第一节段和每个所述第二节段与所述薄膜晶体管的栅电极同层设置，并且每个所述第一节段和毗邻的第二节段通过第一电连接件相互电连接；以及
    所述第二数据线与所述薄膜晶体管的源/漏电极同层设置。
  3. 根据权利要求2所述的阵列基板，其特征在于，
    所述第一数据线的每个所述第一节段在其沿所述第一数据线的延伸方向的两个端部设置有贯穿所述薄膜晶体管的栅极绝缘层和钝化层的第一过孔；
    所述第一数据线的每个所述第二节段在其沿所述第一数据线的延伸方向的两个端部设置有贯穿所述栅极绝缘层和所述钝化层的第二过孔；
    所述薄膜晶体管的源/漏电极上方设置有贯穿所述钝化层的第三过孔；以及
    所述第一电连接件通过所述第一过孔、所述第二过孔和所述第三过孔，电连接所述源/漏电极、所述第一数据线的每个第一节段以及与所述第一节段毗邻的第二节段。
  4. 根据权利要求2或3所述的阵列基板，其特征在于，
    所述第一电连接件与每个亚像素单元的所述像素电极同层设置。
  5. 根据权利要求1所述的阵列基板，其特征在于，
    所述第一数据线包括交替设置的多个第一节段和第二节段，所述第一节段与所述薄膜晶体管的源/漏电极同层设置，所述第二节段与所 述薄膜晶体管的栅电极同层设置，并且每个所述第一节段和毗邻的第二节段通过第二电连接件相互电连接。
  6. 根据权利要求5所述的阵列基板，其特征在于，
    所述第二数据线与所述薄膜晶体管的源/漏电极同层设置。
  7. 根据权利要求6所述的阵列基板，其特征在于，
    所述第一数据线的每个所述第一节段在其沿所述第一数据线的延伸方向的两个端部设置有贯穿所述薄膜晶体管的钝化层的第四过孔；
    所述第一数据线的每个所述第二节段在其沿所述第一数据线的延伸方向的两个端部设置有贯穿所述栅极绝缘层和所述钝化层的第五过孔；以及
    所述第二电连接件通过所述第四过孔和所述第五过孔，电连接所述第一数据线的每个所述第一节段和与所述第一节段毗邻的第二节段。
  8. 根据权利要求5-7中任意一项所述的阵列基板，其特征在于，
    所述第二电连接件与每个亚像素单元的所述像素电极同层设置。
  9. 根据权利要求6所述的阵列基板，其特征在于，
    所述第二数据线包括交替设置的多个第一节段和第二节段；
    所述第二数据线的所述第一节段与所述第一数据线的所述第一节段并排设置，并且与所述薄膜晶体管的栅电极同层设置；
    所述第二数据线的所述第二节段与所述第一数据线的所述第二节段并排设置，并且与所述薄膜晶体管的源/漏电极同层设置；以及
    所述第二数据线的所述第一节段和第二节段通过第三电连接件相互电连接。
  10. 根据权利要求9所述的阵列基板，其特征在于，
    所述第二数据线的每个所述第一节段在其沿所述第二数据线的延伸方向的两个端部设置有贯穿所述薄膜晶体管的栅极绝缘层和钝化层的第六过孔；
    所述第二数据线的每个所述第二节段在其沿所述第二数据线的延伸方向的两个端部设置有贯穿所述钝化层的第七过孔；以及
    所述第三电连接件通过所述第六过孔和所述第七过孔，电连接所述第二数据线的每个所述第一节段和与所述第一节段毗邻的第二节段。
  11. 根据权利要求9或10所述的阵列基板，其特征在于，
    所述第三电连接件与每个亚像素单元的所述像素电极同层设置。
  12. 一种显示面板，包括如权利要求1-11中任意一项所述的阵列基板。
  13. 一种显示装置，包括如权利要求12所述的显示面板。
  14. 一种阵列基板的制作方法，所述阵列基板包括在衬底基板上相互绝缘并且交叉以限定多个亚像素单元的栅线和数据线，每个亚像素单元内形成有薄膜晶体管和像素电极，所述数据线包括并排设置在每两列相邻亚像素单元之间的第一数据线和第二数据线，其中在每两列相邻亚像素单元中，奇数行亚像素单元连接第一数据线，且偶数行亚像素单元连接第二数据线，其特征在于，所述方法包括下述步骤：
    通过第一图案化工艺，在衬底基板上形成包括所述薄膜晶体管的栅电极和栅线以及所述第一数据线的第二节段的图形；
    通过第二图案化工艺形成包括所述薄膜晶体管的源/漏电极和所述第二数据线的第二节段的图形，其中所述第二数据线的所述第二节段与所述第一数据线的所述第二节段并排设置；
    通过第三图案化工艺形成包括所述第一数据线的所述第二节段和所述第二数据线的所述第二节段上方的过孔的图形；以及
    通过第四图案化工艺形成包括电连接件的图形，其中电连接件将所述第一数据线的所述第二节段电连接到毗邻的所述第一数据线的第一节段。
  15. 根据权利要求14所述的方法，其特征在于，
    在所述第一图案化工艺中，形成包括所述薄膜晶体管的所述栅电极和所述栅线、所述第一数据线的所述第二节段以及所述第一数据线的所述第一节段的图形；以及
    在所述第二图案化工艺中，形成包括所述薄膜晶体管的所述源/漏电极以及连续第二数据线的图形。
  16. 根据权利要求15所述的方法，其特征在于，
    在所述第三图案化工艺中，形成包括第一过孔、第二过孔和第三过孔的图形，其中所述第一过孔设置在所述第一数据线的每个所述第一节段在其沿所述第一数据线的延伸方向的两个端部并且贯穿所述薄膜晶体管的栅极绝缘层和钝化层，所述第二过孔设置在所述第一数据 线的每个所述第二节段在其沿所述第一数据线的延伸方向的两个端部并且贯穿所述栅极绝缘层和所述钝化层，并且所述第三过孔设置在所述薄膜晶体管的源/漏电极上方并且贯穿所述钝化层；以及
    在所述第四图案化工艺中，形成包括第一电连接件的图形，其中所述第一电连接件通过所述第一过孔、所述第二过孔以及所述第三过孔，电连接所述源/漏电极、所述第一数据线的每个第一节段以及与所述第一节段毗邻的第二节段。
  17. 根据权利要求14所述的方法，其特征在于，
    在所述第二图案化工艺中，形成包括所述薄膜晶体管的所述源/漏电极、所述第二数据线的所述第二节段以及所述第一数据线的第一节段的图形。
  18. 根据权利要求17所述的方法，其特征在于，
    在所述第二图案化工艺中，形成包括所述薄膜晶体管的所述源/漏电极、连续第二数据线以及所述第一数据线的所述第一节段的图形。
  19. 根据权利要求18所述的方法，其特征在于，
    在所述第三图案化工艺中，形成包括第四过孔和第五过孔的图形，其中所述第四过孔设置在所述第一数据线的每个所述第一节段在其沿所述第一数据线的延伸方向的两个端部并且贯穿所述薄膜晶体管的钝化层，并且所述第五过孔设置在所述第一数据线的每个所述第二节段在其沿所述第一数据线的延伸方向的两个端部并且贯穿所述栅极绝缘层和所述钝化层；以及
    在所述第四图案化工艺中，形成包括第二电连接件的图形，其中所述第二电连接件通过所述第四过孔和所述第五过孔，电连接所述第一数据线的每个所述第一节段和与所述第一节段毗邻的第二节段。
  20. 根据权利要求17所述的方法，其特征在于，
    在所述第一图案化工艺中，形成包括所述薄膜晶体管的所述栅电极和所述栅线、所述第一数据线的所述第二节段以及所述第二数据的第一节段的图形。
  21. 根据权利要求20所述的方法，其特征在于，
    在所述第三图案化工艺中，形成包括第六过孔和第七过孔的图形，其中所述第六过孔设置在所述第二数据线的每个所述第一节段在其沿所述第二数据线的延伸方向的两个端部并且贯穿所述薄膜晶体管的栅 极绝缘层和钝化层，并且所述第七过孔设置在所述第二数据线的每个所述第二节段在其沿所述第二数据线的延伸方向的两个端部并且贯穿所述钝化层；以及
    在所述第四图案化工艺中，形成包括第三电连接件的图形，其中所述第三电连接件通过所述第六过孔和所述第七过孔，电连接所述第二数据线的每个所述第一节段和与所述第一节段毗邻的第二节段。
  22. 根据权利要求14所述的方法，其特征在于，
    在所述第四图案化工艺中，在完成所述第三图案化工艺的所述衬底基板上，沉积第一电连接层，其中所述第一电连接层包括用于形成所述像素电极的导电材料；
    通过曝光，保留将形成像素电极和电连接件的区域的光致抗蚀剂并且移除其余区域的光致抗蚀剂；
    移除所述其余区域的所述导电材料；以及
    剥离将形成像素电极和电连接件的区域的光致抗蚀剂，以形成电连接件和所述像素电极。
  23. 根据权利要求14所述的方法，其特征在于，
    通过所述第四图案化工艺形成包括电连接件的图形的步骤包括：
    在完成所述第三图案化工艺的所述衬底基板上，依次沉积第一电连接层和第二电连接层，其中所述第一电连接层包括用于形成所述像素电极的导电材料，并且所述第二电连接层不包含Al；
    利用半透式掩模板进行曝光，保留将形成电连接件的区域的光致抗蚀剂，部分移除将形成像素电极的区域的光致抗蚀剂，并且全部移除其余区域的光致抗蚀剂；
    干法刻蚀以移除所述其余区域的所述第二电连接层，并且进一步刻蚀以移除所述其余区域的所述第一电连接层；
    灰化光致抗蚀剂，以完全移除将形成像素电极的区域的光致抗蚀剂并且减薄将形成电连接件的区域的光致抗蚀剂；
    干法刻蚀以移除将形成像素电极的区域的所述第二电连接层，从而形成由所述第一电连接层构成的像素电极；以及
    剥离将形成电连接件的区域的光致抗蚀剂，以形成由所述第一电连接层和所述第二电连接层构成的电连接件。
  24. 根据权利要求14所述的方法，其特征在于，
    通过所述第四图案化工艺形成包括电连接件的图形的步骤包括：
    在完成所述第三图案化工艺的所述衬底基板上，依次沉积第一电连接层和第二电连接层，其中所述第一电连接层包括用于形成所述像素电极的导电材料，并且所述第二电连接层包含Al；
    利用半透式掩模板进行曝光，保留将形成电连接件的区域的光致抗蚀剂，部分移除将形成像素电极的区域的光致抗蚀剂，并且全部移除其余区域的光致抗蚀剂；
    干法刻蚀以移除所述其余区域的所述第二电连接层，并且进一步刻蚀以移除所述其余区域的所述第一电连接层；
    灰化光致抗蚀剂，以完全移除将形成像素电极的区域的光致抗蚀剂并且减薄将形成电连接件的区域的光致抗蚀剂；
    对所述第一电连接层退火；
    湿法刻蚀以移除将形成像素电极的区域的所述第二电连接层，从而形成由所述第一电连接层构成的像素电极；以及
    剥离将形成电连接件的区域的光致抗蚀剂，以形成由所述第一电连接层和所述第二电连接层构成的电连接件。
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