WO2017041491A1 - 倒装芯片的封装方法 - Google Patents

倒装芯片的封装方法 Download PDF

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Publication number
WO2017041491A1
WO2017041491A1 PCT/CN2016/080209 CN2016080209W WO2017041491A1 WO 2017041491 A1 WO2017041491 A1 WO 2017041491A1 CN 2016080209 W CN2016080209 W CN 2016080209W WO 2017041491 A1 WO2017041491 A1 WO 2017041491A1
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Prior art keywords
flip chip
photoresist
metal
electrode
package substrate
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PCT/CN2016/080209
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English (en)
French (fr)
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柯全
伊福廷
潘明
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柯全
伊福廷
潘明
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Priority to US15/757,902 priority Critical patent/US10985300B2/en
Priority to JP2018532495A priority patent/JP6777742B2/ja
Publication of WO2017041491A1 publication Critical patent/WO2017041491A1/zh
Priority to US17/095,727 priority patent/US20210090907A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body

Definitions

  • the invention relates to a method for packaging a flip chip, in particular to a method for packaging a flip chip based on an electroforming technology.
  • flip-chip packaging With the development of flip-chip technology, especially the popularity of semiconductor LED (light-emitting diode) illumination, the use of flip-chip packaging for semiconductor LED chips has become a trend, and flip-chip packaging generally uses three types of eutectic, solder paste, silver paste Crystal mode. But no matter what way, high-precision die-bonding is necessary because the distance between the positive and negative electrodes of the flip chip can't be very large; the flip-chip eutectic technology involves expensive production equipment and materials, which makes it costly and cost-effective. The package of solder paste and silver paste is limited to low reliability and poor thermal conductivity and can not be used in high power flip chip packaging. Flip LED technology has been around for a long time, but it is limited for many reasons. Delayed in popularity;
  • Electrode and substrate electrode alignment accuracy becomes a key factor affecting packaging efficiency and finished product; and another packaging method, such as the chip used in the Chinese patent application "Flip-chip packaging method and device” (publication number CN104658929A)
  • the metal substrate is cut along the insulating region between the electrodes on the chip by laser cutting or the like, and the electrical connection between the electrodes of the chip is cut to realize the electrode of the corresponding chip.
  • the electrical connection between the two is cut off.
  • This method has the hidden danger that this cutting behavior will cause a large stress on the chip. Although it is only cutting the metal, it may adversely affect the chip through the two electrodes that have been fixed.
  • the technical problem to be solved by the present invention is to overcome the many defects of the conventional package bonding method of the flip chip in the prior art, and to provide a flip chip packaging method.
  • the invention provides a flip chip packaging method, which comprises: electroforming a metal at the same time on the electrode surface of the flip chip and the surface of the package substrate, and realizing the passage between the electrode of the flip chip and the package substrate Metal connection.
  • the flip chip packaging method comprises the following steps:
  • the flip chip is embedded in the package substrate and the electrode surface of the flip chip is in the same plane as the surface of the package substrate;
  • the metal conductive film as an electrode, a surface electrode surface of flip chip structure within the photoresist mold and the package substrate while the metal electroforming, and such that the inner structure of the photoresist mold Overgrown with the metal to achieve connection between the electrode of the flip chip and the package substrate through the metal;
  • step S 6 further comprising:
  • step S 1 comprising:
  • the silicon substrate is removed, so that flip-chip packaging substrate embedded in a surface electrode and the surface of the flip chip package substrate in the same plane.
  • step S 11 adjacent to the distance between two flip-chip is 6mm.
  • the thickness of the organic sheet is 2mm.
  • step S 13 to grinding or chemically removing the silicon substrate.
  • the metal conductive film comprises a gold conductive layer and a chromium conductive layer, the chromium conductive layer is located above the electrode surface of the flip chip and the surface of the package substrate, and the gold conductive layer is located on the chromium conductive layer.
  • the chromium conductive layer is located above the electrode surface of the flip chip and the surface of the package substrate, and the gold conductive layer is located on the chromium conductive layer.
  • the gold conductive layer has a thickness of 20 to 400 nm, preferably 50 nm
  • the chromium conductive layer has a thickness of 20 to 400 nm, preferably 20 nm.
  • the photoresist is AZ4620 photoresist, AZ-50XT photoresist, SU8 photoresist or PMMA (plexiglass) photoresist.
  • the above several photoresists are commercially available.
  • step S 3 embodiment applied to the photoresist beach.
  • the step S 3 to rotate the photoresist coating the rotation speed of 200-6000 rpm, preferably, 1000 rpm.
  • the metal is copper, nickel or gold.
  • S 6 comprising the step of:
  • the chromium conductive layer covered by the gold conductive layer is etched away by the chromium etching solution.
  • the electrode surface of the flip chip is provided with or without a metal layer.
  • the surface of the package substrate is provided with or without a metal layer.
  • the positive progress of the invention is that the invention utilizes electroforming and lithography technology to accurately ensure the positional accuracy of the electrode structure in the chip, can meet the requirement of small spacing between flip-chip electrodes, and adopts a thick glue process and can A good metal connection is achieved between the electrode and the substrate, so that the heat generated by the high-power flip chip can be dissipated in time, the thermal resistance is effectively reduced, the process is simplified, and the production efficiency is improved.
  • FIG. 1 is a flow chart showing a method of packaging a flip chip according to Embodiment 1 of the present invention.
  • FIG. 2 is a schematic structural view of an intermediate product obtained after performing step 101 in the method of packaging a flip chip according to Embodiment 1 of the present invention.
  • FIG. 3 is a schematic structural view of an intermediate product obtained after performing step 102 in the method of packaging a flip chip according to Embodiment 1 of the present invention.
  • FIG. 4 is a schematic structural view of an intermediate product obtained after performing step 103 in the method of packaging a flip chip according to Embodiment 1 of the present invention.
  • FIG. 5 is a schematic structural diagram of an intermediate product obtained after performing step 104 in the method of packaging a flip chip according to Embodiment 1 of the present invention.
  • FIG. 6 is a schematic structural view of an intermediate product obtained after performing step 105 in the method of packaging a flip chip according to Embodiment 1 of the present invention.
  • FIG. 7 is a schematic structural view of an intermediate product obtained after performing step 106 in the method of packaging a flip chip according to Embodiment 1 of the present invention.
  • FIG. 8 is a schematic structural view of an intermediate product obtained after performing step 107 in the method of packaging a flip chip according to Embodiment 1 of the present invention.
  • FIG. 9 is a flowchart showing a method of packaging a flip chip according to Embodiment 1 of the present invention. A schematic diagram of the structure of the intermediate product obtained.
  • FIG. 10 is a schematic structural view of an intermediate product obtained after performing step 109 in the method of packaging a flip chip according to Embodiment 1 of the present invention.
  • FIG. 11 is a schematic structural view of a product obtained after performing step 110 in the method of packaging a flip chip according to Embodiment 1 of the present invention.
  • Figure 12 is a flow chart showing a method of packaging a flip chip according to a second embodiment of the present invention.
  • Figure 13 is a plan view of an intermediate product obtained after performing step 201 in the method of packaging a flip chip according to Embodiment 2 of the present invention.
  • Figure 14 is a side view of an intermediate product obtained after performing step 201 in the method of packaging a flip chip according to Embodiment 2 of the present invention.
  • FIG. 15 is a schematic structural view of an intermediate product obtained after performing step 202 in the method of packaging a flip chip according to Embodiment 2 of the present invention.
  • FIG. 16 is a schematic structural view of an intermediate product obtained after performing step 203 in the method of packaging a flip chip according to Embodiment 2 of the present invention.
  • FIG. 17 is a schematic structural view of an intermediate product obtained after performing step 205 in the method of packaging a flip chip according to Embodiment 2 of the present invention.
  • FIG. 18 is a schematic structural view of an intermediate product obtained after performing step 206 in the method of packaging a flip chip according to Embodiment 2 of the present invention.
  • FIG. 19 is a plan view of an intermediate product obtained after performing step 208 in the method of packaging a flip chip according to Embodiment 2 of the present invention.
  • FIG. 20 is a side view of an intermediate product obtained after performing step 208 in the method of packaging a flip chip according to Embodiment 2 of the present invention.
  • FIG. 21 is a schematic structural view of an intermediate product obtained after performing step 209 in the method of packaging a flip chip according to Embodiment 2 of the present invention.
  • FIG. 22 is a schematic structural diagram of an intermediate product obtained after performing step 210 in the method of packaging a flip chip according to Embodiment 2 of the present invention.
  • FIG. 23 is a schematic structural view of a product obtained after performing step 211 in the method of packaging a flip chip according to Embodiment 2 of the present invention.
  • the flip chip packaging method of this embodiment includes the following steps:
  • Step 101 arranging a plurality of flip chip 1 in an array on the surface of the silicon substrate 2, and bringing the electrode surface of the flip chip 1 into contact with the surface of the silicon substrate 2, wherein preferably two adjacent
  • the distance between the flip chip 1 is 6 mm, and the structural schematic of the intermediate product obtained after performing step 101 is as shown in FIG. 2 .
  • Step 102 pouring plexiglass 3 on the array surface of the flip chip 1, and flattening and drying the surface of the plexiglass 3 to form an organic sheet having a thickness of 2 mm, and using the organic sheet as a package substrate.
  • a schematic structural view of the intermediate product obtained after performing step 102 is shown in FIG.
  • Step 103 Removing the silicon substrate 2, specifically removing it by grinding or chemically, and inserting the flip chip 1 into the package substrate, and the electrode surface of the flip chip is in the same plane as the surface of the package substrate, thus obtaining The package substrate with the flip chip 1 array embedded, and the electrode surface of the flip chip 1 and the surface of the package substrate are well overlapped, and the structural schematic of the intermediate product obtained after performing step 103 is as shown in FIG. 4 .
  • Step 104 plating a metal conductive film on the electrode surface of the flip chip 1 and the surface of the package substrate as an electrode of an electroforming process, wherein the metal conductive film comprises a gold conductive layer 4 and a chromium conductive layer 5, and the chromium conductive layer 5 is located above the surface of the electrode of the flip chip 1 and the surface of the package substrate, the gold conductive layer 4 is located above the chromium conductive layer 5, preferably, the thickness of the gold conductive layer 4 is 50 nm, the chromium The thickness of the conductive layer 5 is 20 nm, and the intermediate product obtained after performing step 104 is performed.
  • the structure diagram is shown in Figure 5.
  • Step 105 coating a photoresist 6 on the surface of the metal conductive film (specifically, the gold conductive layer 4).
  • the photoresist is AZ4620 photoresist, and is specifically coated in a rotating manner.
  • the AZ4620 photoresist was coated at a rotation speed of 1000 rpm, and then dried in an oven at 90 ° C.
  • a schematic structural view of the intermediate product obtained after performing step 105 is shown in FIG. 6 .
  • Step 106 aligning the electrode structure on the lithographic plate with the electrode structure of the flip chip 1 on the lithography machine and performing photolithography, and obtaining the electrode surface of the flip chip 1 and the surface of the package substrate after exposure and development.
  • the photoresist structure of the region is such that the insulating portion between the electrodes of the flip chip 1 is covered with the photoresist 6, and the structural schematic of the intermediate product obtained after performing step 106 is as shown in FIG.
  • Step 107 performing copper electroforming growth in a photoresist structure mold by using the metal conductive film, specifically, using the metal conductive film as an electrode, and an electrode of the flip chip 1 in the photoresist structure mold Simultaneous electroforming of the metal copper 7 on the surface of the surface and the surface of the package substrate, controlling the time and growth rate, to ensure that the electrode surface of the flip chip 1 and the corresponding package substrate are in the same region of the photoresist structure mold is covered with metal copper 7, and The electrode of the flip chip 1 and the package substrate are connected by metal copper 7, and the structural schematic of the intermediate product obtained after performing step 107 is as shown in FIG.
  • Step 108 dissolving the unexposed photoresist 6 by using the sol liquid, and the structural schematic diagram of the intermediate product obtained after performing step 108 is as shown in FIG.
  • Step 109 etching away the gold conductive layer covered by the photoresist removed in step 108 by using a gold etching solution, and etching the chromium conductive layer covered by the gold conductive layer with a chromium etching solution, thereby cutting off between the flip chip electrodes
  • a gold etching solution etching away the gold conductive layer covered by the photoresist removed in step 108 by using a gold etching solution
  • etching the chromium conductive layer covered by the gold conductive layer with a chromium etching solution thereby cutting off between the flip chip electrodes
  • Step 110 Dissolve the organic sheet (ie, the package substrate) by using a plexiglass solvent to complete the packaging of the flip chip 2.
  • the structure of the product obtained after performing step 110 is as shown in FIG.
  • the flip chip may specifically be an LED flip chip, in specific
  • the electrode surface of the flip chip 1 may or may not be provided with a metal layer
  • the surface of the package substrate may or may not be provided with a metal layer.
  • the package substrate is a ceramic package substrate.
  • the flip chip package method of the embodiment includes the following steps:
  • Step 201 Insert a plurality of flip chip 1 into the ceramic package substrate 8.
  • the flip chip is specifically a 1 mm long, 1 mm wide, and 0.35 mm thick LED flip chip, and the model is specifically CREEDA 1000.
  • the operation is: setting a ceramic package substrate 8 having a thickness (about 0.6 mm) slightly larger than the thickness of the flip chip 1.
  • Each unit center of the ceramic package substrate 8 is provided with a hollow gap which is identical to the chip shape but slightly larger in size, in the ceramic package.
  • the substrate 8 has a side surface provided with a metal layer corresponding to the two electrodes of the flip chip 1 and insulated from each other, and a through hole having a metal connection with the metal layer for external heat sink; a top view of the intermediate product obtained after performing step 201 and The side views are shown in Figures 13 and 14, respectively.
  • Step 202 Place the side of the ceramic package substrate 8 with the metal layer downward on the surface of the silicon wafer, and place the electrode surface of the flip chip 1 downward in the air of the ceramic package substrate 8 to emit light on the flip chip 1.
  • the surface is coated with a fluorescent glue 9, and a fluorescent film can also be disposed.
  • a schematic structural view of the intermediate product obtained after performing step 202 is shown in FIG.
  • Step 203 pouring the silica gel 10 in the hollow space of the ceramic package substrate 8, and the material to be poured is solidified and dried, so that the flip chip 1 and the ceramic package substrate 8 are fixed by the silica gel 10, and the structural schematic diagram of the intermediate product obtained after performing step 203 is as shown in the figure. 16 is shown.
  • Step 204 removing the silicon wafer by grinding or chemically, thereby obtaining an array having the flip chip 1 fixed by the silica gel 10 and the ceramic package substrate 8, and the electrode surface of the flip chip 1 and the surface of the ceramic package substrate 8 are good.
  • Step 205 the metal conductive film is disposed on a surface of the ceramic package substrate 8 on which the metal layer is provided and on the electrode surface of the flip chip 1.
  • the metal conductive film also includes the gold conductive layer 4 and the chrome conductive
  • the layer 5 is specifically set up in the same manner as in the step 104 of the embodiment 1, and the structural diagram of the intermediate product obtained after the step 205 is performed is as shown in FIG.
  • Step 206 applying a photoresist 6 on the surface of the metal conductive film (specifically, the gold conductive layer 4), in the same manner as in the step 105 of the embodiment 1, and performing the structural diagram of the intermediate product obtained after the step 206 is as follows.
  • Figure 18 shows.
  • Step 207 aligning a portion of the electrode structure on the lithographic plate with the electrode structure on the flip chip 1 on the lithography machine and performing photolithography, and then exposing, is an electrode N of the flip chip 1 and the corresponding ceramic package
  • the surface metal of the substrate 8 is in one region, and the surface metal of the corresponding ceramic package substrate 8 of the other electrode P is in another region.
  • Step 208 developing the exposed photoresist to obtain a photoresist structure mold of a single flip chip electrode surface and a surface of the corresponding ceramic package substrate 8 in the same region, and between the electrodes of the flip chip 1
  • the insulating portion is covered with a photoresist 6, and the top and side views of the intermediate product obtained after performing step 208 are shown in Figs. 19 and 20, respectively.
  • Step 209 performing copper electroforming growth in the photoresist structure mold by using the metal conductive film, the specific operation is the same as that in the step 107 of the first embodiment, and the structural schematic diagram of the intermediate product obtained after performing step 209 is as shown in FIG. .
  • Step 210 dissolving the unexposed photoresist 6 by using the sol liquid, and the structural schematic of the intermediate product obtained after performing step 210 is as shown in FIG.
  • Step 211 using a gold etching solution to etch away the gold conductive layer covered by the photoresist removed in step 210, and etching the chromium conductive layer covered by the gold conductive layer with a chromium etching solution, thereby cutting off between the flip chip electrodes Electrical connection, a schematic diagram of the structure of the product obtained after performing step 211 is shown in FIG.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Led Device Packages (AREA)
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Abstract

一种倒装芯片的封装方法，包括：在倒装芯片的电极表面和封装基板的表面同时电铸金属，实现倒装芯片的电极和封装基板之间通过金属连接。具体包括：S1、在倒装芯片周围设置封装基板；S2、在倒装芯片的电极表面和封装基板的表面镀金属导电膜；S3、在金属导电膜的表面涂覆光刻胶；S4、在光刻机上将光刻板上的电极结构与倒装芯片的电极结构对准并进行光刻，获得光刻胶结构模，并使得电极之间的绝缘部位覆盖光刻胶；S5、将金属导电膜作为电极，在光刻胶结构模内电铸金属，使得光刻胶结构模内长满金属；S6、去除覆盖在绝缘部位的光刻胶及光刻胶覆盖的金属导电膜。该方法利用电铸和光刻技术，简化工艺，提高生产效率。

Description

倒装芯片的封装方法
本申请要求申请日为2015年9月11日的中国专利申请
CN201510579955.1的优先权。本申请引用上述中国专利申请的全文。
技术领域
本发明涉及一种倒装芯片的封装方法，特别是涉及一种基于电铸技术的倒装芯片的封装方法。
背景技术
随着倒装芯片技术的发展，特别是半导体LED(发光二极管)照明的普及，半导体LED芯片使用倒装封装已经成为趋势，而倒装封装一般使用共晶、锡膏、银胶三类的固晶方式。但是不管用什么方式，高精密的固晶是必需的，因为倒装芯片的正负电极之间的距离不能很大；倒装共晶技术涉及昂贵生产设备和材料使得其成本偏高，性价比优势体现不出来，而锡膏和银胶的封装方式都限于可靠性较低以及导热性能较差而无法用于大功率倒装芯片的封装，倒装LED技术问世已久，但受限于诸多原因，迟迟无法普及；
除了这三种常见的倒装芯片封装的键合方式外，还有新近出现的电磁脉冲焊接键合方式，如中国专利申请“倒装芯片的封装方法”(公开号为CN103094135A)中所述；这种键合方式的好处是芯片电极和基板电极之间是原子级连接，非常有助于大功率倒装芯片的散热，但是在研制的过程中发现，使用电磁脉冲焊接方式键合时，芯片电极和基板电极对准精度成为影响封装效率和成品的关键因素；而另一种封装方式，如中国专利申请“倒装芯片的封装方法及装置”(公开号为CN104658929A)中所使用的芯片和金属基板实现键合后，再通过激光切割等方式将金属基板沿着芯片上的电极之间的绝缘区域，将芯片的电极之间的电连接切断以实现将相对应芯片的电极之 间的电连接切断，此方法存在的隐患是这个切割行为会导致芯片上的较大的应力，虽然只是在切割金属，但是可能会通过已经固定了的两个电极，对芯片产生不利的影响。
发明内容
本发明要解决的技术问题是为了克服现有技术中倒装芯片的传统封装键合方式存在的很多缺陷，提供一种倒装芯片的封装方法。
本发明是通过下述技术方案来解决上述技术问题的：
本发明提供了一种倒装芯片的封装方法，其特点在于，包括：在倒装芯片的电极表面和封装基板的表面同时电铸金属，并实现倒装芯片的电极和封装基板之间通过所述金属连接。
较佳地，所述倒装芯片的封装方法包括以下步骤：
S1、在倒装芯片周围设置封装基板；
优选地，使得倒装芯片嵌入封装基板中且倒装芯片的电极表面与封装基板的表面位于同一平面；
S2、在倒装芯片的电极表面和封装基板的表面镀金属导电膜；
S3、在金属导电膜的表面涂覆光刻胶；
S4、在光刻机上将光刻板上的电极结构与倒装芯片的电极结构对准并进行光刻，并在曝光和显影之后获得倒装芯片的电极表面和封装基板的表面处于同一区域的光刻胶结构模，并使得倒装芯片的电极之间的绝缘部位覆盖有光刻胶；
S5、将所述金属导电膜作为电极，在所述光刻胶结构模内的倒装芯片的电极表面和封装基板的表面同时电铸所述金属，并使得所述光刻胶结构模内长满所述金属，以实现倒装芯片的电极和封装基板之间通过所述金属连接；
S6、去除步骤S4中覆盖在所述绝缘部位的光刻胶及光刻胶覆盖的金属导电膜。
较佳地，步骤S6之后还包括：
S7、去除所述封装基板。
较佳地，步骤S1包括：
S11、将多个倒装芯片以阵列的方式排布在硅基片表面，并使得倒装芯片的电极表面与硅基片的表面相接触；
S12、在倒装芯片的阵列表面浇筑有机玻璃，并将有机玻璃表面压平且使有机玻璃固化干燥，以形成作为封装基板的有机薄片；
S13、去除硅基片，以使得倒装芯片嵌入封装基板中且倒装芯片的电极表面与封装基板的表面位于同一平面。
较佳地，在步骤S11中相邻两个倒装芯片之间的距离为6mm。
较佳地，在步骤S12中有机薄片的厚度为2mm。
较佳地，在步骤S13中以磨削或化学方式去除硅基片。
较佳地，所述金属导电膜包括金导电层和铬导电层，所述铬导电层位于倒装芯片的电极表面和封装基板的表面的上方，所述金导电层位于所述铬导电层的上方。
较佳地，所述金导电层的厚度为20-400nm，优选地，为50nm，所述铬导电层的厚度为20-400nm，优选地，为20nm。
较佳地，所述光刻胶为AZ4620光刻胶、AZ-50XT光刻胶、SU8光刻胶或PMMA(有机玻璃)光刻胶。其中，上述几种光刻胶均为市售可得。
较佳地，步骤S3中以滩涂的方式涂覆所述光刻胶。
较佳地，步骤S3中以旋转的方式涂覆所述光刻胶，旋转速度为每分钟200-6000转，优选地，为每分钟1000转。
较佳地，所述金属为铜、镍或金。
较佳地，步骤S6包括：
S61、通过溶胶液溶解掉覆盖在所述绝缘部位的光刻胶；
S62、通过金腐蚀液腐蚀掉光刻胶覆盖的金导电层；
S63、通过铬腐蚀液腐蚀掉金导电层覆盖的铬导电层。
较佳地，所述倒装芯片的电极表面设有或不设有金属层。
较佳地，所述封装基板的表面设有或不设有金属层。
本发明的积极进步效果在于：本发明利用电铸和光刻技术，准确保证电极结构在芯片中的位置精度，可以满足倒装芯片电极之间间距微小的需要，同时采用厚胶工艺，并能够在电极和基板之间实现良好的金属连接，从而使大功率倒装芯片产生的热量可以及时地散发出来，有效地降低了热阻，并简化工艺，提高了生产效率。
附图说明
图1为本发明的实施例1的倒装芯片的封装方法的流程图。
图2为本发明的实施例1的倒装芯片的封装方法中执行步骤101之后获得的中间产品的结构示意图。
图3为本发明的实施例1的倒装芯片的封装方法中执行步骤102之后获得的中间产品的结构示意图。
图4为本发明的实施例1的倒装芯片的封装方法中执行步骤103之后获得的中间产品的结构示意图。
图5为本发明的实施例1的倒装芯片的封装方法中执行步骤104之后获得的中间产品的结构示意图。
图6为本发明的实施例1的倒装芯片的封装方法中执行步骤105之后获得的中间产品的结构示意图。
图7为本发明的实施例1的倒装芯片的封装方法中执行步骤106之后获得的中间产品的结构示意图。
图8为本发明的实施例1的倒装芯片的封装方法中执行步骤107之后获得的中间产品的结构示意图。
图9为本发明的实施例1的倒装芯片的封装方法中执行步骤108之后获 得的中间产品的结构示意图。
图10为本发明的实施例1的倒装芯片的封装方法中执行步骤109之后获得的中间产品的结构示意图。
图11为本发明的实施例1的倒装芯片的封装方法中执行步骤110之后获得的产品的结构示意图。
图12为本发明的实施例2的倒装芯片的封装方法的流程图。
图13为本发明的实施例2的倒装芯片的封装方法中执行步骤201之后获得的中间产品的俯视图。
图14为本发明的实施例2的倒装芯片的封装方法中执行步骤201之后获得的中间产品的侧视图。
图15为本发明的实施例2的倒装芯片的封装方法中执行步骤202之后获得的中间产品的结构示意图。
图16为本发明的实施例2的倒装芯片的封装方法中执行步骤203之后获得的中间产品的结构示意图。
图17为本发明的实施例2的倒装芯片的封装方法中执行步骤205之后获得的中间产品的结构示意图。
图18为本发明的实施例2的倒装芯片的封装方法中执行步骤206之后获得的中间产品的结构示意图。
图19为本发明的实施例2的倒装芯片的封装方法中执行步骤208之后获得的中间产品的俯视图。
图20为本发明的实施例2的倒装芯片的封装方法中执行步骤208之后获得的中间产品的侧视图。
图21为本发明的实施例2的倒装芯片的封装方法中执行步骤209之后获得的中间产品的结构示意图。
图22为本发明的实施例2的倒装芯片的封装方法中执行步骤210之后获得的中间产品的结构示意图。
图23为本发明的实施例2的倒装芯片的封装方法中执行步骤211之后获得的产品的结构示意图。
具体实施方式
下面通过实施例的方式进一步说明本发明，但并不因此将本发明限制在所述的实施例范围之中。
实施例1
如图1所示，本实施例的倒装芯片的封装方法包括以下步骤：
步骤101、将多个倒装芯片1以阵列的方式排布在硅基片2表面，并使得倒装芯片1的电极表面与硅基片2的表面相接触，其中优选地，相邻两个倒装芯片1之间的距离为6mm，执行步骤101之后获得的中间产品的结构示意图如图2所示。
步骤102、在倒装芯片1的阵列表面浇筑有机玻璃3，并将有机玻璃3表面压平且使其固化干燥，以形成一个厚度为2mm的有机薄片，并将所述有机薄片作为封装基板，执行步骤102之后获得的中间产品的结构示意图如图3所示。
步骤103、去除硅基片2，具体可以采用磨削或者化学方式去除掉，并且使得倒装芯片1嵌入封装基板中且倒装芯片的电极表面与封装基板的表面位于同一平面，这样就获得了具有倒装芯片1阵列嵌入的封装基板，并且使得倒装芯片1的电极表面与封装基板的表面很好的重合，执行步骤103之后获得的中间产品的结构示意图如图4所示。
步骤104、在倒装芯片1的电极表面和封装基板的表面镀金属导电膜，以作为电铸工艺的电极，其中金属导电膜包括金导电层4和铬导电层5，且所述铬导电层5位于倒装芯片1的电极表面和封装基板的表面的上方，所述金导电层4位于所述铬导电层5的上方，优选地，所述金导电层4的厚度为50nm，所述铬导电层5的厚度为20nm，执行步骤104之后获得的中间产品 的结构示意图如图5所示。
步骤105、在金属导电膜的表面(具体为所述金导电层4)涂覆光刻胶6，在本实施例中，所述光刻胶为AZ4620光刻胶，并具体以旋转的方式涂覆所述AZ4620光刻胶，旋转速度为每分钟1000转，然后在90℃的烘箱内烘干，执行步骤105之后获得的中间产品的结构示意图如图6所示。
步骤106、在光刻机上将光刻板上的电极结构与倒装芯片1的电极结构对准并进行光刻，并在曝光和显影之后获得倒装芯片1的电极表面和封装基板的表面处于同一区域的光刻胶结构模，并使得倒装芯片1的电极之间的绝缘部位覆盖有光刻胶6，执行步骤106之后获得的中间产品的结构示意图如图7所示。
步骤107、利用所述金属导电膜进行光刻胶结构模内的铜电铸生长，具体操作为将所述金属导电膜作为电极，在所述光刻胶结构模内的倒装芯片1的电极表面和封装基板的表面同时电铸金属铜7，控制时间和生长速度，以保证倒装芯片1的电极表面和相应封装基板处于同一区域的光刻胶结构模内长满金属铜7，并实现倒装芯片1的电极和封装基板之间通过金属铜7连接，执行步骤107之后获得的中间产品的结构示意图如图8所示。
步骤108、利用溶胶液将没有曝光的光刻胶6溶解掉，执行步骤108之后获得的中间产品的结构示意图如图9所示。
步骤109、利用金腐蚀液腐蚀掉步骤108中去除的光刻胶下所覆盖的金导电层，并利用铬腐蚀液腐蚀掉金导电层所覆盖的铬导电层，从而切断倒装芯片电极之间的电连接，执行步骤109之后获得的中间产品的结构示意图如图10所示。
步骤110、利用有机玻璃溶剂，将所述有机薄片(即封装基板)溶解掉，从而完成倒装芯片2的封装，执行步骤110之后获得的产品的结构示意图如图11所示。
其中，在本实施例中，所述倒装芯片具体可为LED倒装芯片，在具体 实施过程中，所述倒装芯片1的电极表面本身可设有或不设有金属层，所述封装基板的表面本身也可设有或不设有金属层。
实施例2
本实施例与实施例1的主要区别在于：在本实施例中，所述封装基板采用陶瓷封装基板，如图12所示，本实施例的倒装芯片的封装方法包括以下步骤：
步骤201、将多个倒装芯片1嵌入陶瓷封装基板8中，本实施例中，所述倒装芯片具体为1mm长、1mm宽、0.35mm厚的LED倒装芯片，型号具体为CREEDA1000，具体操作为：设置厚度(约0.6mm)稍大于倒装芯片1的厚度的陶瓷封装基板8，每个陶瓷封装基板8的单位中心设有和芯片形状一致但尺寸稍大的镂空缺口，在陶瓷封装基板8有一侧面设置有和倒装芯片1的两个电极相对应且相互绝缘的金属层以及和金属层存在金属连接的通孔用于外接热沉；执行步骤201之后获得的中间产品的俯视图和侧视图分别如图13和14所示。
步骤202、将陶瓷封装基板8的设有金属层的一面向下放置在硅片表面，将倒装芯片1的电极表面向下放入陶瓷封装基板8的镂空中，在倒装芯片1的出光表面涂覆荧光胶9，也可以设置荧光膜，执行步骤202之后获得的中间产品的结构示意图如图15所示。
步骤203、在陶瓷封装基板8的镂空中浇筑硅胶10，待浇筑材料固化干燥，从而使得倒装芯片1和陶瓷封装基板8通过硅胶10固定，执行步骤203之后获得的中间产品的结构示意图如图16所示。
步骤204、将硅片以磨削或化学方式去除，从而获得具有倒装芯片1通过硅胶10和陶瓷封装基板8固定的阵列，并且倒装芯片1的电极表面与陶瓷封装基板8的表面很好的重合。
步骤205、在陶瓷封装基板8的设有金属层的一面以及倒装芯片1的电极表面设置所述金属导电膜，所述金属导电膜同样包括金导电层4和铬导电 层5，具体设置与实施例1的步骤104中相同，执行步骤205之后获得的中间产品的结构示意图如图17所示。
步骤206、在金属导电膜的表面(具体为所述金导电层4)涂覆光刻胶6，执行方式与实施例1的步骤105中相同，执行步骤206之后获得的中间产品的结构示意图如图18所示。
步骤207、在光刻机上将光刻板上的电极结构的一部分与倒装芯片1上的电极结构对准并进行光刻，然后曝光，是倒装芯片1的一个电极N和相对应的陶瓷封装基板8表面金属在一个区域内，另一个电极P的相对应的陶瓷封装基板8的表面金属在另一个区域内。
步骤208、将曝光的光刻胶进行显影，获得单个倒装芯片的电极表面和相应的陶瓷封装基板8的表面在同一区域的光刻胶结构模，并使得倒装芯片1的电极之间的绝缘部位覆盖有光刻胶6，执行步骤208之后获得的中间产品的俯视图和侧视图分别如图19和20所示。
步骤209、利用所述金属导电膜进行光刻胶结构模内的铜电铸生长，具体操作与实施例1的步骤107中相同，执行步骤209之后获得的中间产品的结构示意图如图21所示。
步骤210、利用溶胶液将没有曝光的光刻胶6溶解掉，执行步骤210之后获得的中间产品的结构示意图如图22所示。
步骤211、利用金腐蚀液腐蚀掉步骤210中去除的光刻胶下所覆盖的金导电层，并利用铬腐蚀液腐蚀掉金导电层所覆盖的铬导电层，从而切断倒装芯片电极之间的电连接，执行步骤211之后获得的产品的结构示意图如图23所示。
虽然以上描述了本发明的具体实施方式，但是本领域的技术人员应当理解，这些仅是举例说明，本发明的保护范围是由所附权利要求书限定的。本领域的技术人员在不背离本发明的原理和实质的前提下，可以对这些实施方式做出多种变更或修改，但这些变更和修改均落入本发明的保护范围。

Claims (12)

  1. 一种倒装芯片的封装方法，其特征在于，在倒装芯片的电极表面和封装基板的表面同时电铸金属，并实现倒装芯片的电极和封装基板之间通过所述金属连接。
  2. 如权利要求1所述的封装方法，其特征在于，包括以下步骤：
    S1、在倒装芯片周围设置封装基板；
    S2、在倒装芯片的电极表面和封装基板的表面镀金属导电膜；
    S3、在金属导电膜的表面涂覆光刻胶；
    S4、在光刻机上将光刻板上的电极结构与倒装芯片的电极结构对准并进行光刻，并在曝光和显影之后获得倒装芯片的电极表面和封装基板的表面处于同一区域的光刻胶结构模，并使得倒装芯片的电极之间的绝缘部位覆盖有光刻胶；
    S5、将所述金属导电膜作为电极，在所述光刻胶结构模内的倒装芯片的电极表面和封装基板的表面同时电铸所述金属，并使得所述光刻胶结构模内长满所述金属，以实现倒装芯片的电极和封装基板之间通过所述金属连接；
    S6、去除步骤S4中覆盖在所述绝缘部位的光刻胶及光刻胶覆盖的金属导电膜。
  3. 如权利要求2所述的封装方法，其特征在于，步骤S6之后还包括：
    S7、去除所述封装基板。
  4. 如权利要求2-3中至少一项所述的封装方法，其特征在于，所述金属导电膜包括金导电层和铬导电层，所述铬导电层位于倒装芯片的电极表面和封装基板的表面的上方，所述金导电层位于所述铬导电层的上方。
  5. 如权利要求4所述的封装方法，其特征在于，所述金导电层的厚度为20-400nm，所述铬导电层的厚度为20-400nm。
  6. 如权利要求2-5中至少一项所述的封装方法，其特征在于，所述光 刻胶为AZ4620光刻胶、AZ-50XT光刻胶、SU8光刻胶或PMMA光刻胶。
  7. 如权利要求2-6中至少一项所述的封装方法，其特征在于，步骤S3中以滩涂的方式涂覆所述光刻胶。
  8. 如权利要求2-6中至少一项所述的封装方法，其特征在于，步骤S3中以旋转的方式涂覆所述光刻胶，旋转速度为每分钟200-6000转。
  9. 如权利要求1-8中至少一项所述的封装方法，其特征在于，所述金属为铜、镍或金。
  10. 如权利要求4-5中至少一项所述的封装方法，其特征在于，步骤S6包括：
    S61、通过溶胶液溶解掉覆盖在所述绝缘部位的光刻胶；
    S62、通过金腐蚀液腐蚀掉光刻胶覆盖的金导电层；
    S63、通过铬腐蚀液腐蚀掉金导电层覆盖的铬导电层。
  11. 如权利要求1-10中至少一项所述的封装方法，其特征在于，所述倒装芯片的电极表面设有或不设有金属层。
  12. 如权利要求1-11中至少一项所述的封装方法，其特征在于，所述封装基板的表面设有或不设有金属层。
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