JP5748336B2 - 半導体装置の製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 99
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 239000011347 resin Substances 0.000 claims description 87
- 229920005989 resin Polymers 0.000 claims description 87
- 238000000034 method Methods 0.000 claims description 42
- 239000007788 liquid Substances 0.000 claims description 20
- 238000002347 injection Methods 0.000 claims description 11
- 239000007924 injection Substances 0.000 claims description 11
- 238000007639 printing Methods 0.000 claims description 8
- 238000007599 discharging Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000001179 sorption measurement Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 230000003466 anti-cipated effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H01L2224/76—Apparatus for connecting with build-up interconnects
- H01L2224/7615—Means for depositing
- H01L2224/76151—Means for direct writing
- H01L2224/76155—Jetting means, e.g. ink jet
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- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/821—Forming a build-up interconnect
- H01L2224/82101—Forming a build-up interconnect by additive methods, e.g. direct writing
- H01L2224/82102—Forming a build-up interconnect by additive methods, e.g. direct writing using jetting, e.g. ink jet
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- H—ELECTRICITY
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- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
- H01L2224/83874—Ultraviolet [UV] curing
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- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
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- Manufacturing & Machinery (AREA)
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Description
まず、図1(d)に基づいてLEDパッケージの構成を説明する。
まず、絶縁性樹脂注入工程で、図1(a)に示すように、ディスペンサ20(又はインクジェット装置)によって紫外線硬化型又は熱硬化型の液状の絶縁性樹脂16を素子搭載凹部12内に注入する。この際、絶縁性樹脂16の注入量は、素子搭載凹部12の容積よりLED素子13の体積分だけ少ない量に設定する。
尚、本発明は、上記各実施例1〜3のようなLED素子等の発光素子の搭載構造に限定されず、上面に電極部が設けられた様々な半導体素子の搭載構造に適用可能である等、要旨を逸脱しない範囲内で種々変更して実施できる。
Claims (4)
- 搭載部材に形成した素子搭載凹部内に半導体素子を搭載し、該半導体素子上面の電極部と該搭載部材上面の電極部とを配線で接続した半導体装置の製造方法において、
前記素子搭載凹部の容積より前記半導体素子の体積分だけ少ない量の液状の絶縁性樹脂を該素子搭載凹部内に注入する工程と、
吸着ノズルに前記半導体素子を吸着して該半導体素子を前記素子搭載凹部内の絶縁性樹脂の液中に浸すように下降させて該半導体素子上面の電極部の高さ位置が前記搭載部材上面の電極部の高さ位置と一致したときに該半導体素子の下降をストップさせる素子セット工程と、
前記素子搭載凹部内の絶縁性樹脂を硬化させて前記半導体素子を該絶縁性樹脂で固定すると共に、該半導体素子上面の電極部と前記搭載部材上面の電極部との間の配線経路を該絶縁性樹脂で平坦化し、前記吸着ノズルによる該半導体素子の吸着を解除して該吸着ノズルを元の位置へ戻す工程と、
前記配線経路に前記配線を形成する配線形成工程と
を含むことを特徴とする半導体装置の製造方法。 - 搭載部材に形成した素子搭載凹部内に半導体素子を搭載し、該半導体素子上面の電極部と該搭載部材上面の電極部とを配線で接続した半導体装置の製造方法において、
吸着ノズルに前記半導体素子を吸着して該半導体素子を前記素子搭載凹部内に下降させて該半導体素子上面の電極部の高さ位置が前記搭載部材上面の電極部の高さ位置と一致したときに該半導体素子の下降をストップさせる素子セット工程と、
前記素子搭載凹部内の前記半導体素子の周囲の隙間に液状の絶縁性樹脂を注入して該絶縁性樹脂の液面が該半導体素子上面の電極部と同一高さになったときに該絶縁性樹脂の注入を停止する工程と、
前記素子搭載凹部内の絶縁性樹脂を硬化させて前記半導体素子を該絶縁性樹脂で固定すると共に、該半導体素子上面の電極部と前記搭載部材上面の電極部との間の配線経路を該絶縁性樹脂で平坦化して、前記吸着ノズルによる該半導体素子の吸着を解除して該吸着ノズルを元の位置へ戻す工程と、
前記配線経路に前記配線を形成する配線形成工程と
を含むことを特徴とする半導体装置の製造方法。 - 前記吸着ノズルには、前記素子セット工程で該吸着ノズルに吸着した半導体素子上面の電極部の高さ位置が前記搭載部材上面の電極部の高さ位置と一致したときに該搭載部材上面に当接して該吸着ノズルの下降をストップさせるストッパーが設けられていることを特徴とする請求項1又は2に記載の半導体装置の製造方法。
- 前記配線形成工程で、液滴吐出法又は印刷法により前記配線経路に前記配線を形成することを特徴とする請求項1乃至3のいずれかに記載の半導体装置の製造方法。
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JP6037544B2 (ja) * | 2012-06-19 | 2016-12-07 | 富士機械製造株式会社 | Ledパッケージ及びその製造方法 |
JP6037545B2 (ja) * | 2012-06-19 | 2016-12-07 | 富士機械製造株式会社 | Ledパッケージ及びその製造方法 |
JP6149932B2 (ja) * | 2013-07-31 | 2017-06-21 | 富士電機株式会社 | 半導体装置 |
WO2016039593A1 (ko) | 2014-09-12 | 2016-03-17 | 주식회사 세미콘라이트 | 반도체 발광소자의 제조 방법 |
KR101638124B1 (ko) * | 2014-10-23 | 2016-07-11 | 주식회사 세미콘라이트 | 반도체 발광소자 및 이의 제조 방법 |
KR101638125B1 (ko) * | 2014-10-23 | 2016-07-11 | 주식회사 세미콘라이트 | 반도체 발광소자 및 이의 제조 방법 |
CN105161436B (zh) * | 2015-09-11 | 2018-05-22 | 柯全 | 倒装芯片的封装方法 |
EP3471135A4 (en) * | 2016-06-08 | 2019-05-01 | Fuji Corporation | CIRCUIT FORMING METHOD |
WO2018056788A1 (ko) * | 2016-09-26 | 2018-03-29 | 주식회사 세미콘라이트 | 반도체 발광소자 및 이의 제조 방법 |
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JPS63147339A (ja) * | 1986-12-11 | 1988-06-20 | Nec Ic Microcomput Syst Ltd | 半導体装置 |
JP2005050911A (ja) * | 2003-07-30 | 2005-02-24 | Seiko Epson Corp | 半導体装置 |
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