WO2017008493A1 - 导电过孔结构、阵列基板和显示装置的制作方法 - Google Patents

导电过孔结构、阵列基板和显示装置的制作方法 Download PDF

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WO2017008493A1
WO2017008493A1 PCT/CN2016/071615 CN2016071615W WO2017008493A1 WO 2017008493 A1 WO2017008493 A1 WO 2017008493A1 CN 2016071615 W CN2016071615 W CN 2016071615W WO 2017008493 A1 WO2017008493 A1 WO 2017008493A1
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Prior art keywords
insulating layer
metal
forming
organic insulating
layer
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PCT/CN2016/071615
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English (en)
French (fr)
Inventor
林致远
黄寅虎
邹志翔
操彬彬
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to EP16739383.4A priority Critical patent/EP3324427A4/en
Priority to US15/114,219 priority patent/US10134770B2/en
Publication of WO2017008493A1 publication Critical patent/WO2017008493A1/zh

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    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel

Definitions

  • At least one embodiment of the present invention is directed to a method of fabricating a conductive via structure, a method of fabricating an array substrate, and a method of fabricating a display device.
  • the requirements for the resistance of the structure such as the gate line and the data line in the metal layer also increase.
  • the mainstream aluminum wiring has been unable to meet the display performance requirements due to its high resistivity.
  • the resistivity of copper is 30% lower than that of aluminum. Therefore, the use of copper metal to form gate lines and data lines in metal layers has become the mainstream choice.
  • a common electrode disposed on an array substrate may occur in a liquid crystal display.
  • a metal layer for example, a gate metal layer or a source/drain metal layer
  • Capacitance which causes the display to consume too much power.
  • organic insulating layer for example, a resin layer
  • the combination of a copper metal layer and an organic insulating layer can simultaneously reduce resistance and capacitance, greatly reduce impedance, reduce energy consumption, and improve product performance.
  • At least one embodiment of the present invention provides a method for fabricating a conductive via structure, a method for fabricating the array substrate, and a method for fabricating the display device, so as to avoid the metal structure on the array substrate as much as possible while minimizing cost Poor contact between the metal structure and other components caused by severe oxidation after the formation of the organic insulating layer.
  • At least one embodiment of the present invention provides a method of fabricating an array substrate, the method comprising: forming a first metal layer including a first metal structure; forming a non-metal layer film on the first metal layer, The non-metal layer film includes a first portion corresponding to the first metal structure; an organic insulating layer film is formed on the non-metal layer film, and the organic insulating layer film is patterned Forming a first organic insulating layer via corresponding to the first portion; baking the organic insulating layer film subjected to the patterning treatment to form an organic insulating layer; and after forming the organic insulating layer, The first portion of the non-metal layer film is removed to form a non-metal layer and expose a portion of the surface of the first metal structure.
  • At least one embodiment of the present invention also provides a method of fabricating an array substrate, the method comprising: forming an insulating layer film; forming an organic insulating layer film on the insulating layer film, and patterning the organic insulating layer film Processing to form a plurality of organic insulating layer vias, such that an orthographic projection of the plurality of organic insulating layer vias on the surface of the insulating layer film overlaps with the insulating layer film; The organic insulating layer film is baked to form an organic insulating layer; and the insulating layer film is etched by using the organic insulating layer as a mask to form an insulating layer and the insulating layer Multiple insulation layers are through holes.
  • At least one embodiment of the present invention provides a method of fabricating a display device, the display device including an array substrate, the method comprising: fabricating the array substrate by the above-described fabrication method.
  • At least one embodiment of the present invention provides a method of fabricating a conductive via structure, the method comprising: forming a metal layer, the metal layer comprising a metal structure; forming a non-metal layer film on the metal layer, the non- The metal layer film includes a portion corresponding to the metal structure; an organic insulating layer film is formed on the non-metal layer film, and the organic insulating layer film is patterned to form an organic insulating layer via, the organic insulating layer a via hole corresponding to the portion of the non-metal layer film; a baking treatment of the organic insulating layer film subjected to the patterning treatment to form an organic insulating layer; and after forming the organic insulating layer, removing the portion The portion of the non-metal layer film is formed to form a non-metal layer and expose a portion of the surface of the metal structure.
  • 1 is a partial cross-sectional view of an array substrate
  • FIG. 2a is a cross-sectional view of the array substrate shown in FIG. 1 at a common electrode line before forming an organic insulating layer;
  • FIG. 2b is a cross-sectional view of the array substrate shown in FIG. 1 at a common electrode line after forming an organic insulating layer schematic diagram;
  • FIG. 3 is a flowchart of a method for fabricating an array substrate according to an embodiment of the present invention.
  • FIGS. 4a to 4c are schematic diagrams showing steps of fabricating a first metal layer, a first insulating layer, and an organic insulating layer in an array substrate by using the fabrication method provided by the embodiment of the present invention
  • FIG. 5 is a schematic top plan view of an array substrate which can be fabricated by using the manufacturing method provided by the embodiment of the invention
  • 6a is a partial cross-sectional view of an array substrate which can be fabricated by using the manufacturing method provided by the embodiment of the present invention
  • 6b is a partial cross-sectional view of an array substrate which can be fabricated by using the manufacturing method provided by the embodiment of the present invention
  • FIGS. 7a to 7c are schematic diagrams showing steps of fabricating a first metal layer, a first sub-insulating layer, a second sub-insulating layer, and an organic insulating layer in an array substrate by using the fabrication method provided by the embodiment of the present invention
  • FIGS. 8a to 8d are schematic diagrams showing steps of fabricating a first metal layer, a second insulating layer, a first insulating layer, and an organic insulating layer in an array substrate by using the manufacturing method provided by the embodiment of the present invention
  • FIGS. 9a to 9c are schematic diagrams showing steps of fabricating a first metal layer, a first insulating layer, a second insulating layer, and an organic insulating layer in an array substrate by using the fabrication method provided by the embodiment of the present invention
  • FIG. 10 is a partial cross-sectional view of an array substrate which can be fabricated by using the manufacturing method provided by the embodiment of the present invention
  • 11a to 11c are schematic diagrams showing steps of fabricating a second metal layer, a first insulating layer, and an organic insulating layer in an array substrate by using the fabrication method provided by the embodiment of the present invention
  • 12a to 12e are schematic diagrams showing steps of fabricating a first metal layer, an active layer, and an organic insulating layer in an array substrate by using the fabrication method provided by the embodiment of the present invention
  • FIG. 13 is a flowchart of another method for fabricating an array substrate according to an embodiment of the present invention.
  • 14a to 14c are schematic views showing steps of fabricating an insulating layer and an organic insulating layer in an array substrate by using the manufacturing method provided by the embodiment of the present invention
  • FIG. 15 is a flowchart of a method for fabricating a conductive via structure according to an embodiment of the present invention.
  • FIG. 1 is a partial cross-sectional view of an array substrate in an ADS mode.
  • a thin film transistor 100, a passivation layer 200, a pixel electrode 300, an organic insulating layer 400, and a common electrode 500 are sequentially disposed on a base substrate.
  • the thin film transistor 100 may employ a bottom gate structure including a gate electrode 110, a gate insulating layer 120, a source electrode 131, a drain electrode 132, and an active layer 140 in contact with the source electrode 131 and the drain electrode 132.
  • the fabrication process of the array substrate shown in FIG. 1 includes, for example, the following steps 1 to 8, which are described in detail below.
  • Step 1 Forming a gate metal layer film, patterning it to form a gate metal layer, the gate metal layer including the gate electrode 110, the common electrode line, and the plurality of gate lines (the common electrode line and the gate line are not shown in FIG. 1) ).
  • Step 2 forming a gate insulating film, the gate insulating film covering the gate 110, the common electrode line, and the gate line formed in the step 1.
  • Step 3 forming a source/drain metal layer film on the gate insulating layer film, patterning the same to form a source/drain metal layer, and the source/drain metal layer includes a source 131, a drain 132, and a plurality of data lines (FIG. 1) Not shown).
  • Step 4 An active layer film is formed, patterned to form an active layer 140, and the active layer 140 is in contact with the source 131 and the drain 132.
  • Step 5 forming a passivation layer film on the active layer 140, patterning it to form a passivation layer 200, a gate insulating layer 120, a plurality of passivation layer vias in the passivation layer 200, and A plurality of vias penetrating the passivation layer 200 and the gate insulating layer 120.
  • the plurality of passivation layer vias located in the passivation layer 200 may include: a portion of the surface exposing the drain 132 for connecting the drain 132 with the first passivation layer via 200a of the subsequently formed pixel electrode, And exposing a portion of the surface of the data line for connecting the data line to the second passivation layer via (not shown in FIG. 1) of the source drive circuit (not shown in FIG. 1).
  • a plurality of vias (not shown in FIG. 1) penetrating the passivation layer 200 and the gate insulating layer 120 may include: exposing a portion of the surface of the gate line for connecting the gate line to the gate driving circuit (FIG. 1) A via hole is not shown in the middle; and a portion of the surface of the common electrode line is exposed for connecting the common electrode line and the via hole of the subsequently formed common electrode.
  • Step 6 Forming the pixel electrode 300 on the passivation layer 200, and connecting the pixel electrode 300 to the drain electrode 132 through the first passivation layer via 200a formed in the step 5.
  • Step 7 An organic insulating layer 400 is formed.
  • forming the organic insulating layer 400 includes: forming an organic insulating layer film; thereafter, patterning the organic insulating layer film to form a plurality of organic insulating layer via holes; thereafter, drying the patterned organic insulating layer film
  • the baking treatment for example, the baking temperature is greater than or equal to 200 ° C to obtain the organic insulating layer 400.
  • the organic insulating layer via may include via holes corresponding to the first and second passivation layer vias formed in the step 5, and the via holes penetrating through the passivation layer 200 and the gate insulating layer 120, respectively.
  • Step 8 A common electrode 500 is formed on the organic insulating layer 400, and the common electrode 500 is connected to the common electrode line through the via hole formed in the portion of the surface of the common electrode line formed in the step 5 and the corresponding via hole formed in the step 7.
  • the inventors of the present application noticed that since the organic insulating layer 400 needs to be subjected to a high-temperature baking treatment in the manufacturing process (for example, a baking temperature of 200 ° C or more), and since the copper metal material is easily oxidized, A metal structure made of a copper metal material and having been exposed to a part of the surface before the formation of the organic insulating layer 400 (for example, a structure including a gate metal layer and/or a source/drain metal layer), the exposed portion of the surface is formed with an organic insulating layer After 400 is severely oxidized, which may cause the metal structure to be in poor contact with other components at the surface of the portion.
  • a high-temperature baking treatment in the manufacturing process for example, a baking temperature of 200 ° C or more
  • the via hole 210 penetrating the gate insulating layer 120 and the passivation layer 200 has exposed a part of the surface of the common electrode line 110a before the organic insulating layer 400 is formed. 111; After the organic insulating layer 400 is formed, part of the surface 111 of the common electrode line 110a is severely oxidized, which easily causes poor contact between the common electrode 500 and the common electrode line 110a.
  • Embodiments of the present invention provide a method for fabricating a conductive via structure, a method for fabricating an array substrate, and a method for fabricating a display device.
  • the embodiment of the present invention enables the metal structure to be formed before forming an organic insulating layer over the metal structure. Part of the surface is covered by the non-metal layer, and the portion of the non-metal layer covering the surface of the portion is removed after the organic insulating layer is formed, and the metal structure can be prevented from being severely formed after the organic insulating layer is formed, while minimizing the cost. Oxidation.
  • a method for fabricating an array substrate includes: forming a first metal layer including a first metal structure; forming a non-metal layer film on the first metal layer to make a non-metal layer
  • the film includes a first portion corresponding to the first metal structure; an organic insulating layer film is formed on the non-metal layer film, and the organic insulating layer film is patterned to form a first organic insulating layer via corresponding to the first portion;
  • the treated organic insulating layer film is subjected to a baking treatment to form an organic insulating layer; and after the organic insulating layer is formed, the first portion of the non-metal layer film is removed to form a non-metal layer and expose a part of the surface of the first metal structure.
  • the method can avoid the metal structure being severely oxidized after forming the organic insulating layer at a low cost.
  • forming the non-metal layer may include etching the first portion of the non-metal layer film with the organic insulating layer as a mask. This saves the mask.
  • the embodiment provides a method for fabricating an array substrate.
  • the non-metal layer film on the first metal layer includes a first insulating layer film, and the non-metal layer includes a first insulating layer and a first a first via in the insulating layer, the first via exposing the portion of the surface of the first metal structure.
  • the method for fabricating the array substrate may include the following steps S11 to S14, which are described in detail below.
  • Step S11 As shown in FIG. 4a, a first metal layer 01 is formed, and the first metal layer 01 includes a first metal structure 01a.
  • the first metal layer 01 can be formed in a manner commonly used in the art, and will not be described herein.
  • Step S12 As shown in FIG. 4a, a first insulating layer film 71' is formed on the first metal layer 01, and the first insulating layer film 71' includes a first portion 71a corresponding to the first metal structure 01a (ie, the first The orthographic projection of the portion 71a on the face of the first metal structure 01a overlaps with the first metal structure 01a).
  • the A structure corresponding to the B structure means that the front projection of the A structure on the surface of the B structure overlaps with the B structure.
  • Step S13 forming an organic insulating layer film 40' on the first insulating layer film 71' as shown in FIG. 4a; patterning the organic insulating layer film 40' to form a first organic insulating layer via 41, such as As shown in FIG. 4b, the first organic insulating layer via 41 corresponds to the first portion 71a of the first insulating layer film 71' (ie, corresponding to the first metal structure 01a), and then the patterned organic insulating layer film 40' is performed. The baking treatment is performed to form the organic insulating layer 40.
  • the first organic insulating layer via 41 corresponds to the first portion of the first insulating layer film 71', that is, the process of patterning the organic insulating film 40', before performing the baking process.
  • the first portion 71a of the first insulating layer film 71' needs to be retained to avoid exposing the first metal structure 01a.
  • the temperature of the baking treatment is greater than or equal to 200 °C. It should be noted that the temperature range of the baking treatment is a temperature range commonly used in the art, and is only used to exemplify the baking treatment, and the present embodiment is not limited.
  • the patterning process in the present embodiment may be any process capable of forming a set pattern in the film, and may be, for example, a process of forming a set pattern by using a mask.
  • Step S14 As shown in FIG. 4c, after the organic insulating layer 40 is formed, the first portion 71a of the first insulating layer film 71' is removed to form the first insulating layer 71 and is located in the first insulating layer 71 and exposed to the first The first via 701 of the partial surface 011 of the metal structure 01a.
  • the first portion 71a of the first insulating layer film 71' may be removed by performing a via process (ie, a process of forming via holes in the insulating layer) on the first insulating layer film 71' using a mask.
  • a via process ie, a process of forming via holes in the insulating layer
  • the first portion 71a of the first insulating layer film 71' may be etched (e.g., dry-etched) using the organic insulating layer 40 as a mask to form the first insulating layer 71 and the first via 701.
  • the organic insulating layer 40 as a mask, the mask for performing the via process on the first insulating layer film can be omitted, thereby reducing the cost.
  • the organic insulating layer 40 may be slightly deformed. Therefore, after the first insulating layer 71 and the first via 701 are formed, the organic insulating layer 40 is subjected to, for example, ashing treatment.
  • the process of forming a via hole in the first insulating layer film between the first metal structure and the organic insulating layer is adjusted to be performed after the organic insulating layer is formed, so that the baking process is performed.
  • the first metal structure is protected by the first insulating layer film to avoid poor contact between the first metal structure and other components due to severe oxidation of the metal structure;
  • the embodiment merely changes the order of the via process of the non-metal layer (for example, the first insulating layer) between the first metal structure and the organic insulating layer. No additional processes have been added and no additional manufacturing costs have been added.
  • a mask for performing a via process on the non-metal layer film (for example, the first insulating layer film) can be omitted, so that the cost can be reduced.
  • This embodiment is applicable to a first metal structure made of a material such as copper metal or copper alloy, that is, the material for forming the first metal structure 01a includes copper metal or copper alloy, because copper is compared with metal materials such as aluminum and molybdenum. The degree of oxidation at higher temperatures is more severe and it is more likely to cause poor contact between the first metal structure and other components.
  • the material for forming the first metal structure 01a is not limited to copper metal or copper alloy, and may be other metals which are severely oxidized after the formation of the organic insulating layer 40 to cause poor contact at the oxidized position.
  • the organic insulating layer 40 Since the function of the organic insulating layer 40 is mainly to increase the distance between the common electrode layer and the metal layer under the common electrode layer, the parasitic capacitance between the common electrode in the common electrode layer and the metal structure in the metal layer is reduced. To reduce power consumption. Therefore, the organic insulating layer 40 has a larger thickness than the other insulating layer located between the common electrode and the metal layer below. For example, the organic insulating layer 40 may have a thickness of 10,000 angstroms to 40,000 angstroms.
  • the inorganic insulating layer (for example, an inorganic insulating layer such as silicon dioxide or silicon nitride) in the array substrate has a thickness of about 4000 angstroms; for example, the thickness of the gate insulating layer may be less than 4000 angstroms; for example, the thickness of the passivation layer. It can range from 2,500 angstroms to 4000 angstroms. Thus, the thickness of the organic insulating layer 40 is much larger than the thickness of the inorganic insulating layer.
  • the material of the organic insulating layer 40 may include a resin (eg, acryl, filter material, etc.).
  • the organic insulating layer 40 is made of these organic materials, so that the organic insulating layer 40 can satisfy both thickness requirements to minimize power consumption and ensure light transmittance.
  • the array substrate may employ a COA (Color Filter On Array) technology, that is, a color filter layer is disposed on the array substrate.
  • COA Color Filter On Array
  • the organic insulating layer 40 It can be a color filter layer.
  • the color filter layer 90 may include a plurality of red filter patterns R, a plurality of green filter patterns G, and a plurality of blue filter patterns B.
  • the gate metal layer and the source/drain metal layer may be disposed on the array substrate.
  • the first metal layer in this embodiment may be a gate metal layer or a source/drain metal layer
  • the first metal structure 01a may be a gate metal layer or
  • the source/drain metal layer includes any metal structure that needs to be exposed to a part of the surface and which may be severely oxidized after forming the organic insulating layer 40, causing poor contact.
  • the first metal layer 01 may be a gate metal layer, and the first metal layer 01 may include a gate electrode 11a, a common electrode line 11c, and a gate line 11b connected to the gate electrode 11a, first The metal structure 01a may include the common electrode line 11c or the gate line 11b; or, the first metal layer 01 may include a gate electrode 11a and a gate line 11b connected to the gate electrode 11a, and the first metal structure 01a may include a gate line 11b.
  • Fig. 6a will be described by taking the first metal structure 01a as the common electrode 11c as an example.
  • the first metal layer 01 may be a source/drain metal layer, and the first metal layer 01 may include a source 13a, a drain 13b, and a data line 13c connected to the source 13a.
  • the first metal structure 01a may include one of the source 13a and the drain 13b or the data line 13c.
  • FIG. 6b will be described by taking the first metal structure 01a as the drain 13b as an example.
  • the thin film transistor 10 is a bottom gate bottom contact structure, that is, the gate electrode 11a is disposed under the active layer 14, and the source electrode 13a and the drain electrode 13b are in contact with the lower surface of the active layer 14.
  • the thin film transistor 10 is a top gate top contact structure, that is, the gate electrode 11a is disposed above the active layer 14, and the source electrode 13a and the drain electrode 13b are in contact with the upper surface of the active layer 14.
  • the embodiment does not limit the type of the thin film transistor 10, that is, the positional relationship between the active layer 14 and the gate electrode 11a in the thin film transistor 10, and the positions of the active layer 14 and the source 13a/drain 13b are not limited. relationship. Further, the present embodiment does not limit the connection relationship between the active layer 14 and the source 13a/drain 13b.
  • an insulating layer may be disposed between the active layer 14 and the source 13a/drain 13b such that the active layer 14 is in contact with the source 13a/drain 13b through via holes; or, for example, the active layer 14 is also It may be connected to the source 13a/drain 13b through a conductive structure.
  • the manufacturing method provided in this embodiment is applicable to an array substrate including a common electrode, that is, the manufacturing method further includes: forming a common electrode 50, the common electrode 50 is disposed on the organic insulating layer 40, and the common electrode 50 is electrically connected to the common electrode line 11c. As shown in Figure 6a.
  • the manufacturing method provided by this embodiment further includes: while forming the common electrode 50 Alternatively, before or after the formation of the common electrode 50, the pixel electrode 30 is formed to connect the pixel electrode 30 with the drain electrode 13b as shown in Fig. 6b.
  • the pixel electrode 30 is located below the common electrode 50. Therefore, the pixel electrode 30 is formed before the common electrode 50.
  • the common electrode 50 is disposed in the same layer as the pixel electrode 30, and therefore, both can be formed at the same time.
  • the first insulating layer 71 may include an insulating layer.
  • the first insulating layer 71 may include a gate insulating layer 12 that is in contact with the gate electrode 11a and located between the gate electrode 11a and the active layer 14, as shown in FIG. 6b, the first insulating layer 71 may A gate insulating layer 12 is included, and the first via 701 may be located in the gate insulating layer 12.
  • the first insulating layer 71 may include a passivation layer covering the thin film transistor.
  • the first insulating layer 71 may also include a plurality of insulating layers.
  • the first insulating layer 71 may include two insulating layers of a first sub-insulating layer 711 (for example, a gate insulating layer 12) and a second sub-insulating layer 712 (for example, a passivation layer 20).
  • a second sub-insulating layer 712 is formed on the first sub-insulating layer 711;
  • the first via 701 includes a first sub-via 701a in the first sub-insulating layer 711 and a second sub-pass in the second sub-insulating layer 712
  • the hole 701b, the first sub-via 701a is in communication with the second sub-via 701b.
  • the manufacturing method of the first insulating layer 71 includes, for example, forming a first sub-insulating layer film 711' and located as shown in FIG. 7a. a second sub-insulating layer film 712' on the first sub-insulating layer film 711' to form a first insulating layer film 71'; thereafter, an organic insulating layer 40 and a first organic insulating layer are formed on the second sub-insulating layer film 712' a layer via 41, as shown in FIG.
  • the organic insulating layer 40 after forming the organic insulating layer 40, part of the material of the first sub-insulating layer film 711' and a portion of the material of the second sub-insulating layer film 712' are removed to expose the first metal a portion of the surface of the structure 01a and forming a first sub-via 701a, a second sub-via 701b, a first sub-insulating layer 711, and a second sub-insulating layer 712, the first insulating layer 71 including a first sub-insulating layer 711 and a second
  • the sub-insulating layer 712, the first via 701 includes a first sub-via 701a and a second sub-via 701b, as shown in FIG. 7c.
  • a second insulating layer may also be formed between the first insulating layer 71 and the organic insulating layer 40.
  • the manufacturing method may include: as shown in FIG. 8a, A second insulating layer 72 is formed on the first metal layer, a via hole 72a in the second insulating layer 72, and a via hole 72a in the second insulating layer 72 corresponds to a part of the surface of the first metal structure 01a; thereafter, as shown in FIG.
  • a first insulating layer film 71' is formed on the second insulating layer 72 such that the material of the first insulating layer film 71' covers the via hole 72a in the second insulating layer 72; thereafter, in the first insulating layer film 71' Forming an organic insulating layer 40 and a first organic insulating layer via 41, the first organic insulating layer via 41 corresponding to the via 72a in the second insulating layer 72, as shown in FIG.
  • a second insulating layer may be formed between the first insulating layer 71 and the first metal layer 01.
  • the fabrication method may include forming via holes 72a in the second insulating layer 72 and the second insulating layer 72 on the first insulating layer film 71', and via holes in the second insulating layer 72 72a corresponds to the first portion 71a of the first insulating layer film 71', as shown in FIG. 9a; thereafter, an organic insulating layer 40 and a first organic insulating layer via 41 are formed on the second insulating layer 72, and the first organic insulating layer passes through The hole 41 corresponds to the via hole 72a in the second insulating layer 72, as shown in FIG.
  • the second metal layer including the second metal structure is formed before the non-metal layer film is formed, and the second metal structure is included when the non-metal layer film is formed. And forming a second organic insulating layer via hole corresponding to the second portion of the non-metal layer film when the organic insulating layer is formed, and removing the second portion to expose the second metal when removing the first portion of the non-metal layer film A portion of the surface of the structure protects the multilayer metal layer on the array substrate to prevent the metal structure in the multilayer metal layer from being severely oxidized after forming the organic insulating layer, resulting in poor contact with other components.
  • non-metal layer film including a first insulating layer film and a second portion of the non-metal layer film as a second portion of the first insulating layer film.
  • the manufacturing method provided in this embodiment may further include: forming a second metal layer 02 before forming the first insulating layer film 71' (for example) For example, a source/drain metal layer), an insulating layer is formed between the second metal layer 02 and the first metal layer 01, the second metal layer includes the second metal structure 02a, and when the first insulating layer film 71' is formed, An insulating layer film 71' further includes a second portion 71b corresponding to the second metal structure 02a; when the organic insulating layer 40 is formed, a second organic insulating layer via 42 in the organic insulating layer 40 is further formed, the second organic insulating layer
  • the via hole 42 corresponds to the second portion 71b of the first insulating layer film 71'; when the first insulating layer 71 is formed, the second via hole 702 is formed in the first insulating layer 71, and the second via hole 702 corresponds to the second organic layer
  • This embodiment is applicable to a second metal structure made of a material such as copper metal or copper alloy, that is, the material for forming the second metal structure 02a may include copper metal or copper alloy.
  • the material for forming the second metal structure 02a is not limited to copper metal or copper alloy, and may be other metals which are severely oxidized after the formation of the organic insulating layer 40 to cause poor contact at the oxidized position.
  • one of the first metal layer 01 and the second metal layer 02 may be a gate metal layer, and the other may be a source/drain metal layer.
  • the first metal layer 01 includes a gate electrode 11a, a common electrode line 11c, and a gate line 11b connected to the gate electrode 11a
  • the first metal structure 01a includes a common electrode line 11c or a gate line 11b
  • the second metal layer 02 includes a source 13a, a drain 13b, and a data line 13c connected to the source 13a
  • the second metal structure 02a includes one of the source 13a and the drain 13b or the data line 13c.
  • the first metal layer 01 includes a gate electrode 11a and a gate line 11b connected to the gate electrode 11a
  • the first metal structure 01a includes a gate line 11b
  • the second metal layer 02 includes a source electrode 13a, a drain electrode 13b, and a source
  • the data line 13c to which the pole 13a is connected, the second metal structure 02a includes one of the source 13a and the drain 13b or the data line 13c.
  • the first metal layer 01 includes a source 13a, a drain 13b, and a data line 13c connected to the source 13a, the first metal structure 01a including one of the source 13a and the drain 13b or the data line 13c,
  • the second metal layer 02 includes a gate electrode 11a, a common electrode line 11c, and a gate line 11b connected to the gate electrode 11a, and the second metal structure 02a includes a common electrode line 11c or a gate line 11b.
  • the first metal layer 01 includes a source 13a, a drain 13b, and a data line 13c connected to the source 13a, the first metal structure 01a including one of the source 13a and the drain 13b or the data line 13c,
  • the second metal layer 02 includes a gate electrode 11a and a gate line 11b connected to the gate electrode 11a, and a second gold layer
  • the genus structure 02a includes a gate line 11b.
  • 11a to 11c illustrate only the first metal layer 01 as a gate metal layer and the second metal layer 02 as a source/drain metal layer.
  • the non-metal layer film further includes an active layer pattern, and the material of the first portion includes a material forming the active layer pattern.
  • the material of the first portion includes a material forming the active layer pattern.
  • the manufacturing method may include the following steps S41 to S44, which are described in detail below.
  • Step S41 forming a first metal layer 01, the first metal layer 01 including the first metal structure 01a, as shown in FIG. 12a.
  • the first metal layer 01 can be formed by a patterning process commonly used in the art, and is not described herein.
  • Fig. 12a shows only the first metal structure 01a included in the first metal layer 01, and other metal structures included in the first metal layer 01 are not shown.
  • Step S42 forming an active layer film 14' on the first metal layer 01, as shown in FIG. 12a; patterning the active layer film 14' to form the active layer pattern 14 and the corresponding first metal structure 01a
  • the first portion (retained portion of the active layer film 14') 14a, the first portion 14a is located on the first metal structure 01a as shown in Fig. 12b.
  • the active layer pattern 14 is described by taking only the active layer pattern 14 and the first portion 14a in contact with the first metal structure 01a.
  • the first metal structure 01a may be the drain of the thin film transistor.
  • the active layer pattern 14 may also be on the first metal structure 01a but not in contact therewith.
  • Step S43 forming an organic insulating film 40' on the active layer pattern 14 and the first portion 14a, as shown in FIG. 12c; patterning the organic insulating film 40' to form a first organic insulating layer via 41, and then The patterned organic insulating film 40' is subjected to a baking treatment to form an organic insulating layer 40, and the first organic insulating layer via 41 is located in the organic insulating layer 40 and corresponds to the first portion 14a as shown in FIG. 12d.
  • the temperature of the baking treatment is greater than or equal to 200 °C. It should be noted that the baking treatment The temperature range is a temperature range commonly used in the art, and is only used to exemplify the baking treatment, and is not limited to the embodiment.
  • Step S44 The first portion 14a of the active layer film 14' is removed to expose a portion of the surface 011 of the first metal structure 01a as shown in Fig. 12e.
  • the material forming the active layer pattern covering the surface of the metal structure ie, the first portion 14a
  • the resistance of the semiconductor material The rate is greater than that of the metal, and removal of the semiconductor material covering the first metal structure can avoid increasing the electrical resistance between the first metal structure and the component it is in contact with.
  • Step S44 serves to prevent poor contact between the first metal structure and other components connected thereto due to severe oxidation of the first metal structure.
  • the manufacturing method provided by the present embodiment is low in cost.
  • the method provided in this embodiment can also be used to protect a plurality of metal layers, so that when the active layer film is formed, the active layer film includes portions corresponding to the metal layers respectively, and corresponding organic insulation is formed when the organic insulating layer is formed.
  • the via holes are formed, and the portions corresponding to the metal layers are removed after the organic insulating layer is formed.
  • This embodiment provides a method for fabricating an array substrate. As shown in FIG. 13 and FIGS. 14a to 14c, the method includes the following steps S41 to S43. These steps are described in detail below.
  • Step S41 As shown in Fig. 14a, an insulating layer film 60' is formed.
  • Step S42 forming an organic insulating layer film 40' on the insulating layer film 60', as shown in FIG. 14a; patterning the organic insulating layer film 40' to form a plurality of organic insulating layer via holes 40a, the plurality of organic The orthographic projection of the insulating layer via 40a on the surface of the insulating layer film 60' overlaps with the insulating layer film 60'; thereafter, the patterned organic insulating layer film 40' is baked to form an organic insulating layer. 40, as shown in Figure 14b.
  • the temperature of the baking treatment may be greater than or equal to 200 °C. It should be noted that the temperature range of the baking treatment is a temperature range commonly used in the art, and is only used for exemplifying the baking treatment, and is not limited to the embodiment.
  • the patterning process in the present embodiment may be any process capable of forming a set pattern in the film, and may be, for example, a process of forming a set pattern by using a mask.
  • Step S43 etching the insulating film 60' with the organic insulating layer 40 as a mask to form a plurality of insulating layer vias 60a in the insulating layer 60 and the insulating layer 60, as shown in Fig. 14c.
  • the insulating layer 60 may include a gate insulating layer and/or a passivation layer.
  • the gate insulating layer is in contact with the gate of the thin film transistor in the array substrate and is located between the gate and the active layer of the thin film transistor, and the passivation layer covers the thin film transistor.
  • the organic insulating layer 40 may be slightly deformed. Therefore, for example, after the first insulating layer 71 and the first via 701 are formed, the organic insulating layer may be formed. Layer 40 is subjected to, for example, ashing.
  • the embodiment provides a method for fabricating a display device.
  • the display device includes an array substrate.
  • the method includes: fabricating the array substrate by using the fabrication method provided in any of the above embodiments.
  • the method of fabricating the display device provided in this embodiment can be used to fabricate a liquid crystal display device.
  • the liquid crystal display device may include an array substrate and a counter substrate (for example, a color filter substrate).
  • the array substrate and the opposite substrate are opposed to each other and sealed by a sealant to form a liquid crystal cell filled with a liquid crystal material.
  • Each of the pixel units of the array substrate includes a pixel electrode for applying an electric field to control the degree of rotation of the liquid crystal material to perform a display operation.
  • the method for fabricating the liquid crystal display device may further include the steps of forming the opposite substrate and forming the array substrate and the opposite substrate, and the steps may be made by a method commonly used in the art, which is not described in this embodiment.
  • the embodiment provides a method for fabricating a conductive via structure, the conductive via structure comprising a metal layer having a metal structure, a non-metal layer disposed on the metal layer, and an organic insulating layer disposed on the non-metal layer;
  • the metal structure is covered by the non-metal layer before the organic insulating layer is formed, and the portion of the surface of the non-metal layer covering the metal structure is removed after the organic insulating layer is formed.
  • the metal structure in the conductive via structure can be prevented from being severely oxidized after the formation of the organic insulating layer at a low cost.
  • the method may include the following steps S61 to S64, which are described in detail below.
  • Step S61 forming a metal layer, the metal layer including a metal structure.
  • the forming material of the metal structure includes copper or a copper alloy.
  • Step S62 forming a non-metal layer film on the metal layer, so that the non-metal layer film includes a portion corresponding to the metal structure.
  • the material of the non-metal layer film may include an insulating material or a semiconductor material.
  • Step S63 forming an organic insulating layer film on the non-metal layer film, patterning the organic insulating layer film to form an organic insulating layer via hole, and the organic insulating layer via hole corresponding to the above portion of the non-metal layer film;
  • the treated organic insulating layer film is subjected to a baking treatment to form an organic insulating layer.
  • Step S64 After forming the organic insulating layer, the above portion of the non-metal layer film is removed to form a non-metal layer and expose a part of the surface of the metal structure.
  • the method for fabricating the conductive via structure provided in this embodiment is applicable to the conductive via structure in any electronic device, as long as the conductive via structure has a metal layer, a non-metal layer disposed on the metal layer, and a non-metal layer disposed on the metal via layer.
  • the organic insulating layer on the layer can be used.
  • the conductive via structure may be disposed on the array substrate or may be disposed in other electronic devices.

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Abstract

一种导电过孔结构的制作方法、阵列基板的制作方法和显示装置的制作方法，阵列基板的制作方法包括：依次形成包括第一金属结构（01a）的第一金属层（01）、包括与第一金属结构（01a）对应的第一部分（71a）的非金属层薄膜、以及有机绝缘层薄膜（40'）；在对有机绝缘层薄膜（40'）进行图案化处理以形成对应第一部分（71a）的第一有机绝缘层过孔（41）之后进行烘烤处理以形成有机绝缘层（40）；之后，去除非金属层薄膜的第一部分（71a），以形成非金属层并暴露出第一金属结构（01a）的部分表面（011）。该方法可以避免金属结构被严重氧化。

Description

导电过孔结构、阵列基板和显示装置的制作方法 技术领域
本发明的至少一个实施例涉及一种导电过孔结构的制作方法、阵列基板的制作方法和显示装置的制作方法。
背景技术
在显示技术领域，随着显示器件尺寸的增大以及刷新率的提高等显示性能要求的提高，对金属层中栅线和数据线等结构的电阻的要求也随之提高。目前主流的铝配线由于电阻系数较高，已经不能满足显示性能的要求。而铜的电阻系数比铝的电阻系数低30％，因此，使用铜金属制作金属层中的栅线和数据线等结构成为主流选择。
在液晶显示器中，例如，在采用ADS(高级超维场转换)模式的液晶显示器中，设置在阵列基板上的公共电极与金属层(例如栅金属层或源漏金属层)之间可产生寄生电容，这造成显示器的功耗过大。通过在公共电极和金属层之间形成一层比较厚的有机绝缘层(例如树脂层)可以降低电路电容，从而使功耗降低，这种方式目前已大量应用于产品当中。
铜金属层与有机绝缘层的结合应用可同时减少电阻及电容，大幅降低阻抗，减少能耗，提升产品性能。
发明内容
本发明的至少一个实施例提供了一种导电过孔结构的制作方法、阵列基板的制作方法和显示装置的制作方法，以在尽量减小成本的前提下尽量避免因阵列基板上的金属结构在形成有机绝缘层之后被严重氧化而造成的该金属结构与其他部件之间接触不良。
本发明的至少一个实施例提供了一种阵列基板的制作方法，该方法包括：形成包括第一金属结构的第一金属层；在所述第一金属层上形成非金属层薄膜，使所述非金属层薄膜包括对应所述第一金属结构的第一部分；在所述非金属层薄膜上形成有机绝缘层薄膜，对所述有机绝缘层薄膜进行图案化处理 以形成对应所述第一部分的第一有机绝缘层过孔；对经过所述图案化处理的所述有机绝缘层薄膜进行烘烤处理以形成有机绝缘层；以及在形成所述有机绝缘层之后，去除所述非金属层薄膜的所述第一部分，以形成非金属层并暴露出所述第一金属结构的部分表面。
本发明的至少一个实施例还提供了一种阵列基板的制作方法，该方法包括：形成绝缘层薄膜；在所述绝缘层薄膜上形成有机绝缘层薄膜，对所述有机绝缘层薄膜进行图案化处理以形成多个有机绝缘层过孔，使所述多个有机绝缘层过孔在所述绝缘层薄膜所在面上的正投影与所述绝缘层薄膜有重叠部分；对经过所述图案化处理的所述有机绝缘层薄膜进行烘烤处理以形成有机绝缘层；以及以所述有机绝缘层为掩膜板，对所述绝缘层薄膜进行刻蚀，以形成绝缘层和所述绝缘层中的多个绝缘层过孔。
本发明的至少一个实施例提供了一种显示装置的制作方法，所述显示装置包括阵列基板，所述方法包括：采用上述制作方法制作所述阵列基板。
本发明的至少一个实施例提供了一种导电过孔结构的制作方法，该方法包括：形成金属层，所述金属层包括金属结构；在所述金属层上形成非金属层薄膜，所述非金属层薄膜包括对应所述金属结构的部分；在所述非金属层薄膜上形成有机绝缘层薄膜，对所述有机绝缘层薄膜进行图案化处理以形成有机绝缘层过孔，所述有机绝缘层过孔对应所述非金属层薄膜的所述部分；对经过所述图案化处理的所述有机绝缘层薄膜进行烘烤处理以形成有机绝缘层；以及在形成所述有机绝缘层之后，去除所述非金属层薄膜的所述部分，以形成非金属层并暴露出所述金属结构的部分表面。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1为一种阵列基板的局部剖视示意图；
图2a为图1所示的阵列基板在形成有机绝缘层之前公共电极线处的剖视示意图；
图2b为图1所示的阵列基板在形成有机绝缘层之后公共电极线处的剖视 示意图；
图3为本发明实施例提供的一种阵列基板的制作方法的流程图；
图4a至图4c为采用本发明实施例提供的制作方法制作阵列基板中的第一金属层、第一绝缘层和有机绝缘层的各步骤的示意图；
图5为一种可以采用本发明实施例提供的制作方法制作的阵列基板的俯视示意图；
图6a为一种可以采用本发明实施例提供的制作方法制作的阵列基板的局部剖视示意图；
图6b为一种可以采用本发明实施例提供的制作方法制作的阵列基板的局部剖视示意图；
图7a至7c为采用本发明实施例提供的制作方法制作阵列基板中的第一金属层、第一子绝缘层、第二子绝缘层和有机绝缘层的各步骤的示意图；
图8a至8d为采用本发明实施例提供的制作方法制作阵列基板中的第一金属层、第二绝缘层、第一绝缘层和有机绝缘层的各步骤的示意图；
图9a至9c为采用本发明实施例提供的制作方法制作阵列基板中的第一金属层、第一绝缘层、第二绝缘层和有机绝缘层的各步骤的示意图；
图10为一种可以采用本发明实施例提供的制作方法制作的阵列基板的局部剖视示意图；
图11a至11c为采用本发明实施例提供的制作方法制作阵列基板中的第二金属层、第一绝缘层和有机绝缘层的各步骤的示意图；
图12a至12e为采用本发明实施例提供的制作方法制作阵列基板中的第一金属层、有源层和有机绝缘层的各步骤的示意图；
图13为本发明实施例提供的另一种阵列基板的制作方法的流程图；
图14a至14c为采用本发明实施例提供的制作方法制作阵列基板中的绝缘层和有机绝缘层的各步骤的示意图；
图15为本发明实施例提供的一种导电过孔结构的制作方法的流程图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然， 所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
图1为一种ADS模式的阵列基板的局部剖视示意图。如图1所示，在衬底基板上依次设置有薄膜晶体管100、钝化层200、像素电极300、有机绝缘层400和公共电极500。例如，该薄膜晶体管100可以采用底栅结构，包括栅极110、栅极绝缘层120、源极131、漏极132以及与源极131和漏极132接触的有源层140。
图1所示的阵列基板的制作过程例如包括以下步骤1～步骤8，下面详细介绍这些步骤。
步骤1：形成栅金属层薄膜，对其进行图案化处理以形成栅金属层，栅金属层包括栅极110、公共电极线和多条栅线(图1中未示出公共电极线和栅线)。
步骤2：形成栅极绝缘层薄膜，栅极绝缘层薄膜覆盖步骤1中形成的栅极110、公共电极线和栅线。
步骤3：在栅极绝缘层薄膜上形成源漏金属层薄膜，对其进行图案化处理以形成源漏金属层，源漏金属层包括源极131、漏极132以及多条数据线(图1中未示出)。
步骤4：形成有源层薄膜，对其进行图案化处理以形成有源层140，有源层140与源极131和漏极132接触。
步骤5：在有源层140上形成钝化层薄膜，对其进行图案化处理以形成钝化层200、栅极绝缘层120、位于钝化层200中的多个钝化层过孔、以及贯穿钝化层200和栅极绝缘层120的多个过孔。
例如，位于钝化层200中的多个钝化层过孔可以包括：暴露出漏极132的部分表面以用于连接漏极132与后续形成的像素电极的第一钝化层过孔200a、以及暴露出数据线的部分表面以用于连接数据线与源极驱动电路(图1中未示出)的第二钝化层过孔(图1中未示出)。
例如，贯穿钝化层200和栅极绝缘层120的多个过孔(图1中未示出)可以包括：暴露出栅线的部分表面以用于连接栅线与栅极驱动电路(图1中未示出)的过孔；以及，暴露出公共电极线的部分表面以用于连接公共电极线和后续形成的公共电极的过孔。
步骤6：在钝化层200上形成像素电极300，使像素电极300通过步骤5中形成的第一钝化层过孔200a与漏极132连接。
步骤7：形成有机绝缘层400。例如，形成有机绝缘层400包括：形成有机绝缘层薄膜；之后，对有机绝缘层薄膜进行图案化处理以形成多个有机绝缘层过孔；之后，对经过图案化处理的有机绝缘层薄膜进行烘烤处理，例如，烘烤温度大于或等于200℃，以得到有机绝缘层400。
在该步骤中，有机绝缘层过孔可以包括与步骤5中形成的第一、二钝化层过孔、贯穿钝化层200和栅极绝缘层120的过孔分别对应连通的过孔。
步骤8：在有机绝缘层400上形成公共电极500，公共电极500通过步骤5中形成的暴露出公共电极线的部分表面的过孔以及步骤7中形成的对应的过孔与公共电极线连接。
在研究中，本申请的发明人注意到，由于有机绝缘层400在制作过程中需要进行高温烘烤处理(例如烘烤温度大于或等于200℃)，并且由于铜金属材料容易被氧化，对于采用铜金属材料制作并且在形成有机绝缘层400之前已经被暴露出部分表面的金属结构(例如栅金属层和/或源漏金属层包括的结构)，其被暴露出的部分表面在形成有机绝缘层400后被严重氧化，这可能造成该金属结构在该部分表面处与其它部件接触不良。
例如，如图2a和图2b所示，在形成有机绝缘层400之前，贯穿栅极绝缘层120和钝化层200的过孔210已经暴露出公共电极线110a的部分表面 111；在形成有机绝缘层400之后，公共电极线110a的部分表面111被严重氧化，这容易造成公共电极500与公共电极线110a之间接触不良。
本发明实施例提供了一种导电过孔结构的制作方法、阵列基板的制作方法和显示装置的制作方法，本发明实施例通过在形成位于金属结构上方的有机绝缘层之前，使该金属结构的部分表面被非金属层覆盖，并且在形成有机绝缘层之后才去除该非金属层的覆盖该部分表面的部分，可以在尽量减小成本的前提下避免该金属结构在形成有机绝缘层之后被严重氧化。
如图3所示，本发明的至少一个实施例提供的阵列基板的制作方法包括：形成包括第一金属结构的第一金属层；在第一金属层上形成非金属层薄膜，使非金属层薄膜包括对应第一金属结构的第一部分；在非金属层薄膜上形成有机绝缘层薄膜，对有机绝缘层薄膜进行图案化处理以形成对应第一部分的第一有机绝缘层过孔；对经过图案化处理的有机绝缘层薄膜进行烘烤处理以形成有机绝缘层；以及在形成有机绝缘层之后，去除非金属层薄膜的第一部分，以形成非金属层并暴露出第一金属结构的部分表面。该方法可以在低成本的前提下尽量避免金属结构在形成有机绝缘层之后被严重氧化。
在本发明的一些实施例中，形成非金属层可以包括：以有机绝缘层为掩膜板，对非金属层薄膜的第一部分进行刻蚀。这样可以节省掩膜板。
下面结合实施例一至实施例三对图3所示的制作方法进行描述。
实施例一
本实施例提供了一种阵列基板的制作方法，在该制作方法中，位于上述第一金属层上的上述非金属层薄膜包括第一绝缘层薄膜，上述非金属层包括第一绝缘层和第一绝缘层中的第一过孔，第一过孔暴露出第一金属结构的上述部分表面。
如图4a至4c所示，该阵列基板的制作方法可以包括以下步骤S11至步骤S14，下面详细介绍这些步骤。
步骤S11：如图4a所示，形成第一金属层01，第一金属层01包括第一金属结构01a。
第一金属层01可以采用本领域常用的方式形成，此处不做赘述。
步骤S12：如图4a所示，在第一金属层01上形成第一绝缘层薄膜71’，第一绝缘层薄膜71’包括对应第一金属结构01a的第一部分71a(即，该第一 部分71a在第一金属结构01a所在面上的正投影与第一金属结构01a有重叠部分)。
需要说明的是，在本实施例以及以下各实施例中，A结构对应B结构指：A结构在B结构所在面上的正投影与B结构有重叠部分。
步骤S13：如图4a所示，在上述第一绝缘层薄膜71’上形成有机绝缘层薄膜40’；对有机绝缘层薄膜40’进行图案化处理以形成第一有机绝缘层过孔41，如图4b所示，第一有机绝缘层过孔41对应第一绝缘层薄膜71’的第一部分71a(即，对应第一金属结构01a)，之后对经过图案化处理的有机绝缘层薄膜40’进行烘烤处理以形成有机绝缘层40。
在该步骤中，在进行烘烤处理之前，第一有机绝缘层过孔41对应第一绝缘层薄膜71’的第一部分，也就是说，在对有机绝缘层薄膜40’进行图案化处理的过程中，第一绝缘层薄膜71’的第一部分71a需要保留下来，以避免暴露出第一金属结构01a。
例如，烘烤处理的温度大于或等于200℃。需要说明的是，该烘烤处理的温度范围为本领域常用的温度范围，仅用于对烘烤处理进行举例说明，并不对本实施例进行限定。
需要说明的是，本实施例中的图案化处理可以为任意的能够在薄膜中形成设定图案的处理工艺，例如可以为利用掩模板形成设定图案的工艺。
步骤S14：如图4c所示，在形成有机绝缘层40之后，去除第一绝缘层薄膜71’的第一部分71a，以形成第一绝缘层71和位于第一绝缘层71中且暴露出第一金属结构01a的部分表面011的第一过孔701。
在该步骤中，例如，可以通过利用掩模板对第一绝缘层薄膜71’进行过孔工艺(即在绝缘层中形成过孔的工艺)的方式去除第一绝缘层薄膜71’的第一部分71a，以形成第一绝缘层71和第一过孔701。
例如，可以以有机绝缘层40为掩膜板，对第一绝缘层薄膜71’的第一部分71a进行刻蚀(例如干刻)，以形成第一绝缘层71和第一过孔701。以有机绝缘层40为掩膜板，可以省去对第一绝缘层薄膜进行过孔工艺的掩模板，从而可以降低成本。
在该示例中，考虑到以有机绝缘层40为掩模板，可能造成有机绝缘层40发生轻微变形，因此，在形成第一绝缘层71和第一过孔701之后，可以 对有机绝缘层40进行例如灰化处理。
本实施例提供的阵列基板的制作方法，将在第一金属结构和有机绝缘层之间的第一绝缘层薄膜中形成过孔的工艺调整到形成有机绝缘层之后进行，使得在进行烘烤处理以形成有机绝缘层的过程中，该第一金属结构被该第一绝缘层薄膜保护，从而避免因该金属结构被严重氧化而造成该第一金属结构与其他部件之间接触不良的现象；并且，相比于图1所示的阵列基板的制作方法，本实施例只是改变了位于第一金属结构和有机绝缘层之间的非金属层(例如第一绝缘层)的过孔工艺的顺序，未增加其他工艺，因而未增加额外的制作成本。此外，在本实施例的至少一个示例中，以有机绝缘层为掩膜板，可以省去对非金属层薄膜(例如第一绝缘层薄膜)进行过孔工艺的掩模板，从而可以降低成本。
本实施例适用于采用铜金属或铜合金等材料制作的第一金属结构，即，第一金属结构01a的形成材料包括铜金属或铜合金，这是因为铜相比铝、钼等金属材料在高温下的氧化程度更严重，更容易造成第一金属结构与其它部件之间接触不良。当然，第一金属结构01a的形成材料并不限于铜金属或铜合金，也可以为其它的在形成有机绝缘层40之后被严重氧化以至于造成该被氧化位置处接触不良的金属。
由于有机绝缘层40的作用主要是增大公共电极层与公共电极层下方的金属层之间的距离，以减小公共电极层中的公共电极与该金属层中的金属结构之间的寄生电容，从而降低功耗。因此，有机绝缘层40与其下方的位于公共电极与金属层之间的其它绝缘层相比具有较大的厚度。例如，有机绝缘层40的厚度可以为10000埃至40000埃。通常，阵列基板中的无机绝缘层(例如二氧化硅或氮化硅等无机绝缘层)的厚度约4000埃左右；例如，栅极绝缘层的厚度可以小于4000埃；例如，钝化层的厚度可以为2500埃至4000埃。由此可见，有机绝缘层40的厚度远大于无机绝缘层的厚度。
在至少一个示例中，有机绝缘层40的材料可以包括树脂(例如亚克力、滤光材料等)。有机绝缘层40采用这些有机材料制作，可以使有机绝缘层40既满足厚度要求以尽量降低功耗，又可以保证透光率。
在至少一个示例中，阵列基板可以采用COA(Color filter On Array)技术，即，将彩色滤光层设置在阵列基板上。在这种情况下，有机绝缘层40 可以为彩色滤光层。
例如，如图5所示，彩色滤光层90可以包括多个红色滤光图案R、多个绿色滤光图案G和多个蓝色滤光图案B。
通常，阵列基板上可以设置有栅金属层和源漏金属层，本实施例中的第一金属层可以为栅金属层或源漏金属层，第一金属结构01a可以相应地为栅金属层或源漏金属层包括的需要被暴露出部分表面且该部分表面在形成有机绝缘层40后可能被严重氧化、造成接触不良的任意金属结构。
例如，如图5和图6a所示，第一金属层01可以为栅金属层，第一金属层01可以包括栅极11a、公共电极线11c和与栅极11a连接的栅线11b，第一金属结构01a可以包括公共电极线11c或栅线11b；或者，第一金属层01可以包括栅极11a和与栅极11a连接的栅线11b，第一金属结构01a可以包括栅线11b。图6a以第一金属结构01a为公共电极11c为例进行说明。
或者，例如，如图5和图6b所示，第一金属层01可以为源漏金属层，第一金属层01可以包括源极13a、漏极13b以及与源极13a连接的数据线13c，第一金属结构01a可以包括源极13a和漏极13b中的一个或数据线13c。图6b以第一金属结构01a为漏极13b为例进行说明。
在图6a中，薄膜晶体管10为底栅底接触结构，即栅极11a设置于有源层14的下方，源极13a和漏极13b与有源层14的下表面接触。在图6b中，薄膜晶体管10为顶栅顶接触结构，即栅极11a设置于有源层14的上方，源极13a和漏极13b与有源层14的上表面接触。
需要说明的是，本实施例不限定薄膜晶体管10的类型，即不限定薄膜晶体管10中有源层14与栅极11a的位置关系，以及有源层14与源极13a/漏极13b的位置关系。此外，本实施例不限定有源层14与源极13a/漏极13b的连接关系。例如，有源层14与源极13a/漏极13b之间还可以设置有绝缘层，从而有源层14与源极13a/漏极13b通过过孔接触；或者，例如，有源层14也可以通过导电结构与源极13a/漏极13b连接。
本实施例提供的制作方法适用于包括公共电极的阵列基板，即该制作方法还包括：形成公共电极50，公共电极50设置于有机绝缘层40上，公共电极50与公共电极线11c电连接，如图6a所示。
进一步地，本实施例提供的制作方法还包括：在形成公共电极50的同时 或者在形成公共电极50之前或之后，形成像素电极30，以使像素电极30与漏极13b连接，如图6b所示。
图6a中，像素电极30位于公共电极50下方，因此，像素电极30在公共电极50之前形成；图6b中，公共电极50与像素电极30同层设置，因此，二者可以同时形成。
本实施例提供的阵列基板的制作方法中，第一绝缘层71可以包括一层绝缘层。例如，第一绝缘层71可以包括栅极绝缘层12，栅极绝缘层12与栅极11a接触并且位于栅极11a和有源层14之间，如图6b所示，第一绝缘层71可以包括栅极绝缘层12，第一过孔701可以位于栅极绝缘层12中。或者，第一绝缘层71可以包括钝化层，钝化层覆盖薄膜晶体管。
或者，第一绝缘层71也可以包括多层绝缘层。例如，如图6a所示，第一绝缘层71可以包括第一子绝缘层711(例如，栅极绝缘层12)和第二子绝缘层712(例如，钝化层20)这两层绝缘层，第二子绝缘层712形成在第一子绝缘层711上；第一过孔701包括第一子绝缘层711中的第一子过孔701a和第二子绝缘层712中的第二子过孔701b，第一子过孔701a与第二子过孔701b连通。图6a仅以第一金属结构01a为公共电极线11c、第一子绝缘层711为栅极绝缘层12、第二子绝缘层712为钝化层20为例进行说明。本发明实施例包括、但不限于此。
当第一绝缘层71包括第一子绝缘层711和第二子绝缘层712时，第一绝缘层71的制作方法例如包括：如图7a所示，形成第一子绝缘层薄膜711’和位于第一子绝缘层薄膜711’上的第二子绝缘层薄膜712’以形成第一绝缘层薄膜71’；之后，在第二子绝缘层薄膜712’上形成有机绝缘层40以及第一有机绝缘层过孔41，如图7b所示；在形成有机绝缘层40之后，去除第一子绝缘层薄膜711’的部分材料和第二子绝缘层薄膜712’的部分材料，以暴露出第一金属结构01a的部分表面并形成第一子过孔701a、第二子过孔701b、第一子绝缘层711和第二子绝缘层712，第一绝缘层71包括第一子绝缘层711和第二子绝缘层712，第一过孔701包括第一子过孔701a和第二子过孔701b，如图7c所示。
在至少一个示例中，第一绝缘层71与有机绝缘层40之间还可以形成有第二绝缘层。在这种情况下，例如，该制作方法可以包括：如图8a所示，在 第一金属层上形成第二绝缘层72、位于第二绝缘层72中的过孔72a，第二绝缘层72中的过孔72a对应第一金属结构01a的部分表面；之后，如图8b所示，在第二绝缘层72上形成第一绝缘层薄膜71’，使第一绝缘层薄膜71’的材料覆盖第二绝缘层72中的过孔72a；之后，在第一绝缘层薄膜71’上形成有机绝缘层40以及第一有机绝缘层过孔41，第一有机绝缘层过孔41对应第二绝缘层72中的过孔72a，如图8c所示；在形成有机绝缘层40之后，去除第一绝缘层薄膜71’的覆盖第二绝缘层72中的过孔72a的部分以暴露出第一金属结构01a的部分表面并形成第一过孔701和第一绝缘层71，如图8d所示。
或者，在至少一个示例中，第一绝缘层71与第一金属层01之间还可以形成有第二绝缘层。在这种情况下，例如，该制作方法可以包括：在第一绝缘层薄膜71’上形成第二绝缘层72和第二绝缘层72中的过孔72a，第二绝缘层72中的过孔72a对应第一绝缘层薄膜71’的第一部分71a，如图9a所示；之后，在第二绝缘层72上形成有机绝缘层40以及第一有机绝缘层过孔41，第一有机绝缘层过孔41对应第二绝缘层72中的过孔72a，如图9b所示；在形成有机绝缘层40之后，去除第一绝缘层薄膜71’的对应第一金属结构01a的第一部分71a，以暴露出第一金属结构01a的部分表面并形成第一绝缘层71和第一过孔701，如图9c所示。
实施例二
在本实施例提供的阵列基板的制作方法中，通过在形成非金属层薄膜之前形成包括第二金属结构的第二金属层、在形成非金属层薄膜时使其包括对应第二金属结构的第二部分、在形成有机绝缘层时还形成对应非金属层薄膜的第二部分的第二有机绝缘层过孔、在去除非金属层薄膜的第一部分时还去除第二部分以暴露出第二金属结构的部分表面，可以对阵列基板上的多层金属层进行保护，以避免该多层金属层中的金属结构在形成有机绝缘层之后被严重氧化导致其与其它部件之间的接触不良。
下面以非金属层薄膜包括第一绝缘层薄膜且非金属层薄膜的第二部分为第一绝缘层薄膜的第二部分为例进行说明。
例如，在实施例一的基础上，如图10至图11c所示，本实施例提供的制作方法还可以包括：在形成第一绝缘层薄膜71’之前，形成第二金属层02(例 如，源漏金属层)，第二金属层02与第一金属层01之间形成有绝缘层，第二金属层包括第二金属结构02a；在形成第一绝缘层薄膜71’时，使第一绝缘层薄膜71’还包括对应第二金属结构02a的第二部分71b；在形成有机绝缘层40时，还形成有机绝缘层40中的第二有机绝缘层过孔42，第二有机绝缘层过孔42对应第一绝缘层薄膜71’的第二部分71b；在形成第一绝缘层71时还形成位于第一绝缘层71中的第二过孔702，第二过孔702对应第二有机绝缘层过孔42且暴露出第二金属结构02a的部分表面021。
本实施例适用于采用铜金属或铜合金等材料制作的第二金属结构，即，第二金属结构02a的形成材料可以包括铜金属或铜合金。这是因为铜相比铝、钼等金属材料在高温下的氧化程度更严重，更容易造成第二金属结构与其它部件之间接触不良。当然，第二金属结构02a的形成材料并不限于铜金属或铜合金，也可以为其它的在形成有机绝缘层40之后被严重氧化以至于造成该被氧化位置处接触不良的金属。
本实施例提供的制作方法中，第一金属层01和第二金属层02中的一个可以为栅金属层，另一个可以为源漏金属层。
例如，如图5和图10所示，第一金属层01包括栅极11a、公共电极线11c和与栅极11a连接的栅线11b，第一金属结构01a包括公共电极线11c或栅线11b，第二金属层02包括源极13a、漏极13b和与源极13a连接的数据线13c，第二金属结构02a包括源极13a和漏极13b中的一个或数据线13c。
或者，例如，第一金属层01包括栅极11a和与栅极11a连接的栅线11b，第一金属结构01a包括栅线11b，第二金属层02包括源极13a、漏极13b和与源极13a连接的数据线13c，第二金属结构02a包括源极13a和漏极13b中的一个或数据线13c。
或者，例如，第一金属层01包括源极13a、漏极13b和与源极13a连接的数据线13c，第一金属结构01a包括源极13a和漏极13b中的一个或数据线13c，第二金属层02包括栅极11a、公共电极线11c和与栅极11a连接的栅线11b，第二金属结构02a包括公共电极线11c或栅线11b。
或者，例如，第一金属层01包括源极13a、漏极13b和与源极13a连接的数据线13c，第一金属结构01a包括源极13a和漏极13b中的一个或数据线13c，第二金属层02包括栅极11a和与栅极11a连接的栅线11b，第二金 属结构02a包括栅线11b。
图11a至图11c仅以第一金属层01为栅金属层、第二金属层02为源漏金属层为例进行说明。
实施例三
本实施例提供的阵列基板的制作方法中，上述非金属层薄膜还包括有源层图案，上述第一部分的材料包括形成有源层图案的材料。本实施例通过利用形成薄膜晶体管中的有源层的材料保护第一金属结构，可以避免该第一金属结构在形成有机绝缘层之后被严重氧化导致的该第一金属结构与其它部件之间接触不良的现象。
下面结合附图对本实施例提供的阵列基板的制作方法进行说明，如图12a～12e所示，该制作方法可以包括以下步骤S41至步骤S44，下面详细介绍这些步骤。
步骤S41：形成第一金属层01，第一金属层01包括第一金属结构01a，如图12a所示。
第一金属层01可以采用本领域常用的图案化处理方式形成，此处不做赘述。图12a只示出了第一金属层01包括的第一金属结构01a，未示出第一金属层01包括的其他金属结构。
步骤S42：在第一金属层01上形成有源层薄膜14’，如图12a所示；对有源层薄膜14’进行图案化处理以形成有源层图案14和对应第一金属结构01a的第一部分(有源层薄膜14’的保留部分)14a，第一部分14a位于第一金属结构01a上，如图12b所示。
图12c仅以有源层图案14和第一部分14a都与第一金属结构01a接触为例进行说明，在这种情况下，例如，第一金属结构01a可以为薄膜晶体管的漏极。当然，有源层图案14也可以位于第一金属结构01a上但不与其接触。
步骤S43：在有源层图案14和第一部分14a上形成有机绝缘薄膜40’，如图12c所示；对有机绝缘薄膜40’进行图案化处理以形成第一有机绝缘层过孔41，之后对经过图案化处理的有机绝缘薄膜40’进行烘烤处理以形成有机绝缘层40，第一有机绝缘层过孔41位于有机绝缘层40中且对应第一部分14a，如图12d所示。
例如，烘烤处理的温度大于或等于200℃。需要说明的是，该烘烤处理 的温度范围为本领域常用的温度范围，仅用于对烘烤处理进行举例说明，并不对本实施例构成限定。
步骤S44：去除有源层薄膜14’的第一部分14a，以暴露出第一金属结构01a的部分表面011，如图12e所示。
在该步骤中，在形成有机绝缘层之后，去除覆盖金属结构的部分表面的形成有源层图案的材料(即第一部分14a)，这是因为有源层图案采用半导体材料制作，半导体材料的电阻率比金属大，去除覆盖第一金属结构的半导体材料可以避免增大该第一金属结构与其接触的部件之间的电阻。
与本领域常用的阵列基板的制作方法(例如图1所示的阵列基板的制作方法)、实施例一和实施例二提供的制作方法相比，本实施例提供的制作方法中只增加了上述步骤S44即可起到避免第一金属结构被严重氧化而造成的该第一金属结构与其连接的其它部件之间接触不良的现象。与在惰性气体氛围中制作有机绝缘层的方式或在形成有机绝缘层之后对金属结构表面进行还原处理等方式相比，本实施例提供的制作方法的成本较低。
本实施例提供的方法也可以用于保护多个金属层，只要在形成有源层薄膜时使该有源层薄膜包括分别对应这些金属层的部分、在形成有机绝缘层时形成相应的有机绝缘层过孔，在形成有机绝缘层后去除对应这些金属层的部分即可。具体实施方式可参见实施例二，重复之处不再赘述。
实施例四
本实施例提供了一种阵列基板的制作方法，如图13和图14a至14c所示，该方法包括以下步骤S41至步骤S43，下面对这些步骤进行详细介绍。
步骤S41：如图14a所示，形成绝缘层薄膜60’。
步骤S42：在绝缘层薄膜60’上形成有机绝缘层薄膜40’，如图14a所示；对有机绝缘层薄膜40’进行图案化处理以形成多个有机绝缘层过孔40a，该多个有机绝缘层过孔40a在绝缘层薄膜60’所在面上的正投影与绝缘层薄膜60’有重叠部分；之后，对经过图案化处理的有机绝缘层薄膜40’进行烘烤处理以形成有机绝缘层40，如图14b所示。
例如，烘烤处理的温度可以大于或等于200℃。需要说明的是，该烘烤处理的温度范围为本领域常用的温度范围，仅用于对烘烤处理进行举例说明，并不对本实施例构成限定。
需要说明的是，本实施例中的图案化处理可以为任意的能够在薄膜中形成设定图案的处理工艺，例如可以为利用掩模板形成设定图案的工艺。
步骤S43：以有机绝缘层40为掩膜板，对绝缘层薄膜60’进行刻蚀，以形成绝缘层60和绝缘层60中的多个绝缘层过孔60a，如图14c所示。
例如，绝缘层60可以包括栅极绝缘层和/或钝化层。栅极绝缘层与阵列基板中薄膜晶体管的栅极接触并且位于栅极和薄膜晶体管的有源层之间，钝化层覆盖薄膜晶体管。
在本实施例中，考虑到以有机绝缘层40为掩模板，可能造成有机绝缘层40发生轻微变形，因此，例如，在形成第一绝缘层71和第一过孔701之后，可以对有机绝缘层40进行例如灰化处理。
实施例五
本实施例提供了一种显示装置的制作方法，该显示装置包括阵列基板，该方法包括：采用上述任一实施例提供的制作方法制作该阵列基板。
例如，本实施例提供的显示装置的制作方法可以用于制作液晶显示装置。
例如，该液晶显示装置可以包括阵列基板与对置基板(例如彩膜基板)，阵列基板与对置基板彼此对置且通过封框胶密封以形成液晶盒，在液晶盒中填充有液晶材料。阵列基板的每个像素单元包括的像素电极用于施加电场以对液晶材料的旋转程度进行控制从而进行显示操作。
相应地，该液晶显示装置的制作方法还可以包括形成对置基板以及将阵列基板与对置基板对盒成型等步骤，这些步骤可以采用本领域常用的方法制作，本实施例不做赘述。
实施例六
本实施例提供了一种导电过孔结构的制作方法，该导电过孔结构包括具有金属结构的金属层、设置于金属层之上的非金属层以及设置于非金属层上的有机绝缘层；在该制作方法中，在形成有机绝缘层之前，金属结构被非金属层覆盖，在形成有机绝缘层之后去除非金属层的覆盖金属结构的部分表面的部分。采用该方法，可以在较低成本的前提下尽量避免导电过孔结构中的金属结构在形成有机绝缘层之后被严重氧化。
如图15所示，该方法可以包括以下步骤S61至步骤S64，下面详细介绍这些步骤。
步骤S61：形成金属层，金属层包括金属结构。例如，该金属结构的形成材料包括铜或铜合金。
步骤S62：在金属层上形成非金属层薄膜，使该非金属层薄膜包括对应上述金属结构的部分。例如，非金属层薄膜的材料可以包括绝缘材料或半导体材料。
步骤S63：在非金属层薄膜上形成有机绝缘层薄膜，对有机绝缘层薄膜进行图案化处理以形成有机绝缘层过孔，有机绝缘层过孔对应非金属层薄膜的上述部分；对经过图案化处理的有机绝缘层薄膜进行烘烤处理以形成有机绝缘层。
步骤S64：在形成有机绝缘层之后，去除非金属层薄膜的上述部分，以形成非金属层并暴露出金属结构的部分表面。
本实施例提供的导电过孔结构的制作方法适用于任意电子器件中的导电过孔结构，只要该导电过孔结构具有金属层、设置在该金属层上的非金属层以及设置在该非金属层上的有机绝缘层即可。例如，该导电过孔结构可以设置于阵列基板上，也可以为设置于其它电子器件中。
本实施例提供的导电过孔结构的制作方法可以参考上述实施例一至实施例三中的相关描述，重复之处不再赘述。
以上所述仅是本发明的示范性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。
本申请要求于2015年7月13日递交的中国专利申请第201510415374.4号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (20)

  1. 一种阵列基板的制作方法，包括：
    形成第一金属层，其中，所述第一金属层包括第一金属结构；
    在所述第一金属层上形成非金属层薄膜，其中，所述非金属层薄膜包括对应所述第一金属结构的第一部分；
    在所述非金属层薄膜上形成有机绝缘层薄膜，对所述有机绝缘层薄膜进行图案化处理以形成第一有机绝缘层过孔，其中，所述第一有机绝缘层过孔对应所述第一部分；
    对经过所述图案化处理的所述有机绝缘层薄膜进行烘烤处理以形成有机绝缘层；以及
    在形成所述有机绝缘层之后，去除所述非金属层薄膜的所述第一部分，以形成非金属层并暴露出所述第一金属结构的部分表面。
  2. 如权利要求1所述的制作方法，其中，所述第一金属结构的形成材料包括铜金属或铜合金。
  3. 如权利要求1或2所述的制作方法，其中，所述有机绝缘层的材料包括树脂。
  4. 如权利要求1至3任一项所述的制作方法，其中，所述有机绝缘层为彩色滤光层。
  5. 如权利要求1至4任一项所述的制作方法，其中，
    所述第一金属层包括栅极、公共电极线和与所述栅极连接的栅线，所述第一金属结构包括所述公共电极线或所述栅线；或者
    所述第一金属层包括栅极和与所述栅极连接的栅线，所述第一金属结构包括所述栅线；或者
    所述第一金属层包括源极、漏极以及与所述源极连接的数据线，所述第一金属结构包括所述源极和所述漏极中的一个或所述数据线。
  6. 如权利要求1至5任一项所述的制作方法，其中，形成所述非金属层包括：
    以所述有机绝缘层为掩膜板，对所述非金属层薄膜的所述第一部分进行刻蚀。
  7. 如权利要求1至6任一项所述的制作方法，其中，形成所述非金属层薄膜包括形成第一绝缘层薄膜，形成所述非金属层包括形成第一绝缘层和所述第一绝缘层中的第一过孔，所述第一过孔暴露出所述第一金属结构的所述部分表面。
  8. 如权利要求7所述制作方法，还包括：形成第二绝缘层和所述第二绝缘层中的过孔，其中，
    在所述第一金属层上形成所述第二绝缘层和所述第二绝缘层中的所述过孔，所述第二绝缘层中的所述过孔对应所述第一金属结构的所述部分表面；在所述第二绝缘层上形成所述第一绝缘层薄膜，所述第一绝缘层薄膜覆盖所述第二绝缘层中的所述过孔；在所述第一绝缘层薄膜上形成所述有机绝缘层和所述第一有机绝缘层过孔，所述第一有机绝缘层过孔对应所述第二绝缘层中的所述过孔；在形成所述有机绝缘层之后，去除所述第一绝缘层薄膜的覆盖所述第二绝缘层中的所述过孔的部分以形成所述第一过孔和所述第一绝缘层；或者
    在所述第一绝缘层薄膜上形成第二绝缘层和所述第二绝缘层中的过孔，所述第二绝缘层中的所述过孔对应所述第一部分；在所述第二绝缘层上形成所述第一有机绝缘层过孔和所述有机绝缘层，所述第一有机绝缘层过孔对应所述第二绝缘层中的所述过孔。
  9. 如权利要求7或8所述的制作方法，其中，
    形成所述第一绝缘层薄膜包括形成第一子绝缘层薄膜和位于所述第一子绝缘层薄膜上的第二子绝缘层薄膜；
    在形成所述有机绝缘层之后，去除所述第一子绝缘层薄膜的部分材料和所述第二子绝缘层薄膜的部分材料，以形成第一子绝缘层、第二子绝缘层、位于所述第一子绝缘层中的第一子过孔和位于所述第二子绝缘层中的第二子过孔，所述第一绝缘层包括所述第一子绝缘层和所述第二子绝缘层，所述第一过孔包括所述第一子过孔和所述第二子过孔。
  10. 如权利要求7或8所述的制作方法，其中，
    所述阵列基板包括薄膜晶体管，所述薄膜晶体管包括栅极和有源层；并且
    所述第一绝缘层包括栅极绝缘层，所述栅极绝缘层与所述栅极接触并且 位于所述栅极和所述有源层之间；和/或，所述第一绝缘层包括钝化层，所述钝化层覆盖所述薄膜晶体管。
  11. 如权利要求1至6任一项所述的制作方法，其中，
    所述非金属层薄膜还包括有源层图案，所述第一部分的材料包括形成所述有源层图案的材料。
  12. 如权利要求1至4任一项所述的制作方法，还包括：在形成所述非金属层薄膜之前，形成第二金属层，所述第二金属层包括第二金属结构；其中，
    所述非金属层薄膜还包括对应所述第二金属结构的第二部分；
    在形成所述有机绝缘层时还形成第二有机绝缘层过孔，所述第二有机绝缘层过孔对应所述第二部分；以及
    去除所述非金属层薄膜的所述第一部分时还去除所述第二部分，以形成所述非金属层并暴露出所述第一金属结构的所述部分表面以及所述第二金属结构的部分表面。
  13. 如权利要求12所述的制作方法，其中，所述第二金属结构的形成材料包括铜金属或铜合金。
  14. 如权利要求12或13所述的制作方法，其中，所述第一金属层包括栅极、公共电极线和与所述栅极连接的栅线，所述第一金属结构包括所述公共电极线或所述栅线，所述第二金属层包括源极、漏极和与所述源极连接的数据线，所述第二金属结构包括所述源极和所述漏极中的一个或所述数据线；或者
    所述第一金属层包括栅极和与所述栅极连接的栅线，所述第一金属结构包括所述栅线，所述第二金属层包括源极、漏极和与所述源极连接的数据线，所述第二金属结构包括所述源极和所述漏极中的一个或所述数据线；或者
    所述第一金属层包括源极、漏极和与所述源极连接的数据线，所述第一金属结构包括所述源极和所述漏极中的一个或所述数据线，所述第二金属层包括栅极、公共电极线和与所述栅极连接的栅线，所述第二金属结构包括所述公共电极线或所述栅线；或者
    所述第一金属层包括源极、漏极和与所述源极连接的数据线，所述第一金属结构包括所述源极和所述漏极中的一个或所述数据线，所述第二金属层 包括栅极和与所述栅极连接的栅线，所述第二金属结构包括所述栅线。
  15. 如权利要求5或14所述的制作方法，还包括：形成公共电极，其中，所述公共电极设置于所述有机绝缘层上，所述公共电极与所述公共电极线电连接。
  16. 如权利要求15所述的制作方法，还包括：
    在形成所述公共电极的同时或者在形成所述公共电极之前或之后，形成像素电极，其中，所述像素电极与所述漏极电连接。
  17. 如权利要求1至16任一项所述的制作方法，其中，所述有机绝缘层的厚度为10000埃至40000埃。
  18. 一种阵列基板的制作方法，包括：
    形成绝缘层薄膜；
    在所述绝缘层薄膜上形成有机绝缘层薄膜，对所述有机绝缘层薄膜进行图案化处理以形成多个有机绝缘层过孔，其中，所述多个有机绝缘层过孔在所述绝缘层薄膜所在面上的正投影与所述绝缘层薄膜有重叠部分；
    对经过所述图案化处理的所述有机绝缘层薄膜进行烘烤处理以形成有机绝缘层；以及
    以所述有机绝缘层为掩膜板，对所述绝缘层薄膜进行刻蚀，以形成绝缘层和所述绝缘层中的多个绝缘层过孔。
  19. 一种显示装置的制作方法，所述显示装置包括阵列基板，所述方法包括：采用如权利要求1至18任一项所述的制作方法制作所述阵列基板。
  20. 一种导电过孔结构的制作方法，包括：
    形成金属层，其中，所述金属层包括金属结构；
    在所述金属层上形成非金属层薄膜，其中，所述非金属层薄膜包括对应所述金属结构的部分；
    在所述非金属层薄膜上形成有机绝缘层薄膜，对所述有机绝缘层薄膜进行图案化处理以形成有机绝缘层过孔，其中，所述有机绝缘层过孔对应所述非金属层薄膜的所述部分；
    对经过所述图案化处理的所述有机绝缘层薄膜进行烘烤处理以形成有机绝缘层；以及
    在形成所述有机绝缘层之后，去除所述非金属层薄膜的所述部分，以形 成非金属层并暴露出所述金属结构的部分表面。
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