Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
  • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02107—Forming insulating materials on a substrate
  • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
  • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
  • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
  • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
  • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
  • H01L21/30604—Chemical etching
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3105—After-treatment
  • H01L21/31051—Planarisation of the insulating layers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3105—After-treatment
  • H01L21/31051—Planarisation of the insulating layers
  • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
  • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3105—After-treatment
  • H01L21/31051—Planarisation of the insulating layers
  • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
  • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
  • H01L21/31056—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching the removal being a selective chemical etching step, e.g. selective dry etching through a mask
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3105—After-treatment
  • H01L21/311—Etching the insulating layers by chemical or physical means
  • H01L21/31105—Etching inorganic layers
  • H01L21/31111—Etching inorganic layers by chemical means
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/113—Isolations within a component, i.e. internal isolations
  • H10D62/115—Dielectric isolations, e.g. air gaps
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0151—Manufacturing their isolation regions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
  • H10D84/0188—Manufacturing their isolation regions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/02—Manufacture or treatment characterised by using material-based technologies
  • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
  • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

• the present disclosure relates to semiconductor integrated circuit (IC) fabrication, and more particularly, to methods of forming shallow trench isolation structures (STIs), e.g., for a complementary metal-oxide semiconductor (CMOS) device.
• STIs shallow trench isolation structures
• CMOS complementary metal-oxide semiconductor
• Shallow trench isolation is an integrated circuit feature that prevents electrical current leakage between adjacent semiconductor device components.
• STI structures are commonly used in CMOS devices, and are typically formed early during the semiconductor device fabrication process, before transistors are formed.
• the key steps of a conventional STI process involve etching a pattern of trenches in a silicon substrate, depositing one or more dielectric materials (e.g., silicon dioxide) to fill the trenches, and removing the excess dielectric using chemical-mechanical planarization (CMP).
• CMP chemical-mechanical planarization
• the CMP processing involved in conventional STI formation may cause one or more related problems.
• the CMP process may produce a significant center-to- edge bias that may result in sufficient variation across the wafer to cause yield fallout.
• CMP may cause localized non-uniformity and dishing of the field oxide.
• the CMP process may leave oxide residue on the largest active areas, which may cause SiN residue that results in yield loss.
• the conventional STI formation processing using CMP involves a relatively large number of steps.
• a method of forming a trench isolation structure for an integrated circuit includes: forming a thin pad oxide layer then a nitride layer over a semiconductor substrate; performing a trench etch process through portions of the nitride layer, pad oxide, and the semiconductor substrate to form a trench; depositing a trench oxide layer over remaining portions of the nitride layer and extending into the trench to form a filled trench; depositing a sacrificial planarizing layer over the deposited oxide, the sacrificial planarizing layer being etch-selective with respect to the trench oxide layer; performing a planarizing etch process that removes the sacrificial planarizing layer and decreases surface variations in an upper surface of the trench oxide layer; performing an
• a semiconductor die may include a semiconductor substrate and a plurality of trench isolation structures (e.g., STIs) formed in the semiconductor substrate by a process including: forming a thin pad oxide layer then a nitride layer over the semiconductor substrate; performing a trench etch process through portions of the nitride layer, pad oxide, and the semiconductor substrate to form a plurality of trenches; depositing a trench oxide layer over remaining portions of the nitride layer and extending into the trenches to form a plurality of filled trenches; depositing a sacrificial planarizing layer over the deposited oxide, the sacrificial planarizing layer being etch-selective with respect to the trench oxide layer; performing a planarizing etch process that removes the sacrificial planarizing layer and decreases surface variations in an upper surface of the trench oxide layer; performing an oxide etch process that is selective to the trench oxide
• a CMOS device comprises a semiconductor structure including a plurality of trench isolation structures formed as discussed above.
• the sacrificial planarizing layer comprises an organosilicate.
• the sacrificial planarizing layer comprises an organo-siloxane based polymer, e.g., according to the chemical formula R x CH3 y SiO z , where R is an organic chromophore.
• the sacrificial planarizing layer may comprise a DUO(TM)193 or DUO(TM)248 anti-reflective coating supplied by Honeywell Electronic Materials, having a location at 101 Columbia Rd, Morristown, NJ 07960.
• FIGURES 1A-1H illustrate a cross-section of an example semiconductor integrated circuit structure, showing a step-by-step process of forming trench isolation structures (e.g., STIs) for an integrated circuit, according to an example embodiment of the invention
• FIGURE 2 is a flowchart of an example method of forming shallow trench isolations for an integrated circuit, e.g., CMOS device, corresponding to the process illustrated in FIGURES 1 A-1H, according to an example embodiment;
• FIGURES 3A-3H illustrate a cross-section of another example semiconductor integrated circuit structure, showing a step-by-step process of forming trench isolation structures (e.g., STIs) for an integrated circuit, according to an example embodiment of the invention.
• trench isolation structures e.g., STIs
• FIGURE 4 is a flowchart of an example method of forming shallow trench isolations for an integrated circuit, e.g., CMOS device, corresponding to the process illustrated in FIGURES 3 A-3H, according to an example embodiment.
• CMOS device e.g., CMOS device
• trench isolation structures e.g., shallow trench isolations (STIs)
• STIs shallow trench isolations
• Such process may reduce or eliminate one or more problems related to CMP processing, and/or may reduce cost and complexity of forming STIs.
• FIGURES 1 A-1H illustrate the steps of an example process of forming trench isolation structures (e.g., STIs) for an integrated circuit, e.g., a CMOS device, according to an example embodiment.
• an integrated circuit structure 10 includes a semiconductor substrate 12, e.g., a silicon (Si) substrate, formed on a wafer surface.
• Si silicon
• S1O2 silicon dioxide
• the oxide layer 13 may be formed or deposited prior to the nitride layer 16 to help stress/adhesion of the nitride to the substrate, and may have a thickness of about 1/10 the thickness of the deposited nitride layer 16.
• a liner oxidation may form a liner oxide layer 14 on the exposed surfaces of the semiconductor substrate 12.
• a trench oxide layer 24 e.g., silicon dioxide (S1O2), is deposited over the structure, and extends into each trench 20 to form filled trenches.
• the trench oxide layer 24 is deposited by High-Density Plasma Chemical Vapor Deposition (HDP CVD).
• the deposited trench oxide layer 24 may have a non-planar topography, e.g., due to the topography of the underlying structure.
• the topography of the trench oxide layer 24 may define a number of upwardly protruding or extending features or regions 26.
• a sacrificial planarizing layer 30 is deposited over the trench oxide layer 24.
• the sacrificial planarizing layer 30 is etch-selective with respect to the trench oxide layer 24.
• the planarizing layer comprises an organosilicate.
• the planarizing layer 30 may comprise an organo-siloxane based polymer, e.g., an organo-siloxane based polymer with the chemical formula R x CH3 y SiO z , where R is an organic chromophore.
• the sacrificial planarizing layer 30 comprises a DUO(TM)193 or DUO(TM)248 anti -reflective coating supplied by Honeywell Electronic Materials, having a location at 101 ColumbiaRd, Morristown, NJ 07960.
• the planarizing layer 30 may be deposited in any suitable manner.
• planarizing layer 30 is spin-coated over the trench oxide layer 24, which provides a partially planarizing effect.
• a planarizing etch process is then performed to remove the sacrificial planarizing layer 30 and decrease surface variations in the upper surface of the trench oxide layer 24, e.g., by reducing or eliminating the upwardly protruding or extending features or regions 26.
• the planarizing etch process may include a single etch process or a series of different etch processes. In the example discussed below, the planarizing etch process shown in FIGURES ID and IE involves three different etches.
• the wafer is etched in an oxide etcher, first with a tuned etch to open the planarizing layer, and then with a short oxide etch selective to the trench oxide layer 24.
• the second etch will cause the upwardly proj ecting oxide areas 26 to be etched, while the lower field areas of the oxide layer 24 are protected by the sacrificial planarizing layer 30.
• the second etch is stopped when the highest points 26 are about level with the bulk planarizing layer 30.
• an etch process that etches through a first substance/layer faster than a second substance/layer is said to be "selective to" the first substance/layer over the second substance/layer.
• a third etch is then performed, which is non-selective with respect to the trench oxide layer 24 and sacrificial planarizing layer 30, to remove the trench oxide layer 24 and sacrificial planarizing layer 30 at similar rates, until the planarizing layer 30 is removed.
• This etch may be stopped before reaching the nitride layer 16, as shown in FIGURE IE.
• an oxide etch that is highly selective to the trench oxide layer 24 is then performed to remove remaining portions of the trench oxide layer 24 outside the filled trenches 20, thereby defining a field oxide 40 in each trench 20.
• a defined amount of over-etch is performed, which may trench the field oxides 40 and clear any residue on the remaining nitride layer 16.
• an optional wet etch is performed to remove oxide residue on the nitride layer 16 and/or to control the height of the field oxides 40.
• the wet etch may be designed to provide a defined height of the field oxides 40 relative to the top of the substrate 12, indicated as distance Di in FIGURE 1G, which height may be selected in order to provide a final height of the field oxides 40, indicated as distance D 2 in FIGURE 1H, based on knowledge of the height-reduction associated with subsequent processing steps.
• the nitride layer 16 is then removed using any suitable removal process, e.g., by an etch selective to the nitride layer 16 over the materials of the field oxide 40 and substrate 12.
• the remaining field oxides 40 i.e., trench isolation structures, may project above the exposed upper surface of the semiconductor substrate 12 by a targeted step height indicated at D 2 , i.e., the height of the top surface of field oxide 40 relative to the top surface 52 of substrate 12.
• step height D 2 and/or top shape of field oxides 40 may be controlled as desired by performing any suitable processes, e.g., plasma etch, wet etch, or by running a long wet removal process (e.g., wet SiN removal) to remove the remaining portions of the nitride layer 16.
• any suitable processes e.g., plasma etch, wet etch, or by running a long wet removal process (e.g., wet SiN removal) to remove the remaining portions of the nitride layer 16.
• the trench isolation structures 40 may be formed without using any chemical-mechanical planarization (CMP) process, which may provide various advantages as discussed above.
• CMP chemical-mechanical planarization
• the nitride removal step may also be performed in-situ with the rest of the planarizing etches, if the optional wet etch is skipped, thereby further reducing the total number of steps.
• FIGURE 2 is a flowchart of an example method 100 of forming shallow trench isolations for an integrated circuit, e.g., CMOS device, according to an example embodiment corresponding to FIGURES 1 A-1H.
• a silicon substrate is formed on a wafer.
• a pad oxidation process forms a pad oxide over the surface of the silicon substrate.
• a silicon nitride layer is deposited over the silicon substrate.
• a trench etch e.g., an STI etch, is performed to form a plurality of trenches.
• a liner oxidation process forms a liner oxide in the formed trenches.
• a silicon dioxide layer (trench oxide layer) is deposited over the wafer by High-Density Plasma Chemical Vapor Deposition (HDP CVD), which fills the etched trenches.
• the deposited silicon dioxide layer may have a non-planar topography, e.g., due to the topography of the underlying structure.
• the silicon dioxide layer may define a number of upwardly protruding or extending features or regions.
• a sacrificial planarizing layer of an organo-siloxane based polymer (e.g., DUO(TM)193 or DUO(TM)248) is deposited over the silicon dioxide layer.
• a tuned etch is performed to open the sacrificial planarizing layer, followed by a short oxide etch selective to the silicon dioxide layer at step 116.
• the etch at step 116 may at least partially etch the upwardly projecting areas of the silicon dioxide, while the lower areas of silicon dioxide are protected by the sacrificial planarizing layer.
• a non-selective etch is performed to etch through the silicon dioxide layer and sacrificial planarizing layer at similar rates, until the sacrificial planarizing layer is removed. This etch may be stopped before reaching the underlying silicon nitride layer.
• an oxide etch that is highly selective to silicon dioxide is then performed to remove portions of the silicon dioxide layer above and outside the filled trenches, thereby defining a field oxide in each trench.
• a defined amount of over-etch is performed, which may trench the field oxides and clear any residue on the remaining silicon nitride layer.
• an optional wet etch is performed to remove oxide residue on the remaining silicon nitride layer and/or to control the height of the field oxides.
• the silicon nitride layer is removed using any suitable removal process, e.g., an etch selective to silicon nitride over the silicon dioxide field oxide and the silicon substrate.
• the remaining field oxides, i.e., trench isolation structures may project above the exposed upper surface of the silicon substrate by a targeted step height, which may be controlled or shaped as desired using any suitable finishing process(es).
• shallow trench isolations may be formed without using any chemical-mechanical planarization (CMP) process, which may provide various advantages as discussed above.
• CMP chemical-mechanical planarization
• FIGURES 3 A-3H illustrate the steps of another example embodiment of a process for forming trench isolation structures (e.g., STIs) for an integrated circuit, e.g., a CMOS device.
• trench isolation structures e.g., STIs
• an integrated circuit structure 10 includes a semiconductor substrate 12, e.g., a silicon (Si) substrate, formed on a wafer surface.
• a trench etch process e.g., an STI etch
• a trench oxide layer 24 e.g., silicon dioxide (S1O2), is deposited over the structure, and extends into each trench 20 to form filled trenches.
• the trench oxide layer 24 is deposited by High-Density Plasma Chemical Vapor Deposition (HDP CVD).
• the deposited trench oxide layer 24 may have a non-planar topography, e.g., due to the topography of the underlying structure.
• the topography of the trench oxide layer 24 may define a number of upwardly protruding or extending features or regions 26.
• a sacrificial planarizing layer 30 is deposited over the trench oxide layer 24.
• the sacrificial planarizing layer 30 is etch-selective with respect to the trench oxide layer 24.
• the planarizing layer comprises an organosilicate.
• the planarizing layer 30 may comprise an organo-siloxane based polymer, e.g., an organo-siloxane based polymer with the chemical formula R x CH3 y SiO z , where R is an organic chromophore.
• the sacrificial planarizing layer 30 comprises a DUO(TM)193 or DUO(TM)248 anti-reflective coating, e.g., as discussed above with reference to FIGURE 1 A.
• the planarizing layer 30 may be deposited in any suitable manner.
• planarizing layer 30 is spin-coated over the trench oxide layer 24, which provides a partially planarizing effect.
• a series of etches are then performed to form the trench isolation structures in the trenches 20, as discussed below, which in the process of forming the trench isolation structures, removes the sacrificial planarizing layer 30 and decrease surface variations in the upper surface of the trench oxide layer 24, e.g., by reducing or eliminating the upwardly protruding or extending features or regions 26.
• a generally non-selective etch (e.g., which, in embodiments that use a DUO(TM) coating, may be referred to as a DUO etch) is performed, which etches the trench oxide layer 24 and sacrificial planarizing layer 30, e.g., DUO(TM) coating (and nitride layer 16, if relevant) at the same or about the same rate.
• This generally non-selective etch may leave portions of the sacrificial planarizing layer 30 in low lying areas of the structure, e.g., above trenches 20, as shown in FIGURE 3D.
• the etch may remove portions of the upwardly projecting oxide areas 26 of the trench oxide layer 24, while the lower field areas of the oxide layer 24 are protected by the sacrificial planarizing layer 30.
• the second etch is stopped when the highest points 26 are about level with the bulk planarizing layer 30.
• an oxide etch is performed that is selective to the trench oxide layer 24 over the sacrificial planarizing layer 30 and nitride layer 16. As shown, the oxide etch may leave sacrificial planarizing layer 30 over the trench areas, while regions 26 shown in FIGURE 3D (e.g., above regions of nitride layer 16) are etched to a depth below the regions of sacrificial planarizing layer 30.
• a second non-selective or generally non-selective clean-up etch is then performed, which may planarize and remove the remaining sacrificial planarizing layer 30 from all areas, in particular over the trenches 20 (field oxide). In some embodiments this etch may be stopped before reaching the nitride layer 16, as shown in FIGURE 3E.
• an oxide etch that is selective to the trench oxide layer 24 over the sacrificial planarizing layer 30 and nitride layer 16 is then performed to remove remaining portions of the trench oxide layer 24 outside the filled trenches 20, thereby defining a field oxide 40 in each trench 20.
• a defined amount of over-etch is performed, which may trench the field oxides 40, thereby setting the final field oxide height, and clear any residue on the remaining nitride layer 16.
• the nitride layer 16 is then removed using any suitable removal process, e.g., by an etch selective to the nitride layer 16 over the materials of the field oxide 40 and substrate 12 (e.g., an SiN etch).
• the remaining field oxides 40 i.e., trench isolation structures, may project above the exposed upper surface of the semiconductor substrate 12 by a targeted step height indicated at D 2 , i.e., the height of the top surface of field oxide 40 relative to the top surface 52 of substrate 12.
• step height D 2 and/or top shape of field oxides 40 may be controlled as desired by performing any suitable processes, e.g., plasma etch, wet etch, or by running a long wet removal process (e.g., wet SiN removal) to remove the remaining portions of the nitride layer 16.
• any suitable processes e.g., plasma etch, wet etch, or by running a long wet removal process (e.g., wet SiN removal) to remove the remaining portions of the nitride layer 16.
• the trench isolation structures 40 may be formed without using any chemical-mechanical planarization (CMP) process, which may provide various advantages as discussed above.
• CMP chemical-mechanical planarization
• the nitride removal step may also be performed in-situ with the rest of the planarizing etches, if the optional wet etch is skipped, thereby further reducing the total number of steps.
• the final nitride etch shown in FIGURE 3H can be completed in-situ with the planarizing etch process.
• FIGURE 4 is a flowchart of an example method 200 of forming shallow trench isolations for an integrated circuit, e.g., CMOS device, according to an example embodiment corresponding to FIGURES 3 A-3H.
• CMOS device e.g., CMOS device
• Steps 202-210 At step 202, a silicon substrate is formed on a wafer.
• a pad oxidation process forms a pad oxide over the surface of the silicon substrate.
• a silicon nitride layer is deposited over the silicon substrate.
• a trench etch e.g., an STI etch, is performed to form a plurality of trenches.
• a liner oxidation process forms a liner oxide in the formed trenches.
• a silicon dioxide layer (trench oxide layer) is deposited over the wafer by High-Density Plasma Chemical Vapor Deposition (HDP CVD), which fills the etched trenches.
• the deposited silicon dioxide layer may have a non- planar topography, e.g., due to the topography of the underlying structure. In particular, the silicon dioxide layer may define a number of upwardly protruding or extending features or regions.
• a sacrificial planarizing layer of an organo-siloxane based polymer (e.g., DUO(TM)193 or DUO(TM)248) is deposited over the silicon dioxide layer.
• a non-selective etch (e.g., DUO etch) is performed to remove tall or upwardly projecting regions of silicon dioxide layer and to remove a partial depth of the sacrificial planarizing layer.
• the etch at step 214 may at least partially etch the upwardly projecting areas of the silicon dioxide, while the lower areas of silicon dioxide are protected by the sacrificial planarizing layer.
• a selective oxide etch is performed to etch portions of silicon dioxide layer to a depth below the remaining sacrificial planarizing layer.
• a non-selective "clean-up" etch is performed to planarize the structure and remove any remaining portions of sacrificial planarizing layer, in particular over the trenches (field oxide). This etch may be stopped before reaching the underlying silicon nitride layer.
• an oxide etch that is highly selective to silicon dioxide is then performed to remove portions of the silicon dioxide layer above and outside the filled trenches, thereby defining a field oxide in each trench.
• a defined amount of over-etch is performed, which may trench the field oxides and clear any residue on the remaining silicon nitride layer.
• the silicon nitride layer is removed using any suitable removal process, e.g., SiN etch selective to silicon nitride over the silicon dioxide field oxide and the silicon substrate.
• the remaining field oxides, i.e., trench isolation structures may project above the exposed upper surface of the silicon substrate by a targeted step height, which may be controlled or shaped as desired using any suitable finishing process(es).
• shallow trench isolations may be formed without using any chemical-mechanical planarization (CMP) process, which may provide various advantages as discussed above.
• CMP chemical-mechanical planarization

Landscapes

• Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• Manufacturing & Machinery (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Chemical & Material Sciences (AREA)
• General Chemical & Material Sciences (AREA)
• Chemical Kinetics & Catalysis (AREA)
• Inorganic Chemistry (AREA)
• Element Separation (AREA)

Priority Applications (4)

Applications Claiming Priority (2)

Publications (1)

Family

ID=56131655

Family Applications (1)

Country Status (7)

Families Citing this family (10)

Citations (4)

Family Cites Families (16)

• 2015
  • 2015-06-10 US US14/735,359 patent/US9627246B2/en active Active
• 2016
  • 2016-06-03 KR KR1020177033788A patent/KR20180015628A/ko not_active Withdrawn
  • 2016-06-03 JP JP2017563194A patent/JP2018517300A/ja not_active Withdrawn
  • 2016-06-03 WO PCT/US2016/035785 patent/WO2016200693A1/en not_active Ceased
  • 2016-06-03 CN CN201680032734.5A patent/CN107690692B/zh active Active
  • 2016-06-03 EP EP16729463.6A patent/EP3308394B1/en active Active
  • 2016-06-08 TW TW105118197A patent/TW201703194A/zh unknown
• 2017
  • 2017-04-17 US US15/489,379 patent/US20170229340A1/en not_active Abandoned

Patent Citations (4)

Also Published As

Similar Documents

Legal Events