JP2018517300A5 - - Google Patents

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Publication number
JP2018517300A5
JP2018517300A5 JP2017563194A JP2017563194A JP2018517300A5 JP 2018517300 A5 JP2018517300 A5 JP 2018517300A5 JP 2017563194 A JP2017563194 A JP 2017563194A JP 2017563194 A JP2017563194 A JP 2017563194A JP 2018517300 A5 JP2018517300 A5 JP 2018517300A5
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JP
Japan
Prior art keywords
trench
layer
oxide
planarization
etch
Prior art date
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Withdrawn
Application number
JP2017563194A
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English (en)
Japanese (ja)
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JP2018517300A (ja
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Publication date
Priority claimed from US14/735,359 external-priority patent/US9627246B2/en
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Publication of JP2018517300A publication Critical patent/JP2018517300A/ja
Publication of JP2018517300A5 publication Critical patent/JP2018517300A5/ja
Withdrawn legal-status Critical Current

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JP2017563194A 2015-06-10 2016-06-03 シャロートレンチアイソレーション構造（ｓｔｉ）を形成する方法 Withdrawn JP2018517300A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/735,359 2015-06-10
US14/735,359 US9627246B2 (en) 2015-06-10 2015-06-10 Method of forming shallow trench isolation (STI) structures
PCT/US2016/035785 WO2016200693A1 (en) 2015-06-10 2016-06-03 Method of forming shallow trench isolation (sti) structures

Publications (2)

Publication Number Publication Date
JP2018517300A JP2018517300A (ja) 2018-06-28
JP2018517300A5 true JP2018517300A5 (enExample) 2019-06-13

Family

ID=56131655

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017563194A Withdrawn JP2018517300A (ja) 2015-06-10 2016-06-03 シャロートレンチアイソレーション構造（ｓｔｉ）を形成する方法

Country Status (7)

Country Link
US (2) US9627246B2 (enExample)
EP (1) EP3308394B1 (enExample)
JP (1) JP2018517300A (enExample)
KR (1) KR20180015628A (enExample)
CN (1) CN107690692B (enExample)
TW (1) TW201703194A (enExample)
WO (1) WO2016200693A1 (enExample)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107017161B (zh) * 2017-05-31 2020-01-24 上海华力微电子有限公司 一种减小sti-cmp过程中碟型凹陷的方法
JP2019169581A (ja) * 2018-03-23 2019-10-03 株式会社東芝 半導体装置の製造方法
CN110707045B (zh) * 2018-10-09 2023-05-12 联华电子股份有限公司 一种制作半导体元件的方法
CN110148579A (zh) * 2019-04-15 2019-08-20 上海华力集成电路制造有限公司 浅沟槽隔离层的制造方法
GB2583348A (en) * 2019-04-24 2020-10-28 Univ Southampton Photonic chip and method of manufacture
CN110660839B (zh) * 2019-11-13 2022-04-29 京东方科技集团股份有限公司 一种显示面板及其制备方法
US11227926B2 (en) * 2020-06-01 2022-01-18 Nanya Technology Corporation Semiconductor device and method for fabricating the same
CN114038744B (zh) * 2021-10-26 2024-12-13 上海华力集成电路制造有限公司 一种mos晶体管制作方法及mos晶体管
CN115346912B (zh) * 2022-10-19 2023-01-03 广州粤芯半导体技术有限公司 浅沟槽隔离结构的制备方法
WO2025212375A1 (en) * 2024-04-05 2025-10-09 Applied Materials, Inc. High-density plasma (hdp) topography improvement with partial gapfill carbon

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US5026666A (en) * 1989-12-28 1991-06-25 At&T Bell Laboratories Method of making integrated circuits having a planarized dielectric
JPH05235184A (ja) * 1992-02-26 1993-09-10 Nec Corp 半導体装置の多層配線構造体の製造方法
JP3311044B2 (ja) * 1992-10-27 2002-08-05 株式会社東芝 半導体装置の製造方法
US5741740A (en) * 1997-06-12 1998-04-21 Taiwan Semiconductor Manufacturing Company, Ltd. Shallow trench isolation (STI) method employing gap filling silicon oxide dielectric layer
US6020621A (en) * 1998-01-28 2000-02-01 Texas Instruments - Acer Incorporated Stress-free shallow trench isolation
US6197658B1 (en) * 1998-10-30 2001-03-06 Taiwan Semiconductor Manufacturing Company Sub-atmospheric pressure thermal chemical vapor deposition (SACVD) trench isolation method with attenuated surface sensitivity
US6300219B1 (en) * 1999-08-30 2001-10-09 Micron Technology, Inc. Method of forming trench isolation regions
US20010053583A1 (en) 1999-12-22 2001-12-20 Simon Fang Shallow trench isolation formation process using a sacrificial layer
US6391781B1 (en) * 2000-01-06 2002-05-21 Oki Electric Industry Co., Ltd. Method of making a semiconductor device
TW492143B (en) 2001-05-11 2002-06-21 Macronix Int Co Ltd Manufacturing method of shallow trench isolation structure
US6664190B2 (en) 2001-09-14 2003-12-16 Chartered Semiconductor Manufacturing Ltd. Pre STI-CMP planarization scheme
KR100406179B1 (ko) * 2001-12-22 2003-11-17 주식회사 하이닉스반도체 플래쉬 메모리 셀의 자기 정렬 플로팅 게이트 형성 방법
KR20030053958A (ko) * 2001-12-24 2003-07-02 동부전자 주식회사 반도체 소자의 트랜지스터 제조방법
JP4018596B2 (ja) * 2002-10-02 2007-12-05 株式会社東芝 半導体装置の製造方法
US7265014B1 (en) * 2004-03-12 2007-09-04 Spansion Llc Avoiding field oxide gouging in shallow trench isolation (STI) regions
US8017493B2 (en) 2008-05-12 2011-09-13 Texas Instruments Incorporated Method of planarizing a semiconductor device
CN102386084B (zh) * 2010-09-01 2014-01-08 中芯国际集成电路制造(上海)有限公司 平坦化晶圆表面的方法
US8629514B2 (en) * 2011-01-18 2014-01-14 Wafertech, Llc Methods and structures for customized STI structures in semiconductor devices
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CN105280545A (zh) * 2014-07-24 2016-01-27 联华电子股份有限公司 半导体装置的浅沟槽隔离结构与其制造方法

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