CN107690692B - 形成浅沟槽隔离(sti)结构的方法 - Google Patents

形成浅沟槽隔离(sti)结构的方法 Download PDF

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CN107690692B
CN107690692B CN201680032734.5A CN201680032734A CN107690692B CN 107690692 B CN107690692 B CN 107690692B CN 201680032734 A CN201680032734 A CN 201680032734A CN 107690692 B CN107690692 B CN 107690692B
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trench
layer
oxide
etch
planarization
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CN107690692A (zh
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贾斯丁·希罗奇·萨托
格雷戈里·艾伦·斯托姆
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Microchip Technology Inc
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
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    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
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    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
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    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • H01L21/31056—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching the removal being a selective chemical etching step, e.g. selective dry etching through a mask
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
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    • H10D84/01—Manufacture or treatment
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    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
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    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

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CN201680032734.5A 2015-06-10 2016-06-03 形成浅沟槽隔离(sti)结构的方法 Active CN107690692B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/735,359 US9627246B2 (en) 2015-06-10 2015-06-10 Method of forming shallow trench isolation (STI) structures
US14/735,359 2015-06-10
PCT/US2016/035785 WO2016200693A1 (en) 2015-06-10 2016-06-03 Method of forming shallow trench isolation (sti) structures

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CN107690692B true CN107690692B (zh) 2022-01-25

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US (2) US9627246B2 (enExample)
EP (1) EP3308394B1 (enExample)
JP (1) JP2018517300A (enExample)
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CN (1) CN107690692B (enExample)
TW (1) TW201703194A (enExample)
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Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107017161B (zh) * 2017-05-31 2020-01-24 上海华力微电子有限公司 一种减小sti-cmp过程中碟型凹陷的方法
JP2019169581A (ja) * 2018-03-23 2019-10-03 株式会社東芝 半導体装置の製造方法
CN110707045B (zh) * 2018-10-09 2023-05-12 联华电子股份有限公司 一种制作半导体元件的方法
CN110148579A (zh) * 2019-04-15 2019-08-20 上海华力集成电路制造有限公司 浅沟槽隔离层的制造方法
GB2583348A (en) * 2019-04-24 2020-10-28 Univ Southampton Photonic chip and method of manufacture
CN110660839B (zh) * 2019-11-13 2022-04-29 京东方科技集团股份有限公司 一种显示面板及其制备方法
US11227926B2 (en) * 2020-06-01 2022-01-18 Nanya Technology Corporation Semiconductor device and method for fabricating the same
CN114038744B (zh) * 2021-10-26 2024-12-13 上海华力集成电路制造有限公司 一种mos晶体管制作方法及mos晶体管
CN115346912B (zh) * 2022-10-19 2023-01-03 广州粤芯半导体技术有限公司 浅沟槽隔离结构的制备方法
US20250313948A1 (en) * 2024-04-05 2025-10-09 Applied Materials, Inc. High-density plasma (hdp) topography improvement with partial gapfill carbon

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6391781B1 (en) * 2000-01-06 2002-05-21 Oki Electric Industry Co., Ltd. Method of making a semiconductor device
CN103208453A (zh) * 2012-01-11 2013-07-17 国际商业机器公司 用于超薄绝缘体上半导体器件的电隔离结构及其制作方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5026666A (en) * 1989-12-28 1991-06-25 At&T Bell Laboratories Method of making integrated circuits having a planarized dielectric
JPH05235184A (ja) * 1992-02-26 1993-09-10 Nec Corp 半導体装置の多層配線構造体の製造方法
JP3311044B2 (ja) * 1992-10-27 2002-08-05 株式会社東芝 半導体装置の製造方法
US5741740A (en) * 1997-06-12 1998-04-21 Taiwan Semiconductor Manufacturing Company, Ltd. Shallow trench isolation (STI) method employing gap filling silicon oxide dielectric layer
US6020621A (en) * 1998-01-28 2000-02-01 Texas Instruments - Acer Incorporated Stress-free shallow trench isolation
US6197658B1 (en) * 1998-10-30 2001-03-06 Taiwan Semiconductor Manufacturing Company Sub-atmospheric pressure thermal chemical vapor deposition (SACVD) trench isolation method with attenuated surface sensitivity
US6300219B1 (en) * 1999-08-30 2001-10-09 Micron Technology, Inc. Method of forming trench isolation regions
US20010053583A1 (en) 1999-12-22 2001-12-20 Simon Fang Shallow trench isolation formation process using a sacrificial layer
TW492143B (en) 2001-05-11 2002-06-21 Macronix Int Co Ltd Manufacturing method of shallow trench isolation structure
US6664190B2 (en) 2001-09-14 2003-12-16 Chartered Semiconductor Manufacturing Ltd. Pre STI-CMP planarization scheme
KR100406179B1 (ko) * 2001-12-22 2003-11-17 주식회사 하이닉스반도체 플래쉬 메모리 셀의 자기 정렬 플로팅 게이트 형성 방법
KR20030053958A (ko) * 2001-12-24 2003-07-02 동부전자 주식회사 반도체 소자의 트랜지스터 제조방법
JP4018596B2 (ja) * 2002-10-02 2007-12-05 株式会社東芝 半導体装置の製造方法
US7265014B1 (en) * 2004-03-12 2007-09-04 Spansion Llc Avoiding field oxide gouging in shallow trench isolation (STI) regions
US8017493B2 (en) 2008-05-12 2011-09-13 Texas Instruments Incorporated Method of planarizing a semiconductor device
CN102386084B (zh) * 2010-09-01 2014-01-08 中芯国际集成电路制造(上海)有限公司 平坦化晶圆表面的方法
US8629514B2 (en) * 2011-01-18 2014-01-14 Wafertech, Llc Methods and structures for customized STI structures in semiconductor devices
CN105280545A (zh) * 2014-07-24 2016-01-27 联华电子股份有限公司 半导体装置的浅沟槽隔离结构与其制造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6391781B1 (en) * 2000-01-06 2002-05-21 Oki Electric Industry Co., Ltd. Method of making a semiconductor device
CN103208453A (zh) * 2012-01-11 2013-07-17 国际商业机器公司 用于超薄绝缘体上半导体器件的电隔离结构及其制作方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
超大规模集成电路制造中硅片平坦化技术的未来发展;郭东明等;《机械工程学报》;20031120(第10期);全文 *

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CN107690692A (zh) 2018-02-13
KR20180015628A (ko) 2018-02-13
US20170229340A1 (en) 2017-08-10
EP3308394B1 (en) 2022-07-27
TW201703194A (zh) 2017-01-16
JP2018517300A (ja) 2018-06-28
US9627246B2 (en) 2017-04-18
US20160365272A1 (en) 2016-12-15
WO2016200693A1 (en) 2016-12-15
EP3308394A1 (en) 2018-04-18

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