WO2016189643A1 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
WO2016189643A1
WO2016189643A1 PCT/JP2015/064998 JP2015064998W WO2016189643A1 WO 2016189643 A1 WO2016189643 A1 WO 2016189643A1 JP 2015064998 W JP2015064998 W JP 2015064998W WO 2016189643 A1 WO2016189643 A1 WO 2016189643A1
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WIPO (PCT)
Prior art keywords
film
solder bonding
metal film
electrode
semiconductor device
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PCT/JP2015/064998
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English (en)
French (fr)
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WO2016189643A9 (ja
Inventor
洋輔 中田
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三菱電機株式会社
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Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to CN201580080357.8A priority Critical patent/CN107615463B/zh
Priority to PCT/JP2015/064998 priority patent/WO2016189643A1/ja
Priority to US15/566,038 priority patent/US10177109B2/en
Priority to JP2017520113A priority patent/JP6456494B2/ja
Priority to DE112015006571.7T priority patent/DE112015006571T5/de
Publication of WO2016189643A1 publication Critical patent/WO2016189643A1/ja
Publication of WO2016189643A9 publication Critical patent/WO2016189643A9/ja

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Definitions

  • the present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device in which a semiconductor element and an external electrode are soldered together.
  • JP-A-2010-272711 a conductive layer made of nickel (Ni) as a metal film for solder bonding is formed on an electrode of a semiconductor element, and gold (Au) as a film for preventing oxidation of the conductive layer or
  • a semiconductor device in which an additional electrode is formed by laminating an anti-oxidation layer made of silver (Ag) or the like.
  • the conventional oxidation preventing film is made of an expensive noble metal material such as Au or Ag, which raises the problem of increasing the manufacturing cost of the semiconductor device.
  • a semiconductor substrate is thinly ground and electrodes are formed on the ground surface.
  • grinding is performed if the heavy metal constituting the metal film for solder bonding is exposed on the surface not to be ground before grinding, or if an oxidation preventing film made of, for example, a heavy metal material is formed on the metal film for solder bonding.
  • Heavy metal material adheres to the grinding surface where semiconductor substrate material (for example, silicon (Si)) is exposed at a time, and the heavy metal material is taken into the substrate material through a heat treatment process such as thermal diffusion performed after grinding. The effect on the lifetime of carriers in the device was enormous.
  • a metal surface and an anti-oxidation film for solder bonding are formed on the surface not ground after the electrode is formed on the ground surface to cover the ground surface and before the heat treatment step.
  • the method of forming was used.
  • Metal elements having an atomic number of 22 or less and excluding alkali metals and alkaline earth metals are less likely to affect semiconductor properties such as carrier lifetime in the device or ohmic contact on the ground surface, and therefore, they are not ground before grinding. , Can be deposited on the surface not ground.
  • the present invention has been made to solve the problems as described above.
  • the main object of the present invention is to reduce the manufacturing cost, to suppress the cracking of the semiconductor substrate, and to form a semiconductor element which does not affect the lifetime even if a metal film for solder bonding is formed before wafer grinding. It is an object of the present invention to provide a method of manufacturing a semiconductor layer in which the solder bonding metal film and the external electrode are well soldered by preventing the oxidation of the solder bonding metal film.
  • a method of manufacturing a semiconductor device comprises the steps of: preparing a semiconductor substrate having a first main surface and a second main surface located opposite to the first main surface; The steps of forming a first electrode on the main surface, forming a metal film for solder bonding on the first electrode, forming a sacrificial film on the metal film for solder bonding, and forming the sacrificial film A step of grinding the second main surface after formation, a step of performing heat treatment after the step of grinding, a step of removing the sacrificial film after the step of performing the heat treatment, the metal film for solder bonding And soldering the external electrode.
  • the thermal oxidation of the solder bonding metal film is suppressed, so the oxidation of the solder bonding metal film is performed.
  • the sacrificial film is finally removed from the semiconductor device and the sacrificial film itself may be thermally oxidized, it is made of a noble metal like an anti-oxidant film which is left without being removed from the semiconductor device.
  • FIG. 2 is a cross-sectional view for illustrating the semiconductor device according to the present embodiment. It is a flowchart of the manufacturing method of the semiconductor device concerning this embodiment.
  • FIG. 7 is a cross-sectional view for illustrating the method of manufacturing a semiconductor device according to the present embodiment.
  • FIG. 7 is a cross-sectional view for illustrating the method of manufacturing a semiconductor device according to the present embodiment.
  • FIG. 7 is a cross-sectional view for illustrating the method of manufacturing a semiconductor device according to the present embodiment.
  • FIG. 7 is a cross-sectional view for illustrating the method of manufacturing a semiconductor device according to the present embodiment.
  • FIG. 7 is a cross-sectional view for illustrating the method of manufacturing a semiconductor device according to the present embodiment.
  • FIG. 7 is a cross-sectional view for illustrating the method of manufacturing a semiconductor device according to the present embodiment.
  • FIG. 7 is a cross-sectional view for illustrating the method of manufacturing a semiconductor device according to the present embodiment.
  • FIG. 7 is a cross-sectional view for illustrating the method of manufacturing a semiconductor device according to the present embodiment.
  • FIG. 7 is a cross-sectional view for illustrating the method of manufacturing a semiconductor device according to the present embodiment.
  • a semiconductor device 100 according to the present embodiment will be described with reference to FIG.
  • the semiconductor device 100 includes the semiconductor element 1 formed on the semiconductor substrate 10.
  • the semiconductor substrate 10 has a first major surface 10A and a third major surface 10C located on the opposite side of the first major surface 10A.
  • the third main surface 10C is formed by partially grinding the second main surface 10B (see FIGS. 3 to 7) located on the opposite side of the first main surface 10A of the semiconductor substrate 10 It is a grinding surface.
  • the semiconductor element 1 may have any element structure, and may be configured as, for example, a vertical IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), or It may be configured as a diode. The element structure is not shown in FIGS.
  • a first electrode 11 serving as a main current path of the semiconductor element 1 and a control electrode 13 are formed on the first major surface 10A.
  • a first solder bonding metal film 21 is formed on the first electrode 11.
  • the first solder bonding metal film 21 is connected to the first external electrode 41 via the solder 31.
  • the first solder bonding metal film 21 and the first external electrode 41 are soldered together.
  • the control electrode 13 is connected to the third external electrode 43 via the metal wire 33. In other words, the control electrode 13 and the third external electrode 43 are wire-bonded.
  • a guard ring 14 is formed to surround the first electrode 11 and the control electrode 13 on the first major surface 10A.
  • the breakdown voltage holding area is formed to surround the cell area in which the element structure of the semiconductor element 1 is formed.
  • the semiconductor element 1 is configured as an IGBT
  • the first electrode 11 is configured as an emitter electrode
  • the control electrode 13 is configured as a gate electrode.
  • a protective film 15 is formed on the first major surface 10A. The protective film 15 may be formed on the withstand voltage holding area in which at least the guard ring 14 is formed, but the first main surface 10A so as to have an opening on the first electrode 11 and the control electrode 13 It may be formed on top.
  • a second electrode 12 which is a main current path of the semiconductor element 1 is formed.
  • a second solder bonding metal film 22 is formed on the second electrode 12.
  • the second solder bonding metal film 22 is connected to the second external electrodes 42 and 52 via the solder 32.
  • the second external electrodes 42 and 52 are formed by laminating and bonding the upper electrode 42 and the lower electrode 52.
  • the second solder bonding metal film 22 and the upper electrode 42 are soldered together.
  • the upper electrode 42 is connected to the fourth external electrode 44 via the solder 34.
  • the semiconductor device 100 is sealed by the sealing body 60 except for a part of the first external electrode 41, the lower electrodes 52 of the second external electrodes 42 and 52, the third external electrode 43, and the fourth external electrode 44. .
  • the material forming the semiconductor substrate 10 is, for example, silicon.
  • the material constituting the first electrode 11 and the control electrode 13 may be any material having conductivity, but preferably contains 95% by mass or more of aluminum (Al).
  • the material constituting the second electrode 12 contains, for example, Al.
  • the solders 31, 32, 34 may be made of any solder material, and the main constituent material is Sn.
  • Materials constituting the first solder bonding metal film 21 and the second solder bonding metal film 22 include, for example, nickel (Ni). That is, the materials constituting the first solder bonding metal film 21 and the second solder bonding metal film 22 may contain a metal element having an atomic number of 23 or more. In this way, it is possible to easily form an intermetallic compound and tin (Sn), which is the main constituent material of the solder 31, and solder bonding can be easily performed by a known method.
  • the film thickness of the first solder bonding metal film 21 can be arbitrarily set according to the bonding condition with the first external electrode 41 through the solder 31, but is, for example, 0.5 ⁇ m to 5 ⁇ m, preferably 1 ⁇ m. It is an extent.
  • the film thickness of the second solder bonding metal film 22 may be arbitrarily set according to the bonding conditions with the upper electrode 42 through the solder 32, the dicing conditions for the semiconductor substrate 10, etc., for example, 0.5 ⁇ m to 5 ⁇ m. Or less, preferably about 1 ⁇ m. In this way, the mechanical strength of the first solder bonding metal film 21 and the second solder bonding metal film 22 is maintained before and after the solder bonding with the first external electrode 41 or the second external electrodes 42, 52. Can. As a result, the reliability of the bonding interface between the first solder bonding metal film 21 and the first external electrode 41 and the reliability of the bonding interface between the second solder bonding metal film 22 and the upper electrode 42 can be secured. .
  • the first solder bonding metal film 21 and the second solder bonding metal film 22 can be easily made. Can be formed. As a result, the processing time in the step of forming the first solder bonding metal film 21 and the processing time in the step of forming the second solder bonding metal film 22 can be shortened, and a decrease in manufacturing yield is suppressed. can do.
  • the material constituting the protective film 15 may be any material having electrical insulation, and includes, for example, polyimide (photosensitive polyimide or non-photosensitive polyimide).
  • the material which comprises the metal wire 33 should just be any material which has electroconductivity, for example, contains A1.
  • the metal wire 33 is configured, for example, as an Al wire.
  • the material constituting the first external electrode 41, the second external electrodes 42, 52, the third external electrode 43, and the fourth external electrode 44 may be any material having conductivity, for example, copper (Cu) including.
  • the first outer electrode 41, the second outer electrodes 42, 52, the third outer electrode 43, and the fourth outer electrode 44 are configured, for example, as a Cu plate.
  • the material constituting the sealing body 60 may be any material having electrical insulation, and is, for example, a resin material, for example, a gel-like resin material before curing.
  • the semiconductor substrate 10 is prepared (step (S01)).
  • the semiconductor substrate 10 has a first major surface 10A and a second major surface 10B opposite to the first major surface 10A.
  • the film thickness of the semiconductor substrate 10 (the distance between the first major surface 10A and the second major surface 10B) is larger than the film thickness necessary for the semiconductor element 1 (the film thickness of the semiconductor substrate 10 in the semiconductor device 100), For example, it is 750 ⁇ m.
  • an element structure (not shown) of the semiconductor element 1 is formed on the side of the first major surface 10A of the semiconductor substrate 10 (step (S02)).
  • an element structure on the first major surface 10A side is formed on the first major surface 10A of the semiconductor substrate 10 by, for example, ion implantation or thermal diffusion.
  • this step (S01) includes the step of forming a gate insulating film, thereby forming the element structure of the insulated gate field effect transistor on the first main surface 10A side. Be done.
  • the first electrode 11 is formed on the first main surface 10A of the semiconductor substrate 10 (step (S03).
  • Any method of forming the first electrode 11 may be used.
  • a sputtering method or a vapor deposition method can be employed, and any method can be employed to pattern the first electrode 11.
  • a mask sputtering method or a lift-off method can be employed.
  • the control electrode 13 and the guard ring 14 are formed on the first major surface 10A of the semiconductor substrate 10.
  • the first solder bonding metal film 21 and the sacrificial film 23 are formed on the first electrode 11 (step (S04))
  • the method of forming the film 23 may be any method, for example, a sputtering method or a vapor deposition method
  • Fig. 4 shows that the first solder bonding metal film 21 and the sacrificial film 23 are formed by the sputtering method.
  • FIG. 2 is a cross-sectional view showing a method.
  • a metal mask 70 for sputtering having an opening 70a is prepared.
  • the opening 70a of the metal mask 70 is formed on the first main surface 10A on the central portion of the first electrode 11 (the area where the first solder bonding metal film 21 is to be formed) and on the first main surface 10A. They are formed and arranged to overlap in the intersecting direction (for example, the vertical direction).
  • the metal mask 70 is formed on the first major surface 10A so as to overlap the region other than the region where the first solder bonding metal film 21 is to be formed in the above-mentioned intersecting direction.
  • the first solder bonding metal film 21 and the sacrificial film 23 are formed through the metal mask 70.
  • the first solder bonding metal film 21 and the sacrificial film 23 are formed by mask sputtering.
  • the first solder bonding metal film 21 and the sacrificial film 23 are formed only on the region overlapping the opening 70 a on the first electrode 11.
  • the material constituting the sacrificial film 23 may be a material which can be selectively removed by etching as compared to the first solder bonding metal film 21.
  • the material has an atomic number of 22 or less, and an alkali metal or alkaline earth It is composed of an element which does not contain a metalloid, and more preferably contains titanium (Ti) or Al.
  • Ti titanium
  • the sacrificial film 23 can be easily removed while suppressing the etching of the first solder bonding metal film 21 in the step (S10) of removing the sacrificial film 23 described later.
  • the first solder bonding metal film 21 and the sacrificial film 23 can be easily and continuously formed in the same process.
  • the film thickness of the sacrificial film 23 may be arbitrarily set according to the heat treatment condition performed after the present step (S04), the etching condition in the step of removing the sacrificial film 23, etc., but is for example 0.02 ⁇ m or more and 1 ⁇ m or less And preferably about 0.1 ⁇ m.
  • oxygen (O 2 ) in the heat treatment step (for example, the ion implantation or thermal diffusion step in the step of forming the device structure on the third major surface 10C side) performed after the present step (S04) Can be prevented from reaching the first solder bonding metal film 21, and the thermal oxidation of Ni contained in the first solder bonding metal film 21 can be prevented.
  • the sacrificial film 23 can be easily formed and removed by suppressing the film thickness of the sacrificial film 23 within the above numerical range, the processing time in the process of forming and removing the sacrificial film 23 is shortened. It is possible to suppress the reduction of the manufacturing yield.
  • the first solder bonding metal film 21 and the sacrificial film 23 may be formed by the lift-off method.
  • FIG. 5 is a cross-sectional view showing a method of forming the first solder bonding metal film 21 and the sacrificial film 23 by the lift-off method.
  • a lift-off mask 80 having an opening 80a is prepared.
  • the lift-off mask 80 is, for example, a resist film, and the opening 80 a is formed by photolithography.
  • the opening 80 a is formed to expose the central portion of the first electrode 11 (the region where the first solder bonding metal film 21 is to be formed) on the first major surface 10 ⁇ / b> A.
  • the lift-off mask 80 is formed on the first major surface 10A so as to cover a region other than the region where the first solder bonding metal film 21 is to be formed.
  • the first solder bonding metal film 21 and the sacrificial film 23 are formed through the lift-off mask 80.
  • the first solder bonding metal film 21 and the sacrificial film 23 are formed, for example, by sputtering.
  • the first solder bonding metal film 21 and the sacrificial film 23 are formed on the first electrode 11 exposed in the opening 80 a of the lift-off mask 80 and on the lift-off mask 80.
  • the lift-off mask 80 is removed by any method.
  • the first solder bonding metal film 21 and the sacrificial film 23 formed on the lift-off mask 80 are also removed from the first main surface 10A, as shown in FIG. 5C. Only the first solder bonding metal film 21 and the sacrificial film 23 formed directly on the electrode 11 are left.
  • the first solder bonding metal film 21 and the sacrificial film 23 may be formed in separate steps. For example, in the present step (S04), after the step of forming the first solder bonding metal film 21, the step of forming the sacrificial film 23 may be performed.
  • the protective film 15 is formed on the first major surface 10A (step (S05)). Specifically, the protective film 15 is formed on the first major surface 10A, with the outer peripheral end of the first electrode 11 and the first solder bonding metal film 21, the outer peripheral end of the control electrode 13, and a guard ring. It is formed to cover 14.
  • the protective film 15 is formed by photolithography.
  • the material forming the protective film 15 is non-photosensitive polyimide, a non-photosensitive polyimide is coated on the first major surface 10A, and then a photo resist is used on the non-photosensitive polyimide.
  • the protective film 15 is formed by forming an etching mask by plate making and processing a non-photosensitive polyimide using the etching mask.
  • the protective film 15 is preferably not formed on the area to be diced in the dicing step described later.
  • the back surface (second main surface 10B) of the semiconductor substrate 10 is ground (step (S06)).
  • the second main surface 10B of the semiconductor substrate 10 is ground leaving an outer peripheral region c within a predetermined distance (for example, 2 mm) in the radial direction from the outer peripheral end of the semiconductor substrate
  • the main surface 10C is surfaced.
  • the film thickness (the distance between the first major surface 10A and the second major surface 10B) of the portion ground in the semiconductor substrate 10 is, for example, 100 ⁇ m.
  • the method of grinding the semiconductor substrate 10 may employ any method.
  • the present step (S06) is performed in a state in which a noble metal such as gold (Au) and a heavy metal such as Ni are not exposed on the first main surface 10A and the third main surface 10C.
  • This step (S06) is performed in a state where the semiconductor substrate 10, the first solder bonding metal film 21, the control electrode 13, and the protective film 15 are exposed, but all include noble metals and heavy metals as constituent materials. Not. Therefore, in the present step (S06), grinding powder containing a noble metal or heavy metal adheres to a region where semiconductor substrate 10 is exposed on second main surface 10B and first main surface 10A formed by grinding. It is being prevented.
  • an element structure (not shown) of the semiconductor element 1 is formed on the third main surface 10C side (step (S07)).
  • semiconductor element 1 is configured as an IGBT
  • a collector region is formed by ion implantation and thermal diffusion to third main surface 10C.
  • the semiconductor substrate 10 is heated to a predetermined temperature.
  • the grinding powder containing a noble metal or heavy metal is not attached on the area where the semiconductor substrate 10 is exposed on the third major surface 10C and the first major surface 10A, the semiconductor according to this step (S07) Thermal diffusion of noble metals and heavy metals into the substrate 10 is prevented.
  • the second electrode 12 is formed on the back surface (third main surface 10C) of the semiconductor substrate 10 (step (S08)).
  • the second electrode 12 may be formed by any method, for example, by sputtering.
  • the collector region and the second electrode are formed by depositing a material (for example, Al) constituting the second electrode 12 on the third major surface 10C in a state where the semiconductor substrate 10 is heated to a predetermined temperature. It is possible to reduce the electrical resistance at the bonding interface with T.12. The same effect can also be obtained by heating the semiconductor substrate 10 to a predetermined temperature after depositing the material forming the second electrode 12 without heating the semiconductor substrate 10.
  • the heat treatment process for the semiconductor substrate 10 in this case may be performed after the process (S09) for forming the second solder bonding metal film 22 described later.
  • the second solder bonding metal film 22 is formed on the second electrode 12 (step (S09)).
  • the method for forming the second metal film for solder bonding 22 may be any method, for example, a sputtering method, a vapor deposition method, or the like.
  • the anti-oxidation film 24 be formed on the second solder bonding metal film 22.
  • the material forming the anti-oxidation film 24 can be any material that is less likely to be oxidized as compared to the second solder bonding metal film 22, but is preferably Au.
  • the film thickness of the antioxidant film 24 may be arbitrarily set according to the bonding conditions with the second external electrodes 42 and 52 through the solder 32, but is, for example, 0.02 ⁇ m or more and 1 ⁇ m or less, preferably 0.1 ⁇ m. It is an extent.
  • the second solder bonding metal film 22 is covered with the oxidation preventing film 24, the oxidation of the second solder bonding metal film 22 can be prevented, and the second solder bonding metal film can be prevented. It is possible to prevent the decrease in the solder wettability of 22.
  • the solder wettability of the second solder bonding metal film 22 is lowered, a void is generated in the solder 32, and the heat conduction from the semiconductor element 1 to the second external electrode 42, 52 is generated on the void. There is a problem that it may be inhibited to generate heat locally on the void.
  • the formation of the oxidation preventing film 24 suppresses generation of voids in the solder 32 connecting the second solder bonding metal film 22 and the second external electrodes 42 and 52.
  • good heat conduction and electric conduction can be realized in the entire bonding surface of the second solder bonding metal film 22 and the upper electrode 42 (for example, the entire third major surface 10C).
  • the area of the region b (see FIG. 1) joined by the solder 32 on the third major surface 10C side is the solder via the solder 31 on the first major surface 10A side. It is larger than the area of the joined region a (see FIG. 1). Therefore, the solder 32 has a larger contribution rate to the cooling of the semiconductor element 1 than the solder 31. Therefore, it is preferable to suppress the occurrence of voids in the solder 32 over the entire surface of the second solder bonding metal film 22, so that the anti-oxidation film 24 is formed over the entire surface of the second solder bonding metal film 22. Is preferred.
  • the second electrode 12, the second solder bonding metal film 22, and the oxidation preventing film 24 are formed by being laminated on the third main surface 10 C of the semiconductor substrate 10. Ru.
  • the second electrode 12, the second solder bonding metal film 22, and the oxidation preventing film 24 may be continuously formed in the same process.
  • the sacrificial film 23 is removed (step (S10)).
  • a method of removing the sacrificial film 23 may be any method, for example, a wet etching method.
  • this step (S10) is performed, for example, by immersing the first major surface 10A of the semiconductor substrate 10 in hydrofluoric acid.
  • this step (S10) is performed, for example, by immersing the first main surface 10A of the semiconductor substrate 10 in phosphoric acid.
  • the sacrificial film 23 can be selectively removed by wet etching as compared to the first solder bonding metal film 21 by any method.
  • the semiconductor substrate 10 is diced (step (S11)). Thereby, the semiconductor element 1 is cut out from the semiconductor substrate 10.
  • the method of dicing the semiconductor substrate 10 may be any method, for example, blade dicing.
  • the first solder bonding metal film 21 of the semiconductor element 1 and the first external electrode 41 are soldered (step (S12)).
  • the solder of the solid phase is disposed between the first solder bonding metal film 21 and the first outer electrode 41, and heat treatment is applied to cool the first solder bonding metal film 21 and the first outer electrode 41. And are joined via the solder 31.
  • the second solder bonding metal film 22 and the upper electrodes 42 of the second external electrodes 42 and 52 are joined via the solder 32.
  • the present step (S12) is performed without heat treatment from the previous step (S11) from which the sacrificial film 23 is removed, the first solder bonding metal film 21 is formed in the present step (S12).
  • the oxide film is not formed with the heat treatment.
  • a heat treatment in which the semiconductor substrate 10 is heated to a predetermined temperature in a reducing atmosphere is performed as a pretreatment for the present step (S 12). It may be applied. In this way, the first solder bonding metal film 21 and the oxide film formed on the solid phase solder surface can be removed simultaneously, and the solder wettability of the first solder bonding metal film 21 is recovered. be able to.
  • the anti-oxidation film 24 is formed on the second solder bonding metal film 22, no oxide film is formed. Further, when the film thickness of the oxidation preventing film 24 is about 0.1 ⁇ m, the oxidation preventing film 24 is contained in the solder 32 at the time of solder bonding between the second solder bonding metal film 22 and the second external electrodes 42, 52. It disappears by spreading.
  • step (S13) the semiconductor element 1 is sealed by the sealing body 60 (step (S13)).
  • the step of forming sealing body 60 is, for example, a transfer molding method.
  • the semiconductor device 100 as shown in FIG. 1 is manufactured.
  • the step of heat treatment (S07) is performed after the step of forming the sacrificial film 23 on the first solder bonding metal film 21 (S04), and in the step (S07), the first solder bonding metal is formed.
  • a sacrificial film 23 is formed on the film 21.
  • the step of removing the sacrificial film 23 (S10) is carried out after the step of heat treatment (S07), and then the step of solder bonding the first solder bonding metal film 21 to the first external electrode 41 (S12) is carried out Be done. Therefore, in the step of soldering (S12), no thermal oxide film is formed on the first solder bonding metal film 21 by heat treatment, and only a natural oxide film is formed.
  • a pretreatment before soldering in the bonding step (S12) a simple method for removing a natural oxide film without forming an oxidation preventing film made of a noble metal on the first solder bonding metal film 21.
  • the first solder bonding metal film 21 and the first external electrode 41 can be well soldered through the solder 31 in which no void is generated.
  • the sacrificial film 23 may be finally removed from the semiconductor device 100, and the sacrificial film 23 itself may be made of a material that is easily oxidized. That is, it is not necessary to form a film made of heavy metal like the anti-oxidation film 24 left on the semiconductor device 100 without being removed from the top of the first solder bonding metal film 21.
  • the thermal oxidation of the first solder bonding metal film 21 can be suppressed by the sacrificial film 23 made of a low cost material.
  • the semiconductor substrate 10 is cracked. The occurrence is suppressed.
  • the manufacturing cost is suppressed, and the cracking of the semiconductor substrate is suppressed, and the first solder bonding metal film 21 and the first external electrode 41 are well connected thermally and electrically via the solder 31.
  • the film thickness of the semiconductor substrate 10 is equal to that of the step (S03). It implements with respect to the semiconductor substrate 10 which has the uniform film thickness before reducing partially. Therefore, in the step (S03), since warpage or the like is suppressed in the semiconductor substrate 10, the first solder bonding metal film 21 and the sacrificial film 23 can be easily made by, for example, a lift-off method using photolithography. It can be formed.
  • the first solder bonding metal film 21 and the sacrificial film 23 are formed by the sputtering method, if the film thickness of the semiconductor substrate 10 is partially reduced, the temperature of the semiconductor substrate 10 is rapidly increased. Temperature non-uniformity occurs to cause cracking or the like of the semiconductor substrate 10.
  • the first solder bonding metal film 21 and the sacrificial film 23 are formed on the semiconductor substrate 10 having a uniform film thickness before being partially ground. Even if sputtering is used, generation of cracks and the like in the semiconductor substrate 10 can be suppressed.
  • the semiconductor substrate 10 can be prevented from being cracked or the like by physical contact such as transportation of the semiconductor substrate 10 or fixation of the semiconductor substrate 10 in each processing apparatus. The semiconductor substrate 10 can be easily handled.
  • the material forming the sacrificial film 23 is preferably a material that can be selectively removed by etching compared to the first solder bonding metal film 21.
  • the sacrificial film 23 can be easily removed in the step of removing the sacrificial film 23 (S10). Furthermore, since the film reduction of the first solder bonding metal film 21 is suppressed in the step (S10), the mechanical strength of the first solder bonding metal film 21 is measured before and after the solder bonding with the first external electrode 41. Can be maintained. As a result, the reliability of the bonding interface between the first solder bonding metal film 21 and the first external electrode 41 can be secured.
  • the material constituting the first solder bonding metal film 21 contains Ni.
  • Ni in the first solder bonding metal film 21 can easily form an intermetallic compound with Sn, which is the main constituent material of the solder 31, so the first solder bonding metal film 21 can be formed.
  • the first external electrode 41 have a good bonding state. Also, in this case, the first solder bonding metal film 21 and the first external electrode 41 can be easily soldered by the known method.
  • the material constituting the sacrificial film 23 preferably contains at least one of Ti and Al.
  • the sacrificial film 23 can be easily removed while suppressing the etching of the first solder bonding metal film 21 in the step (S10) of removing the sacrificial film 23 described later.
  • the first solder bonding metal film 21 and the sacrificial film 23 can be easily and continuously formed in the same process.
  • the semiconductor device 100 is manufactured in which the manufacturing cost is reduced and the metal film for solder bonding and the external electrode are well soldered by preventing the oxidation of the metal film for solder bonding. be able to.
  • the method of manufacturing a semiconductor device according to the present embodiment preferably includes the step (S05) of forming the protective film 15 on the first major surface 10A of the semiconductor substrate 10.
  • the step (S10) of removing the sacrificial film 23 is preferably performed after the step (S05) of forming the protective film 15.
  • the step of grinding (S06) is preferably performed after the step of forming protective film 15 (S05).
  • the step (S05) of forming the protective film 15 and the steps (S01 to S04) performed before the step (S05) are performed before the film thickness of the semiconductor substrate 10 is partially reduced. It implements with respect to the semiconductor substrate 10 which has uniform film thickness. Therefore, in the step (S05), the occurrence of warpage or the like in the semiconductor substrate 10 is suppressed, so that the protective film 15 can be easily formed using, for example, photolithography. Further, in the step (S05) of forming the protective film 15, it is possible to suppress the occurrence of a crack or the like in the semiconductor substrate 10, and the semiconductor substrate 10 can be easily handled.
  • the material which comprises the protective film 15 contains a polyimide. In this way, even if a residual of protective film 15 occurs in the step of forming protective film 15 (S05), the hydrofluoric acid or phosphoric acid in the step of removing sacrificial film 23 (S10) is used. By the etching process, the residual film can be easily removed together with the sacrificial film 23.
  • the material which comprises the 1st electrode 11 contains Al, and the content rate of Al in the 1st electrode 11 is 95 mass% or more. In this way, the first electrode 11 can be easily formed by a known method.
  • the material constituting the control electrode 13 contains Al in order to realize excellent bonding reliability between the metal wire 33 and the control electrode 13,
  • the content of Al in the control electrode 13 is preferably 95% by mass or more. Also in such a case, if the first electrode 11 is configured as described above, in the step of forming the first electrode 11, the first electrode 11 and the control electrode 13 are simultaneously formed on the first major surface 10A. It can be formed.
  • the step (S06) of grinding after forming the sacrificial film 23 is performed, and the element structure is formed on the third major surface 10C side after the step (S06).
  • the step (S07) of forming the step (S07) is performed, and the step (S10) of removing the sacrificial film 23 is performed after the step (S07), and the step (S12) of soldering is performed after the step (S10).
  • the protective film 15 may be formed after the first solder bonding metal film 21 is formed, and then the sacrificial film 23 may be formed.
  • the sacrificial film 23 may be formed, for example, on a portion of the first solder bonding metal film 21 and the protective film 15 facing the opening exposing the first solder bonding metal film 21. Also in this case, the same function and effect as the method of manufacturing a semiconductor device according to the present embodiment can be obtained.
  • the present invention is particularly advantageously applied to a method of manufacturing a semiconductor device provided with a semiconductor substrate in which a semiconductor element and an external electrode are soldered and which is ground to reduce a film thickness.
  • SYMBOLS 1 semiconductor element 10 semiconductor substrate, 10A 1st main surface, 10B 2nd main surface, 10C 3rd main surface, 11 1st electrode, 12 2nd electrode, 13 control electrode, 14 guard ring, 15 protection Film, 21 first solder bonding metal film, 22 second solder bonding metal film, 23 sacrificial film, 24 antioxidant film, 31, 32, 34 solder, 33 metal wire, 41 first external electrode, 42 upper electrode ( Second external electrode), 52 lower electrode (second external electrode), 43 third external electrode, 44 fourth external electrode, 60 sealing body, 70 metal mask, 70a, 80a opening, 80 lift-off mask, 100 semiconductor apparatus.

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Abstract

第１の主面と、第１の主面の反対側に位置する第２の主面とを有する半導体基板を準備する工程（Ｓ０１）と、第１の主面上に第１電極を形成する工程（Ｓ０２）と、第１電極上にはんだ接合用金属膜（第１はんだ接合用金属膜）を形成する工程（Ｓ０３）と、第１はんだ接合用金属膜上に犠牲膜を形成する工程（Ｓ０４）と、犠牲膜を形成した後に第２の主面を研削する工程（Ｓ０６）と、研削する工程（Ｓ０６）の後に熱処理を行う工程（第３の主面側に素子構造を形成する工程（Ｓ０７））と、熱処理を行う工程（Ｓ０７）の後に犠牲膜を除去する工程（Ｓ１０）と、第１はんだ接合用金属膜と第１外部電極とをはんだ接合する工程（Ｓ１２）とを備える。

Description

半導体装置の製造方法
　本発明は、半導体装置の製造方法に関し、特に半導体素子と外部電極とがはんだ接合されている半導体装置の製造方法に関する。
　半導体素子に形成されている電極と外部電極とがはんだ接合されている半導体装置が知られている（たとえば特開２００８－１８２０７４号公報参照）。はんだにより半導体素子の電極と外部電極とを直接接合することにより、電気抵抗を下げ、大電流通電が可能な配線接続を実現することができる。
　また、はんだ接合される半導体素子の電極上に、酸化膜の形成を抑制するための酸化防止膜が形成された半導体装置が知られている。特開２０１０－２７２７１１号公報には、半導体素子の電極上に、はんだ接合用の金属膜としてニッケル（Ｎｉ）からなる導電体層と、該導体層の酸化を防止する膜として金（Ａｕ）または銀（Ａｇ）などからなる酸化防止層とが積層した付加電極が形成されている半導体デバイスが開示されている。
特開２００８－１８２０７４号公報 特開２０１０－２７２７１１号公報
　しかしながら、従来の酸化防止膜は上述のようにＡｕやＡｇなどの高価な貴金属材料で構成されており、半導体装置の製造コストを高めているという問題がある。
　また、パワー半導体装置などでは、通電性能を改善するために半導体基板を薄く研削し研削面に電極形成することが行われている。このとき、研削前に、研削されない面にはんだ接合用の金属膜を構成する重金属が露出していたり、はんだ接合用金属膜上に例えば重金属材料からなる酸化防止膜を形成しておくと、研削時において半導体基板材料（たとえばケイ素（Ｓｉ））が露出している研削面に重金属材料が付着し、研削後に実施される熱拡散などの熱処理工程を経ることにより基板材料中に重金属材料が取り込まれ、素子中のキャリアのライフタイムに与える影響が甚大であった。そのため、従来の半導体装置の製造方法では、研削面に電極を形成して研削面を被覆した後であって熱処理工程前に、研削されていない面上にはんだ接合用の金属膜および酸化防止膜を形成する方法が採用されていた。原子番号２２以下で、かつ、アルカリ金属、アルカリ土類金属を除く金属元素は、素子中のキャリアのライフタイムまたは研削面のオーミックコンタクトなどの半導体特性に影響を与える可能性が低く、研削前に、研削されない面上に堆積することができる。一方、原子番号２６以上の重金属、アルカリ金属、アルカリ土類金属、もしくは磁性を有する金属元素は、素子中のキャリアのライフタイムや研削面のオーミックコンタクトなどの半導体特性に影響を与える可能性が高いため、研削前に、研削されない面上に堆積することは避けることが望ましい。
　しかしながら、研削後に研削されていない面上に酸化防止膜などを形成する場合、搬送中や成膜中などに半導体基板に割れが生じることがあり、歩留まりが低下するといった問題が発生していた。
　本発明は、上記のような課題を解決するためになされたものである。本発明の主たる目的は、製造コストが低減されているとともに、半導体基板の割れが抑制されており、さらにウエハ研削前にはんだ接合用金属膜を形成してもライフタイムに影響しない半導体素子を形成できるとともに、はんだ接合用金属膜の酸化が防止されることによりはんだ接合用金属膜と外部電極とが良好にはんだ接合されている、半導体層の製造方法を提供することにある。
　本発明に係る半導体装置の製造方法は、第１の主面と、前記第１の主面の反対側に位置する第２の主面とを有する半導体基板を準備する工程と、前記第１の主面上に第１電極を形成する工程と、前記第１電極上にはんだ接合用金属膜を形成する工程と、前記はんだ接合用金属膜上に犠牲膜を形成する工程と、前記犠牲膜を形成した後に前記第２の主面を研削する工程と、前記研削する工程の後に熱処理を行う工程と、前記熱処理を行う工程の後に前記犠牲膜を除去する工程と、前記はんだ接合用金属膜と外部電極とをはんだ接合する工程とを備える。
　本発明によれば、はんだ接合用金属膜上に犠牲膜が形成されている状態で熱処理が行われるため、はんだ接合用金属膜の熱酸化が抑制されているので、はんだ接合用金属膜の酸化が防止されることによりはんだ接合用金属膜と外部電極とが良好にはんだ接合されている、半導体装置の製造方法を提供することができる。また、犠牲膜は半導体装置上から最終的に除去されるものであり犠牲膜自体は熱酸化されてもよいため、半導体装置上から除去されずに残される酸化防止膜のように貴金属で構成されている必要がない。そのため、製造コストが低減されている、半導体装置の製造方法を提供することができる。さらにウエハ研削前にはんだ接合用金属膜を形成してもライフタイムに影響しない半導体素子を形成できる。また、研削する工程の後に第１の主面上に酸化防止膜などを形成する工程が実施されないため、半導体基板に割れが生じることが抑制されている、半導体装置の製造方法を提供することができる。
本実施の形態に係る半導体装置を説明するための断面図である。 本実施の形態に係る半導体装置の製造方法のフローチャートである。 本実施の形態に係る半導体装置の製造方法を説明するための断面図である。 本実施の形態に係る半導体装置の製造方法を説明するための断面図である。 本実施の形態に係る半導体装置の製造方法を説明するための断面図である。 本実施の形態に係る半導体装置の製造方法を説明するための断面図である。 本実施の形態に係る半導体装置の製造方法を説明するための断面図である。 本実施の形態に係る半導体装置の製造方法を説明するための断面図である。 本実施の形態に係る半導体装置の製造方法を説明するための断面図である。 本実施の形態に係る半導体装置の製造方法を説明するための断面図である。
　以下、図面を参照して、本発明の実施の形態について説明する。なお、以下の図面において同一または相当する部分には、同一の参照符号を付し、その説明は繰り返さない。
　図１を参照して、本実施の形態に係る半導体装置１００について説明する。半導体装置１００は、半導体基板１０に形成されている半導体素子１を備える。
　半導体基板１０は、第１の主面１０Ａと第１の主面１０Ａの反対側に位置する第３の主面１０Ｃとを有している。第３の主面１０Ｃは、半導体基板１０の第１の主面１０Ａの反対側に位置する第２の主面１０Ｂ（図３～図７参照）が部分的に研削されることにより形成された研削面である。半導体素子１は、任意の素子構造を有していればよく、たとえば縦型ＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ　Ｇａｔｅ　Ｂｉｐｏｌａｒ　Ｔｒａｎｓｉｓｔｏｒ）またはＭＯＳＦＥＴ（Ｍｅｔａｌ－Ｏｘｉｄｅ－Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｆｉｅｌｄ－Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ）として構成されていてもよいし、整流ダイオードとして構成されていてもよい。なお、図１～図１０において、素子構造の図示は省略する。
　第１の主面１０Ａ上には、半導体素子１の主な電流経路となる第１電極１１と、制御用電極１３とが形成されている。第１電極１１上には、第１はんだ接合用金属膜２１が形成されている。第１はんだ接合用金属膜２１は、はんだ３１を介して第１外部電極４１と接続されている。第１はんだ接合用金属膜２１と第１外部電極４１とは、はんだ接合されている。制御用電極１３は、金属ワイヤ３３を介して第３外部電極４３と接続されている。言い換えると、制御用電極１３と第３外部電極４３とは、ワイヤボンディングされている。
　また、第１の主面１０Ａにおいて第１電極１１および制御用電極１３を囲うようにガードリング１４が形成されている。言い換えると、半導体素子１の素子構造が形成されているセル領域を囲むように耐圧保持領域が形成されている。半導体素子１がＩＧＢＴとして構成されている場合には、たとえば第１電極１１がエミッタ電極、制御用電極１３がゲート電極として構成されている。第１の主面１０Ａ上には、保護膜１５が形成されている。保護膜１５は、少なくともガードリング１４が形成されている耐圧保持領域上に形成されていればよいが、第１電極１１および制御用電極１３上に開口部を有するように第１の主面１０Ａ上に形成されていてもよい。
　第３の主面１０Ｃ上には、半導体素子１の主な電流経路となる第２電極１２が形成されている。第２電極１２上には、第２はんだ接合用金属膜２２が形成されている。第２はんだ接合用金属膜２２は、はんだ３２を介して第２外部電極４２，５２と接続されている。第２外部電極４２，５２は、上部電極４２と下部電極５２とが積層して接合されたものである。第２はんだ接合用金属膜２２と上部電極４２とは、はんだ接合されている。上部電極４２は、はんだ３４を介して第４外部電極４４と接続されている。
　半導体装置１００は、第１外部電極４１、第２外部電極４２，５２の下部電極５２、第３外部電極４３、第４外部電極４４の一部を除き、封止体６０により封止されている。
　半導体基板１０を構成する材料は、たとえばシリコンである。第１電極１１および制御用電極１３を構成する材料は、導電性を有する任意の材料とすればよいが、好ましくはアルミニウム（Ａｌ）を９５質量％以上含む。第２電極１２を構成する材料は、たとえばＡｌを含む。
　はんだ３１，３２，３４は、任意のはんだ材料で構成されていればよく、主な構成材料がＳｎである。
　第１はんだ接合用金属膜２１および第２はんだ接合用金属膜２２を構成する材料は、たとえばニッケル（Ｎｉ）を含む。つまり、第１はんだ接合用金属膜２１および第２はんだ接合用金属膜２２を構成する材料は、原子番号２３以上の金属元素を含んでいてもよい。このようにすれば、はんだ３１の主な構成材料であるスズ（Ｓｎ）と金属間化合物を容易に形成することができ、周知の方法により容易にはんだ接合可能である。第１はんだ接合用金属膜２１の膜厚は、はんだ３１を介した第１外部電極４１との接合条件に応じて任意に設定され得るが、たとえば０．５μｍ以上５μｍ以下であり、好ましくは１μｍ程度である。第２はんだ接合用金属膜２２の膜厚は、はんだ３２を介した上部電極４２との接合条件や、半導体基板１０に対するダイシング条件などに応じて任意に設定され得るが、たとえば０．５μｍ以上５μｍ以下であり、好ましくは１μｍ程度である。このようにすれば、第１はんだ接合用金属膜２１および第２はんだ接合用金属膜２２の機械的強度を第１外部電極４１または第２外部電極４２，５２とのはんだ接合前後で維持することができる。その結果、第１はんだ接合用金属膜２１と第１外部電極４１との接合界面の信頼性および第２はんだ接合用金属膜２２と上部電極４２との接合界面の信頼性を確保することができる。また、第１はんだ接合用金属膜２１および第２はんだ接合用金属膜２２の膜厚を上記数値範囲内に抑えることにより第１はんだ接合用金属膜２１および第２はんだ接合用金属膜２２を容易に形成することができる。その結果、第１はんだ接合用金属膜２１を形成する工程での処理時間および第２はんだ接合用金属膜２２を形成する工程での処理時間を短縮することができ、かつ製造歩留まりの低下を抑制することができる。
　保護膜１５を構成する材料は、電気的絶縁性を有する任意の材料であればよいが、たとえばポリイミド（感光性ポリイミドまたは非感光性ポリイミド）を含む。
　金属ワイヤ３３を構成する材料は導電性を有する任意の材料であればよく、たとえばＡ１を含む。金属ワイヤ３３はたとえばＡｌワイヤとして構成されている。
　第１外部電極４１、第２外部電極４２，５２、第３外部電極４３、および第４外部電極４４を構成する材料は、導電性を有する任意の材料であればよいが、たとえば銅（Ｃｕ）を含む。第１外部電極４１、第２外部電極４２，５２、第３外部電極４３、および第４外部電極４４は、たとえばＣｕ板として構成されている。
　封止体６０を構成する材料は、電気的絶縁性を有する任意の材料であればよいが、たとえば樹脂材料であり、たとえば硬化前においてはゲル状の樹脂材料である。
　図２～図１０を参照して、本実施の形態に係る半導体装置の製造方法について説明する。
　まず、半導体基板１０が準備される（工程（Ｓ０１））。半導体基板１０は、第１の主面１０Ａと第１の主面１０Ａと反対側に位置する第２の主面１０Ｂとを有する。半導体基板１０の膜厚（第１の主面１０Ａと第２の主面１０Ｂとの距離）は、半導体素子１として必要な膜厚（半導体装置１００における半導体基板１０の膜厚）よりも厚く、たとえば７５０μｍである。
　次に、半導体基板１０の第１の主面１０Ａ側において半導体素子１の素子構造（図示しない）が形成される（工程（Ｓ０２））。具体的には、半導体基板１０の第１の主面１０Ａに対し、たとえばイオン注入または熱拡散などにより第１の主面１０Ａ側の素子構造が形成される。半導体素子１がＩＧＢＴとして構成される場合には、本工程（Ｓ０１）はゲート絶縁膜を形成する工程を含み、これにより第１の主面１０Ａ側に絶縁ゲート型電界効果トランジスタの素子構造が形成される。
　次に、図３に示されるように、半導体基板１０の第１の主面１０Ａ上に第１電極１１が形成される（工程（Ｓ０３）。第１電極１１を成膜する方法は、任意の方法を採用することができ、たとえばスパッタリング法または蒸着法である。また、第１電極１１をパターニングする方法は、任意の方法を採用することができるが、たとえばマスクスパッタリング法やリフトオフ法である。本工程（Ｓ０３）では、第１電極１１に加えて、半導体基板１０の第１の主面１０Ａ上に、制御用電極１３およびガードリング１４が形成される。
　次に、図４に示されるように、第１電極１１上に第１はんだ接合用金属膜２１および犠牲膜２３が形成される（工程（Ｓ０４）。第１はんだ接合用金属膜２１および犠牲膜２３を成膜する方法は、任意の方法を採用することができるが、たとえばスパッタリング法または蒸着法である。図４は、スパッタリング法により第１はんだ接合用金属膜２１および犠牲膜２３を形成する方法を示す断面図である。
　図４（ａ）に示されるように、開口部７０ａを有するスパッタリング用の金属マスク７０を準備する。金属マスク７０の開口部７０ａは、第１の主面１０Ａ上における第１電極１１の中央部分（第１はんだ接合用金属膜２１が形成されるべき領域）上と、第１の主面１０Ａに交差する方向（たとえば垂直な方向）において重なるように形成され、配置されている。言い換えると、金属マスク７０は、第１の主面１０Ａ上において第１はんだ接合用金属膜２１が形成されるべき領域以外の領域と上記交差する方向において重なるよう形成されている。
　次に、図４（ｂ）に示されるように、金属マスク７０を介して第１はんだ接合用金属膜２１および犠牲膜２３が成膜される。第１はんだ接合用金属膜２１および犠牲膜２３は、マスクスパッタリング法により成膜される。これにより、図４（ｃ）に示されるように、第１電極１１上において開口部７０ａと重なる領域上にのみ第１はんだ接合用金属膜２１および犠牲膜２３が形成される。
　犠牲膜２３を構成する材料は、第１はんだ接合用金属膜２１と比べてエッチングにより選択的に除去可能な材料であればよいが、好ましくは原子番号２２以下で、かつ、アルカリ金属、アルカリ土類金属を含まない元素で構成されており、より好ましくはチタン（Ｔｉ）またはＡｌを含む。このようにすれば、後述する犠牲膜２３を除去する工程（Ｓ１０）において、第１はんだ接合用金属膜２１のエッチングを抑制しながら犠牲膜２３を容易に除去することができる。また、このようにすれば、第１はんだ接合用金属膜２１と犠牲膜２３とを同一工程において連続して容易に形成することができる。
　犠牲膜２３の膜厚は、本工程（Ｓ０４）後に実施される熱処理条件や犠牲膜２３を除去する工程でのエッチング条件などに応じて任意に設定され得るが、たとえば０．０２μｍ以上１μｍ以下であり、好ましくは０．１μｍ程度である。このようにすれば、本工程（Ｓ０４）後に実施される熱処理工程（たとえば、第３の主面１０Ｃ側において素子構造を形成する工程でのイオン注入または熱拡散工程）において、酸素（Ｏ２）が第１はんだ接合用金属膜２１に到達することを防止することができ、第１はんだ接合用金属膜２１に含まれるＮｉが熱酸化することを防止することができる。また、犠牲膜２３の膜厚を上記数値範囲内に抑えることにより犠牲膜２３を容易に形成しまた除去することができるため、犠牲膜２３を形成する工程および除去する工程での処理時間を短縮することができ、かつ製造歩留まりの低下を抑制することができる。
　なお、本工程（Ｓ０４）は、リフトオフ法により第１はんだ接合用金属膜２１および犠牲膜２３が形成されてもよい。図５は、リフトオフ法により第１はんだ接合用金属膜２１および犠牲膜２３を形成する方法を示す断面図である。
　図５（ａ）に示されるように、開口部８０ａを有するリフトオフ用マスク８０を準備する。リフトオフ用マスク８０は、たとえばレジスト膜であり、写真製版により開口部８０ａが形成されている。開口部８０ａは、第１の主面１０Ａ上における第１電極１１の中央部分（第１はんだ接合用金属膜２１が形成されるべき領域）を露出するように形成されている。言い換えると、リフトオフ用マスク８０は、第１の主面１０Ａ上において第１はんだ接合用金属膜２１が形成されるべき領域以外の領域を覆うように形成されている。
　次に、図５（ｂ）に示されるように、リフトオフ用マスク８０を介して第１はんだ接合用金属膜２１および犠牲膜２３が成膜される。第１はんだ接合用金属膜２１および犠牲膜２３は、たとえばスパッタリング法により成膜される。これにより、第１はんだ接合用金属膜２１および犠牲膜２３は、リフトオフ用マスク８０の開口部８０ａ内に露出している第１電極１１上およびリフトオフ用マスク８０上に形成される。その後、任意の方法によりリフトオフ用マスク８０が除去される。これにより、リフトオフ用マスク８０上に形成されていた第１はんだ接合用金属膜２１および犠牲膜２３も第１の主面１０Ａ上から取り除かれ、図５（ｃ）に示されるように、第１電極１１上に直接形成された第１はんだ接合用金属膜２１および犠牲膜２３のみが残される。
　なお、第１はんだ接合用金属膜２１と犠牲膜２３とは、別工程により形成されてもよい。たとえば、本工程（Ｓ０４）では、第１はんだ接合用金属膜２１を形成する工程の後に、犠牲膜２３を形成する工程が実施されてもよい。
　次に、図６に示されるように、第１の主面１０Ａ上に保護膜１５が形成される（工程（Ｓ０５））。具体的には、保護膜１５は、第１の主面１０Ａ上において、第１電極１１および第１はんだ接合用金属膜２１の外周端部と、制御用電極１３の外周端部と、ガードリング１４上を覆うように形成される。保護膜１５を構成する材料が感光性ポリイミドである場合には、写真製版により保護膜１５が形成される。また、保護膜１５を構成する材料が非感光性ポリイミドである場合には、非感光性ポリイミドを第１の主面１０Ａ上に塗布した後、非感光性ポリイミド上に感光性レジストを用いて写真製版によりエッチングマスクを形成し、該エッチングマスクを用いて非感光性ポリイミドを加工することにより、保護膜１５が形成される。保護膜１５は、好ましくは後述するダイシング工程においてダイシングされる領域上に形成されない。
　次に、図７に示されるように、半導体基板１０の裏面（第２の主面１０Ｂ）が研削される（工程（Ｓ０６））。具体的には、半導体基板１０の第２の主面１０Ｂが、半導体基板１０の外周端部から径方向に所定の距離（たとえば２ｍｍ）内にある外周領域ｃを残して研削され、第３の主面１０Ｃが面出しされる。このようにして、半導体基板１０において研削された部分の膜厚（第１の主面１０Ａと第２の主面１０Ｂとの距離）は、たとえば１００μｍとなる。半導体基板１０を研削する方法は、任意の方法を採用し得る。外周領域ｃの膜厚を維持して外周領域ｃに囲まれている内側領域のみを研削することにより、研削後の半導体基板１０に反りなどが発生することを抑制することができる。なお、本工程（Ｓ０６）は、第１の主面１０Ａおよび第３の主面１０Ｃ側において、金（Ａｕ）などの貴金属、およびＮｉなどの重金属が露出していない状態で行われる。本工程（Ｓ０６）は、半導体基板１０、第１はんだ接合用金属膜２１、制御用電極１３、および保護膜１５が露出している状態で行われるが、いずれも貴金属および重金属を構成材料に含んでいない。そのため、本工程（Ｓ０６）では、研削により形成される第２の主面１０Ｂ上および第１の主面１０Ａ上において半導体基板１０が表出している領域などに貴金属または重金属を含む研削粉が付着することが防止されている。
　次に、第３の主面１０Ｃ側において半導体素子１の素子構造（図示しない）が形成される（工程（Ｓ０７））。たとえば半導体素子１がＩＧＢＴとして構成される場合には、第３の主面１０Ｃに対するイオン注入および熱拡散により、コレクタ領域が形成される。本工程（Ｓ０７）では、半導体基板１０は所定の温度に加熱される。このとき、貴金属または重金属を含む研削粉は第３の主面１０Ｃおよび第１の主面１０Ａ上において半導体基板１０が表出している領域上に付着していないため、本工程（Ｓ０７）により半導体基板１０内に貴金属および重金属が熱拡散することが防止されている。
　次に、半導体基板１０の裏面（第３の主面１０Ｃ）に第２電極１２が形成される（工程（Ｓ０８））。第２電極１２は、任意の方法により形成され得るが、たとえばスパッタリング法により形成される。このとき、半導体基板１０が所定の温度に加熱された状態で第２電極１２を構成する材料（たとえばＡｌ）を第３の主面１０Ｃ上に成膜することにより、上記コレクタ領域と第２電極１２との接合界面の電気抵抗を低減することができる。また、半導体基板１０を加熱せずに第２電極１２を構成する材料を成膜した後、半導体基板１０を所定の温度に加熱することによっても、同様の効果を奏することができる。なお、この場合の半導体基板１０に対する熱処理工程は、後述する第２はんだ接合用金属膜２２を形成する工程（Ｓ０９）の後に実施してもよい。
　次に、第２電極１２上に第２はんだ接合用金属膜２２が形成される（工程（Ｓ０９））。第２はんだ接合用金属膜２２を形成する方法は、任意の方法を採用し得るが、たとえばスパッタリング法または蒸着法などである。本工程（Ｓ０９）では、第２はんだ接合用金属膜２２上に酸化防止膜２４が形成されるのが好ましい。酸化防止膜２４を構成する材料は、第２はんだ接合用金属膜２２と比べて酸化し難い任意の材料とすることができるが、好ましくはＡｕである。酸化防止膜２４の膜厚は、はんだ３２を介した第２外部電極４２，５２との接合条件に応じて任意に設定され得るが、たとえば０．０２μｍ以上１μｍ以下であり、好ましくは０．１μｍ程度である。
　このようにすれば、酸化防止膜２４により第２はんだ接合用金属膜２２が覆われていることにより第２はんだ接合用金属膜２２の酸化を防止することができ、第２はんだ接合用金属膜２２のはんだ濡れ性の低下を防止することができる。第２はんだ接合用金属膜２２のはんだ濡れ性が低下している場合には、はんだ３２中にボイドが発生し、当該ボイド上で半導体素子１から第２外部電極４２，５２への熱伝導が阻害されてボイド上で局所的に発熱するといった問題が生じることがある。これに対し、酸化防止膜２４が形成されていることにより、第２はんだ接合用金属膜２２と第２外部電極４２，５２とを接続するはんだ３２中にボイドが発生することを抑制することができき、第２はんだ接合用金属膜２２と上部電極４２との接合面全体（たとえば第３の主面１０Ｃの全体）において良好な熱伝導および電気伝導を実現することができる。
　なお、半導体装置１００において、第３の主面１０Ｃ側ではんだ３２を介してはんだ接合されている領域ｂ（図１参照）の面積は、第１の主面１０Ａ側ではんだ３１を介してはんだ接合されている領域ａ（図１参照）の面積よりも大きい。そのため、はんだ３２は、はんだ３１と比べて半導体素子１の冷却に対する寄与率が大きい。よって、第２はんだ接合用金属膜２２の全面上においてはんだ３２中のボイド発生が抑制されているのが好ましく、そのために酸化防止膜２４が第２はんだ接合用金属膜２２の全面上に形成されるのが好ましい。
　このようにして、図８に示されるように、第２電極１２、第２はんだ接合用金属膜２２、および酸化防止膜２４が半導体基板１０の第３の主面１０Ｃ上に積層して形成される。なお、第２電極１２、第２はんだ接合用金属膜２２、および酸化防止膜２４は、同一工程において連続して形成されてもよい。
　次に、図９に示されるように、犠牲膜２３が除去される（工程（Ｓ１０））。犠牲膜２３を除去する方法は、任意の方法を採用し得るが、たとえばウエットエッチング法である。犠牲膜２３を構成する材料がＴｉである場合には、本工程（Ｓ１０）はたとえば半導体基板１０の第１の主面１０Ａをフッ酸に浸漬させることにより実施される。また、犠牲膜２３を構成する材料がＡｌである場合には、本工程（Ｓ１０）はたとえば半導体基板１０の第１の主面１０Ａをリン酸に浸漬させることにより実施される。いずれの方法によっても、第１はんだ接合用金属膜２１と比べてウエットエッチングにより犠牲膜２３を選択的に除去することができる。
　次に、図１０に示されるように、半導体基板１０がダイシングされる（工程（Ｓ１１））。これにより、半導体基板１０から半導体素子１が切り出される。半導体基板１０をダイシングする方法は、任意の方法を採用し得るが、たとえばブレードダイシング法である。
　次に、半導体素子１の第１はんだ接合用金属膜２１と第１外部電極４１とがはんだ接合される（工程（Ｓ１２））。たとえば、第１はんだ接合用金属膜２１と第１外部電極４１との間に固相のはんだを配置し熱処理を加えて冷却することにより、第１はんだ接合用金属膜２１と第１外部電極４１とがはんだ３１を介して接合される。同様に、第２はんだ接合用金属膜２２と第２外部電極４２，５２の上部電極４２との間に固相のはんだを配置し熱処理を加えて冷却することにより、第２はんだ接合用金属膜２２と第２外部電極４２，５２とがはんだ３２を介して接合される。
　このとき、犠牲膜２３が除去された先の工程（Ｓ１１）から熱処理が施されること無く本工程（Ｓ１２）が実施されるため、本工程（Ｓ１２）において第１はんだ接合用金属膜２１上には熱処理に伴う酸化膜が形成されていない。しかし、第１はんだ接合用金属膜２１上には自然酸化膜が形成され得るため、本工程（Ｓ１２）の前処理として、還元性雰囲気下において半導体基板１０が所定の温度に加熱される熱処理が施されてもよい。このようにすれば、第１はんだ接合用金属膜２１および固相のはんだ表面に形成されている酸化膜を同時に除去することができ、第１はんだ接合用金属膜２１のはんだ濡れ性を回復することができる。なお、第２はんだ接合用金属膜２２上には酸化防止膜２４が形成されているため、酸化膜が形成されていない。また、酸化防止膜２４の膜厚が０．１μｍ程度である場合には、酸化防止膜２４は第２はんだ接合用金属膜２２と第２外部電極４２，５２とのはんだ接合時にはんだ３２内に拡散することによって消滅する。
　次に、半導体素子１が封止体６０により封止される（工程（Ｓ１３））。封止体６０を形成する工程は、たとえばトランスファモールド法である。このようにして、図１に示されるような半導体装置１００が製造される。
　次に、本実施の形態に係る半導体装置の製造方法の作用効果について説明する。
　本実施の形態に係る半導体装置の製造方法は、第１の主面１０Ａと、第１の主面１０Ａの反対側に位置する第２の主面１０Ｂとを有する半導体基板１０を準備する工程（Ｓ０１）と、第１の主面１０Ａ上に第１電極１１を形成する工程（Ｓ０２）と、第１電極１１上に第１はんだ接合用金属膜２１（はんだ接合用金属膜）を形成する工程（Ｓ０３）と、第１はんだ接合用金属膜２１上に犠牲膜２３を形成する工程（Ｓ０４）と、犠牲膜２３を形成した後に第２の主面１０Ｂを研削する工程（Ｓ０６）と、研削する工程（Ｓ０６）の後に熱処理を行う工程（第３の主面１０Ｃ側に素子構造を形成する工程（Ｓ０７））と、熱処理を行う工程（Ｓ０７）の後に犠牲膜２３を除去する工程（Ｓ１０）と、第１はんだ接合用金属膜２１と第１外部電極４１とをはんだ接合する工程（Ｓ１２）とを備える。
　このようにすれば、熱処理を行う工程（Ｓ０７）は第１はんだ接合用金属膜２１に犠牲膜２３を形成する工程（Ｓ０４）の後に実施され、当該工程（Ｓ０７）において第１はんだ接合用金属膜２１上には犠牲膜２３が形成されている。犠牲膜２３を除去する工程（Ｓ１０）は熱処理を行う工程（Ｓ０７）の後に実施され、さらにその後第１はんだ接合用金属膜２１が第１外部電極４１とをはんだ接合する工程（Ｓ１２）が実施される。そのため、はんだ接合する工程（Ｓ１２）において、第１はんだ接合用金属膜２１上には熱処理による熱酸化膜は形成されておらず、自然酸化膜のみが形成されている。
　そのため、接合する工程（Ｓ１２）におけるはんだ接合する前の前処理として、第１はんだ接合用金属膜２１上に貴金属からなる酸化防止膜を形成することなく、自然酸化膜を除去するための簡単な前処理のみを行うことによって、第１はんだ接合用金属膜２１と第１外部電極４１とはボイドが発生していないはんだ３１を介して良好にはんだ接合され得る。
　また、犠牲膜２３は半導体装置１００上から最終的に除去されるものであり犠牲膜２３自体は酸化されやすい材料で構成されていてもよい。つまり、第１はんだ接合用金属膜２１上には、半導体装置１００上から除去されずに残される酸化防止膜２４のように重金属で構成された膜を形成する必要がなく、酸化防止膜２４よりも低コスト材料からなる犠牲膜２３により第１はんだ接合用金属膜２１の熱酸化を抑制することができる。
　また、本実施の形態に係る半導体装置の製造方法では、研削する工程（Ｓ０６）の後に第１の主面１０Ａ上に酸化防止膜などを形成する工程が実施されないため、半導体基板１０に割れが生じることが抑制されている。
　つまり、本実施の形態に係る半導体装置の製造方法により製造される半導体装置１００は、製造コストが抑制されているとともに、半導体基板の割れが抑制されており、かつ、第１はんだ接合用金属膜２１と第１外部電極４１とがはんだ３１を介して熱的および電気的に良好に接続されている。
　また、第１はんだ接合用金属膜２１および犠牲膜２３を形成する工程（Ｓ０３）は、研削する工程（Ｓ０７）の前に実施されるため、該工程（Ｓ０３）は半導体基板１０の膜厚が部分的に減じられる前の一様な膜厚を有する半導体基板１０に対して実施される。そのため、当該工程（Ｓ０３）において、半導体基板１０に反りなどが生じることが抑制されているため、たとえば写真製版を利用したリフトオフ法などにより第１はんだ接合用金属膜２１および犠牲膜２３を容易に形成することができる。また、第１はんだ接合用金属膜２１および犠牲膜２３をスパッタリング法により形成する場合に、半導体基板１０の膜厚が部分的に減じられていると半導体基板１０の温度が部分的に急上昇して温度ムラが生じて半導体基板１０の割れなどが生じる。しかし、本実施の形態に係る半導体装置の製造方法では、部分的に研削される前の膜厚が一様な半導体基板１０に第１はんだ接合用金属膜２１および犠牲膜２３を形成するため、スパッタリング法を用いても半導体基板１０に割れなどが生じることを抑制することができる。また、当該工程（Ｓ０３）において、各処理装置内での半導体基板１０の搬送または半導体基板１０の固定などの物理的接触によっても、半導体基板１０に割れなどが生じることを抑制することができ、半導体基板１０を容易に取扱うことができる。
　犠牲膜２３を構成する材料は、第１はんだ接合用金属膜２１と比べてエッチングにより選択的に除去可能な材料であるのが好ましい。
　このようにすれば、犠牲膜２３を除去する工程（Ｓ１０）において、犠牲膜２３を容易に除去することができる。さらに、当該工程（Ｓ１０）において第１はんだ接合用金属膜２１の膜減りが抑制されているため、第１はんだ接合用金属膜２１の機械的強度を第１外部電極４１とのはんだ接合前後で維持することができる。その結果、第１はんだ接合用金属膜２１と第１外部電極４１との接合界面の信頼性を確保することができる。
　第１はんだ接合用金属膜２１を構成する材料はＮｉを含むのが好ましい。このようにすれば、第１はんだ接合用金属膜２１中のＮｉがはんだ３１の主な構成材料であるＳｎと金属間化合物を容易に形成することができるため、第１はんだ接合用金属膜２１と第１外部電極４１とは良好な接合状態を有している。また、このようにすれば、第１はんだ接合用金属膜２１と第１外部電極４１とを周知の方法により容易にはんだ接合可能である。
　また、犠牲膜２３を構成する材料はＴｉおよびＡｌの少なくともいずれか一方を含むのが好ましい。このようにすれば、後述する犠牲膜２３を除去する工程（Ｓ１０）において、第１はんだ接合用金属膜２１のエッチングを抑制しながら犠牲膜２３を容易に除去することができる。また、このようにすれば、第１はんだ接合用金属膜２１と犠牲膜２３とを同一工程において連続して容易に形成することができる。これにより、製造コストが低減されており、かつ、はんだ接合用金属膜の酸化が防止されることによりはんだ接合用金属膜と外部電極とが良好にはんだ接合されている、半導体装置１００を製造することができる。
　本実施の形態に係る半導体装置の製造方法は、半導体基板１０の第１の主面１０Ａ上に保護膜１５を形成する工程（Ｓ０５）を備えるのが好ましい。
　このようにすれば、第１はんだ接合用金属膜２１と第１外部電極４１とをはんだ接合する工程（Ｓ１２）において、いわゆるはんだ飛び（はんだボールの飛散）が生じた場合にも、飛散したはんだが半導体装置１００の電気的特性不良を引き起こすことを防止することができる。
　本実施の形態に係る半導体装置の製造方法において、犠牲膜２３を除去する工程（Ｓ１０）は、保護膜１５を形成する工程（Ｓ０５）の後に実施されるのが好ましい。
　このようにすれば、このようにすれば、保護膜１５を形成する工程（Ｓ０５）において保護膜１５の残差が生じた場合にも、後の犠牲膜２３を除去する工程（Ｓ１０）におけるエッチング処理により、犠牲膜２３とともに当該残差を除去することができる。
　本実施の形態に係る半導体装置の製造方法において、研削する工程（Ｓ０６）は、保護膜１５を形成する工程（Ｓ０５）の後に実施されるのが好ましい。
　このようにすれば、保護膜１５を形成する工程（Ｓ０５）および当該工程（Ｓ０５）前に実施される各工程（Ｓ０１～Ｓ０４）は、半導体基板１０の膜厚が部分的に減じられる前の一様な膜厚を有する半導体基板１０に対して実施される。そのため、当該工程（Ｓ０５）において、半導体基板１０に反りなどが生じることが抑制されているため、たとえば写真製版を利用して保護膜１５を容易に形成することができる。また、保護膜１５を形成する工程（Ｓ０５）において、半導体基板１０に割れなどが生じることを抑制することができ、また、半導体基板１０を容易に取扱うことができる。
　保護膜１５を構成する材料はポリイミドを含むのが好ましい。このようにすれば、保護膜１５を形成する工程（Ｓ０５）において保護膜１５の残差が生じた場合にも、後の犠牲膜２３を除去する工程（Ｓ１０）におけるフッ酸またはリン酸を用いたエッチング処理により、犠牲膜２３とともに当該残差を容易に除去することができる。
　第１電極１１を構成する材料はＡｌを含み、第１電極１１中のＡｌの含有率は９５質量％以上であるのが好ましい。このようにすれば、第１電極１１は周知の方法で容易に形成され得る。また、金属ワイヤ３３がＡｌワイヤとして構成されている場合には、金属ワイヤ３３と制御用電極１３との優れた接合信頼性を実現するため、制御用電極１３を構成する材料はＡｌを含み、制御用電極１３中のＡｌの含有率が９５質量％以上であるのが好ましい。このような場合にも、第１電極１１を上記のような構成とすれば、第１電極１１を形成する工程において第１電極１１と制御用電極１３とは第１の主面１０Ａ上に同時に形成されることができる。
　なお、本実施の形態に係る半導体装置１００の製造方法は、犠牲膜２３を形成した後に研削する工程（Ｓ０６）を実施し、該工程（Ｓ０６）の後に第３の主面１０Ｃ側に素子構造を形成する工程（Ｓ０７）を実施し、該工程（Ｓ０７）の後に犠牲膜２３を除去する工程（Ｓ１０）を実施し、かつ、該工程（Ｓ１０）の後にはんだ接合する工程（Ｓ１２）を実施する限りにおいて、他の工程間の前後関係については上記順に限られるものでは無い。たとえば、第１はんだ接合用金属膜２１を形成した後に保護膜１５を形成し、その後犠牲膜２３を形成してもよい。この場合、犠牲膜２３は、たとえば第１はんだ接合用金属膜２１および保護膜１５において第１はんだ接合用金属膜２１を表出している開口部に面している一部分上に形成されてもよい。このようにしても、本実施の形態に係る半導体装置の製造方法と同様の作用効果を奏することができる。
　今回開示された実施の形態はすべての点で例示であって、制限的なものではないと考えられるべきである。本発明の範囲は上記した説明ではなく請求の範囲によって示され、請求の範囲と均等の意味、および範囲内でのすべての変更が含まれることが意図される。
　本発明は、半導体素子と外部電極とがはんだ接合されており、かつ研削されて膜厚が減じられた半導体基板を備える半導体装置の製造方法に特に有利に適用される。
　１　半導体素子、１０　半導体基板、１０Ａ　第１の主面、１０Ｂ　第２の主面、１０Ｃ　第３の主面、１１　第１電極、１２　第２電極、１３　制御用電極、１４　ガードリング、１５　保護膜、２１　第１はんだ接合用金属膜、２２　第２はんだ接合用金属膜、２３　犠牲膜、２４　酸化防止膜、３１，３２，３４　はんだ、３３　金属ワイヤ、４１　第１外部電極、４２　上部電極（第２外部電極）、５２　下部電極（第２外部電極）、４３　第３外部電極、４４　第４外部電極、６０　封止体、７０　金属マスク、７０ａ，８０ａ　開口部、８０　リフトオフ用マスク、１００　半導体装置。

Claims (11)

  1. 　第１の主面と、前記第１の主面の反対側に位置する第２の主面とを有する半導体基板を準備する工程と、
    　前記第１の主面上に第１電極を形成する工程と、
    　前記第１電極上にはんだ接合用金属膜を形成する工程と、
    　前記はんだ接合用金属膜上に犠牲膜を形成する工程と、
    　前記犠牲膜を形成した後に前記第２の主面を研削する工程と、
    　前記研削する工程の後に熱処理を行う工程と、
    　前記熱処理を行う工程の後に前記犠牲膜を除去する工程と、
    　前記はんだ接合用金属膜と外部電極とをはんだ接合する工程とを備える、半導体装置の製造方法。
  2. 　前記犠牲膜を構成する材料は、前記はんだ接合用金属膜と比べてエッチングにより選択的に除去可能な材料である、請求項１に記載の半導体装置の製造方法。
  3. 　前記犠牲膜を構成する材料は、原子番号２２以下であり、かつアルカリ金属、アルカリ土類金属を含まない元素を含む、請求項２に記載の半導体装置の製造方法。
  4. 　前記犠牲膜を構成する材料はチタンおよびアルミニウムの少なくともいずれか一方を含む、請求項３に記載の半導体装置の製造方法。
  5. 　前記はんだ接合用金属膜を構成する材料は、原子番号２３以上の金属元素を含む、請求項請求項１～請求項４のいずれか１項に記載の半導体装置の製造方法。
  6. 　前記はんだ接合用金属膜を構成する材料はニッケルを含む、請求項５に記載の半導体装置の製造方法。
  7. 　前記半導体基板の前記第１の主面上に保護膜を形成する工程を備える、請求項１～請求項６のいずれか１項に記載の半導体装置の製造方法。
  8. 　前記犠牲膜を除去する工程は、前記保護膜を形成する工程の後に実施される、請求項７に記載の半導体装置の製造方法。
  9. 　前記研削する工程は、前記保護膜を形成する工程の後に実施される、請求項７または請求項８に記載の半導体装置の製造方法。
  10. 　前記保護膜を構成する材料はポリイミドを含む、請求項７～請求項９のいずれか１項に記載の半導体装置の製造方法。
  11. 　前記第１電極を構成する材料はアルミニウムを含み、
    　前記第１電極中のアルミニウムの含有率は９５質量％以上である、請求項１～請求項１０のいずれか１項に記載の半導体装置の製造方法。
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