WO2016176946A1 - 一种氧化物薄膜晶体管、阵列基板和显示装置 - Google Patents

一种氧化物薄膜晶体管、阵列基板和显示装置 Download PDF

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WO2016176946A1
WO2016176946A1 PCT/CN2015/089633 CN2015089633W WO2016176946A1 WO 2016176946 A1 WO2016176946 A1 WO 2016176946A1 CN 2015089633 W CN2015089633 W CN 2015089633W WO 2016176946 A1 WO2016176946 A1 WO 2016176946A1
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oxide layer
oxide
film transistor
channel
thin film
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French (fr)
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王美丽
孙宏达
刘凤娟
辛龙宝
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京东方科技集团股份有限公司
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Priority to EP15891197.4A priority Critical patent/EP3293771A4/en
Priority to US15/037,610 priority patent/US10141449B2/en
Publication of WO2016176946A1 publication Critical patent/WO2016176946A1/zh

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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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    • H01L29/22—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIBVI compounds
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • Embodiments of the present invention relate to an oxide thin film transistor, an array substrate, and a display device.
  • the mobility of low-temperature polysilicon can be as high as 100 cm 2 /Vs, but its preparation cost is high, and uniformity needs to be further improved in producing a large-sized back sheet.
  • oxide channel materials include indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO) and other materials, and the mobility is about 10 to 30 cm 2 /Vs, which needs further application in practical applications. improve.
  • the number of carriers in the channel is generally increased by doping the oxide channel layer with metal ions, thereby achieving the purpose of improving the mobility of the TFT.
  • the doping ions are mostly ions with large orbital radius and weak metal ion-oxygen bond energy, such as In 3+ and Sn 4+ plasmas.
  • weak metal ion-oxygen bond energy such as In 3+ and Sn 4+ plasmas.
  • the bonding energy between the doping ions and oxygen is weak, oxygen vacancies and oxygen dangling bonds are easily formed, which ultimately affects the stability of the oxide TFT.
  • the present invention provides an oxide thin film transistor, an array substrate, and a display device to solve the technical problems of poor stability, low mobility, and the like of the oxide thin film transistor in the prior art.
  • the present invention provides an oxide thin film transistor: an oxide channel layer of the oxide thin film transistor includes a front channel oxide layer and a back channel oxide layer, and a conduction band bottom of the back channel oxide layer is high
  • the conduction band of the front channel oxide layer has a forbidden band width greater than a forbidden band width of the front channel oxide layer.
  • the material of the oxide channel layer is an oxide or an oxynitride.
  • the material of the back channel oxide layer is the same as the material of the front channel oxide layer, the material of the back channel oxide layer has ion doping, and the material of the front channel oxide layer does not have Ion doping or having ion doping different from the material of the back channel oxide layer.
  • the material of the back channel oxide layer is different from the material of the front channel oxide layer.
  • the material of the back channel oxide layer and the material of the front channel oxide layer have ion doping.
  • the ion doping is metal ion doping.
  • the doped metal ions of the back channel oxide layer have a smaller work function than the material of the front channel oxide layer.
  • the ions are any one of calcium, magnesium, sodium, potassium, lithium, indium, tin, antimony, bismuth, and antimony.
  • the material of the back channel oxide layer is different from the material of the front channel oxide layer, and the material of the back channel oxide layer and the material of the front channel oxide layer do not have ion doping.
  • At least one of a material of the back channel oxide layer and a material of the front channel oxide layer is zinc oxide, indium gallium zinc oxide, indium tin zinc oxide or zirconium oxide.
  • the invention provides an array substrate comprising the oxide thin film transistor of any of the above.
  • the present invention also provides a display device comprising the array substrate as described above.
  • the oxide thin film transistor, the array substrate, and the display device provided by the present invention a large amount of electrons can be accumulated by a potential energy difference formed between the oxide channel layers of the multilayer structure, thereby enhancing the oxide channel layer.
  • the carrier concentration is such that the mobility of the TFT is improved without deteriorating the stability of the TFT.
  • FIG. 1 is a schematic structural view of an oxide thin film transistor according to an embodiment of the present invention.
  • FIG. 2 is a schematic view showing an interface potential energy well of an oxide channel layer of an oxide thin film transistor of Embodiment 1 of the present invention
  • FIG. 3 is a schematic view showing electron transport of an oxide channel layer of an oxide thin film transistor of Embodiment 1 of the present invention
  • FIG. 4 is a schematic view showing an interface potential energy well of an oxide channel layer of an oxide thin film transistor of Embodiment 2 of the present invention.
  • Fig. 5 is a view showing electron transport of an oxide channel layer of an oxide thin film transistor of Example 2 of the present invention.
  • an embodiment of the present invention first provides an oxide thin film transistor, as shown in FIG. 1: an oxide channel layer of an oxide thin film transistor includes a front channel oxide layer 1 and a back channel oxide layer 2, and back channel oxidation
  • the conduction band bottom of the object layer 2 is higher than the conduction band bottom of the front channel oxide layer 1
  • the forbidden band width of the back channel oxide layer 2 is larger than the forbidden band width of the front channel oxide layer 1.
  • 3 is a substrate
  • 4 is a gate
  • 5 is a gate oxide layer.
  • the work function also known as the work function and the work function, is the minimum amount of energy required to move an electron from the interior of the solid to the surface of the object.
  • Valence band or valence band usually the highest energy band in a semiconductor or insulator that can be filled by electrons at absolute zero.
  • the conduction band is the energy space formed by free electrons, that is, the energy range of freely moving electrons in the solid structure; the band gap refers to a band width (unit is electron volts (ev) ), the energy of electrons in a solid cannot be continuously valued, but some discontinuous energy bands.
  • a bound electron must acquire enough energy to transition to a conduction band. The minimum value of this energy is the forbidden band width.
  • the band bending is due to the fact that after the two different materials are in contact, the potential energy of the electrons in different regions is different, so that the band bending is formed, and the band bending is low, that is, the place where the electron filling amount is more, that is, the potential energy trap. Due to the potential difference between the conduction band levels of the two channel materials, At the interface between the back channel oxide and the front channel oxide, the electrons of the back channel oxide are transported to the front channel, and a potential well is formed at the interface due to band bending and a large amount of electrons are accumulated, thereby lifting the front trench.
  • the carrier concentration of the channel achieves the purpose of increasing the mobility of the TFT.
  • the material of the oxide channel layer may be an oxide or an oxynitride.
  • the material of the back channel oxide layer 2 may be the same as the material of the front channel oxide layer 1, in which case the material of the back channel oxide layer 2 has ion doping, and the front channel oxide layer 1
  • the material may not have ion doping or have ion doping different from the material of the back channel oxide layer 2.
  • the material of the back channel oxide layer 2 may be different from the material of the front channel oxide layer 1, and the material of the back channel oxide layer 2 and the material of the front channel oxide layer 1 may or may not be With ion doping.
  • the ion doping may be metal ion doping.
  • the doped metal ions of the back channel oxide layer 2 may have a smaller work function than the material of the front channel oxide layer 1.
  • the dopant ion may be a metal ion having a lower work function such as calcium, magnesium, sodium, potassium, lithium, indium, tin, antimony, bismuth, or antimony, or other alloy or other material having a lower work function.
  • the ion is not limited in the present invention. The concentration of ion doping is determined according to actual needs.
  • At least one of the material of the back channel oxide layer 2 and the material of the front channel oxide layer 1 may be zinc oxide, indium gallium zinc oxide, indium tin zinc oxide or zirconium oxide.
  • the oxide thin film transistor may be a bottom gate structure, a top gate structure, or a coplanar structure.
  • the oxide thin film transistor may be an etch barrier type (ESL) or a back channel etch type (BCE).
  • ESL etch barrier type
  • BCE back channel etch type
  • Embodiment 1 of the present invention provides an oxide thin film transistor which is a ZnO system TFT having a bottom gate structure.
  • the back channel oxide layer 2 is an ion doped ZnO system with a large band gap
  • the front channel oxide layer 1 is an ion doped or non-ion doped ZnO system with a forbidden bandwidth. Small.
  • a front channel oxide layer 1 is deposited on the gate insulating layer 5, which is a ZnO system material, and then a back channel oxide layer 2 formed by a low work function ion doped ZnO system material is deposited, labeled as ZnO. :M, wherein M represents a doped metal ion, which may be a metal ion such as Ca 2+ or Mg 2+ having a low work function.
  • a metal Ca 2+ is exemplified as ZnO:Ca.
  • the ZnO system material in the first embodiment may be ZnO or an ion doped zinc oxide system material such as IGZO, ITZO or the like.
  • the forbidden band width (Eg) of calcium oxide CaO is 7.1 eV
  • the forbidden band width of the ZnO system is ⁇ 3 eV
  • the conduction band energy level of ZnO:Ca of the back channel oxide layer 2 is higher than that of the front channel oxide layer 1, and the electrons flow from the ZnO:Ca conduction band of the back channel oxide layer 2 to the front channel oxide layer.
  • the ZnO conduction band of 1 increases the front channel carrier concentration.
  • the back channel oxide layer 2 is ZnO:M, and the doped metal ions thereof are required to satisfy a work function having a smaller ZnO system than the front channel oxide layer 1, that is, a conduction band doped with a metal ion oxide.
  • the bottom is higher than the conduction band bottom of ZnO system.
  • the conduction band bottom of ZnO:M is higher than the conduction band bottom of ZnO system, which satisfies the bending of ZnO:M/ZnO interface band and the formation of potential energy well.
  • the ZnO system of the front channel oxide layer 1 may be ion doped or non-ion doped, which needs to satisfy the forbidden band width smaller than that of the back channel oxide layer 2, and the conduction band bottom ratio is back channel oxidation.
  • the material of the layer 2 has a low conduction band bottom.
  • the material of the back channel oxide layer 2 and the front channel oxide layer 1 belong to the same system.
  • Embodiment 2 of the present invention provides an oxide thin film transistor in which the back channel oxide layer 2 is different in material from the front channel oxide layer 1.
  • a front channel oxide layer 1 is deposited on the gate insulating layer 5, and a ZnO system material having a small band gap and a low conduction band level is deposited on the layer, and the forbidden band width of the ZnO system is ⁇ 3 eV; then ZrO 3 is deposited thereon.
  • System material, ZrO 3 has a forbidden band width of -5.5eV. Since the conduction band difference between ZnO and ZrO 3 is different from the forbidden band width, electrons are transported from ZrO 3 to ZnO and a potential energy well is formed at the ZrO 3 /ZnO interface. See Figure 4, the highest concentration of electrons accumulated in the potential well The interface potential energy well with the highest electron concentration becomes the main channel of electron transport, as shown in Fig. 5, which finally improves the mobility of the TFT device.
  • both ZnO and ZrO 3 may include ion doping or non-ion doping.
  • Embodiment 3 of the present invention provides an array substrate including the oxide thin film transistor according to at least one of the above-described first and second embodiments of the present invention.
  • Embodiment 4 of the present invention provides a display device including the array substrate according to Embodiment 3 of the present invention.
  • the display device may be any device or device having a display function such as a display panel, a display, a television, a mobile phone, a navigator, an e-book or a tablet.
  • the oxide thin film transistor, the array substrate, and the display device provided by the embodiments of the present invention, a large amount of electrons can be accumulated by a potential energy difference formed between the oxide channel layers of the multilayer structure, thereby enhancing the oxide channel.
  • the carrier concentration of the layer is achieved to improve the mobility of the TFT without destroying the stability of the TFT.

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Abstract

提供一种氧化物薄膜晶体管、阵列基板和显示装置，所述氧化物薄膜晶体管的氧化物沟道层包括前沟道氧化物层（1）和背沟道氧化物层（2），所述背沟道氧化物层的导带底高于所述前沟道氧化物层的导带底，所述背沟道氧化物层的禁带宽度大于所述前沟道氧化物层的禁带宽度。在提供的氧化物薄膜晶体管、阵列基板和显示装置中，能够通过在多层结构的氧化物沟道层（1、2）之间形成的势能差来积累大量电子，从而提升氧化物沟道层载流子浓度，达到在不破坏TFT稳定性的基础上提高TFT迁移率的目的。

Description

一种氧化物薄膜晶体管、阵列基板和显示装置 技术领域
本发明的实施例涉及一种氧化物薄膜晶体管、阵列基板和显示装置。
背景技术
随着高图像分辨率、高刷新率、3D等技术发展的需求，高迁移率TFT材料的开发至关重要。低温多晶硅的迁移率可高达100cm2/Vs，但其制备成本高，且在生产大尺寸背板时均匀性还需进一步改善。目前研究较多的氧化物沟道材料包括铟镓锌氧化物(IGZO)、铟锡锌氧化物(ITZO)等材料，其迁移率在10～30cm2/Vs左右，在实际应用时还需进一步提高。
在氧化物TFT行业，普遍通过对氧化物沟道层进行金属离子的掺杂来增加沟道中载流子数量，达到提高TFT迁移率的目的。其中掺杂离子多为轨道半径大、金属离子-氧键能弱的离子，例如In3+，Sn4+等离子。但由于掺杂离子与氧的键能较弱，易形成氧空位及氧悬挂键，最终影响氧化物TFT的稳定性。
发明内容
本发明提供一种氧化物薄膜晶体管、阵列基板和显示装置，以解决现有技术中氧化物薄膜晶体管稳定性差、迁移率低等的技术问题。
本发明提供一种氧化物薄膜晶体管：所述氧化物薄膜晶体管的氧化物沟道层包括前沟道氧化物层和背沟道氧化物层，所述背沟道氧化物层的导带底高于所述前沟道氧化物层的导带底，所述背沟道氧化物层的禁带宽度大于所述前沟道氧化物层的禁带宽度。
进一步地，
所述氧化物沟道层的材料为氧化物或氮氧化物。
进一步地，
所述背沟道氧化物层的材料与所述前沟道氧化物层的材料相同，所述背沟道氧化物层的材料具有离子掺杂，所述前沟道氧化物层的材料不具有离子掺杂或具有与所述背沟道氧化物层的材料不同的离子掺杂。
进一步地，
所述背沟道氧化物层的材料与所述前沟道氧化物层的材料不同。可选地，所述背沟道氧化物层的材料和所述前沟道氧化物层的材料具有离子掺杂。
进一步地，
所述离子掺杂为金属离子掺杂。
进一步地，
所述背沟道氧化物层的掺杂金属离子具有比所述前沟道氧化物层的材料小的功函数。
进一步地，
所述离子为钙、镁、钠、钾、锂、铟、锡、鉿、铯、铷中的任一种离子。
进一步地，
所述背沟道氧化物层的材料与所述前沟道氧化物层的材料不同，所述背沟道氧化物层的材料和所述前沟道氧化物层的材料不具有离子掺杂。
进一步地，
所述背沟道氧化物层的材料和所述前沟道氧化物层的材料中的至少之一为氧化锌、铟镓锌氧化物、氧化铟锡锌或氧化锆。
另一方面，本发明还提供一种阵列基板，包括如上任一项所述的氧化物薄膜晶体管。
再一方面，本发明还提供一种显示装置，包括如上所述的阵列基板。
可见，在本发明提供的氧化物薄膜晶体管、阵列基板和显示装置中，能够通过在多层结构的氧化物沟道层之间形成的势能差来积累大量电子，从而提升氧化物沟道层中的载流子浓度，达到在不破坏TFT稳定性的基础上提高TFT迁移率的目的。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例的氧化物薄膜晶体管结构示意图；
图2是本发明实施例1的氧化物薄膜晶体管的氧化物沟道层的界面势能阱的示意图；
图3是本发明实施例1的氧化物薄膜晶体管的氧化物沟道层的电子传输的示意图；
图4是本发明实施例2的氧化物薄膜晶体管的氧化物沟道层的界面势能阱的示意图；
图5是本发明实施例2的氧化物薄膜晶体管的氧化物沟道层的电子传输的示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
在本发明的描述中，需要说明的是，术语“上”、“下”、“顶”、“底” 等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
此外，在本发明的描述中，除非另有说明，“多个”的含义是两个或两个以上。
本发明实施例首先提供一种氧化物薄膜晶体管，如图1所示：氧化物薄膜晶体管的氧化物沟道层包括前沟道氧化物层1和背沟道氧化物层2，背沟道氧化物层2的导带底高于前沟道氧化物层1的导带底，背沟道氧化物层2的禁带宽度大于前沟道氧化物层1的禁带宽度。另外，图1中，3为衬底、4为栅极、5为栅氧化物层。
本领域技术人员应该理解，晶体中电子所能具有的能量范围，在物理学中往往形象化地用一条条水平横线表示电子的各个能量值。能量愈大，线的位置愈高，一定能量范围内的许多能级(彼此相隔很近)形成一条带，称为能带。各种晶体能带数目及其宽度等都不相同。相邻两能带间的能量范围称为“能隙”或“禁带”。功函数(work function)又称功函、逸出功，是把一个电子从固体内部刚刚移到此物体表面所需的最少的能量。价带(valence band)或称价电带，通常是指半导体或绝缘体中，在绝对零度下能被电子占满的最高能带。导带(conduction band)是由自由电子形成的能量空间，即固体结构内自由运动的电子所具有的能量范围；禁带宽度(Band gap)是指一个能带宽度(单位是电子伏特(ev))，固体中电子的能量是不可以连续取值的，而是一些不连续的能带，要导电就要有自由电子存在，由前可知自由电子存在的能带称为导带(能导电)，被束缚的电子要成为自由电子，就必须获得足够能量从而跃迁到导带，这个能量的最小值就是禁带宽度。能带弯曲是由于两个不同的材料接触之后，由于电子在不同区域内的势能不同，从而形成能带弯曲，能带弯曲偏低的地方就是电子填充数量更多的地方，即势能阱。由于在两种沟道材料的导带能级之间存在势能差，在 背沟道氧化物与前沟道氧化物之间的界面处，背沟道氧化物的电子向前沟道传输，并且在界面处由于能带弯曲形成势能阱并积累大量电子，从而提升前沟道载流子浓度，达到提高TFT迁移率的目的。
其中，氧化物沟道层的材料可以为氧化物或氮氧化物。
可选地，背沟道氧化物层2的材料与前沟道氧化物层1的材料可以相同，此时背沟道氧化物层2的材料具有离子掺杂，而前沟道氧化物层1的材料可以不具有离子掺杂或具有与背沟道氧化物层2的材料不同的离子掺杂。
可选地，背沟道氧化物层2的材料与前沟道氧化物层1的材料可以不同，背沟道氧化物层2的材料和前沟道氧化物层1的材料均可以具有或不具有离子掺杂。
其中，离子掺杂可以为金属离子掺杂。
可选地，背沟道氧化物层2的掺杂金属离子可以具有比前沟道氧化物层1材料小的功函数。
其中，可选地，掺杂离子可以为钙、镁、钠、钾、锂、铟、锡、鉿、铯、铷等功函数较低的金属离子，或其他功函数较低的合金或其他材料的离子，本发明对此不做限定。离子掺杂的浓度根据实际需要而定。
可选地，背沟道氧化物层2的材料和前沟道氧化物层1的材料中的至少之一可以为氧化锌、铟镓锌氧化物、氧化铟锡锌或氧化锆。
可选地，氧化物薄膜晶体管可以为底栅结构、顶栅结构或共面结构。
可选地，氧化物薄膜晶体管可以为刻蚀阻挡型(ESL)或背沟道刻蚀型(BCE)。
实施例1：
本发明实施例1提供一种氧化物薄膜晶体管，为底栅结构的ZnO体系TFT。其中背沟道氧化物层2为离子掺杂的ZnO体系，禁带宽度大，前沟道氧化物层1为离子掺杂或非离子掺杂的ZnO体系，禁带宽 度小。
其中，在栅极绝缘层5上沉积前沟道氧化物层1，其为ZnO体系材料，然后沉积由低功函数离子掺杂的ZnO体系材料形成的背沟道氧化物层2，标记为ZnO：M，其中M代表掺杂金属离子，可以为低功函数的Ca2+或者Mg2+等金属离子。在本实施例1中，举例为金属Ca2+，记为ZnO：Ca。
本实施例1中的ZnO体系材料可以为ZnO或离子掺杂的氧化锌体系材料，如：IGZO，ITZO等材料。其中，由于氧化钙CaO的禁带宽度(Eg)为7.1eV，ZnO体系的禁带宽度～3eV，所以Eg(ZnO)<Eg(ZnO：Ca)<Eg(CaO)。背沟道氧化物层2的ZnO：Ca的导带能级高于前沟道氧化物层1的ZnO，电子由背沟道氧化物层2的ZnO：Ca导带流向前沟道氧化物层1的ZnO导带，由此增加了前沟道载流子浓度。此外，参见图2，由于能带弯曲在ZnO：Ca/ZnO界面会形成势能阱，在势能阱中聚集的电子的浓度最高，而电子浓度最高的界面势能阱成为电子传输的主要沟道，参见图3，最终提高了TFT器件的迁移率。注意在图2和图4中，Ec表示导带底(进入导带的电子具有的最低能量)，Ev表示价带顶(价带中电子具有的最高能量)，Ev到Ec的距离即为禁带宽度。
其中，背沟道氧化物层2为ZnO：M，其掺杂的金属离子需满足具有比前沟道氧化物层1的ZnO体系小的功函数，即，掺杂金属离子氧化物的导带底高于ZnO体系的导带底，离子掺杂后ZnO：M的导带底高于ZnO体系的导带底，从而满足ZnO：M/ZnO界面能带弯曲及势能阱形成条件。
并且，前沟道氧化物层1的ZnO体系可为离子掺杂或非离子掺杂的，其需满足禁带宽度比背沟道氧化物层2的材料小，导带底比背沟道氧化物层2的材料的导带底低的特点。
在本实施例1中，背沟道氧化物层2与前沟道氧化物层1的材料属于相同体系。
实施例2：
本发明实施例2提供一种氧化物薄膜晶体管，背沟道氧化物层2与前沟道氧化物层1的材料不同。
其中，栅极绝缘层5上沉积前沟道氧化物层1，此层上沉积禁带宽度小，导带能级低的ZnO体系材料，ZnO体系的禁带宽度～3eV；然后沉积有ZrO3体系材料，ZrO3的禁带宽度～5.5eV。由于ZnO与ZrO3之间的导带能级差与禁带宽度差，电子由ZrO3向ZnO传输，并在ZrO3/ZnO界面形成势能阱，参见图4，在势能阱中聚集的电子浓度最高，而电子浓度最高的界面势能阱成为电子传输的主要沟道，见图5，最终提高了TFT器件的迁移率。
其中，ZnO与ZrO3均可包括离子掺杂或非离子掺杂。
实施例3：
本发明实施例3提供一种阵列基板，包括根据本发明上述实施例1和2中的至少之一所述的氧化物薄膜晶体管。
实施例4：
本发明实施例4提供一种显示装置，包括如本发明实施例3所述的阵列基板。该显示装置可以为显示面板、显示器、电视机、手机、导航仪、电子书或平板电脑等任意具有显示功能的设备或器件。
可见，在本发明实施例提供的氧化物薄膜晶体管、阵列基板和显示装置中，能够通过在多层结构的氧化物沟道层之间形成的势能差来积累大量电子，从而提升氧化物沟道层载流子浓度，达到在不破坏TFT稳定性的基础上提高TFT迁移率的目的。
最后应说明的是：以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。
本申请要求于2015年5月7日递交的中国专利申请第201510229537.X号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (12)

  1. 一种氧化物薄膜晶体管，其特征在于：所述氧化物薄膜晶体管的氧化物沟道层包括前沟道氧化物层和背沟道氧化物层，所述背沟道氧化物层的导带底高于所述前沟道氧化物层的导带底，所述背沟道氧化物层的禁带宽度大于所述前沟道氧化物层的禁带宽度。
  2. 根据权利要求1所述的氧化物薄膜晶体管，其特征在于：
    所述氧化物沟道层的材料为氧化物或氮氧化物。
  3. 根据权利要求1所述的氧化物薄膜晶体管，其特征在于：
    所述背沟道氧化物层的材料与所述前沟道氧化物层的材料相同，所述背沟道氧化物层的材料具有离子掺杂，所述前沟道氧化物层的材料不具有离子掺杂或具有与所述背沟道氧化物层的材料不同的离子掺杂。
  4. 根据权利要求1所述的氧化物薄膜晶体管，其特征在于：
    所述背沟道氧化物层的材料与所述前沟道氧化物层的材料不同。
  5. 根据权利要求4所述的氧化物薄膜晶体管，其特征在于：
    所述背沟道氧化物层的材料和所述前沟道氧化物层的材料具有离子掺杂。
  6. 根据权利要求3到5中任一项所述的氧化物薄膜晶体管，其特征在于：
    所述离子掺杂为金属离子掺杂。
  7. 根据权利要求6所述的氧化物薄膜晶体管，其特征在于：
    所述背沟道氧化物层的掺杂金属离子具有比所述前沟道氧化物层的材料小的功函数。
  8. 根据权利要求3到5中任一项所述的氧化物薄膜晶体管，其特征在于：
    所述离子为钙、镁、钠、钾、锂、铟、锡、鉿、铯和铷中的任一种。
  9. 根据权利要求4所述的氧化物薄膜晶体管，其特征在于：
    所述背沟道氧化物层的材料和所述前沟道氧化物层的材料不具有离子掺杂。
  10. 根据权利要求1所述的氧化物薄膜晶体管，其特征在于：
    所述背沟道氧化物层的材料和所述前沟道氧化物层的材料中的至少之一为氧化锌、铟镓锌氧化物、氧化铟锡锌或氧化锆。
  11. 一种阵列基板，其特征在于，包括如上任一项权利要求所述的氧化物薄膜晶体管。
  12. 一种显示装置，其特征在于，包括如权利要求11所述的阵列基板。
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