CN105655354A - 薄膜晶体管、阵列基板及其制备方法以及显示装置 - Google Patents
薄膜晶体管、阵列基板及其制备方法以及显示装置 Download PDFInfo
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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Abstract
本发明公开了一种薄膜晶体管、阵列基板、显示装置及阵列基板的制备方法,以提高薄膜晶体管半导体层的抗酸性,并降低薄膜晶体管的制备成本。薄膜晶体管包括半导体层,所述半导体层包括掺入锡的氧化锆。在本发明的技术方案中,退火处理后的半导体层的抗酸性较强,可以在其表面通过湿法刻蚀形成源漏电极层,相比现有技术,无需设置刻蚀阻挡层,因此,薄膜晶体管的制备工艺得到了简化,生产成本较低;并且,氧化锆中掺入锡后,锡可以调控氧化锆的能带结构,使氧化锆的能级发生变化,进而容易形成载流子,增强了半导体层的导电性;此外,该薄膜晶体管的半导体层不包含铟,因此大大降低了制备成本。
Description
技术领域
本发明涉及显示技术领域,尤其涉及一种薄膜晶体管、阵列基板、显示装置及阵列基板的制备方法。
背景技术
近年来,在平板显示尤其是有机发光二极管(OrganicLight-EmittingDiode,简称OLED)领域,基于半导体设计的薄膜晶体管(ThinFilmTransistor,简称TFT)越来越受到业内人士的重视。
目前,应用于平板显示的薄膜晶体管的半导体层的材料主要为硅,包括非晶硅、多晶硅、微晶硅等。然而,非晶硅薄膜晶体管对光较为敏感、迁移率较低(<1cm2/Vs),且稳定性较差;多晶硅薄膜晶体管虽然迁移率较高,但是由于晶界的影响导致其电学均匀性较差,此外,多晶硅制备温度高、成本高以及难以大面积晶化的特性,限制了其在平板显示中的应用;微晶硅制备难度较大,晶粒控制技术难度较高,不容易实现大面积规模量产。
在传统硅工艺制备的半导体层存在众多缺陷的情况下,氧化物半导体层应运而生。氧化物半导体层具有迁移率较高、对可见光透明的优点,在平板显示的TFT领域,氧化物半导体层已经逐渐替代传统硅工艺制备的半导体层,并成为主流趋势。
现有技术中,氧化物半导体层的代表主要为氧化铟镓锌(IGZO)、氧化铟锌(IZO)等,IGZO或者IZO等材料对酸均较为敏感,无法在其表面采用湿法刻蚀的方法刻蚀源漏电极层,因此,现有技术通常需要在半导体层的表面增加一层刻蚀阻挡层,来保护半导体层不被刻蚀液损坏,这使得薄膜晶体管的制备工艺较为繁琐,制备成本较高,此外,地球上铟的含量有限,导致其价格昂贵,这无形之中又增加了薄膜晶体管的制备成本。
发明内容
本发明的目的是提供一种薄膜晶体管、阵列基板、显示装置及阵列基板的制备方法,以提高薄膜晶体管半导体层的抗酸性,并降低薄膜晶体管的制备成本。
本发明实施例提供一种薄膜晶体管,包括半导体层,所述半导体层包括掺入锡的氧化锆。
在本发明实施例中,薄膜晶体管的半导体层为掺入锡的氧化锆,退火处理后的半导体层的抗酸性较强,可以在其表面通过湿法刻蚀形成源漏电极层,相比现有技术,无需设置刻蚀阻挡层,因此,薄膜晶体管的制备工艺得到了简化,生产成本较低;并且,氧化锆中掺入锡后,锡可以调控氧化锆的能带结构,使得氧化锆的能级发生变化,进而容易形成载流子,增强了半导体层的导电性;此外,相比现有技术,本发明实施例提供的薄膜晶体管的半导体层不包含铟,因此大大降低了薄膜晶体管的制备成本。
具体的,所述氧化锆中掺入锡的量为1%~95%。
优选的,所述氧化锆中掺入锡的量为10%~90%。
更优的,所述氧化锆中掺入锡的量为50%。
具体的,所述半导体层的厚度为10nm~200nm。
本发明实施例提供了一种阵列基板,包括如上述任一技术方案所述的薄膜晶体管。该阵列基板的制备工艺较为简单,成本较低。
本发明实施例提供了一种显示装置,包括上述任一技术方案所述的阵列基板。该显示装置的制备工艺较为简单,成本较低。
本发明实施例提供了一种阵列基板的制备方法,包括:形成半导体层,所述半导体层包括掺入锡的氧化锆;对所述半导体层进行退火处理。采用该方法制备的阵列基板,其薄膜晶体管的半导体层抗酸性较高,薄膜晶体管的成本较低。
优选的,所述形成半导体层,具体包括:形成掺入锡的氧化锆覆盖层;采用浓度为5%的盐酸刻蚀所述掺入锡的氧化锆覆盖层,形成半导体层。
优选的,所述对所述半导体层进行退火处理,具体包括:将所述半导体层在200℃~500℃之间进行20min~120min的退火处理。
更优的,所述对所述半导体层进行退火处理,具体包括:将所述半导体层在350℃的条件下进行30min的退火处理。
优选的,所述氧化锆覆盖层中掺入锡的量为1%~95%,在此条件下,刻蚀所述掺入锡的氧化锆覆盖层的速率大于100nm/min,并且在对所述半导体层进行退火处理后,浓度为5%的盐酸对所述半导体层的破坏刻蚀速率小于50nm/min。
更优的,所述氧化锆覆盖层中掺入锡的量为10%~90%,在此条件下,刻蚀所述掺入锡的氧化锆覆盖层的速率大于200nm/min,并且在对所述半导体层进行退火处理后,浓度为5%的盐酸对所述半导体层的破坏刻蚀速率小于20nm/min。
附图说明
图1为本发明一实施例阵列基板的截面示意图;
图2为本发明另一实施例阵列基板的截面示意图;
图3为本发明一实施例阵列基板的制备方法流程图;
图4为本发明另一实施例阵列基板的制备方法流程图;
图5为本发明又一实施例阵列基板的制备方法流程图;
图6为本发明实施例半导体层载流子迁移率随含锡量的变化曲线图。
附图标记说明:
1-基板
2-栅极
3-栅极绝缘层
4-半导体层
51-源极
52-漏极
具体实施方式
为了提高薄膜晶体管半导体层的抗酸性,并降低薄膜晶体管的制备成本,本发明实施例提供了一种薄膜晶体管、阵列基板、显示装置及阵列基板的制备方法。
本发明实施例提供了一种薄膜晶体管,如图1所示,包括半导体层4,半导体层4包括掺入锡的氧化锆。
上述薄膜晶体管还包括栅极2、栅极绝缘层3、位于半导体层4之上且间隔设置的源极51和漏极52。在本发明实施例中,薄膜晶体管的半导体层为掺入锡的氧化锆,退火处理后的半导体层的抗酸性较强,可以在其表面通过湿法刻蚀形成源漏电极层,相比现有技术,无需设置刻蚀阻挡层,因此,薄膜晶体管的制备工艺得到了简化,生产成本较低;并且,氧化锆中掺入锡后,锡可以调控氧化锆的能带结构,使得氧化锆的能级发生变化,进而容易形成载流子,增强了半导体层的导电性;此外,相比现有技术,本发明实施例提供的薄膜晶体管的半导体层不包含铟,因此大大降低了薄膜晶体管的制备成本。
较优的,氧化锆中掺入锡的量为1%~95%。
更优的,氧化锆中掺入锡的量为10%~90%。
在本发明实施例中,掺入锡的氧化锆(以下简称掺锡氧化锆)通常采用物理气相沉积的方法制备。刚制备出的掺锡氧化锆为非晶态,当氧化锆中掺入锡的量为1%~95%时,掺锡氧化锆在5%浓度的盐酸下的刻蚀速率大于100nm/min,更优的,当氧化锆中掺入锡的量为10%~90%时,掺锡氧化锆在5%浓度的盐酸下的刻蚀速率大于200nm/min。基于掺锡氧化锆这样的特性,在薄膜晶体管的制备过程中,本领域技术人员可以采用浓度为5%的盐酸对掺锡氧化锆进行湿法刻蚀图形化处理,进而形成薄膜晶体管的半导体层。
此后,将半导体层在200℃~500℃之间进行20min~120min的退火处理,退火处理后的半导体层为晶态,此时,半导体层抗酸的破坏刻蚀性越来越强,当半导体层掺入锡的量为1%~95%时,5%浓度的盐酸对其的破坏刻蚀速率小于50nm/min,更优的,当半导体层掺入锡的量在10%~90%时,5%浓度的盐酸对其的破坏刻蚀速率小于20nm/min。基于半导体层退火处理后的抗酸特性,本领域技术人员可以在薄膜晶体管的半导体层表面制备金属电极层,然后在金属电极层表面采用浓度为5%的盐酸对金属电极层进行湿法刻蚀图形化处理,进而形成源极和漏极,同时不影响半导体层的结构。而现有技术中的半导体层由于对酸较为敏感,无法在其上表面采取湿法刻蚀图形化的方式形成源漏极,因此,现有技术通常需要在半导体层的表面增加一层刻蚀阻挡层,来保护半导体层不被刻蚀液损坏,因此,相比现有技术而言,本发明实施例大大简化了工艺步骤,并且降低了工艺成本。
更优的,氧化锆中掺入锡的量为50%。除此之外,氧化锆中掺入锡的量还可优选为10%、30%或者90%。
如图6所示,为半导体层载流子迁移率随半导体层含锡量的变化曲线图。本申请的发明人经过测试,发现掺入锡的量为10%的氧化锆,其载流子迁移率为1.1cm2V-1s-1,掺入锡的量为30%的氧化锆,其载流子迁移率为2.3cm2V-1s-1,掺入锡的量为50%的氧化锆,其载流子迁移率为4.5cm2V-1s-1,此时载流子的迁移率达到峰值,掺入锡的量为90%的氧化锆,其载流子迁移率为4.2cm2V-1s-1。由上述含锡量为10%、30%、50%或90%的氧化锆制备的半导体层中,载流子迁移率相对较大,有利于增强半导体层的导电性。
在上述各实施例中,栅极2通常为导电材料,例如可以为金属、金属合金、导电金属氧化物或者为两层以上的导电材料,如钼(Mo)/铝(Al)/钼(Mo)等,栅极的厚度通常为50nm~1000nm;栅极绝缘层3通常为电介质材料,例如可以为二氧化硅(SiO2)、氮化硅(SiNx)、氮氧化硅(Si-O-N)、氧化铝(Al2O3)、五氧化二钽(Ta2O5)、三氧化二钇(Y2O3)或者二氧化铪(HfO2)中的一层或多层,栅极绝缘层的厚度通常为0nm~1000nm;源极51和漏极52通常为导电材料,例如可以为金属、金属合金、导电金属氧化物或者为两层以上的导电材料,如钼(Mo)/铝(Al)/钼(Mo)等,源极和漏极的厚度通常均为10nm~100nm。
本发明实施例提供的薄膜晶体管的半导体层的具体厚度不限,优选为10nm~200nm。该半导体层的载流子浓度不小于1*1015cm-3,不大于1*1019cm-3,载流子浓度在此范围内的半导体层,其导电性能较高。
本发明实施例还提供了一种阵列基板,包括上述任一实施例所述的薄膜晶体管。该阵列基板制备工艺较为简单,成本较低。
该阵列基板可以为顶栅型薄膜晶体管或者底栅型薄膜晶体管,如图1所示,为底栅型薄膜晶体管,如图2所示,为顶栅型薄膜晶体管。请参考图1和图2所示,阵列基板还包括基板1,上述任一实施例所述的薄膜晶体管在基板1上呈阵列排布,基板1的具体材料不限,例如可以为玻璃、塑料或者表面被氧化的硅片等。
本发明实施例还提供了一种显示装置,包括上述技术方案所述的阵列基板。该显示装置的制备工艺较为简单,成本较低。
如图3所示,本发明实施例还提供了一种阵列基板的制备方法,包括:
步骤301:形成半导体层,半导体层包括掺入锡的氧化锆;
步骤302:对半导体层进行退火处理。
其中,步骤301具体包括:
形成掺入锡的氧化锆覆盖层;
采用浓度为5%的盐酸刻蚀掺入锡的氧化锆覆盖层,形成半导体层。
步骤302具体包括:
将半导体层在200℃~500℃之间进行20min~120min的退火处理。
优选的,步骤302具体可为:将半导体层在350℃的条件下进行30min的退火处理。
在本发明方法的一个优选实施例中,氧化锆覆盖层中掺入锡的量为1%~95%,在此条件下,浓度为5%的盐酸对掺入锡的氧化锆覆盖层的刻蚀速率大于100nm/min,并且在对半导体层进行退火处理后,浓度为5%的盐酸对半导体层的破坏刻蚀速率小于50nm/min。
在本发明方法的另一优选实施例中,氧化锆覆盖层中掺入锡的量为10%~90%,在此条件下,浓度为5%的盐酸对掺入锡的氧化锆覆盖层的刻蚀速率大于200nm/min,并且在对半导体层进行退火处理后,浓度为5%的盐酸对半导体层的破坏刻蚀速率小于20nm/min。
如图4所示,当薄膜晶体管为底栅型薄膜晶体管时,阵列基板的制备方法包括:
步骤101:在基板上形成栅极和栅线;
步骤102:在栅极之上形成栅极绝缘层;
步骤103:在栅极绝缘层之上形成半导体层,半导体层包括掺入锡的氧化锆;
步骤104:对半导体层进行退火处理;
步骤105:在半导体层之上形成数据线、相间隔的源极和漏极。
采用该方法制备的阵列基板,其薄膜晶体管的半导体层抗酸性较高,薄膜晶体管的成本较低。
如图5所示,当薄膜晶体管为顶栅型薄膜晶体管时,阵列基板的制备方法包括:
步骤201:在基板上形成数据线、相间隔的源极和漏极;
步骤202:在源极和漏极上形成半导体层,半导体层包括掺入锡的氧化锆;
步骤203:对半导体层进行退火处理;
步骤204:在半导体层上形成栅极绝缘层;
步骤205:在栅极绝缘层上形成栅极和栅线。
采用该方法制备的阵列基板,其薄膜晶体管的半导体层抗酸性较高,薄膜晶体管的成本较低。
在该方法中,未经退火处理的掺锡氧化锆抗酸性较差,基于掺锡氧化锆这样的特性,在薄膜晶体管的制备过程中,本领域技术人员可以湿法刻蚀图形化该掺锡氧化锆,进而形成薄膜晶体管的半导体层;此后,将半导体层在200℃~500℃之间进行20min~120min的退火处理。栅极绝缘层的制备通常采用金属阳极氧化的方式,金属阳极氧化的电解液通常为酸性溶液,基于半导体层退火处理后的抗酸特性,本领域技术人员可以在薄膜晶体管的半导体层表面制备栅极绝缘层,同时不影响半导体层的结构。而现有技术中的半导体层由于对酸较为敏感,无法在其上表面采取阳极氧化的方式形成栅极绝缘层,因此,现有技术通常需要在半导体层的表面增加一层电解阻挡层,来保护半导体层不被电解液损坏,因此,相比现有技术而言,本发明实施例大大简化了工艺步骤,并且降低了工艺成本。
上述阵列基板的制备方法中,对半导体层进行退火处理的温度具体不限,优选为200℃~500℃,更优的,退火处理的温度为350℃,对半导体层进行退火处理的时间具体也不限,优选为20min~120min,更优的,退火处理的时间为30min。
下面,仅举一具体实施例列举阵列基板的制备方法,但读者应知,其具体制备过程不局限于此:
第一步:在基板上采用溅射的方法制备一层金属薄膜,如Al-Nd薄膜,该金属薄膜的厚度通常为300nm,之后,采取光刻的方法进行图形化,进而形成栅极2;
第二步:在栅极2的上表面,对金属(如Al)进行阳极氧化,形成厚度为200nm的栅极绝缘层3;
第三步:在栅极绝缘层3的表面采用溅射的方法,形成掺锡氧化锆覆盖层,掺锡氧化锆覆盖层的厚度通常为10nm~200nm,然后,采用浓度为5%的盐酸对掺锡氧化锆覆盖层进行湿法刻蚀图形化处理,形成半导体层4;
第四步:将半导体层在350℃的条件下进行30min的退火处理;
第五步:在退火处理后的半导体层4表面制备金属电极层,采用浓度为5%的盐酸对金属电极层进行湿法刻蚀图形化处理,形成源极51和漏极52。
显然,本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样,倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内,则本发明也意图包含这些改动和变型在内。
Claims (13)
1.一种薄膜晶体管,其特征在于,包括半导体层,所述半导体层包括掺入锡的氧化锆。
2.如权利要求1所述的薄膜晶体管,其特征在于,所述氧化锆中掺入锡的量为1%~95%。
3.如权利要求2所述的薄膜晶体管,其特征在于,所述氧化锆中掺入锡的量为10%~90%。
4.如权利要求3所述的薄膜晶体管,其特征在于,所述氧化锆中掺入锡的量为50%。
5.如权利要求1所述的薄膜晶体管,其特征在于,所述半导体层的厚度为10nm~200nm。
6.一种阵列基板,其特征在于,包括如权利要求1~5任一项所述的薄膜晶体管。
7.一种显示装置,其特征在于,包括如权利要求6所述的阵列基板。
8.一种阵列基板的制备方法,其特征在于,包括:
形成半导体层,所述半导体层包括掺入锡的氧化锆;
对所述半导体层进行退火处理。
9.如权利要求8所述的制备方法,其特征在于,所述形成半导体层,具体包括:
形成掺入锡的氧化锆覆盖层;
采用浓度为5%的盐酸刻蚀所述掺入锡的氧化锆覆盖层,形成半导体层。
10.如权利要求9所述的制备方法,其特征在于,所述对所述半导体层进行退火处理,具体包括:
将所述半导体层在200℃~500℃之间进行20min~120min的退火处理。
11.如权利要求9或10所述的制备方法,其特征在于,所述对所述半导体层进行退火处理,具体包括:
将所述半导体层在350℃的条件下进行30min的退火处理。
12.如权利要求11所述的制备方法,其特征在于,所述氧化锆覆盖层中掺入锡的量为1%~95%,在此条件下,刻蚀所述掺入锡的氧化锆覆盖层的速率大于100nm/min,并且在对所述半导体层进行退火处理后,浓度为5%的盐酸对所述半导体层的破坏刻蚀速率小于50nm/min。
13.如权利要求12所述的制备方法,其特征在于,所述氧化锆覆盖层中掺入锡的量为10%~90%,在此条件下,刻蚀所述掺入锡的氧化锆覆盖层的速率大于200nm/min,并且在对所述半导体层进行退火处理后,浓度为5%的盐酸对所述半导体层的破坏刻蚀速率小于20nm/min。
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