WO2017193657A1 - 薄膜晶体管、阵列基板、显示面板以及显示装置及其制造方法 - Google Patents

薄膜晶体管、阵列基板、显示面板以及显示装置及其制造方法 Download PDF

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WO2017193657A1
WO2017193657A1 PCT/CN2017/073157 CN2017073157W WO2017193657A1 WO 2017193657 A1 WO2017193657 A1 WO 2017193657A1 CN 2017073157 W CN2017073157 W CN 2017073157W WO 2017193657 A1 WO2017193657 A1 WO 2017193657A1
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layer
doped layer
forming
doped
gate insulating
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PCT/CN2017/073157
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English (en)
French (fr)
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吕振华
王世君
陈希
尤杨
王磊
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京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Priority to US15/556,941 priority Critical patent/US10943926B2/en
Publication of WO2017193657A1 publication Critical patent/WO2017193657A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • the present disclosure relates to the field of display technology. More specifically, it relates to a thin film transistor and a method of fabricating the same, an array substrate and a method of fabricating the same, a display panel, a method of fabricating the same, a display device, and a method of fabricating the same.
  • the channel length L of the thin film transistor is difficult to be further shortened by the limitation of the accuracy of the Array process exposure apparatus employed in the prior art.
  • the pixel density (Pixels Per Inch, PPI) of high-end products is getting higher and higher, and pixel charging time is getting less and less.
  • the width of the thin film transistor has to be continuously increased, which seriously affects the pixel aperture ratio (AR), so that the power consumption of the liquid crystal display is significantly increased.
  • Embodiments of the present disclosure provide a thin film transistor and a method of fabricating the same, an array substrate and a method of fabricating the same, a display panel, a method of fabricating the same, a display device, and a method of fabricating the same, which can solve the problem that the channel length cannot be further reduced in the prior art. The problem.
  • a first aspect of the present disclosure provides a thin film transistor, the thin film transistor package a gate insulating layer; an active layer having a source region, a drain region, and a channel region between the source region and the drain region; in the source region a first doped layer; a second doped layer on the drain region, wherein the thin film transistor further comprises: disposed between the first doped layer and the second doped layer At least one third doped layer, wherein the first doped layer, the second doped layer, and the third doped layer have the same conductivity type, and wherein
  • the third doped layer is located in the channel region and is in contact with the gate insulating layer, and the third doped layer is not simultaneously different from the first doped layer and the second doped layer Contact, or
  • the third doped layer is on the channel region and is only in contact with the first doped layer or the second doped layer.
  • the thin film transistor further includes: a source electrode disposed on the first doped layer; a drain electrode disposed on the second doped layer,
  • the gate insulating layer is located on a side opposite to a side of the active layer on which the first doped layer and the second doped layer are formed, and is located in the active layer and Between the substrates.
  • the thin film transistor further includes: a source electrode disposed on the first doped layer; a drain electrode disposed on the second doped layer,
  • the gate insulating layer is located on the same side as the side of the active layer on which the first doped layer and the second doped layer are formed, and the active layer is located on the gate Between the insulating layer and the substrate.
  • the active layer comprises amorphous silicon.
  • the conductivity type of the first doped layer, the second doped layer, and the third doped layer is N-type.
  • Another object of the present disclosure is to provide an array substrate.
  • a second aspect of the present disclosure provides an array substrate including the above-described thin film transistor.
  • a third aspect of the present disclosure provides a display panel including the above array substrate.
  • a fourth aspect of the present disclosure provides a display device including the above display panel.
  • a fifth aspect of the present disclosure provides a method of fabricating a thin film transistor, comprising: forming an active layer having a source region, a drain region, and the source region and the drain region a channel region between the first doped layer on the source region and a second doped layer on the drain region, wherein the manufacturing method further includes:
  • the third doped layer is located in the channel region and is in contact with the gate insulating layer, and the third doped layer is not in contact with the first doped layer and the second doped layer, or
  • the third doped layer is on the channel region and is only in contact with the first doped layer or the second doped layer.
  • the method of fabricating the thin film transistor further includes: forming a gate electrode on the substrate; forming the gate insulating layer on the gate electrode;
  • forming the active layer includes: forming an active layer on the gate insulating layer after forming the gate insulating layer;
  • Forming the third doped layer includes forming a third doped layer in the channel region and in contact with the gate insulating layer in an ion implantation method.
  • the method of fabricating the thin film transistor further includes: forming a gate electrode on the substrate; forming the gate insulating layer on the gate electrode; and, at the first doping Forming a source electrode on the layer and forming a drain electrode on the second doped layer;
  • forming the active layer includes: forming an active layer on the gate insulating layer after forming the gate insulating layer;
  • Forming the third doped layer includes: forming a capping layer on the exposed surface of the channel region after forming the source electrode and the drain electrode; patterning the cap layer to form Forming the third doped layer on the channel region and only in contact with the first doped layer or the second doped layer.
  • the method of fabricating the thin film transistor further includes: forming the active layer on a substrate and forming the first doped layer and the second doped layer after the trench Forming the gate insulating layer on the track region;
  • forming the third doped layer comprises: forming, by the ion implantation method, the third doped layer in the channel region and in contact with the gate insulating layer.
  • the method of fabricating the thin film transistor further includes: forming a source electrode on the first doped layer and forming a drain electrode on the second doped layer; and, on the substrate After forming the active layer and forming the first doped layer and the second doped layer, forming the gate insulating layer on the channel region;
  • the forming the third doped layer comprises: forming a cap layer on the exposed surface of the channel after forming the source electrode and the drain electrode, and before forming the gate insulating layer Patterning the cap layer to form the third doped layer on the channel region and only in contact with the first doped layer or the second doped layer.
  • the active layer comprises amorphous silicon.
  • the conductivity type of the first doped layer, the second doped layer, and the third doped layer is N-type.
  • Still another object of the present disclosure is to provide a method of fabricating an array substrate.
  • a sixth aspect of the present disclosure provides a method of fabricating an array substrate, including the above-described method of fabricating a thin film transistor.
  • Still another object of the present disclosure is to provide a method of manufacturing a display panel.
  • a seventh aspect of the present disclosure provides a method of manufacturing a display panel comprising the above-described method of fabricating an array substrate.
  • An eighth aspect of the present disclosure provides a method of manufacturing a display device including the above-described method of manufacturing a display panel.
  • Thin film transistor provided by embodiment of the present disclosure, manufacturing method thereof, array substrate and a manufacturing method thereof, a display panel and a method of manufacturing the same, and a display device and a method of fabricating the same, wherein at least one third doped layer is disposed between the first doped layer and the second doped layer, wherein the first The doped layer, the second doped layer, and the third doped layer have the same conductivity type, and wherein
  • the third doped layer is located in the channel region and is in contact with the gate insulating layer, and the third doped layer is not simultaneously different from the first doped layer and the second doped layer Contacting, or the third doped layer is located on the channel region and only in contact with the first doped layer or the second doped layer, which can reduce the channel length and avoid affecting the pixel aperture ratio and Power consumption is rising.
  • FIG. 1(a) is a schematic illustration of a transistor in accordance with an embodiment of the present disclosure
  • FIG. 1(b) is a schematic illustration of a transistor in accordance with an embodiment of the present disclosure
  • FIG. 2(a) is a schematic diagram of a transistor in accordance with an embodiment of the present disclosure
  • FIG. 2(b) is a schematic diagram of a transistor in accordance with an embodiment of the present disclosure
  • 3(a) is a schematic illustration of a manufacturing process in accordance with an embodiment of the present disclosure
  • 3(b) is a schematic diagram of a manufacturing process in accordance with an embodiment of the present disclosure.
  • FIG. 4(a) is a schematic illustration of a manufacturing process in accordance with an embodiment of the present disclosure
  • 4(b) is a schematic diagram of a manufacturing process in accordance with one embodiment of the present disclosure.
  • the terms “upper”, “lower”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom” and The derivative should refer to the public text.
  • the terms “overlay”, “on top of”, “positioned on” or “positioned on top of” mean that a first element, such as a first structure, exists in a second element, such as a second structure. Above, wherein an intermediate element such as an interface structure may exist between the first element and the second element.
  • the term “contacting” means connecting a first element such as a first structure and a second element such as a second structure, with or without other elements at the interface of the two elements.
  • a thin film transistor of an embodiment of the present disclosure includes: a gate insulating layer 1; an active layer 2 having a source region, a drain region, and a source region and a drain a channel region between the pole regions; a first doped layer 3 on the source region; and a second doped layer 4 on the drain region.
  • the thin film transistor further includes: at least one third doping layer 5 disposed between the first doping layer 3 and the second doping layer 4, the first doping layer 3, the second doping layer 4, and the third doping layer
  • the impurity layer 5 has the same conductivity type, and wherein the third doping layer 5 is located in the channel region and is in contact with the gate insulating layer 1, and the third doping layer 5 is not simultaneously different from the first doping layer 3 and the second doped layer contact 4 (see FIG. 1 (a) and FIG. 2 (a)); or the third doped layer 5 is located on the channel region and only with the first doped layer 3 or the second doping
  • the impurity layer 4 is in contact (see Fig. 1(b) and Fig. 2(b)).
  • the source region of the active layer herein refers to the region of the active layer corresponding to the source electrode
  • the drain region of the active layer refers to the drain electrode of the active layer.
  • the region, the channel region of the active layer refers to the region of the active layer between its source region and the drain region.
  • the gate insulating layer is located on a side opposite to a side of the active layer on which the first doped layer and the second doped layer are formed, and is located between the active layer and the substrate. That is, in this case, the structure of the thin film transistor is a bottom gate structure.
  • FIG. 1(a) exemplarily shows the case where the third doping layer 5 is located in the channel region.
  • a gate electrode 7 is provided on a substrate 6, a gate insulating layer 1 is provided on the gate electrode 7, and an active layer 2 is provided on the gate insulating layer 1.
  • a first doped layer 3 and a second doped layer 4 are disposed on the active layer 2, a source electrode 8 is disposed on the first doped layer 3, and a drain electrode 9 is disposed on the second doped layer 4.
  • the third doped layer 5 is disposed between the first doped layer 3 and the second doped layer 4.
  • the positions of the source and drain can be interchanged.
  • the thickness of the third doping layer 5 is not particularly limited.
  • the third doping layer 5 is in contact with the gate insulating layer 1, that is, one side of the third doping layer 5 reaches one surface of the active layer. It should be noted that the opposite side of the third doped layer 5 does not necessarily need to reach the other surface opposite to the active layer 2.
  • FIG. 1(a) shows the case where the opposite side of the third doped layer 5 does not reach the other surface opposite to the active layer 2, the embodiment of the present disclosure also includes the third doped layer 5 instead. The case where one side reaches the other surface opposite to the active layer 2.
  • embodiments of the present disclosure may also include the case where the opposite side of the third doped layer 5 exceeds the other surface opposite the active layer 2.
  • the third doped layer 5 in FIG. 1(a) is not in contact with the first doped layer 3, it is not in contact with the second doped layer 4, however, the third doping may be performed as needed.
  • the impurity layer 5 is disposed in contact with the first doping layer 3 or the second doping layer 4 as long as the third doping layer 5 is not in contact with the first doping layer 3 and the second doping layer 4 at the same time.
  • FIG. 1(b) exemplarily shows the case where the third doping layer 5 is located on the channel region.
  • a gate electrode 7 is provided on the substrate 6, a gate insulating layer 1 is provided on the gate electrode 7, and an active layer 2 is provided on the gate insulating layer 1,
  • a first doped layer 3 and a second doped layer 4 are disposed on the active layer 2, a source electrode 8 is disposed on the first doped layer 3, and a drain electrode 9 is disposed on the second doped layer 4.
  • the third doped layer 5 is disposed between the first doped layer 3 and the second doped layer 4.
  • the positions of the source and drain can be interchanged.
  • the third doped layer is exemplified by the third doped layer being in contact with the second doped layer 4.
  • the third doping layer 5 is located on the channel, and one side thereof is in contact with the active layer 2. It is to be noted that the thickness of the third doping layer 5 is not particularly limited. Although in FIG. 1(b), the thickness of the third doping layer 5 is the same as that of the second doping layer 4, the thickness of the third doping layer 5 may also be the same as the second doping layer. 4 is not the same.
  • the gate insulating layer is located on the same side as the side of the active layer on which the first doped layer and the second doped layer are formed, and the active layer is on the gate insulating layer and the substrate. between. That is, in this case, the structure of the thin film transistor is a top gate structure.
  • FIG. 2(a) exemplarily shows the case where the third doping layer 5 is located in the channel region.
  • An active layer 2 is disposed on the substrate 6, and a first doping layer 3, a second doping layer 4, and a gate insulating layer 1 are disposed on the active layer 2, and the first doping layer 3 is disposed on the first doping layer 3
  • the source electrode 8 is provided with a drain electrode 9 on the second doped layer 4, and a gate electrode 7 is disposed on the gate insulating layer 1, wherein the first doped layer 3 and the second doped layer 4 are A third doping layer 5 is disposed therebetween.
  • the positions of the source and drain can be interchanged.
  • the thickness of the third doping layer 5 is not particularly limited.
  • the third doping layer 5 is in contact with the active layer 2, that is, one side of the third doping layer 5 reaches one surface of the active layer. It should be noted that the opposite side of the third doped layer 5 does not necessarily need to reach the other surface opposite to the active layer 2.
  • FIG. 2(a) shows the case where the opposite side of the third doped layer 5 does not reach the other surface opposite to the active layer 2, the embodiment of the present disclosure also includes the third doped layer 5 instead. The case where one side reaches the other surface opposite to the active layer 2.
  • the third doped layer 5 in FIG. 2(a) is not in contact with the first doped layer 3, it is not in contact with the second doped layer 4, however, the third doping may be performed as needed.
  • the impurity layer 5 is disposed in contact with the first doping layer 3 or the second doping layer 5 as long as the third doping layer 5 is not in contact with the first doping layer 3 and the second doping layer 4 at the same time.
  • FIG. 2(b) exemplarily shows the case where the third doping layer 5 is located on the channel region.
  • an active layer 2 is disposed on the substrate 6, and a first doped layer 3, a second doped layer 4, and a gate insulating layer 1 are disposed on the active layer 2,
  • a gate electrode 7 is disposed on the gate insulating layer 1
  • a source electrode 8 is disposed on the first doping layer 3
  • a drain electrode 9 is disposed on the second doping layer 4, wherein the first doping layer is disposed on the first doping layer
  • a third doped layer 5 is disposed between the 3 and the second doped layer 4.
  • the positions of the source and drain can be interchanged.
  • the third doped layer is in contact with the first doped layer 3.
  • the third doping layer 5 is located on the channel, and one side thereof is in contact with the active layer 2. It is to be noted that the thickness of the third doping layer 5 is not particularly limited. Although in FIG. 2(b), the thickness of the third doping layer 5 is the same as that of the second doping layer 4, However, the thickness of the third doping layer 5 may also be different from that of the second doping layer 4.
  • the doping concentration of the third doping layer 5 can be selected according to actual needs. The disclosure is not limited herein.
  • the third doped layer is heavily doped.
  • the third doped layer has an impurity concentration of more than 10 18 atoms per cubic centimeter.
  • the first doped layer, the second doped layer and the third doped layer have the same conductivity type, for example, both N-type or P-type, doped with phosphorus or antimony to obtain N-type, doped with boron Or indium element to get P type. Further, the first doped layer, the second doped layer and the third doped layer are N-type amorphous silicon materials.
  • a manufacturing method of an embodiment of the present disclosure includes: forming a gate insulating layer; forming an active layer having a source region, a drain region, and a channel region between the source region and the drain region; forming a first doped layer on the source region and a second doped layer on the drain region.
  • the manufacturing method further includes forming at least one third doped layer between the first doped layer and the second doped layer, wherein the first doped layer, the second doped layer, and the third doped layer have the same conductivity Types of.
  • the third doped layer is located in the channel region and is in contact with the gate insulating layer, and the third doped layer is not in contact with the first doped layer and the second doped layer; or The third doped layer is on the channel region and is only in contact with the first doped layer or the second doped layer.
  • the gate insulating layer is located on a side opposite to a side of the active layer on which the first doped layer and the second doped layer are formed, and is located between the active layer and the substrate. That is, in this case, the structure of the thin film transistor is a bottom gate structure.
  • FIG. 3 exemplarily illustrates an exemplary method for a bottom gate structure.
  • the process of forming the thin film transistor includes the following steps:
  • S14 forming a first doped layer on a source region of the active layer, and forming a second doped layer on a drain region of the active layer.
  • S15 forming a source electrode on the first doped layer and a drain electrode on the second doped layer.
  • a third doping layer located in the channel region and in contact with the gate insulating layer is formed in the channel region by ion implantation.
  • the step S161 of forming the third doped layer by the ion implantation method after the step S15 of forming the source electrode and the drain electrode is taken as an example.
  • the step S161 of forming the third doped layer by the ion implantation method does not have to be adjusted after the step S15 of forming the source electrode and the drain electrode, and may be adjusted according to actual needs.
  • the implanted ions are phosphorus ions. Or cesium ions.
  • the process of forming the thin film transistor includes the following steps:
  • S14 forming a first doped layer on a source region of the active layer, and forming a second doped layer on a drain region of the active layer.
  • S15 forming a source electrode on the first doped layer and a drain electrode on the second doped layer.
  • the cover layer is an N-type amorphous silicon material.
  • the gate insulating layer is located on the same side as the side of the active layer on which the first doped layer and the second doped layer are formed, and the active layer is on the gate insulating layer and the substrate between. That is, in this case, the structure of the thin film transistor is a top gate structure.
  • FIG. 4 exemplarily illustrates an exemplary method for a top gate structure.
  • the process of forming the thin film transistor includes the following steps:
  • S241 forming a third doped layer in the channel region and in contact with the gate insulating layer in the channel region by using an ion implantation method.
  • the step S241 of forming the third doped layer by the ion implantation method after the step S23 of forming the source electrode and the drain electrode is exemplified here.
  • the step S241 of forming the third doped layer by the ion implantation method does not necessarily have to be performed after the step S23 of forming the source electrode and the drain electrode, and may be adjusted according to actual needs.
  • the implanted ions are phosphorus ions or cerium ions.
  • the process of forming the thin film transistor includes the following steps:
  • the cover layer is an N-type amorphous silicon material.
  • the first doped layer, the second doped layer, and the third doped layer are doped to have the same conductivity type, for example, both are N-type (or both are P-type ).
  • the doping concentration of the third doping layer 5 can be selected according to actual needs. The disclosure is not limited herein.
  • the third doped layer is heavily doped.
  • the third doped layer has an impurity concentration of more than 10 18 atoms per cubic centimeter.
  • the material of the active layer may include amorphous silicon, and may include any other suitable material.
  • One embodiment of the present disclosure provides an array substrate including the thin film transistor of the foregoing embodiment.
  • the array substrate includes a substrate on which a data line, a gate line, a pixel electrode, and the foregoing thin film transistor are disposed.
  • Another embodiment of the present disclosure provides a display panel including the array substrate of the foregoing embodiment.
  • Yet another embodiment of the present disclosure provides a display device including the display panel of the foregoing embodiment.
  • Embodiments of the present disclosure provide a solution that significantly shortens the channel length.
  • a third doped layer is disposed between the first and second doped layers on the source region and the drain region of the active layer, and the three doped layers have the same conductivity type.
  • the third doped layer may be located in the channel region and in contact with the gate insulating layer, and the third doped layer is not in contact with the first doped layer and the second doped layer.
  • the third doped layer may also be on the channel region and only in contact with the first doped layer or the second doped layer.
  • the display device in the embodiment of the present disclosure may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

一种薄膜晶体管、阵列基板、显示面板以及显示装置及其制造方法。该薄膜晶体管包括：栅极绝缘层（1）；具有源极区域、漏极区域以及位于所述源极区域和所述漏极区域之间的沟道区域的有源层（2）；在所述源极区域上的第一掺杂层（3）；在所述漏极区域上的第二掺杂层（4）；设置在所述第一掺杂层（3）和所述第二掺杂层（4）之间的至少一个第三掺杂层（5），其中所述第一掺杂层（3）、所述第二掺杂层（4）和所述第三掺杂层（5）具有相同的导电类型，并且其中，所述第三掺杂层（5）位于所述沟道区域中且与所述栅极绝缘层（1）接触、不同时与所述第一掺杂层（3）和所述第二掺杂层（4）接触，或者所述第三掺杂层（5）位于所述沟道区域上且仅与所述第一掺杂层（3）或所述第二掺杂层（4）接触。

Description

薄膜晶体管、阵列基板、显示面板以及显示装置及其制造方法
相关申请的交叉引用
本申请要求于2016年05月13日递交的中国专利申请第201610318303.7号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开文本涉及显示技术领域。更具体地，涉及一种薄膜晶体管及其制造方法、阵列基板及其制造方法、显示面板及其制造方法以及显示装置及其制造方法。
背景技术
对于薄膜晶体管(Thin-Film Transistor，TFT)，其沟道的宽度与长度的比值(W/L)越大，开态电流Ion则越大。然而，受到现有技术中采用的阵列(Array)工艺曝光设备精度的限制，薄膜晶体管的沟道长度L难以进一步缩短。随之高端产品的像素密度(Pixels Per Inch，PPI)越来越高，像素充电时间越来越少。为了满足产品的充电率需求，不得不将薄膜晶体管的宽度不断增加，严重影响了像素开口率(Aperture Ratio，AR)，使得液晶显示屏功耗显著上升。
发明内容
本公开文本的实施例提供一种薄膜晶体管及其制造方法、阵列基板及其制造方法、显示面板及其制造方法以及显示装置及其制造方法，能够解决现有技术中的无法进一步降低沟道长度的问题。
本公开文本的一个目的在于提供一种薄膜晶体管。
本公开文本的第一方面提供了一种薄膜晶体管，所述薄膜晶体管包 括：栅极绝缘层；有源层，所述有源层具有源极区域、漏极区域以及位于所述源极区域和所述漏极区域之间的沟道区域；在所述源极区域上的第一掺杂层；在所述漏极区域上的第二掺杂层，其中，所述薄膜晶体管还包括：设置在所述第一掺杂层和所述第二掺杂层之间的至少一个第三掺杂层，其中所述第一掺杂层、所述第二掺杂层和所述第三掺杂层具有相同的导电类型，并且其中，
所述第三掺杂层位于所述沟道区域中且与所述栅极绝缘层接触，且所述第三掺杂层不同时与所述第一掺杂层和所述第二掺杂层接触，或者
所述第三掺杂层位于所述沟道区域上且仅与所述第一掺杂层或所述第二掺杂层接触。
在一种实施方式中，所述薄膜晶体管进一步包括：设置在所述第一掺杂层上的源极电极；设置在所述第二掺杂层上的漏极电极，
并且其中，所述栅极绝缘层位于与所述有源层的形成有所述第一掺杂层和所述第二掺杂层的一侧相反的一侧，且位于所述有源层和衬底之间。
在一个实施例中，所述薄膜晶体管进一步包括：设置在所述第一掺杂层上的源极电极；设置在所述第二掺杂层上的漏极电极，
并且其中，所述栅极绝缘层位于与所述有源层的形成有所述第一掺杂层和所述第二掺杂层的一侧相同的一侧，有源层位于所述栅极绝缘层和衬底之间。
在一个实施例中，所述有源层包括非晶硅。
在一个实施例中，所述第一掺杂层、所述第二掺杂层和所述第三掺杂层的所述导电类型为N型。
本公开文本的另一个目的在于提供一种阵列基板。
本公开文本的第二方面提供了一种阵列基板，所述阵列基板包括上述的薄膜晶体管。
本公开文本的又一个目的在于提供一种显示面板。
本公开文本的第三方面提供了一种显示面板，所述显示面板包括上述的阵列基板。
本公开文本的再一个目的在于提供一种显示装置。
本公开文本的第四方面提供了一种显示装置，所述显示装置包括上述的显示面板。
本公开文本的又一个目的在于提供一种薄膜晶体管的制造方法。
本公开文本的第五方面提供了一种薄膜晶体管的制造方法，包括：形成有源层，所述有源层具有源极区域、漏极区域以及位于所述源极区域和所述漏极区域之间的沟道区域；形成在所述源极区域上的第一掺杂层和在所述漏极区域上的第二掺杂层，其中，所述制造方法还包括：
在所述第一掺杂层和所述第二掺杂层之间形成至少一个第三掺杂层，其中所述第一掺杂层、所述第二掺杂层和所述第三掺杂层具有相同的导电类型，并且其中，
所述第三掺杂层位于所述沟道区域中且与栅极绝缘层接触，且所述第三掺杂层不同时与所述第一掺杂层和所述第二掺杂层接触，或者
所述第三掺杂层位于所述沟道区域上且仅与所述第一掺杂层或所述第二掺杂层接触。
在一种实施方式中，所述薄膜晶体管的制造方法进一步包括：在衬底上形成栅极电极；在所述栅极电极上形成所述栅极绝缘层；
其中，形成有源层包括：在形成所述栅极绝缘层之后在所述栅极绝缘层上形成有源层；
形成所述第三掺杂层包括：采用离子注入法，在所述沟道区域中形成位于所述沟道区域中且与所述栅极绝缘层接触的所述第三掺杂层。
在一种实施方式中，所述薄膜晶体管的制造方法进一步包括：在衬底上形成栅极电极；在所述栅极电极上形成所述栅极绝缘层；以及，在所述第一掺杂层上形成源极电极和在所述第二掺杂层上形成漏极电极；
其中，形成有源层包括：在形成所述栅极绝缘层之后，在所述栅极绝缘层上形成有源层；
形成所述第三掺杂层包括：在形成所述源极电极和所述漏极电极之后，在所述沟道区域的暴露表面上形成覆盖层；对所述覆盖层构图，以形 成位于所述沟道区域上且仅与所述第一掺杂层或所述第二掺杂层接触的所述第三掺杂层。
在一种实施方式中，所述薄膜晶体管的制造方法进一步包括：在衬底上形成所述有源层和形成所述第一掺杂层和所述第二掺杂层之后，在所述沟道区域上形成所述栅极绝缘层；
其中，形成所述第三掺杂层包括：采用离子注入法，在所述沟道区域中形成位于所述沟道区域中且与所述栅极绝缘层接触的所述第三掺杂层。
在一种实施方式中，所述薄膜晶体管的制造方法进一步包括：在所述第一掺杂层上形成源极电极和在所述第二掺杂层上形成漏极电极；以及，在衬底上形成所述有源层和形成所述第一掺杂层和所述第二掺杂层之后，在所述沟道区域上形成所述栅极绝缘层；
其中，形成所述第三掺杂层包括：在形成所述源极电极和所述漏极电极之后，且在形成所述栅极绝缘层之前，在所述沟道的暴露表面上形成覆盖层；对所述覆盖层构图，以形成位于所述沟道区域上且仅与所述第一掺杂层或所述第二掺杂层接触的所述第三掺杂层。
在一个实施例中，所述有源层包括非晶硅。
在一个实施例中，所述第一掺杂层、所述第二掺杂层和所述第三掺杂层的所述导电类型为N型。
本公开文本的又一个目的在于提供一种阵列基板的制造方法。
本公开文本的第六方面提供了一种阵列基板的制造方法，包括上述的薄膜晶体管的制造方法。
本公开文本的又一个目的在于提供一种显示面板的制造方法。
本公开文本的第七方面提供了一种显示面板的制造方法，包括上述的阵列基板的制造方法。
本公开文本的又一个目的在于提供一种显示装置的制造方法。
本公开文本的第八方面提供了一种显示装置的制造方法，包括上述的显示面板的制造方法。
本公开文本的实施例所提供的薄膜晶体管及其制造方法、阵列基板及 其制造方法、显示面板及其制造方法以及显示装置及其制造方法，在所述第一掺杂层和所述第二掺杂层之间设置至少一个第三掺杂层，其中所述第一掺杂层、所述第二掺杂层和所述第三掺杂层具有相同的导电类型，并且其中，
所述第三掺杂层位于所述沟道区域中且与所述栅极绝缘层接触，且所述第三掺杂层不同时与所述第一掺杂层和所述第二掺杂层接触，或者所述第三掺杂层位于所述沟道区域上且仅与所述第一掺杂层或所述第二掺杂层接触，能够降低沟道长度，避免了影响像素开口率和功耗上升。
附图说明
为了更清楚地说明本公开文本的实施例的技术方案，下面将对实施例的附图进行简要说明，应当知道，以下描述的附图仅仅涉及本公开文本的一些实施例，而非对本公开文本的限制，其中：
图1(a)为根据本公开文本的一个实施例的晶体管的示意图；
图1(b)为根据本公开文本的一个实施例的晶体管的示意图；
图2(a)为根据本公开文本的一个实施例的晶体管的示意图；
图2(b)为根据本公开文本的一个实施例的晶体管的示意图；
图3(a)为根据本公开文本的一个实施例的制造流程的示意图；
图3(b)为根据本公开文本的一个实施例的制造流程的示意图；
图4(a)为根据本公开文本的一个实施例的制造流程的示意图；
图4(b)为根据本公开文本的一个实施例的制造流程的示意图。
具体实施方式
为了使本公开文本的实施例的目的、技术方案和优点更加清楚，下面将接合附图，对本公开文本的实施例的技术方案进行清楚、完整的描述。显然，所描述的实施例是本公开文本的一部分实施例，而不是全部的实施例。基于所描述的本公开文本的实施例，本领域技术人员在无需创造性劳动的前提下所获得的所有其他实施例，也都属于本公开文本保护的范围。
当介绍本公开文本的元素及其实施例时，冠词“一”、“一个”、“该”和“所述”旨在表示存在一个或者多个要素。用语“包含”、“包括”、“含有”和“具有”旨在包括性的并且表示可以存在除所列要素之外的另外的要素。
出于下文表面描述的目的，如其在附图中被标定方向那样，术语“上”、“下”、“左”、“右”“垂直”、“水平”、“顶”、“底”及其派生词应涉及公开文本。术语“上覆”、“在……顶上”、“定位在……上”或者“定位在……顶上”意味着诸如第一结构的第一要素存在于诸如第二结构的第二要素上，其中，在第一要素和第二要素之间可存在诸如界面结构的中间要素。术语“接触”意味着连接诸如第一结构的第一要素和诸如第二结构的第二要素，而在两个要素的界面处可以有或者没有其它要素。
图1和图2为根据本公开文本的不同实施例的晶体管的示意图。如图1和图2所示，本公开文本的实施例的薄膜晶体管包括：栅极绝缘层1；有源层2，该有源层具有源极区域、漏极区域以及位于源极区域和漏极区域之间的沟道区域；在源极区域上的第一掺杂层3；在漏极区域上的第二掺杂层4。薄膜晶体管还包括：设置在第一掺杂层3和第二掺杂层4之间的至少一个第三掺杂层5，该第一掺杂层3、第二掺杂层4和第三掺杂层5具有相同的导电类型，并且其中，该第三掺杂层5位于沟道区域中且与栅极绝缘层接触1，且所述第三掺杂层5不同时与第一掺杂层3和第二掺杂层接触4(参见图1(a)和图2(a))；或者该第三掺杂层5位于沟道区域上且仅与第一掺杂层3或第二掺杂层4接触(参见图1(b)和图2(b))。
本领域技术人员可以明白，这里的有源层的源极区域是指有源层的与源极电极相对应的区域，有源层的漏极区域是指有源层的与漏极电极相对应的区域，有源层的沟道区域是指有源层的在其源极区域和漏极区域之间的区域。
在一种实施方式中，栅极绝缘层位于与有源层的形成有第一掺杂层和第二掺杂层的一侧相反的一侧，且位于有源层和衬底之间。即，在该情况下，薄膜晶体管的结构为底栅结构。
对于底栅结构，具体地，图1(a)示例性示出了第三掺杂层5位于沟道区域中的情况。如图1(a)所示，在衬底6上设置有栅极电极7，在栅极电极7上设置有栅极绝缘层1，在栅极绝缘层1上设置有有源层2，在有源层2上设置有第一掺杂层3和第二掺杂层4，在第一掺杂层3上设置有源极电极8，在第二掺杂层4上设置有漏极电极9，其中在第一掺杂层3和第二掺杂层4之间设置有第三掺杂层5。这里，源极和漏极的位置可以互换。对于图1(a)所示的情况，需要指出，第三掺杂层5的厚度不受特别限制。第三掺杂层5与栅极绝缘层1接触，即，第三掺杂层5的一侧到达有源层的一个表面。需要注意，第三掺杂层5相反的一侧不一定需要到达有源层2相反的另一个表面。虽然图1(a)示出了第三掺杂层5相反的一侧没有到达有源层2相反的另一个表面的情况，然而，本公开文本的实施例也包括第三掺杂层5相反的一侧到达有源层2相反的另一个表面的情况。当然，本公开文本的实施例也可以包括第三掺杂层5相反的一侧超过有源层2相反的另一个表面的情况。
还需要指出，虽然图1(a)中的第三掺杂层5未与第一掺杂层3接触，其也未与第二掺杂层4接触，然而，可以根据需要，将第三掺杂层5设置为与第一掺杂层3或者第二掺杂层4接触，只要满足第三掺杂层5不同时与第一掺杂层3和第二掺杂层4接触即可。
对于底栅结构，具体地，图1(b)示例性示出了第三掺杂层5位于沟道区域上的情况。如图1(b)所示，在衬底6上设置有栅极电极7，在栅极电极7上设置有栅极绝缘层1，在栅极绝缘层1上设置有有源层2，在有源层2上设置有第一掺杂层3和第二掺杂层4，在第一掺杂层3上设置有源极电极8，在第二掺杂层4上设置有漏极电极9，其中在第一掺杂层3和第二掺杂层4之间设置有第三掺杂层5。这里，源极和漏极的位置可以互换。图1(b)以第三掺杂层与第二掺杂层4接触为示例。如图1(b)所示，第三掺杂层5位于沟道上，且其一侧与有源层2接触。需要指出，第三掺杂层5的厚度不受特别限制。虽然在图1(b)中，第三掺杂层5的厚度与第二掺杂层4一样，然而第三掺杂层5的厚度也可以与第二掺杂层 4不一样。
在另一种实施方式中，栅极绝缘层位于与有源层的形成有第一掺杂层和第二掺杂层的一侧相同的一侧，有源层位于栅极绝缘层和衬底之间。即，在该情况下，薄膜晶体管的结构为顶栅结构。
对于顶栅结构，具体地，图2(a)示例性示出了第三掺杂层5位于沟道区域中的情况。在衬底6上设置有有源层2，在有源层2上设置有第一掺杂层3、第二掺杂层4以及栅极绝缘层1，在第一掺杂层3上设置有源极电极8，在第二掺杂层4上设置有漏极电极9，在栅极绝缘层1上设置有栅极电极7，其中在第一掺杂层3和第二掺杂层4之间设置有第三掺杂层5。这里，源极和漏极的位置可以互换。需要指出，第三掺杂层5的厚度不受特别限制。第三掺杂层5与有源层2接触，即，第三掺杂层5的一侧到达有源层的一个表面。需要注意，第三掺杂层5相反的一侧不一定需要到达有源层2相反的另一个表面。虽然图2(a)示出了第三掺杂层5相反的一侧没有到达有源层2相反的另一个表面的情况，然而，本公开文本的实施例也包括第三掺杂层5相反的一侧到达有源层2相反的另一个表面的情况。
还需要指出，虽然图2(a)中的第三掺杂层5未与第一掺杂层3接触，其也未与第二掺杂层4接触，然而，可以根据需要，将第三掺杂层5设置为与第一掺杂层3或者第二掺杂层5接触，只要满足第三掺杂层5不同时与第一掺杂层3和第二掺杂层4接触即可。
对于顶栅结构，具体地，图2(b)示例性示出了第三掺杂层5位于沟道区域上的情况。如图2(b)所示，在衬底6上设置有有源层2，在有源层2上设置有第一掺杂层3、第二掺杂层4以及栅极绝缘层1，在栅极绝缘层1上设置有栅极电极7，在第一掺杂层3上设置有源极电极8，在第二掺杂层4上设置有漏极电极9，其中在第一掺杂层3和第二掺杂层4之间设置有第三掺杂层5。这里，源极和漏极的位置可以互换。图2(b)以第三掺杂层与第一掺杂层3接触为示例。如图1(b)所示，第三掺杂层5位于沟道上，且其一侧与有源层2接触。需要指出，第三掺杂层5的厚度不受特别限制。虽然在图2(b)中，第三掺杂层5的厚度与第二掺杂层4一样， 然而第三掺杂层5的厚度也可以与第二掺杂层4不一样。
第三掺杂层5的掺杂浓度可以根据实际需要而选择。本公开文本在此不做限制。在一种实施方式中，第三掺杂层被重掺杂。例如，第三掺杂层的杂质浓度为每立方厘米原子数大于1018个。第一掺杂层、第二掺杂层和第三掺杂层具有相同的导电类型，例如，都为N型或者都为P型，掺入磷元素或锑元素得到N型，掺入硼元素或铟元素得到P型。进一步地，第一掺杂层、第二掺杂层和第三掺杂层为N型非晶硅材料。
图3-图4为根据本公开文本的实施例的制造流程的示意图。本公开文本的实施例的制造方法包括：形成栅极绝缘层；形成有源层，有源层具有源极区域、漏极区域以及位于源极区域和漏极区域之间的沟道区域；形成在源极区域上的第一掺杂层和在漏极区域上的第二掺杂层。该制造方法还包括在第一掺杂层和第二掺杂层之间形成至少一个第三掺杂层，其中第一掺杂层、第二掺杂层和第三掺杂层具有相同的导电类型。并且其中，第三掺杂层位于沟道区域中且与栅极绝缘层接触，且所述第三掺杂层不同时与所述第一掺杂层和所述第二掺杂层接触；或者第三掺杂层位于沟道区域上且仅与第一掺杂层或第二掺杂层接触。
在一种实施方式中，栅极绝缘层位于与有源层的形成有第一掺杂层和第二掺杂层的一侧相反的一侧，且位于有源层和衬底之间。即，在该情况下，薄膜晶体管的结构为底栅结构。
具体地，图3示例性示出对于底栅结构的示例性方法。
如图3(a)所示，在一个实施例中，当在沟道区域中形成第三掺杂层时,形成薄膜晶体管的流程包括以下步骤：
S11：在衬底上形成栅极电极。
S12：在栅极电极上形成栅极绝缘层。
S13：在栅极绝缘层上形成有源层。
S14：在有源层的源极区域上形成第一掺杂层，在有源层的漏极区域上形成第二掺杂层。
S15：在第一掺杂层上形成源极电极，在第二掺杂层上形成漏极电极。
S161：采用离子注入法，在沟道区域中形成位于沟道区域中且与栅极绝缘层接触的第三掺杂层。
需要说明，这里以在形成源极电极和漏极电极的步骤S15之后，采用离子注入法形成第三掺杂层的步骤S161为示例。然而，采用离子注入法形成第三掺杂层的步骤S161不一定要在形成源极电极和漏极电极的步骤S15之后，也可以根据实际需要而进行调整，优选地，注入的离子为磷离子或锑离子。
如图3(b)所示，在一个实施例中，当在沟道区域上形成第三掺杂层时,形成薄膜晶体管的流程包括以下步骤：
S11：在衬底上形成栅极电极。
S12：在栅极电极上形成栅极绝缘层。
S13：在栅极绝缘层上形成有源层。
S14：在有源层的源极区域上形成第一掺杂层，在有源层的漏极区域上形成第二掺杂层。
S15：在第一掺杂层上形成源极电极，在第二掺杂层上形成漏极电极。
S162：在沟道区域的暴露表面上形成覆盖层；对所述覆盖层构图，以形成位于沟道区域上且仅与第一掺杂层或第二掺杂层接触的第三掺杂层。优选地，所述覆盖层为N型非晶硅材料。
在另一种实施方式中，栅极绝缘层位于与有源层的形成有第一掺杂层和第二掺杂层的一侧相同的一侧，有源层位于栅极绝缘层和衬底之间。即，在该情况下，薄膜晶体管的结构为顶栅结构。
具体地，图4示例性示出对于顶栅结构的示例性方法。
如图4(a)所示，在一个实施例中，当在沟道区域中形成第三掺杂层时，形成薄膜晶体管的流程包括以下步骤：
S21：在衬底上形成有源层。
S22：在有源层的源极区域上形成第一掺杂层，在有源层的漏极区域上形成第二掺杂层。
S23：在第一掺杂层上形成源极电极，在第二掺杂层上形成漏极电极。
S241：采用离子注入法，在沟道区域中形成位于沟道区域中且与栅极绝缘层接触的第三掺杂层。
S25：在有源层的沟道区域上形成栅极绝缘层。
S26：在栅极绝缘层上形成栅极电极。
需要说明，这里以在形成源极电极和漏极电极的步骤S23之后，采用离子注入法形成第三掺杂层的步骤S241为示例。然而，采用离子注入法形成第三掺杂层的步骤S241不一定要在形成源极电极和漏极电极的步骤S23之后，也可以根据实际需要而进行调整。，优选地，注入的离子为磷离子或锑离子。
如图4(b)所示，在一个实施例中，当在沟道区域上形成第三掺杂层时，形成薄膜晶体管的流程包括以下步骤：
S21：在衬底上形成有源层。
S22：在有源层的源极区域上形成第一掺杂层，在有源层的漏极区域上形成第二掺杂层。
S23：在第一掺杂层上形成源极电极，在第二掺杂层上形成漏极电极。
S242：在沟道的暴露表面上形成覆盖层；对覆盖层构图，以形成位于沟道区域上且仅与第一掺杂层或第二掺杂层接触的第三掺杂层。优选地，所述覆盖层为N型非晶硅材料。
S25：在有源层的沟道区域上形成栅极绝缘层。
S26：在栅极绝缘层上形成栅极电极。
在本公开文本的实施例的方法中，将第一掺杂层、第二掺杂层和第三掺杂层掺杂为具有相同的导电类型，例如，都为N型(或者都为P型)。此外，第三掺杂层5的掺杂浓度可以根据实际需要而选择。本公开文本在此不做限制。在一种实施方式中，第三掺杂层被重掺杂。例如，第三掺杂层的杂质浓度为每立方厘米原子数大于1018个。有源层的材料可以包括非晶硅，也可以包括其它任何合适的材料。
本公开文本中描绘的流程图仅仅是示例性的。在不脱离本公开文本精 神的情况下，可以存在该流程图或其中描述的步骤的很多变型。例如，所述步骤可以以不同的顺序进行，或者可以添加、删除或者修改步骤。这些变型都被认为是所要求保护的方面的一部分。
本公开文本的一个实施例提供了一种阵列基板，其包括前述实施例的薄膜晶体管。具体地，该阵列基板包括衬底基板，在衬底基板上设置有数据线、栅线、像素电极和前述薄膜晶体管。本公开文本的另一个实施例提供了一种显示面板，其包括前述实施例的阵列基板。本公开文本的又一个实施例提供了一种显示装置，其包括前述实施例的显示面板。
本公开文本的一个实施例提供了一种阵列基板的制造方法，其包括前述实施例的薄膜晶体管的制造方法。本公开文本的另一个实施例提供了一种显示面板的制造方法，其包括前述实施例的阵列基板的制造方法。本公开文本的又一个实施例提供了一种显示装置的制造方法，其包括前述实施例的显示面板的制造方法。
本公开文本的实施例提供了显著缩短沟道长度的方案。在有源层的源极区域和漏极区域上的第一和第二掺杂层之间设置第三掺杂层，且三个掺杂层具有相同的导电类型。第三掺杂层可以位于沟道区域中且与栅极绝缘层接触，且第三掺杂层不同时与第一掺杂层和第二掺杂层接触。第三掺杂层也可以位于沟道区域上且仅与第一掺杂层或第二掺杂层接触。通过本公开文本的实施例方案能够降低沟道长度，避免了影响像素开口率和功耗上升。
本公开文本的实施例中的显示装置可以为：手机、平板电脑、电视机、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
已经描述了某特定实施例，这些实施例仅通过举例的方式展现，而且不旨在限制本公开文本的范围。事实上，本文所描述的新颖实施例可以以各种其它形式来实施；此外，可在不脱离本公开文本的精神下，做出以本文所描述的实施例的形式的各种省略、替代和改变。所附权利要求以及它们的等价物旨在覆盖落在本公开文本范围和精神内的此类形式或者修改。

Claims (18)

  1. 一种薄膜晶体管，包括：栅极绝缘层；有源层，所述有源层具有源极区域、漏极区域以及位于所述源极区域和所述漏极区域之间的沟道区域；在所述源极区域上的第一掺杂层；在所述漏极区域上的第二掺杂层，其中，所述薄膜晶体管还包括：
    设置在所述第一掺杂层和所述第二掺杂层之间的至少一个第三掺杂层，其中所述第一掺杂层、所述第二掺杂层和所述第三掺杂层具有相同的导电类型，并且其中，
    所述第三掺杂层位于所述沟道区域中且与所述栅极绝缘层接触，且所述第三掺杂层不同时与所述第一掺杂层和所述第二掺杂层接触，或者
    所述第三掺杂层位于所述沟道区域上且仅与所述第一掺杂层或所述第二掺杂层接触。
  2. 根据权利要求1所述的薄膜晶体管，进一步包括：设置在所述第一掺杂层上的源极电极；设置在所述第二掺杂层上的漏极电极，
    并且其中，所述栅极绝缘层位于与所述有源层的形成有所述第一掺杂层和所述第二掺杂层的一侧相反的一侧，且位于所述有源层和衬底之间。
  3. 根据权利要求1所述的薄膜晶体管，进一步包括：设置在所述第一掺杂层上的源极电极；设置在所述第二掺杂层上的漏极电极，
    并且其中，所述栅极绝缘层位于与所述有源层的形成有所述第一掺杂层和所述第二掺杂层的一侧相同的一侧，有源层位于所述栅极绝缘层和衬底之间。
  4. 根据权利要求1-3中任一项所述的薄膜晶体管，其中，所述有源层包括非晶硅。
  5. 根据权利要求1-3中任一项所述的薄膜晶体管，其中，所述第一掺杂层、所述第二掺杂层和所述第三掺杂层的所述导电类型为N型。
  6. 一种阵列基板，包括根据权利要求1-5中任一项所述的薄膜晶体管。
  7. 一种显示面板，包括根据权利要求6所述的阵列基板。
  8. 一种显示装置，包括根据权利要求7所述的显示面板。
  9. 一种薄膜晶体管的制造方法，包括：形成有源层，所述有源层具有源极区域、漏极区域以及位于所述源极区域和所述漏极区域之间的沟道区域；形成在所述源极区域上的第一掺杂层和在所述漏极区域上的第二掺杂层，其中，所述制造方法还包括：
    在所述第一掺杂层和所述第二掺杂层之间形成至少一个第三掺杂层，其中所述第一掺杂层、所述第二掺杂层和所述第三掺杂层具有相同的导电类型，并且其中，
    所述第三掺杂层位于所述沟道区域中且与栅极绝缘层接触，且所述第三掺杂层不同时与所述第一掺杂层和所述第二掺杂层接触，或者
    所述第三掺杂层位于所述沟道区域上且仅与所述第一掺杂层或所述第二掺杂层接触。
  10. 根据权利要求9所述的制造方法，进一步包括：在衬底上形成栅极电极；在所述栅极电极上形成所述栅极绝缘层；
    其中，形成有源层包括：在形成所述栅极绝缘层之后在所述栅极绝缘层上形成有源层；
    形成所述第三掺杂层包括：采用离子注入法，在所述沟道区域中形成位于所述沟道区域中且与所述栅极绝缘层接触的所述第三掺杂层。
  11. 根据权利要求9所述的制造方法，进一步包括：在衬底上形成栅极电极；在所述栅极电极上形成所述栅极绝缘层；以及，在所述第一掺杂层上形成源极电极和在所述第二掺杂层上形成漏极电极，
    其中，形成有源层包括：在形成所述栅极绝缘层之后，在所述栅极绝缘层上形成有源层；
    形成所述第三掺杂层包括：在形成所述源极电极和所述漏极电极之后，在所述沟道区域的暴露表面上形成覆盖层；对所述覆盖层构图，以形成位于所述沟道区域上且仅与所述第一掺杂层或所述第二掺杂层接触的所述第三掺杂层。
  12. 根据权利要求9所述的制造方法，进一步包括：在衬底上形成所述有源层和形成所述第一掺杂层和所述第二掺杂层之后，在所述沟道区域 上形成所述栅极绝缘层；
    其中，形成所述第三掺杂层包括：采用离子注入法，在所述沟道区域中形成位于所述沟道区域中且与所述栅极绝缘层接触的所述第三掺杂层。
  13. 根据权利要求9所述的制造方法，进一步包括：在所述第一掺杂层上形成源极电极和在所述第二掺杂层上形成漏极电极；以及，在衬底上形成所述有源层和形成所述第一掺杂层和所述第二掺杂层之后，在所述沟道区域上形成所述栅极绝缘层；
    其中，形成所述第三掺杂层包括：在形成所述源极电极和所述漏极电极之后，且在形成所述栅极绝缘层之前，在所述沟道的暴露表面上形成覆盖层；对所述覆盖层构图，以形成位于所述沟道区域上且仅与所述第一掺杂层或所述第二掺杂层接触的所述第三掺杂层。
  14. 根据权利要求9-13中任一项所述的制造方法，其中，所述有源层包括非晶硅。
  15. 根据权利要求9-13中任一项所述的制造方法，其中，所述第一掺杂层、所述第二掺杂层和所述第三掺杂层的所述导电类型为N型。
  16. 一种阵列基板的制造方法，包括根据权利要求9-15中任一项所述的薄膜晶体管的制造方法。
  17. 一种显示面板的制造方法，包括根据权利要求16所述的阵列基板的制造方法。
  18. 一种显示装置的制造方法，包括根据权利要求17所述的显示面板的制造方法。
PCT/CN2017/073157 2016-05-13 2017-02-09 薄膜晶体管、阵列基板、显示面板以及显示装置及其制造方法 WO2017193657A1 (zh)

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