WO2016058321A1 - 薄膜晶体管、其制作方法、阵列基板及显示装置 - Google Patents

薄膜晶体管、其制作方法、阵列基板及显示装置 Download PDF

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WO2016058321A1
WO2016058321A1 PCT/CN2015/074270 CN2015074270W WO2016058321A1 WO 2016058321 A1 WO2016058321 A1 WO 2016058321A1 CN 2015074270 W CN2015074270 W CN 2015074270W WO 2016058321 A1 WO2016058321 A1 WO 2016058321A1
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active layer
thin film
film transistor
substrate
orthographic projection
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PCT/CN2015/074270
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English (en)
French (fr)
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张莹
李鑫
朱红
于洪俊
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京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Priority to US14/778,939 priority Critical patent/US9608011B2/en
Priority to EP15762463.6A priority patent/EP3208851A4/en
Publication of WO2016058321A1 publication Critical patent/WO2016058321A1/zh

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    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
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Definitions

  • the present invention relates to the field of display technologies, and more particularly to a thin film transistor, a method of fabricating the same, an array substrate, and a display device.
  • thin film transistors play an important role in the production of display devices.
  • the on-state of the thin-film transistor is used to quickly charge the pixel capacitance of the display device, and the off-state of the thin film transistor is used to maintain the voltage of the pixel capacitor, thereby achieving uniformity of fast response and good storage.
  • Thin film transistors are widely used as large-area liquid crystal displays and contact image sensors because of their very high ratio of on-state current (Ion) to off-state current (Ioff) and steep transfer characteristics. .
  • FIG. 1 a specific structure of a conventional bottom-gate anti-stack type amorphous silicon thin film transistor is as shown in FIG. 1 , which includes a substrate substrate 01 , a gate electrode 02 disposed on the substrate substrate 01 , and is disposed on the gate electrode 02 .
  • An active layer 03 insulated from the gate 02, and a source 04 and a drain 05 which are oppositely disposed and electrically connected to the active layer 03, respectively.
  • a gate insulating layer 06 is disposed between the gate electrode 02 and the active layer 03, and a passivation layer 07 is disposed over the source electrode 04 and the drain electrode 05.
  • the gate insulating layer 06 is usually made of a-SiNx film
  • the active layer 03 is usually made of a-Si:H film
  • the passivation layer 07 is usually made of a-SiNx film
  • the gate 02, the source 04 and the drain 05 are usually used.
  • Metal chrome material In order to improve the contact characteristics of the source 04 and the a-Si:H film, the drain 05 and the a-Si:H film, a thin n + -type a-Si:H film is interposed therebetween as the ohmic contact layer 08.
  • the a-Si:H film which is an active layer of a thin film transistor, has a good photosensitive property. s material. However, under backlight conditions, the resistance of the active layer itself changes, thereby increasing the off-state current of the thin film transistor by two to three orders of magnitude. This greatly reduces the ratio of the on-state current to the off-state current of the thin film transistor, which seriously affects the image display quality of the liquid crystal display.
  • the embodiments of the present invention provide a thin film transistor, a manufacturing method thereof, an array substrate, and a display device, thereby effectively suppressing an increase in an off-state current, increasing a ratio of an on-state current to an off-state current, thereby improving a thin film.
  • the luminescence properties of the transistor are described in detail below.
  • an embodiment of the present invention provides a thin film transistor including: a substrate, a gate disposed on the substrate, and an active layer disposed on the gate and insulated from the gate And a source and a drain that are oppositely disposed and electrically connected to the active layer respectively;
  • the active layer includes a first active layer and a second active layer which are disposed in a stacked manner; wherein
  • An orthographic projection of the first active layer on the base substrate covers an orthographic projection of the source, the drain, and a gap between the source and the drain on the base substrate, and Covering an orthographic projection of the gate on the substrate;
  • the second active layer is located at a gap between the source and the drain, and an orthographic projection on the substrate is located in a region where the gate is orthographically projected on the substrate.
  • the second active layer is located above the first active layer and is connected to the first active layer.
  • the second active layer is electrically connected to the first active layer; or the second active layer and the first active layer are insulated from each other and separately from the source, The drain is electrically connected.
  • the thin film transistor provided by the embodiment of the present invention further includes: disposed between the first active layer and the source, and disposed on the first active layer and An ohmic contact layer between the drains.
  • the thin film transistor provided by the embodiment of the present invention further includes: a light shielding layer disposed above the second active layer and insulated from the second active layer;
  • An orthographic projection of the light shielding layer on the substrate substrate covers an orthographic projection of the second active layer on the substrate substrate.
  • the thickness of the second active layer is greater than the thickness of the first active layer.
  • the first active layer has a thickness of 60 nm to 100 nm.
  • a sum of thicknesses of the first active layer and the second active layer is 100 nm to 500 nm.
  • the embodiment of the invention provides an array substrate, which comprises the above-mentioned thin film transistor provided by the embodiment of the invention.
  • a display device includes the above array substrate provided by the embodiment of the invention.
  • the embodiment of the invention further provides a method for fabricating the above thin film transistor provided by the embodiment of the invention, comprising:
  • a pattern of the second active layer, the source and the drain is formed on the first active layer.
  • Embodiments of the present invention provide a thin film transistor, a method of fabricating the same, an array substrate, and a display device.
  • the active layer in the thin film transistor includes a first active layer and a second active layer disposed in a stacked manner; wherein an orthographic projection of the first active layer on the substrate substrate covers the source and the drain, and is located at the source and the drain An orthographic projection of the gap between the poles on the base substrate and covering the orthographic projection of the gate on the base substrate; the second active layer is located at a gap between the source and the drain, and on the base substrate The orthographic projection is located in the region of the gate where the orthographic projection on the substrate is located.
  • the expression “orthoprojection” means that the projection direction is perpendicular to the plane of projection.
  • a orthographic projection on B means that A will be in a direction perpendicular to B. Project onto B.
  • FIG. 1 is a schematic structural view of a bottom gate reverse stacked thin film transistor in the prior art
  • FIG. 2 is a schematic structural diagram of a thin film transistor according to an embodiment of the present invention.
  • FIG. 3 is a flowchart of a method for fabricating a thin film transistor according to an embodiment of the present invention.
  • each film layer and the size and shape of the regions in the drawings do not reflect the true proportions of the respective components of the thin film transistor.
  • the purpose of the drawings is merely to illustrate the invention.
  • An embodiment of the present invention provides a thin film transistor, as shown in FIG. 2, comprising: a substrate substrate 11, a gate electrode 12 disposed on the substrate substrate, and an active device disposed on the gate electrode 12 and insulated from the gate electrode a layer 13, and a source 14 and a drain 15 that are oppositely disposed and electrically connected to the active layer respectively;
  • the active layer 13 includes a first active layer 131 and a second active layer 132 which are disposed in a stacked manner;
  • the orthographic projection of the first active layer 131 on the substrate substrate 11 covers the source 14 , the drain 15 , and the orthographic projection of the gap between the source 14 and the drain 15 on the substrate 11 , and covers the gate
  • the second active layer 132 is located at a gap between the source 14 and the drain 15, and the orthographic projection on the base substrate 11 is located in a region where the orthographic projection of the gate 12 on the substrate substrate 11 is located.
  • the active layer in the thin film transistor includes a first active layer and a second active layer which are stackedly disposed; wherein the first active layer is orthographically projected on the substrate Covering the source, the drain, and the orthographic projection of the gap between the source and the drain on the substrate, and covering the orthographic projection of the gate on the substrate; the second active layer is at the source and the drain
  • the gap between the gaps and the orthographic projection on the base substrate is in the region where the orthographic projection of the gate on the substrate is located.
  • the region where the second active layer of the thin film transistor is located is blocked by the gate, only the region of the first active layer that is not blocked by the gate can generate photo-generated carriers.
  • the second active layer 132 is located above the first active layer 131 and is connected to the first active layer 131, in particular Electrical connection.
  • the first active layer 131 and the second active layer 132 are still integrated, thereby facilitating the transmission of current.
  • the first active layer 131 and the second active layer 132 are also insulated from each other and electrically connected to the source and the drain, respectively, and are not described herein.
  • the thickness of the second active layer 132 is generally greater than the thickness of the first active layer 131.
  • the first active layer 131 absorbs only a small number of photons under backlight illumination conditions. Since the number of photons absorbed by the amorphous silicon film directly determines the number of photogenerated carriers generated in the film, the number of photogenerated carriers generated is reduced. Therefore, the adverse effect of the backlight on the off-state current of the thin film transistor can be effectively suppressed, that is, the rise of the off-state current is effectively suppressed, and the ratio of the on-state current to the off-state current is further increased.
  • the thickness of the first active layer 131 is 60 nm to 100 nm.
  • the thickness of the first active layer under the source and the drain illuminated by the backlight is very thin, so that the number of photons absorbed under backlight illumination is small, and the generated off current of the photogenerated carrier to the thin film transistor is generated.
  • the impact is much smaller than conventional thin film transistor structures. Assuming that the absorption coefficient ⁇ of the a-Si:H film is 1 ⁇ 10 4 cm -1 , the thickness of the first active layer 131 is 80 nm, and the total film thickness of the active layer in the conventional thin film transistor structure is 300 nm.
  • the thin film transistor provided by the embodiment of the invention can ensure a high ratio of the on-state current to the off-state current, thereby improving the luminescence performance of the thin film transistor and enhancing the image display quality of the display device.
  • the sum of the thicknesses of the first active layer 131 and the second active layer 132 is 100 nm to 500 nm.
  • the sum of the thicknesses of the two layers is close to the total thickness of the active layer in the conventional thin film transistor structure, so that it is ensured that the on-state current of the thin film transistor is not adversely affected.
  • the thin film transistor provided by the embodiment of the present invention may further include: disposed between the first active layer 131 and the source 14 and disposed at the first An ohmic contact layer 16 between the active layer 131 and the drain 15.
  • the embodiment of the present invention further includes: a light shielding layer 17 disposed above the second active layer 132 and insulated from the second active layer 132; and an orthographic projection of the light shielding layer 17 on the substrate substrate 11 The orthographic projection of the two active layers 132 on the base substrate 11.
  • a gate insulating layer 18 disposed between the gate electrode 12 and the active layer 13 may be generally included, and the gate insulating layer 18 may be The gate electrode 12 and the active layer 13 are insulated from each other; and, in general, a passivation layer 19 disposed over the source 14 and the drain 15 may be further included, and the passivation layer 19 may have the light shielding layer 17 and the second active layer 132 are insulated from each other and will not be described here.
  • an embodiment of the present invention further provides an array substrate including the above-mentioned thin film transistor provided by the embodiment of the present invention. Since the principle of solving the problem of the array substrate is similar to that of the foregoing thin film transistor, the implementation of the array substrate can be referred to the implementation of the thin film transistor, and the repeated description is omitted.
  • the above-mentioned array substrate provided by the embodiment of the present invention can be applied to a liquid crystal display panel, and can also be applied to an organic electroluminescence display panel, which is not limited herein.
  • an embodiment of the present invention further provides a display device including the above array substrate provided by the embodiment of the present invention.
  • the display device can be a display, a mobile phone, a television, a notebook, an all-in-one, or the like.
  • Other indispensable components of the display device are understood by those of ordinary skill in the art, and are not described herein, nor should they be construed as limiting the invention.
  • an embodiment of the present invention further provides a method for fabricating the above thin film transistor according to an embodiment of the present invention. Since the principle of solving the problem is similar to the foregoing thin film transistor, the implementation of the method can be referred to the implementation of the thin film transistor, and the repeated description will not be repeated.
  • the method for fabricating the thin film transistor provided by the embodiment of the present invention, as shown in FIG. 3, specifically includes the following steps:
  • a metal material is deposited on the substrate, and the metal material is patterned to form a pattern of the gate.
  • an amorphous silicon material is deposited on the substrate substrate on which the gate is formed, and the amorphous silicon material is patterned to form a pattern of the first active layer.
  • the pattern of forming the second active layer, the source and the drain on the first active layer may be specifically as follows:
  • an amorphous silicon material is deposited on the first active layer, and the amorphous silicon material is patterned, so that the orthographic projection of the amorphous silicon material on the substrate is at the gate on the substrate. a region in which the orthographic projection on the substrate is located, thereby forming a pattern of the second active layer;
  • a metal material is deposited on the second active layer, and the metal material is patterned, so that the orthographic projection of the metal material on the substrate is not included in the orthographic projection of the first active layer on the substrate.
  • the gate is in the area of the orthographic projection on the base substrate, thereby forming a pattern of source and drain connected to the second active layer.
  • a metal material is deposited on the first active layer, and the metal material is patterned to form an orthographic projection of the metal material on the substrate substrate on the substrate of the first active layer.
  • the pattern of the source and the drain is not included in the area of the orthographic projection of the gate on the substrate;
  • an amorphous silicon material is deposited on the source and the drain, and the amorphous silicon material is patterned, so that the orthographic projection of the amorphous silicon material on the substrate is located on the underlying projection of the gate on the substrate. In the region where it is located, thereby forming a pattern of the second active layer connected to the source and the drain.
  • A-SiNx film is sequentially deposited as a gate insulating layer and a-Si:H film as a first active layer on a continuous separation plasma enhanced chemical vapor deposition (PECVD) apparatus. And an n+ type a-Si:H film as an ohmic contact layer.
  • the raw material gas used is hydrogen diluted silane (SiH 4 ), wherein the content of SiH 4 is 10%, and ammonia gas and hydrogen diluted phosphane (PH 3 ), wherein the content of PH 3 is 20%;
  • a second layer of a-Si of a certain thickness is deposited by PECVD using the process parameters of the a-Si:H film grown in Table 1. : H film, and through the photolithography process, forming a second active layer. It should be specially noted that when plasma etching n+ type a-Si:H film and depositing second layer a-Si:H film, certain process measures should be taken to eliminate the interface state between them;
  • an a-SiNx film is further prepared as a passivation layer on the second active layer.
  • a metal chromium film is deposited on the passivation layer and a light shielding layer is formed by a photolithography process.
  • an amorphous silicon-based film is etched by a plasma etching technique using tetrafluoromethane (CF 4 ) gas, and a-Si:H and a- are obtained by controlling substrate temperature, reaction chamber gas pressure, and radio frequency power. Selective etching of SiNx films.
  • Embodiments of the present invention provide a thin film transistor, a method of fabricating the same, an array substrate, and Display device.
  • the active layer in the thin film transistor includes a first active layer and a second active layer disposed in a stacked manner; wherein an orthographic projection of the first active layer on the substrate substrate covers the source and the drain, and is located at the source and the drain An orthographic projection of the gap between the poles on the base substrate and covering the orthographic projection of the gate on the base substrate; the second active layer is located at a gap between the source and the drain, and on the base substrate The orthographic projection is located in the region of the gate where the orthographic projection on the substrate is located.

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Abstract

一种薄膜晶体管及其制作方法、阵列基板及显示装置。薄膜晶体管中的有源层（13）包括层叠设置的第一有源层（131）和第二有源层（132）；其中，第一有源层（131）在衬底基板（11）上的正投影覆盖源极（14）、漏极（15）以及位于源极（14）和漏极（15）之间的间隙在衬底基板（11）上的正投影，且覆盖栅极（12）在衬底基板（11）上的正投影；第二有源层（132）位于源极（14）和漏极（15）之间的间隙处，且在衬底基板（11）上的正投影位于栅极（12）在衬底基板（11）上的正投影所在的区域内。在背光光照条件下，由于薄膜晶体管的第二有源层（132）所在的区域被栅极（12）遮挡，所以只有第一有源层（131）中没有被栅极（12）遮挡的区域可以产生光生载流子。因此，这样的结构产生的光生载流子数目较少，有效抑制了关态电流的上升，从而提高了开态电流与关态电流之比，进一步提升了薄膜晶体管的发光性能，增强了显示器件的图像显示质量。

Description

薄膜晶体管、其制作方法、阵列基板及显示装置
相关申请的引用
本申请要求于2014年10月13日递交的中国专利申请号201410539188.7的优先权，在此引用该中国专利申请所公开的全部内容作为本申请的一部分。
技术领域
本发明涉及显示技术领域，尤指一种薄膜晶体管、其制作方法、阵列基板及显示装置。
背景技术
通常，在显示器件的生产中，薄膜晶体管(Thin-film Transistor，TFT)起到十分重要的作用。主要利用薄膜晶体管的开态对显示器件的像素电容快速充电，利用薄膜晶体管的关态来保持像素电容的电压，从而实现快速响应和良好存储的统一。由于薄膜晶体管具有非常高的开态电流(Ion)与关态电流(Ioff)之比和陡峭的转移特性，因而作为非线性开关元件被广泛地应用于大面积液晶显示器以及接触型图像传感器等领域。
目前，常规的底栅反堆栈型非晶硅薄膜晶体管的具体结构如图1所示，其包括：衬底基板01、设置在衬底基板01上的栅极02、设置在栅极02上且与栅极02绝缘的有源层03、以及相对而置且分别与有源层03电性连接的源极04和漏极05。当通过安装在衬底基板01中的电路将电流施加到栅极02时，加载到源极04的电流通过有源层03传输到漏极05，从而驱动显示器件的像素单元显示图像。在栅极02与有源层03之间设置有栅绝缘层06，在源极04和漏极05之上设置有钝化层07。其中，栅绝缘层06通常采用a-SiNx薄膜，有源层03通常采用a-Si：H薄膜，钝化层07通常采用a-SiNx薄膜，栅极02、源极04和漏极05通常采用金属铬材料。为了改善源极04与a-Si：H薄膜、漏极05与a-Si：H薄膜的接触特性，在其间插入了薄的n+型a-Si：H薄膜以作为欧姆接触层08。
作为薄膜晶体管的有源层的a-Si：H薄膜是一种具有良好光敏特性 的材料。但是在背光光照条件下，有源层自身的电阻阻值会发生改变，从而使薄膜晶体管的关态电流上升2～3个数量级。这样大大减小了薄膜晶体管的开态电流与关态电流之比，严重地影响了液晶显示器的图像显示质量。
因此，如何在背光光照条件下提高薄膜晶体管的开态电流与关态电流之比，是本领域技术人员亟需解决的技术问题。
发明内容
有鉴于此，本发明实施例提供了一种薄膜晶体管、其制作方法、阵列基板及显示装置，由此可以有效抑制关态电流的上升，提高开态电流与关态电流之比，从而提升薄膜晶体管的发光性能。
因此，本发明实施例提供了一种薄膜晶体管，其包括：衬底基板、设置在所述衬底基板上的栅极、设置在所述栅极上且与所述栅极绝缘的有源层、以及相对而置且分别与所述有源层电性连接的源极和漏极；
所述有源层包括层叠设置的第一有源层和第二有源层；其中，
所述第一有源层在所述衬底基板上的正投影覆盖所述源极、漏极以及位于所述源极和漏极之间的间隙在所述衬底基板上的正投影，且覆盖所述栅极在所述衬底基板上的正投影；
所述第二有源层位于所述源极和漏极之间的间隙处，且在衬底基板上的正投影位于所述栅极在所述衬底基板上的正投影所在的区域内。
在一种可能的实现方式中，在本发明实施例提供的上述薄膜晶体管中，所述第二有源层位于所述第一有源层的上方且与所述第一有源层相互连接。特别地，所述第二有源层与所述第一有源层电性连接；或者，所述第二有源层与所述第一有源层相互绝缘，并单独与所述源极、所述漏极电性连接。
在一种可能的实现方式中，本发明实施例提供的上述薄膜晶体管，还包括：设置在所述第一有源层与所述源极之间以及设置在所述第一有源层和所述漏极之间的欧姆接触层。
在一种可能的实现方式中，本发明实施例提供的上述薄膜晶体管，还包括：设置在所述第二有源层的上方且与所述第二有源层相互绝缘的遮光层；
所述遮光层在所述衬底基板上的正投影覆盖所述第二有源层在所述衬底基板上的正投影。
在一种可能的实现方式中，在本发明实施例提供的上述薄膜晶体管中，所述第二有源层的厚度大于所述第一有源层的厚度。
在一种可能的实现方式中，在本发明实施例提供的上述薄膜晶体管中，所述第一有源层的厚度为60nm至100nm。
在一种可能的实现方式中，在本发明实施例提供的上述薄膜晶体管中，所述第一有源层和所述第二有源层的厚度之和为100nm至500nm。
本发明实施例提供了一种阵列基板，包括本发明实施例提供的上述薄膜晶体管。
本发明实施例提供的一种显示装置，包括本发明实施例提供的上述阵列基板。
本发明实施例还提供了一种本发明实施例提供的上述薄膜晶体管的制作方法，包括：
在衬底基板上形成栅极的图形；
在形成有所述栅极的衬底基板上形成第一有源层的图形；
在所述第一有源层上形成第二有源层、源极和漏极的图形。
本发明实施例的有益效果包括：
本发明实施例提供了一种薄膜晶体管、其制作方法、阵列基板及显示装置。薄膜晶体管中的有源层包括层叠设置的第一有源层和第二有源层；其中，第一有源层在衬底基板上的正投影覆盖源极、漏极以及位于源极和漏极之间的间隙在衬底基板上的正投影，且覆盖栅极在衬底基板上的正投影；第二有源层位于源极和漏极之间的间隙处，且在衬底基板上的正投影位于栅极在衬底基板上的正投影所在的区域内。在背光光照条件下，由于薄膜晶体管的第二有源层所在的区域被栅极遮挡，所以只有第一有源层中没有被栅极遮挡的区域可以产生光生载流子。因此，这样的结构产生的光生载流子数目较少，有效抑制了关态电流的上升，从而提高了开态电流与关态电流之比，进一步提升了薄膜晶体管的发光性能，增强了显示器件的图像显示质量。
如本文中所使用的，表述“正投影”是指投影方向垂直于投影平面。由此，表述“A在B上的正投影”是指在垂直于B的方向上将A 投影到B上。
附图说明
图1为现有技术中的底栅反堆栈型薄膜晶体管的结构示意图；
图2为本发明实施例提供的薄膜晶体管的结构示意图；
图3为本发明实施例提供的薄膜晶体管的制作方法的流程图。
具体实施方式
下面结合附图，对本发明实施例提供的薄膜晶体管、其制作方法、阵列基板及显示装置的具体实施方式进行详细地说明。
其中，附图中各膜层的厚度和区域的大小形状不反映薄膜晶体管的各部件的真实比例。附图的目的只是示意说明本发明内容。
本发明实施例提供了一种薄膜晶体管，如图2所示，其包括：衬底基板11、设置在衬底基板上的栅极12、设置在栅极12上且与栅极绝缘的有源层13、以及相对而置且分别与有源层电性连接的源极14和漏极15；
该有源层13包括层叠设置的第一有源层131和第二有源层132；其中，
该第一有源层131在衬底基板11上的正投影覆盖源极14、漏极15以及位于源极14和漏极15之间的间隙在衬底基板11上的正投影，且覆盖栅极12在衬底基板11上的正投影；
该第二有源层132位于源极14和漏极15之间的间隙处，且在衬底基板11上的正投影位于栅极12在衬底基板11上的正投影所在的区域内。
在本发明实施例提供的上述薄膜晶体管中，薄膜晶体管中的有源层包括层叠设置的第一有源层和第二有源层；其中，第一有源层在衬底基板上的正投影覆盖源极、漏极以及位于源极和漏极之间的间隙在衬底基板上的正投影，且覆盖栅极在衬底基板上的正投影；第二有源层位于源极和漏极之间的间隙处，且在衬底基板上的正投影位于栅极在衬底基板上的正投影所在的区域内。在背光光照条件下，由于薄膜晶体管的第二有源层所在的区域被栅极遮挡，所以只有第一有源层中没有被栅极遮挡的区域可以产生光生载流子。因此，这样的结构产生 的光生载流子数目较少，有效抑制了关态电流的上升，从而提高了开态电流与关态电流之比，进一步提升了薄膜晶体管的发光性能，增强了显示器件的图像显示质量。
进一步地，在具体实施时，在本发明实施例提供的上述薄膜晶体管中，该第二有源层132位于第一有源层131的上方且与第一有源层131相互连接，特别地为电性连接。这样，在外部看来，第一有源层131和第二有源层132仍是一个整体，从而有利于电流的传输。另外，第一有源层131和第二有源层132也可相互绝缘，并单独与源极、漏极电性连接，在此不做赘述。
在具体实施时，在本发明实施例提供的上述薄膜晶体管中，第二有源层132的厚度一般大于第一有源层131的厚度。这样，在背光光照条件下，第一有源层131只吸收较少的光子数目。由于被非晶硅薄膜吸收的光子数目直接决定着在膜内产生的光生载流子数目，所以产生的光生载流子的数目减少。因此，能够有效抑制背光照对薄膜晶体管的关态电流的不良影响，即，有效抑制关态电流的上升，进一步提高开态电流与关态电流之比。
在具体实施时，在本发明实施例提供的上述薄膜晶体管中，第一有源层131的厚度为60nm至100nm。这样，受背光光照的源极和漏极下面的第一有源层的膜厚很薄，从而在背光光照条件下吸收的光子数目很少，产生的光生载流子对薄膜晶体管的关态电流的影响远远小于常规薄膜晶体管结构。假设a-Si：H薄膜的吸收系数α为1×104cm-1，则第一有源层131的厚度为80nm，而常规薄膜晶体管结构中的有源层的总膜厚为300nm。计算表明，在相同强度的背光照射下，这样的第一层有源层中产生的光生载流子数目只有常规薄膜晶体管结构的百分之三十。因此，本发明实施例提供的上述薄膜晶体管可以保证高的开态电流与关态电流之比，从而提升薄膜晶体管的发光性能，增强显示器件的图像显示质量。
在具体实施时，在本发明实施例提供的上述薄膜晶体管中，第一有源层131和第二有源层132的厚度之和为100nm至500nm。这两层的厚度之和与常规薄膜晶体管结构中的有源层的总厚度接近，从而可以保证不对薄膜晶体管的开态电流造成不良影响。
一般地，在具体实施时，为了改善源极14与有源层13、漏极15 与有源层13的接触特性，具体地，如图2所示，本发明实施例提供的上述薄膜晶体管还可以包括：设置在第一有源层131与源极14之间以及设置在第一有源层131与漏极15之间的欧姆接触层16。
在具体实施时，由于薄膜晶体管的电性能易受光影响，所以为了防止外部光线对薄膜晶体管的第二有源层产生影响，避免造成关态电流的上升，如图2所示，本发明实施例提供的上述薄膜晶体管还包括：设置在第二有源层132的上方且与第二有源层132相互绝缘的遮光层17；并且，该遮光层17在衬底基板11上的正投影覆盖第二有源层132在衬底基板11上的正投影。
具体地，在本发明实施例提供的上述薄膜晶体管中，如图2所示，一般还可以包括设置在栅极12与有源层13之间的栅绝缘层18，该栅绝缘层18可以使栅极12与有源层13相互绝缘；并且，一般还可以包括设置在源极14和漏极15之上的钝化层19，该钝化层19可以使遮光层17与第二有源层132相互绝缘，在此不再赘述。
基于同一发明构思，本发明实施例还提供了一种阵列基板，其包括本发明实施例提供的上述薄膜晶体管。由于该阵列基板解决问题的原理与前述薄膜晶体管相似，因此该阵列基板的实施可以参见薄膜晶体管的实施，重复之处不再赘述。
在具体实施时，本发明实施例提供的上述阵列基板可以应用于液晶显示面板，也可以应用于有机电致发光显示面板，在此不做限定。
基于同一发明构思，本发明实施例还提供了一种显示装置，其包括本发明实施例提供的上述阵列基板。该显示装置可以是显示器、手机、电视、笔记本、一体机等。显示装置的其它必不可少的组成部分均为本领域普通技术人员应该理解到的，在此不做赘述，也不应将其作为对本发明的限制。
基于同一发明构思，本发明实施例还提供了一种本发明实施例提供的上述薄膜晶体管的制作方法。由于该方法解决问题的原理与前述薄膜晶体管相似，因此该方法的实施可以参见薄膜晶体管的实施，重复之处不再赘述。
在具体实施时，本发明实施例提供的薄膜晶体管的制作方法，如图3所示，具体包括以下步骤：
S101、在衬底基板上形成栅极的图形；
在具体实施时，在衬底基板上沉积一层金属材料，对金属材料进行构图工艺，从而形成栅极的图形。
S102、在形成有栅极的衬底基板上形成第一有源层的图形；
在具体实施时，在形成有栅极的衬底基板上沉积一层非晶硅材料，对非晶硅材料进行构图工艺，从而形成第一有源层的图形。
S103、在第一有源层上形成第二有源层、源极和漏极的图形。
在具体实施时，在第一有源层上形成第二有源层、源极和漏极的图形具体可以采用如下方式：
在具体实施时，首先，在第一有源层上沉积一层非晶硅材料，对非晶硅材料进行构图工艺，使非晶硅材料在衬底基板上的正投影位于栅极在衬底基板上的正投影所在的区域内，从而形成第二有源层的图形；
然后，在第二有源层上沉积一层金属材料，对金属材料进行构图工艺，使金属材料在衬底基板上的正投影位于第一有源层在衬底基板上的正投影中不包括栅极在衬底基板上的正投影的区域内，从而形成与第二有源层相连接的源极和漏极的图形。
或者是，首先，在第一有源层上沉积一层金属材料，对金属材料进行构图工艺，使金属材料在衬底基板上的正投影位于第一有源层在衬底基板上的正投影中不包括栅极在衬底基板上的正投影的区域内，从而形成源极和漏极的图形；
然后，在源极和漏极上沉积一层非晶硅材料，对非晶硅材料进行构图工艺，使非晶硅材料在衬底基板上的正投影位于栅极在衬底基板上的正投影所在的区域内，从而形成与源极和漏极相连接的第二有源层的图形。
下面以一个具体实例详细说明本发明实施例提供的薄膜晶体管的制作方法，该方法具体步骤如下：
1、在洁净的平板玻璃上沉积一层金属铬膜，并通过光刻工艺，形成栅极的图形；
2、在连续式分离的多反应室等离子体增强化学气相沉积(Plasma Enhanced Chemical Vapor Depositio，PECVD)设备上依次沉积a-SiNx薄膜作为栅绝缘层、a-Si：H薄膜作为第一有源层和n+型a-Si：H薄膜作为欧姆接触层。在制备过程中，所用原料气体为氢气稀释的硅烷(SiH4)， 其中SiH4的含量为10％，以及氨气和氢气稀释的磷烷(PH3)，其中PH3的含量为20％；
下表1中列出了制备非晶硅基薄膜的工艺参数。
表1
Figure PCTCN2015074270-appb-000001
3、在通过光刻工艺形成一层n+型a-Si：H薄膜之后，再沉积一层金属铬膜，并通过光刻工艺，形成源极和漏极；
4、在将源、漏极间的n+型a-Si：H薄膜刻蚀之后，再用PECVD法以表1中生长a-Si：H薄膜的工艺参数沉积一定厚度的第二层a-Si：H薄膜，并通过光刻工艺，形成第二有源层。应特别注意的是，在等离子体刻蚀n+型a-Si：H薄膜和沉积第二层a-Si：H薄膜时，应采用一定的工艺措施消除其间的界面态；
5、为消除正面光照对TFT性能的影响，在第二有源层上再制备a-SiNx薄膜作为钝化层。在钝化层上再沉积金属铬膜，并通过光刻工艺，形成遮光层。在制备过程中，采用四氟甲烷(CF4)气体的等离子体刻蚀技术刻蚀非晶硅基薄膜，并且通过控制衬底温度、反应室气压和射频功率获得a-Si：H与a-SiNx薄膜的选择性刻蚀。其中，非晶硅薄膜晶体管的导电沟道的宽度W与长度L之比为W∶L＝100∶10，这样可以保证较高的开态电流。
至此，经过实例提供的上述步骤1至5制作出了本发明实施例提供的上述薄膜晶体管。
本发明实施例提供了一种薄膜晶体管、其制作方法、阵列基板及 显示装置。薄膜晶体管中的有源层包括层叠设置的第一有源层和第二有源层；其中，第一有源层在衬底基板上的正投影覆盖源极、漏极以及位于源极和漏极之间的间隙在衬底基板上的正投影，且覆盖栅极在衬底基板上的正投影；第二有源层位于源极和漏极之间的间隙处，且在衬底基板上的正投影位于栅极在衬底基板上的正投影所在的区域内。在背光光照条件下，由于薄膜晶体管的第二有源层所在的区域被栅极遮挡，所以只有第一有源层中没有被栅极遮挡的区域可以产生光生载流子。因此，这样的结构产生的光生载流子数目较少，有效抑制了关态电流的上升，从而提高了开态电流与关态电流之比，进一步提升了薄膜晶体管的发光性能，增强了显示器件的图像显示质量。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (12)

  1. 一种薄膜晶体管，包括衬底基板、设置在所述衬底基板上的栅极、设置在所述栅极上且与所述栅极绝缘的有源层、以及相对而置且分别与所述有源层电性连接的源极和漏极，其中：
    所述有源层包括层叠设置的第一有源层和第二有源层；并且其中，
    所述第一有源层在所述衬底基板上的正投影覆盖所述源极、漏极以及位于所述源极和漏极之间的间隙在所述衬底基板上的正投影，且覆盖所述栅极在所述衬底基板上的正投影；
    所述第二有源层位于所述源极和漏极之间的间隙处，且在所述衬底基板上的正投影位于所述栅极在所述衬底基板上的正投影所在的区域内。
  2. 如权利要求1所述的薄膜晶体管，其中，所述第二有源层位于所述第一有源层的上方且与所述第一有源层相互连接。
  3. 如权利要求2所述的薄膜晶体管，其中，所述第二有源层与所述第一有源层电性连接。
  4. 如权利要求2所述的薄膜晶体管，其中，所述第二有源与所述第一有源层相互绝缘，并且单独与所述源极、漏极电性连接。
  5. 如权利要求1所述的薄膜晶体管，还包括：设置在所述第一有源层与所述源极之间以及设置在所述第一有源层与所述漏极之间的欧姆接触层。
  6. 如权利要求1所述的薄膜晶体管，还包括：设置在所述第二有源层的上方且与所述第二有源层相互绝缘的遮光层；
    所述遮光层在所述衬底基板上的正投影覆盖所述第二有源层在所述衬底基板上的正投影。
  7. 如权利要求1-6中任一项所述的薄膜晶体管，其中，所述第二有源层的厚度大于所述第一有源层的厚度。
  8. 如权利要求7所述的薄膜晶体管，其中，所述第一有源层的厚度为60nm至100nm。
  9. 如权利要求8所述的薄膜晶体管，其中，所述第一有源层和所述第二有源层的厚度之和为100nm至500nm。
  10. 一种阵列基板，包括如权利要求1-9中任一项所述的薄膜晶体 管。
  11. 一种显示装置，包括如权利要求10所述的阵列基板。
  12. 一种如权利要求1-9中任一项所述的薄膜晶体管的制作方法，包括：
    在衬底基板上形成栅极的图形；
    在形成有所述栅极的衬底基板上形成第一有源层的图形；
    在所述第一有源层上形成第二有源层、源极和漏极的图形。
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