WO2016169388A1 - 像素电路及其驱动方法和显示装置 - Google Patents

像素电路及其驱动方法和显示装置 Download PDF

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Publication number
WO2016169388A1
WO2016169388A1 PCT/CN2016/077393 CN2016077393W WO2016169388A1 WO 2016169388 A1 WO2016169388 A1 WO 2016169388A1 CN 2016077393 W CN2016077393 W CN 2016077393W WO 2016169388 A1 WO2016169388 A1 WO 2016169388A1
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Prior art keywords
transistor
node
level
pixel circuit
data
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PCT/CN2016/077393
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English (en)
French (fr)
Inventor
张盛东
孟雪
冷传利
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北京大学深圳研究生院
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Priority to US15/569,027 priority Critical patent/US10679554B2/en
Publication of WO2016169388A1 publication Critical patent/WO2016169388A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8051—Anodes
    • H10K59/80518—Reflective anodes, e.g. ITO combined with thick metallic layers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits

Definitions

  • the present invention relates to the field of display devices, and in particular, to a pixel circuit, a driving method thereof, and a display device.
  • OLED Organic Light-Emitting Diode
  • PMOLED passive matrix OLED
  • AMOLED active matrix OLED
  • the passive matrix drive is low in cost, the crosstalk phenomenon cannot achieve high-resolution display, and the passive matrix drive current is large, which reduces the service life of the OLED.
  • the active matrix OLED driving method has a different number of transistors as current sources on each pixel, avoiding crosstalk, requiring less driving current, lower power consumption, and increasing the lifetime of the OLED. Achieve high resolution display.
  • the pixel circuit of the conventional AMOLED is a simple two-film Thin Film Transistor (TFT) structure.
  • TFT Thin Film Transistor
  • this structure is simple, it cannot compensate for the threshold voltage drift of the driving transistor T1 and the OLED or is made of a polycrystalline material for the TFT device. This results in threshold voltage non-uniformity of the TFT devices throughout the panel.
  • the threshold voltage of the driving transistor T1 the threshold voltage of the OLED drifts, or the values across the panel are inconsistent, the driving current I DS changes, and different pixels on the panel drift differently due to different bias voltages. This will cause unevenness in the display of the panel.
  • the driving method of the pixel circuit is mainly divided into two types, one is a driving mode for progressive scanning illumination, and the other is a driving method for collectively compensating for common illumination.
  • each row of pixel circuits is sequentially driven in one frame time, as shown in FIG. 1, the driving process of each row includes initialization, threshold compensation, programming, and illumination stages, when each The pixels of one row enter the illumination phase immediately after programming, and the initialization and threshold compensation phases are referred to herein as the compensation phase.
  • the compensation phase As a whole, one part is used for compensation, one part is used for illumination, and the whole frame is used for one frame. Time is used to illuminate.
  • the pixel compensation and programming time per line is short, and the illumination time is long, but each row of pixel circuits requires an independent control line, and the gate driving circuit is relatively complicated.
  • each line of driving in one frame time The process includes initialization, threshold compensation, programming and illumination. Unlike traditional progressive scan illumination, all pixels are compensated together, and then each row of pixels is programmed sequentially, waiting for all rows of pixels to complete programming and then illuminate together.
  • the initialization and threshold compensation phases are referred to herein as the compensation phase.
  • the compensation phase As a whole, one part is used for compensation, one part is used for illumination, and the illumination time is short in one frame time.
  • the control lines of all the pixel circuits on the panel are shared (that is, the global control lines are used), but since there is a large amount of waiting idle time in each row in the programming phase, the overall programming time is longer and the illumination time is longer. short.
  • the present application provides a pixel circuit, a driving method thereof and a display device, which compensate for threshold voltage drift of a driving transistor and a light emitting element, thereby achieving more uniform light emission while reducing circuit complexity.
  • an embodiment provides a pixel circuit, including:
  • a driving transistor and a light emitting element connected in series between the first level end and the second level end, and a second transistor, a third transistor, a fourth transistor, a first capacitor and a second capacitor; a first pole connection of the driving transistor
  • the second pole of the third transistor forms a first node; the second pole of the driving transistor is connected to the first end of the light emitting element; the control pole of the driving transistor is connected to one end of the first capacitor to form a second node; a second pole connected to the fourth transistor at one end forms a third node; a control pole of the third transistor is used for inputting the illumination control signal; and a first pole of the third transistor and a second end of the light emitting component are respectively connected to the first electrical a flat end and a second level terminal; a first electrode of the second transistor is connected to the first node, a second electrode of the second transistor is connected to the second node, a control electrode of the second transistor is used for inputting the first control signal;
  • the first pole is for connecting to
  • an embodiment provides a display device, including:
  • a pixel circuit matrix comprising the above pixel circuits arranged in a matrix of n rows and m columns, wherein n and m are integers greater than 0; a gate driving circuit for generating a scan pulse signal and passing along the first Each row of scan lines formed by the direction supplies a desired scan signal to the pixel circuit; the data drive circuit is configured to generate a data voltage signal representative of the gray scale information, and provide a data signal to the pixel circuit through each of the data lines formed along the second direction; a first control line for simultaneously providing a first control signal to each pixel circuit in the matrix of the pixel circuit; an illumination control line, And a controller for simultaneously providing illumination control signals to each pixel circuit in the pixel circuit matrix; and a controller for providing control timing to the gate driving circuit, the data driving circuit, and the first control line and the illumination control line.
  • an embodiment provides a pixel circuit driving method, each driving cycle includes a dark data writing phase, an initialization and a threshold compensation phase, and an illumination phase, and the driving method includes:
  • the fourth transistor transmits a dark data voltage to the third node in response to the effective level of the scan signal, and controls the light emitting element to be in a non-lighting state; in the initialization and threshold compensation phase, the third node receives the reference power.
  • the second node adjusts the potential according to the threshold voltage of the driving transistor and the light emitting element, and stores the potential through the first capacitor; in the light emitting phase, the third transistor is turned on in response to the effective level of the light emitting control signal,
  • the fourth transistor is responsive to the active level of the scan signal to conduct the illuminating data voltage to the third node and is capacitively coupled to the second node;
  • the driving transistor is responsive to the potential conduction of the second node to drive the illuminating element to emit light.
  • the potential of the driving transistor control electrode is adjusted by the connection mode of the driving transistor by using the diode, thereby reading the threshold voltage of the driving transistor and the light emitting element, and maintaining the potential of the driving transistor control electrode with the second capacitance, and storing
  • the first capacitor enables compensation of the threshold voltage of the driving transistor, which in turn compensates for the non-uniformity of the display of the pixel circuit.
  • the pixel circuit has a simple structure and requires less control lines.
  • the first control line and the illumination control line are global lines, which reduces the complexity of the pixel circuit driving and also reduces the cost.
  • FIG. 1 is a schematic diagram of a progressive scan illumination driving method in the prior art
  • FIG. 2 is a schematic diagram of a centralized compensation common light driving mode in the prior art
  • FIG. 3a is a structural diagram of a pixel circuit disclosed in Embodiment 1;
  • FIG. 3a is a structural diagram of a pixel circuit disclosed in Embodiment 1;
  • FIG. 3b is a structural diagram of another pixel circuit disclosed in Embodiment 1; FIG.
  • 4a is a timing diagram of an operation of a pixel circuit disclosed in an embodiment
  • FIG. 4b is a timing diagram of an operation of a pixel circuit disclosed in another embodiment
  • FIG. 5a is a structural diagram of a pixel circuit disclosed in Embodiment 2; FIG.
  • FIG. 5b is a structural diagram of another pixel circuit disclosed in Embodiment 2; FIG.
  • FIG. 5c is a timing diagram of an operation of a pixel circuit disclosed in Embodiment 2; FIG.
  • FIG. 5d is a timing diagram of an operation of another pixel circuit disclosed in Embodiment 2; FIG.
  • FIG. 6a is a structural diagram of a pixel circuit disclosed in Embodiment 3.
  • FIG. 6b is a structural diagram of another pixel circuit disclosed in Embodiment 3.
  • FIG. 7 is a schematic structural diagram of a display device disclosed in Embodiment 4.
  • the transistor in the present application may be a transistor of any structure, such as a bipolar transistor (BJT) or a field effect transistor (FET).
  • BJT bipolar transistor
  • FET field effect transistor
  • the gate of the transistor is the base of the bipolar transistor
  • the first pole can be the collector or emitter of the bipolar transistor
  • the corresponding second pole can be a bipolar transistor.
  • Emitter or collector in the actual application process, “emitter” and “collector” can be interchanged according to signal flow direction;
  • the transistor is a field effect transistor, its control electrode refers to the gate of the field effect transistor,
  • One pole can be the drain or source of the field effect transistor, and the corresponding second pole can be the source or drain of the field effect transistor.
  • the transistor in the display is typically a field effect transistor: a thin film transistor (TFT).
  • TFT thin film transistor
  • the present application will be described in detail by taking a transistor as a field effect transistor.
  • the transistor may also be a bipolar transistor.
  • the light-emitting element is an Organic Light-Emitting Diode (OLED). In other embodiments, other light-emitting elements may also be used.
  • the first end of the illuminating element can be a cathode or an anode, and correspondingly, the second end of the illuminating element is an anode or a cathode. It will be understood by those skilled in the art that the current should flow from the anode of the light-emitting element to the cathode, and therefore, based on the flow direction of the current, the anode and cathode of the light-emitting element can be determined.
  • the effective level can be either a high level or a low level, which can be adaptively replaced according to the function of the specific component.
  • the first level terminal and the second level terminal are both ends of the power supply provided for the operation of the pixel circuit.
  • the first level terminal may be a high level terminal V DD and the second level terminal may be a low level terminal V SS or a ground line, and in other embodiments, may be adaptively replaced.
  • the first level terminal eg, the high level terminal V DD
  • the second level terminal eg, the low level terminal V SS
  • the first level terminal eg, the high level terminal V DD
  • the second level terminal eg, the low level terminal V SS
  • the third node C identifies the relevant part of the circuit structure and cannot be identified as an additional terminal introduced in the circuit.
  • V H the high level
  • V L the low level
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • a structure diagram of a pixel circuit disclosed in the embodiment includes: a driving transistor T1 and a light emitting element OLED connected in series between a first level terminal VDD and a second level terminal VSS, and The second transistor T2, the third transistor T3, the fourth transistor T4, the first capacitor C1, and the second capacitor C2.
  • each transistor (the driving transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4) is an N-type thin film transistor; in the pixel circuit shown in FIG. 3b, each transistor (The driving transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4) are P-type thin film transistors.
  • the first pole of the driving transistor T1 is connected to the second pole of the third transistor T3 to form the first node A; the second pole of the driving transistor T1 is connected to the first end of the light emitting element OLED; the control pole of the driving transistor T1 is connected to the first One end of the capacitor C1 forms a second node B; the other end of the first capacitor C1 is connected to the second pole of the fourth transistor T4 to form a third node C.
  • the control electrode of the third transistor T3 is used to input the light emission control signal V EM ; the first electrode of the third transistor T3 and the second end of the light emitting element OLED are used to be connected to the first level terminal VDD and the second level terminal VSS, respectively.
  • the first end of the light emitting element OLED is an anode
  • the second end of the light emitting element OLED is a cathode
  • the first pole of the third transistor T3 is used to be connected to the first level terminal VDD.
  • the second end of the light emitting element OLED is connected to the second level terminal VSS.
  • the first end of the light emitting element OLED is a cathode, and the second end of the light emitting element OLED is an anode.
  • the first terminal of the third transistor T3 is for connection to the second level terminal VSS, and the second terminal of the light emitting element OLED is for connection to the first level terminal VDD.
  • the first pole of the second transistor T2 is connected to the first node A, the second pole of the second transistor T2 is connected to the second node B, and the gate of the second transistor T2 is used to input the first control signal V CM .
  • the first pole of the fourth transistor T4 is for connection to the data line Data.
  • the data line Data is used to provide a data signal, or is also used to provide a reference level Vref , in other embodiments, fourth The reference level V ref input to transistor T4 can also be provided in other ways.
  • the gate of the fourth transistor T4 is used to input the scan signal VScan .
  • the data signal includes: a dark data voltage and a light-emitting data voltage V Data , the dark data voltage is a potential capable of causing the light-emitting element OLED not to emit light, and the light-emitting data voltage V Data is a potential for driving the light-emitting element OLED to emit light, please refer to 3a, when the driving transistor T1 is an N-type transistor, the dark data level is low; referring to FIG. 3b, when the driving transistor T1 is a P-type transistor, the dark data level is high.
  • the second capacitor C2 is connected between the control electrode of the driving transistor T1 and the second end of the light emitting element OLED.
  • the second capacitor C2 is connected to the control electrode of the driving transistor T1 by a direct connection.
  • the connection may also be made by indirect connection, for example, the end of the second capacitor C2 is connected to the third node C.
  • the pixel circuits operate in a first phase, a second phase, and a third phase in sequence.
  • the first phase may be a dark data writing phase
  • the second phase may include an initialization and a threshold compensation phase
  • the third phase is an illumination phase.
  • FIG. 4a and FIG. 4b respectively correspond to the working timing diagrams of the pixel circuits shown in FIG. 3a and FIG. 3b of the present embodiment.
  • the working process of the pixel circuit of the present embodiment will be described below with reference to FIG. 3a and FIG. 4a.
  • each transistor is a P-type transistor, for example, in the circuit shown in FIG. 3b, the high and low states of the respective control signals are inverted from the signal state of the circuit shown in FIG. 3a, in the following, if not In particular, this principle is followed.
  • the light-emission control signal V EM is at an active level (for example, a high level)
  • the scan signal V Scan is at an active level (for example, a high level).
  • the first control signal V CM is at a low level.
  • the second transistor T2 is controlled to be in an off state by the first control signal V CM
  • the third transistor T3 is turned on in response to the active level of the light emission control signal V EM and is in an on state
  • the fourth transistor T4 is responsive to the scan signal V Scan The effective level is turned on.
  • the dark data voltage is transmitted on the data line Data
  • the dark data voltage is transmitted to the third node C through the turned-on fourth transistor T4, thereby causing the light emitting element OLED of the pixel circuit. is closed.
  • the effective levels of the scan signals VScan corresponding to each row of pixel circuits may come in sequence (V Scan [1], V Scan [2] as shown in FIG. 4).
  • V Scan [n] represents the scanning signal of the pixel circuit of the nth row, so that each row of pixels is sequentially written with dark data, so that the light-emitting elements of each row of pixels are sequentially turned off until The last row of pixels completes the writing of dark data, all of the light-emitting elements are turned off, and the pixel circuits of each row are guaranteed to have the same illumination time.
  • the initialization and threshold compensation phases as indicated by (2) in Figure 4a, first come to the initialization phase and then to the threshold compensation phase.
  • the illumination control signal V EM is maintained at an active level (eg, a high level), the first control signal V CM becomes an active level (eg, a high level), and the scan signal V Scan is at an active level (eg, high) Level), at this time, the data line transmits the reference level V ref ; then, the third transistor T3 is in an on state corresponding to the active level (eg, high level) of the light emission control signal V EM , the fourth transistor T4 In response to the active level (eg, high level) of the scan signal VScan being in an on state, the second transistor T2 is in an on state in response to an active level (eg, a high level) of the first control signal V CM ; thus, the data line
  • the effective levels of the scan signals V Scan corresponding to each row of pixel circuits can come simultaneously, and each pixel circuit simultaneously completes the initialization process.
  • the initialization potentials of the first node A and the second node B are provided by the potential of the second level terminal VSS (such as the low level V L ).
  • the first control signal V CM remains at an active level (eg, a high level)
  • the scan signal V Scan remains at an active level (eg, a high level)
  • the illumination control signal V EM becomes a low level.
  • the data line is still transmitted as the reference level V ref ; then, the third transistor T3 is controlled to be in an off state by the light emission control signal V EM , and the fourth transistor T4 is kept in an on state, and thus the potential of the third node C Maintaining as V ref ; the first node A and the second node B are connected by the turned-on second transistor T2.
  • the driving transistor T1 forms a diode connection form, and the potentials of the first node A and the second node B pass through the diode.
  • the potentials of the first node A and the second node B are charged to the driving transistor T1 by the potential provided by the first level terminal VDD to complete the driving transistor T1.
  • a process of threshold voltage compensation of the light-emitting element OLED it should be noted that, in a preferred embodiment, when there are multiple rows of pixel circuits, the effective levels of the scan signals V Scan corresponding to each row of pixel circuits may arrive at the same time, and each pixel circuit simultaneously completes the threshold compensation process.
  • the scanning signal V Scan is maintained at an active level (eg, a high level)
  • the first control signal V CM becomes a low level
  • the illumination control signal V EM becomes an active level (for example, a high level).
  • the data line is transmitted as the light-emitting data voltage V Data ; then, the third transistor T3 and the fourth transistor T4 are in an on state, and the light-emitting data on the data line
  • the voltage V Data is transmitted to the third node C through the turned-on fourth transistor T4, so that the potential of the third node C changes from V ref to V Data , under the coupling of the first capacitor C1 and the second capacitor C2,
  • the potential of the two-node B becomes
  • the third transistor T3 is turned on in response to the effective level of the light-emission control signal V EM , and the driving transistor T1 is driven to emit light in response to the potential of the second node B to drive the light-emitting element OLED, and the current flowing through the light-emitting element OLED is:
  • ⁇ n , C ox , W, and L are the effective mobility, the gate capacitance per unit area, the channel width, and the channel length of the driving transistor T1, respectively. It can be seen from the formula (1-1) that the current flowing through the light-emitting element OLED is independent of the threshold voltage of the driving transistor T1 and the threshold voltage of the OLED itself, so that the pixel circuit in this embodiment can compensate the display well. Inhomogeneity.
  • the pixel circuit in this embodiment can not only compensate for the drift of the threshold voltage of the driving transistor, but also compensate for the drift of the threshold voltage of the OLED.
  • the voltage driving method based on the independent compensation frame combines the advantages of the progressive scanning and the centralized compensation common light driving mode, thereby effectively reducing the complexity of the peripheral gate driving circuit and reducing the cost. The lighting time is greatly increased, and the programming speed and panel resolution of the pixel circuit are improved.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • a structure of a pixel circuit disclosed in the embodiment is different from the above embodiment.
  • the pixel circuit disclosed in this embodiment further includes: a fifth transistor T5, to the third node C.
  • the supplied reference level V ref is transmitted by the fifth transistor T5.
  • the first pole of the fifth transistor T5 is for inputting the reference level V ref
  • the second pole of the fifth transistor T5 is connected to the third node C
  • the gate of the fifth transistor T5 is for inputting the first control signal V CM .
  • each transistor is an N-type transistor, and the effective level of each transistor is turned on, the dark data voltage is low, and the first node A and the second node B are
  • the initialization potential is provided by the first level terminal VDD; in another embodiment, referring to FIG. 5b, each transistor is a P-type transistor, and the effective level of each transistor is turned on, and the dark data voltage is high.
  • the initialization potentials of the first node A and the second node B are provided by the second level terminal VSS.
  • FIG. 5c is a working timing diagram of the pixel circuit shown in FIG. 5a
  • FIG. 5d is a working timing diagram of the pixel circuit shown in FIG. 5b.
  • the driving process of the disclosed pixel circuit is substantially the same as that of the above embodiment, except that in the second stage, in the second stage, when the first control signal V CM is at an active level, the fifth transistor T5 responds to the first control.
  • the active level of signal V CM conducts a reference level V ref to third node C to initialize the third node C potential.
  • the fourth transistor T4 should be scanned by the signal V Scan is controlled in an off state to prevent the fourth transistor T4 from transmitting undesired signal interference to the third node C at this stage. Accordingly, in one embodiment, when the fourth transistor T4 is an N-type transistor, The phase scan signal V Scan should be low; in another embodiment, when the fourth transistor T4 is a P-type transistor, the scan signal V Scan should be at a high level at this stage.
  • the other stages of the pixel circuit driving process disclosed in this embodiment are the same as those in the above embodiment, and are not described herein again.
  • the present embodiment needs to separately configure a data transmission line for the fifth transistor T5 to provide the reference level V ref , but the timing control of the data line Data can be simplified. There is no need to frequently change the signal transmitted by the data line Data, which is more conducive to the timing control of the controller.
  • Embodiment 3 is a diagrammatic representation of Embodiment 3
  • FIG. 6a and FIG. 6b a schematic diagram of a structure of a pixel circuit disclosed in the embodiment is shown.
  • one end of the second capacitor C2 is directly connected to the control electrode of the driving transistor T1.
  • the second The capacitor C2 is connected to the control electrode of the driving transistor T1 by an indirect connection, and the second capacitor C2 is connected to the third node C at the end connected to the control electrode of the driving transistor T1, and the second capacitor is realized by the coupling of the first capacitor C1.
  • This end of C2 is electrically connected to the control electrode of the driving transistor T1.
  • the connection manners of other components are the same as those in the foregoing embodiment, and details are not described herein again.
  • each of the transistors (the driving transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4) is an N-type thin film transistor; in the pixel circuit shown in FIG. 6b, each transistor (driving) The transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4) are P-type thin film transistors.
  • FIG. 4a and FIG. 4b are operation timing diagrams of the pixel circuits shown in FIG. 6a and FIG. 6b respectively.
  • the working process of the pixel circuit of the present embodiment will be described below with reference to FIG. 6a and FIG. 4a.
  • each transistor is a P-type transistor, for example, in the circuit shown in FIG. 6b, the high and low states of the respective control signals are inverted from the signal state of the circuit shown in FIG. 6a, in the following, if not In particular, this principle is followed.
  • the illumination control signal V EM is at an active level (eg, a high level)
  • the scan signal V Scan is at an active level (eg, a high level)
  • the first control signal V CM is at a low level.
  • the second transistor T2 is controlled to be in an off state by the first control signal V CM
  • the third transistor T3 is turned on in response to the active level of the light emission control signal V EM and is in an on state
  • the fourth transistor T4 is responsive to the scan signal V Scan The active level is turned on.
  • the dark data voltage is transmitted on the data line Data
  • the dark data voltage is transmitted to the third node C through the turned-on fourth transistor T4, and is coupled to the second node through the capacitor.
  • the effective levels of the scan signals V Scan corresponding to each row of pixel circuits may also arrive sequentially, so that each row of pixels is sequentially written with dark data, thereby The light-emitting elements of each row of pixels are sequentially turned off until the last row of pixels completes the writing of dark data, all of the light-emitting elements are turned off, and the pixel circuits of each row are guaranteed to have the same light-emitting time.
  • the illumination control signal V EM is maintained at an active level (eg, a high level), the first control signal V CM becomes an active level (eg, a high level), and the scan signal V Scan is at an active level (eg, high) Level), at this time, the data line transmits the reference level V ref ; then, the third transistor T3 is in an on state corresponding to the active level (eg, high level) of the light emission control signal V EM , the fourth transistor T4 In response to the active level (eg, high level) of the scan signal VScan being in an on state, the second transistor T2 is in an on state in response to an active level (eg, a high level) of the first control signal V CM ; thus, the data line
  • the effective levels of the scan signals V Scan corresponding to each row of pixel circuits can come simultaneously, and each pixel circuit simultaneously completes the initialization process.
  • the initialization potentials of the first node A and the second node B are provided by the potential of the second level terminal VSS (such as the low level V L ).
  • the first control signal V CM remains at an active level (eg, a high level)
  • the scan signal V Scan remains at an active level (eg, a high level)
  • the illumination control signal V EM becomes a low level.
  • the data line is still transmitted as the reference level V ref ; then, the third transistor T3 is controlled to be in an off state by the light emission control signal V EM , and the fourth transistor T4 is kept in an on state, and thus the potential of the third node C Maintaining as V ref ; the first node A and the second node B are connected by the turned-on second transistor T2.
  • the driving transistor T1 forms a diode connection form, and the potentials of the first node A and the second node B pass through the diode.
  • V C1 is the voltage difference across the first capacitive element C1.
  • the potentials of the first node A and the second node B are charged to the driving transistor T1 by the potential provided by the first level terminal VDD to complete the driving transistor T1.
  • a process of threshold voltage compensation of the light-emitting element OLED may arrive at the same time, and each pixel circuit simultaneously completes the threshold compensation process.
  • the scan signal V Scan is maintained at an active level (eg, a high level), the first control signal V CM becomes a low level, and the light emission control signal V EM becomes an active level (eg, a high level),
  • the data line transmits the illuminating data voltage V Data ; then, the third transistor T3 and the fourth transistor T4 are in an on state, and the illuminating data voltage V Data on the data line is transmitted to the fourth transistor T4 that is turned on.
  • the potential of the third node C changes from V ref to V Data , and under the coupling of the first capacitor C1, the potential of the second node B becomes V OLED +V TH -V ref +V Data ,
  • the driving transistor T1 drives the light emitting element OLED to emit light in response to the potential conduction of the second node B.
  • the current flowing through the light emitting element OLED is:
  • ⁇ n , C ox , W, and L are the effective mobility, the gate capacitance per unit area, the channel width, and the channel length of the driving transistor T1, respectively. It can be seen from the equation (3-1) that the current flowing through the light-emitting element OLED is independent of the threshold voltage of the driving transistor T1 and the threshold voltage of the OLED itself, so that the pixel circuit in this embodiment can compensate the display well. Inhomogeneity.
  • the fifth transistor T5 is not shown. In an alternative embodiment, the fifth transistor T5 may also be used to transmit the reference level V ref .
  • the fourth transistor T4 when the fifth transistor T5 transmits the reference level V ref , the fourth transistor T4 should also be controlled in the off state by the scan signal V Scan , as described in the above embodiment. This will not be repeated here.
  • each driving cycle of the pixel circuit includes a dark data writing phase, an initialization, and a threshold.
  • the value compensation phase and the illumination phase, the driving methods include:
  • the fourth transistor T4 transmits a dark data voltage to the third node C in response to the effective level of the scan signal VScan , and controls the light emitting element OLED in a non-lighting state;
  • the third node C receives the reference level V ref to initialize the third node C potential; the second node B adjusts the potential according to the threshold voltages of the driving transistor T1 and the light emitting element OLED and stores the potential through the first capacitor C1 Potential
  • the fourth transistor T4 transmits the illuminating data voltage V Data to the third node C in response to the effective level of the scan signal V Scan , and is capacitively coupled to the second node B; the third transistor T3 responds to the illuminating control signal V The effective level of the EM is turned on, and the driving transistor T1 drives the light emitting element OLED to emit light in response to the potential conduction of the second node B.
  • Embodiment 4 is a diagrammatic representation of Embodiment 4:
  • the embodiment also discloses a display device.
  • a schematic structural diagram of a display device is also disclosed.
  • the display device includes:
  • the display panel 100 includes the pixel circuits Pixel[1][1]...Pixel[n][m] provided by the above embodiments arranged in a matrix of n rows and m columns, where n and m are integers greater than 0.
  • Pixel[n][m] represents a pixel circuit of the nth row and m columns; a plurality of scan lines Gate[1]...Gate[n] in a first direction (for example, a lateral direction) connected to each pixel, wherein, Gate [n] represents a scan line corresponding to the n-th row of pixel circuits for providing a scan control signal to the pixel circuit of the line, such as a scan signal V Scan ; and a plurality of data lines Data [in the second direction (for example, vertical direction) [ 1] Data[m], where Data[m] represents a data line corresponding to the pixel circuit of the mth column, and is used for providing data signals of each pixel circuit, including: dark data voltage and illuminating data
  • the first control signal V CM and the illuminating control signal V EM required by the pixel circuit may also be provided by a global line, for example, the first control line CM is used for the pixel.
  • Each pixel circuit in the circuit matrix simultaneously provides a first control signal V CM
  • an illumination control line EM is used to simultaneously provide an illumination control signal V EM to each pixel circuit in the matrix of the pixel circuit.
  • the power lines and the like required for the first level end and the second level end may also be provided by a global line, and those skilled in the art may adjust according to the requirements of the specific pixel circuit.
  • the gate driving circuit 200 is configured to generate a scan pulse signal and provide a desired scan control signal to the pixel circuit through the respective scan lines Gate[1]...Gate[n] formed along the first direction.
  • the data driving circuit 300, the signal output end of the data driving circuit 300 is coupled to the corresponding data line Data[1]...Data[m] in the display panel 100, and the data signal generated by the data driving circuit 300 passes through the data line Data[1]. ]...Data[m] is transferred to the corresponding pixel unit to achieve image gray scale.
  • the controller 400 is configured to provide control timing to the gate driving circuit, the data driving circuit, and the first control line CM and the illumination control line EM.
  • each row of scanning lines sequentially supplies an effective level of the scanning signal VScan to each pixel circuit in rows, and each pixel circuit sequentially receives dark data voltages in rows;
  • the illumination control line EM simultaneously supplies the corresponding level of the first control signal V CM and the level corresponding to the illumination control signal V EM to each pixel circuit; each pixel circuit simultaneously extracts the effective level of the scan signal V Scan provided by the scan line of the current line.
  • the illumination control line EM simultaneously supplies an effective level of the illumination control signal V EM to each pixel circuit, and each row of scan lines sequentially supplies an effective level of the scan signal V Scan to each pixel circuit, and each pixel circuit sequentially receives the illumination data in a row. With the voltage V Data , each pixel circuit starts to emit light in sequence.

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Abstract

提供一种像素电路，包括：用于串联在第一电平端（VDD）和第二电平端（VSS）之间的驱动晶体管（T1）和发光元件（OLED），以及第二晶体管（T2）、第三晶体管（T3）、第四晶体管（T4）、第一电容（C1）和第二电容（C2），在驱动晶体管（T1）的控制极和发光元件（OLED）的第二端之间连接第二电容（C2），通过第一电容（C1）存储阈值电压，从而实现了对驱动晶体管和发光元件的阈值电压补偿，继而补偿了像素电路显示的不均匀性。还提供了一种显示装置，其中，第一控制线（CM）以及发光控制线（EM）均为全局线。还提供了一种像素电路驱动方法。

Description

像素电路及其驱动方法和显示装置 技术领域
本发明涉及显示器件领域，具体涉及一种像素电路及其驱动方法和显示装置。
背景技术
有机发光二极管(Organic Light-Emitting Diode，OLED)显示因具有高亮度、高发光效率、宽视角和低功耗等优点，近年来被人们广泛研究，并迅速应用到新一代的显示当中。OLED显示的驱动方式可以为无源矩阵驱动(Passive Matrix OLED，PMOLED)和有源矩阵驱动(Active Matrix OLED，AMOLED)两种。无源矩阵驱动虽然成本低廉，但是存在交叉串扰现象不能实现高分辨率的显示，且无源矩阵驱动电流大，降低了OLED的使用寿命。相比之下，有源矩阵OLED驱动方式在每个像素上设置数目不同的晶体管作为电流源，避免了交叉串扰，所需的驱动电流较小，功耗较低，使OLED的寿命增加，可以实现高分辨的显示。
传统AMOLED的像素电路是简单的两薄膜场效应晶体管(Thin Film Transistor，TFT)结构，这种电路虽然结构简单，但是不能补偿驱动晶体管T1和OLED阈值电压漂移或因TFT器件采用多晶材料制成而导致面板各处TFT器件的阈值电压不均匀性。当驱动晶体管T1阈值电压、OLED阈值电压发生漂移或在面板上各处的值不一致时，驱动电流IDS就会改变，并且面板上不同的像素因偏置电压的不同漂移情况也不一样，这样就会造成面板显示的不均匀性。
目前，像素电路的驱动方式主要分为两种，一种为逐行扫描发光的驱动方式，另一种为集中补偿共同发光的驱动方式。
对于逐行扫描发光的驱动方式，在一帧的时间内，每一行像素电路分别依次进行驱动，如图1所示，每行的驱动过程都包括初始化、阈值补偿、编程和发光阶段，当每一行的像素完成编程后立即进入发光阶段，在此将初始化和阈值补偿阶段简称为补偿阶段，整体来看，在一帧的时间内，一部分用于补偿，一部分用于发光，且整个一帧的时间都用来发光。这种驱动方式，每行像素补偿和编程时间较短，发光时间较长，但是每行像素电路都需要独立的控制线，栅极驱动电路比较复杂。
对于集中补偿共同发光的驱动方式，在一帧的时间内，每行的驱动 过程都包括初始化，阈值补偿，编程和发光阶段，与传统逐行扫描发光驱动方式不同的是，所有像素一起进行补偿，然后每行像素依次进行编程，等待所有行像素都完成编程之后一起进行发光，如图2所示，在此将初始化和阈值补偿阶段简称为补偿阶段，整体来看，在一帧的时间内，一部分用于补偿，一部分用于发光，且发光时间较短。这种驱动方式，面板上所有像素电路的控制线是共享的(即采用全局控制线)，但是，由于在编程阶段每行都存在大量的等待空闲时间，所以整体编程时间较长，发光时间较短。
发明内容
本申请提供一种像素电路及其驱动方法和显示装置，补偿驱动晶体管和发光元件的阈值电压漂移，实现更加均匀的发光，同时降低电路的复杂性。
根据第一方面，一种实施例中提供一种像素电路，包括：
用于串联在第一电平端和第二电平端之间的驱动晶体管和发光元件，以及第二晶体管、第三晶体管、第四晶体管、第一电容和第二电容；驱动晶体管的第一极连接至第三晶体管的第二极形成第一节点；驱动晶体管的第二极连接至发光元件的第一端；驱动晶体管的控制极连接至第一电容的一端形成第二节点；第一电容的另一端连接至第四晶体管的第二极形成第三节点；第三晶体管的控制极用于输入发光控制信号；第三晶体管的第一极和发光元件的第二端用于分别连接至第一电平端和第二电平端；第二晶体管的第一极连接至第一节点，第二晶体管的第二极连接至第二节点，第二晶体管的控制极用于输入第一控制信号；第四晶体管的第一极用于连接至数据线，用于输入数据信号或者还用于输入参考电平；第四晶体管的控制极用于输入扫描信号；第二电容连接至驱动晶体管的控制极和发光元件的第二端之间。
根据第二方面，一种实施例中提供一种显示装置，包括：
像素电路矩阵，所述像素电路矩阵包括排列成n行m列矩阵的上述像素电路，所述n和m为大于0的整数；栅极驱动电路，用于产生扫描脉冲信号，并通过沿第一方向形成的各行扫描线向像素电路提供所需的扫描信号；数据驱动电路，用于产生代表灰度信息的数据电压信号，并通过沿第二方向形成的各数据线向像素电路提供数据信号；第一控制线，用于向像素电路矩阵中各像素电路同时提供第一控制信号；发光控制线， 用于向像素电路矩阵中各像素电路同时提供发光控制信号；控制器，用于向栅极驱动电路、数据驱动电路以及第一控制线和发光控制线提供控制时序。
根据第三方面，一种实施例中提供一种像素电路驱动方法，每一驱动周期包括暗数据写入阶段、初始化及阈值补偿阶段和发光阶段，驱动方法包括：
在暗数据写入阶段，第四晶体管响应扫描信号的有效电平导通向第三节点传输暗数据电压，将发光元件控制在不发光状态；在初始化和阈值补偿阶段，第三节点接收参考电平以初始化第三节点电位；第二节点根据驱动晶体管和发光元件的阈值电压调整电位，并通过第一电容存储该电位；在发光阶段，第三晶体管响应发光控制信号的有效电平导通，第四晶体管响应扫描信号的有效电平导通向第三节点传输发光数据电压，并通过电容耦合至第二节点；驱动晶体管响应第二节点的电位导通驱动发光元件发光。
依据上述实施例的像素电路，通过驱动晶体管采用二极管的连接形式调整驱动晶体管控制极的电位，从而读取驱动晶体管和发光元件的阈值电压，利用第二电容维持驱动晶体管控制极的电位，并存储于第一电容，从而能够实现对驱动晶体管阈值电压的补偿，继而补偿了像素电路显示的不均匀性。该像素电路结构简单，所需的控制线较少。
依据上述实施例的显示装置，第一控制线以及发光控制线均为全局线，降低了像素电路驱动的复杂性，也有利于降低成本。
附图说明
图1为现有技术中逐行扫描发光驱动方式原理图；
图2为现有技术中集中补偿共同发光驱动方式原理图；
图3a为实施例一公开的一种像素电路结构图；
图3b为实施例一公开的另一种像素电路结构图；
图4a为一种实施例公开的一种像素电路的一种工作时序图；
图4b为另一种实施例公开的一种像素电路的一种工作时序图；
图5a为实施例二公开的一种像素电路结构图；
图5b为实施例二公开的另一种像素电路结构图；
图5c为实施例二公开的一种像素电路的一种工作时序图；
图5d为实施例二公开的另一种像素电路的一种工作时序图；
图6a为实施例三公开的一种像素电路结构图；
图6b为实施例三公开的另一种像素电路结构图；
图7为实施例四公开的一种显示装置结构原理图。
具体实施方式
下面通过具体实施方式结合附图对本发明作进一步详细说明。
首先对一些术语进行说明：本申请中的晶体管可以是任何结构的晶体管，比如双极型晶体管(BJT)或者场效应晶体管(FET)。当晶体管为双极型晶体管时，其控制极是指双极型晶体管的基极，第一极可以为双极型晶体管的集电极或发射极，对应的第二极可以为双极型晶体管的发射极或集电极，在实际应用过程中，“发射极”和“集电极”可以依据信号流向而互换；当晶体管为场效应晶体管时，其控制极是指场效应晶体管的栅极，第一极可以为场效应晶体管的漏极或源极，对应的第二极可以为场效应晶体管的源极或漏极，在实际应用过程中，“源极”和“漏极”可以依据信号流向而互换。显示器中的晶体管通常为一种场效应晶体管：薄膜晶体管(TFT)。下面以晶体管为场效应晶体管为例对本申请做详细的说明，在其它实施例中晶体管也可以是双极型晶体管。
发光元件为有机发光二极管(Organic Light-Emitting Diode，OLED)，在其它实施例中，也可以是其它发光元件。发光元件的第一端可以是阴极或阳极，相应地，则发光元件的第二端为阳极或阴极。本领域技术人员应当理解：电流应从发光元件的阳极流向阴极，因此，基于电流的流向，可以确定发光元件的阳极和阴极。
有效电平可以是高电平，也可以是低电平，可根据具体元器件的功能实现作适应性地置换。
第一电平端和第二电平端是为像素电路工作所提供的电源两端。在一种实施例中，第一电平端可以为高电平端VDD，第二电平端为低电平端VSS或地线，在其它实施例中，也可以作适应性地置换。需要说明的是：对于像素电路而言，第一电平端(例如高电平端VDD)和第二电平端(例如低电平端VSS)并非本申请像素电路的一部分，为了使本领域技术人员更好地理解本申请的技术方案，而特别引入第一电平端和第二电平端予以描述。
需要说明的是，为了描述方便，也为了使本领域技术人员更清楚地理解本申请的技术方案，本申请文件中引入第一节点A、第二节点B和 第三节点C对电路结构相关部分进行标识，不能认定为电路中额外引入的端子。
为描述方便，高电平采用VH表征，低电平采用VL表征。
实施例一：
请参考图3a和图3b，为本实施例公开的一种像素电路结构图，包括：用于串联在第一电平端VDD和第二电平端VSS之间的驱动晶体管T1和发光元件OLED，以及第二晶体管T2、第三晶体管T3、第四晶体管T4、第一电容C1和第二电容C2。其中，图3a所示的像素电路中，各晶体管(驱动晶体管T1、第二晶体管T2、第三晶体管T3和第四晶体管T4)为N型薄膜晶体管；图3b所示的像素电路中，各晶体管(驱动晶体管T1、第二晶体管T2、第三晶体管T3和第四晶体管T4)为P型薄膜晶体管。
驱动晶体管T1的第一极连接至第三晶体管T3的第二极形成第一节点A；驱动晶体管T1的第二极连接至发光元件OLED的第一端；驱动晶体管T1的控制极连接至第一电容C1的一端形成第二节点B；第一电容C1的另一端连接至第四晶体管T4的第二极形成第三节点C。
第三晶体管T3的控制极用于输入发光控制信号VEM；第三晶体管T3的第一极和发光元件OLED的第二端用于分别连接至第一电平端VDD和第二电平端VSS。在一种实施例中，请参考图3a，发光元件OLED的第一端为阳极，发光元件OLED的第二端为阴极，第三晶体管T3的第一极用于连接至第一电平端VDD，发光元件OLED的第二端用于连接至第二电平端VSS；在另一种实施例中，请参考图3b，发光元件OLED的第一端为阴极，发光元件OLED的第二端为阳极，第三晶体管T3的第一极用于连接至第二电平端VSS，发光元件OLED的第二端用于连接至第一电平端VDD。
第二晶体管T2的第一极连接至第一节点A，第二晶体管T2的第二极连接至第二节点B，第二晶体管T2的控制极用于输入第一控制信号VCM。
第四晶体管T4的第一极用于连接至数据线Data，在具体实施例中，数据线Data用于提供数据信号，或者还用于提供参考电平Vref，在其它实施例中，第四晶体管T4输入的参考电平Vref也可采用其它方式提供。 第四晶体管T4的控制极用于输入扫描信号VScan。在本实施例中，数据信号包括：暗数据电压和发光数据电压VData，暗数据电压为能够使得发光元件OLED不发光的电位，发光数据电压VData为驱动发光元件OLED发光的电位，请参考图3a，当驱动晶体管T1为N型晶体管时，暗数据电平为低电平；请参考图3b，当驱动晶体管T1为P型晶体管时，暗数据电平为高电平。
第二电容C2连接至驱动晶体管T1的控制极和发光元件OLED的第二端之间，在本实施例中，第二电容C2与驱动晶体管T1的控制极相连的一端采用直接连接的方式连接，在其它实施例中，也可以采用间接连接的方式进行连接，例如，第二电容C2的该端连接至第三节点C。
在具体实施例中，像素电路依次工作于第一阶段、第二阶段和第三阶段。在本实施例中，第一阶段可以为暗数据写入阶段，第二阶段可以包括初始化和阈值补偿阶段，第三阶段为发光阶段。
请参考图4a和图4b，分别对应为本实施例图3a和图3b所示像素电路的工作时序图，下文结合图3a和图4a为例对本实施像素电路的工作过程予以说明。需要说明的是，当各晶体管为P型晶体管时，例如在图3b所示的电路中，其各控制信号的高、低状态与图3a所示电路的信号状态反相，在下文中，若未特别说明，均遵循此原则。
在第一阶段，如图4a中(1)所标示的暗数据写入阶段，发光控制信号VEM为有效电平(例如高电平)，扫描信号VScan为有效电平(例如高电平)，第一控制信号VCM为低电平。于是，第二晶体管T2由第一控制信号VCM控制在截止状态，第三晶体管T3响应发光控制信号VEM的有效电平导通并处于导通状态，第四晶体管T4响应扫描信号VScan的有效电平导通，此时，由于数据线Data上传输的为暗数据电压，于是，该暗数据电压通过导通的第四晶体管T4传输到第三节点C，从而使得像素电路的发光元件OLED被关闭。在优选的实施例中，当具有多行像素电路时，每行像素电路对应的扫描信号VScan的有效电平可以依次到来(如图4所示的VScan[1]、VScan[2]……VScan[n]，其中，VScan[n]表示第n行像素电路的扫描信号)，于是，每行像素被依次写入暗数据，从而每行像素的发光元件被依次关闭，直到最后一行像素完成暗数据的写入，所有的发光元件都被关闭，而且保证了每行的像素电路具有相同的发光时间。
在第二阶段，如图4a中(2)所标示的初始化和阈值补偿阶段，首先到来的为初始化阶段，而后为阈值补偿阶段。
在初始化阶段：发光控制信号VEM保持为有效电平(例如高电平)，第一控制信号VCM变为有效电平(例如高电平)，扫描信号VScan为有效电平(例如高电平)，此时，数据线上传输的为参考电平Vref；于是，第三晶体管T3响应发光控制信号VEM的有效电平(例如高电平)处于导通状态，第四晶体管T4响应扫描信号VScan的有效电平(例如高电平)处于导通状态，第二晶体管T2响应第一控制信号VCM的有效电平(例如高电平)处于导通状态；于是，数据线上传输的参考电平Vref通过导通的第四晶体管T4传输到第三节点C以初始化第三节点C电位，即第三节点C的电位为VC＝Vref；第一节点A和第二节点B通过导通的第二晶体管T2连通，第一电平端VDD通过导通的第三晶体管T3向连通的第一节点A和第二节点B传输第一电平端VDD的电位(如高电平VH)，以初始化第一节点A和第二节点B的电位，此时，第一节点A和第二节点B的电位为VA＝VB＝VH；于是完成了各节点电位的初始化过程。需要说明的是，在优选的实施例中，当具有多行像素电路时，每行像素电路对应的扫描信号VScan的有效电平可以同时到来，各像素电路同时完成初始化过程。需要说明的是，在另一种实施例中，请参考图3b，第一节点A和第二节点B的初始化电位由第二电平端VSS的电位(如低电平VL)提供，此时，第一节点A和第二节点B的电位为VA＝VB＝VL。
在阈值补偿阶段：第一控制信号VCM保持为有效电平(例如高电平)，扫描信号VScan保持为有效电平(例如高电平)，发光控制信号VEM变为低电平，此时，数据线上传输的依旧为参考电平Vref；于是，第三晶体管T3由发光控制信号VEM控制在截止状态，第四晶体管T4保持导通状态，于是，第三节点C的电位保持为Vref；第一节点A和第二节点B通过导通的第二晶体管T2连通，此时，驱动晶体管T1形成了二极管的连接形式，第一节点A和第二节点B的电位通过二极管形式的连接驱动晶体管T1向第二电平端VSS放电至驱动晶体管T1截止，此时第一节点A和第二节点B的电位为VA＝VB＝VOLED+VTH，其中，VTH和VOLED分别为驱动晶体管T1的阈值电压和发光元件OLED的阳极电位，此时，VC1＝VB-VC＝VOLED+VTH-Vref，其中，VC1为第一电容元件C1两端的压差，于是实现了对驱动晶体管T1和发光元件OLED的阈值电压的补偿。需 要说明的是，在另一种实施例中，请参考图3b，第一节点A和第二节点B的电位通过第一电平端VDD提供的电位充电至驱动晶体管T1截止，以完成驱动晶体管T1和发光元件OLED的阈值电压补偿的过程。需要说明的是，在优选的实施例中，当具有多行像素电路时，每行像素电路对应的扫描信号VScan的有效电平可以同时到来，各像素电路同时完成阈值补偿过程。
在第三阶段，如图4a中(3)所标示的发光阶段，扫描信号VScan保持为有效电平(例如高电平)，第一控制信号VCM变为低电平，发光控制信号VEM变为有效电平(例如高电平)，此时，数据线上传输的为发光数据电压VData；于是，第三晶体管T3和第四晶体管T4为导通状态，数据线上的发光数据电压VData通过导通的第四晶体管T4传输至第三节点C，于是，第三节点C的电位由Vref变为VData，在第一电容C1和第二电容C2的耦合作用下，第二节点B的电位变为
Figure PCTCN2016077393-appb-000001
第三晶体管T3响应发光控制信号VEM的有效电平导通，驱动晶体管T1响应第二节点B的电位导通驱动发光元件OLED发光，此时流过发光元件OLED的电流为：
Figure PCTCN2016077393-appb-000002
其中，μn、Cox、W、L分别为驱动晶体管T1的有效迁移率、单位面积栅电容、沟道宽度和沟道长度。从式(1-1)可以看出，最终流过发光元件OLED的电流与驱动晶体管T1的阈值电压以及OLED本身的阈值电压都无关，从而本实施例中的像素电路可以很好的补偿显示的不均匀性。
需要说明的是，在优选的实施例中，当具有多行像素电路时，如图4a和图4b所示的“1”、“2”……“M”行，每行像素电路对应的扫描信号VScan的有效电平可以依次到来，于是，每行像素电路的第四晶体管T4依次变为导通状态，被依次写入发光数据电压VData。
本实施例中的像素电路不仅可以补偿驱动晶体管阈值电压的漂移，还可以补偿OLED阈值电压的漂移。此外，在优选的实施例中，利用基于独立补偿帧的电压驱动方式，结合了逐行扫描和集中补偿共同发光驱动方式的优点，既有效减少外围栅极驱动电路的复杂程度，降低成本，还大大增加了发光时间，提高了像素电路的编程速度和面板分辨率。
实施例二：
请参考图5a和图5b，为本实施例公开的一种像素电路结构图，与上述实施例不同之处在于，本实施例公开的像素电路还包括：第五晶体管T5，向第三节点C提供的参考电平Vref由第五晶体管T5传输。
第五晶体管T5的第一极用于输入参考电平Vref，第五晶体管T5的第二极连接至第三节点C，第五晶体管T5的控制极用于输入第一控制信号VCM。在一种实施例中，请参考图5a，各晶体管为N型晶体管，各晶体管导通的有效电平为高电平，暗数据电压为低电平，第一节点A和第二节点B的初始化电位由第一电平端VDD提供；在另一种实施例中，请参考图5b，各晶体管为P型晶体管，各晶体管导通的有效电平为低电平，暗数据电压为高电平，第一节点A和第二节点B的初始化电位由第二电平端VSS提供。
本实施例像素电路的驱动过程分别如图5c和图5d所示，其中，图5c为图5a所示像素电路的工作时序示意图，图5d为图5b所示像素电路的工作时序示意图本实施例公开的像素电路的驱动过程与上述实施例大致相同，所不同的是，在本实施例中，在第二阶段，当第一控制信号VCM为有效电平时，第五晶体管T5响应第一控制信号VCM的有效电平导通向第三节点C传输参考电平Vref以初始化第三节点C电位。由于参考电平Vref通过第五晶体管T5传输至第三节点C，而第四晶体管T4的第二极也连接至第三节点C，因此，在第二阶段，第四晶体管T4应由扫描信号VScan控制在截止状态，以防止第四晶体管T4在该阶段向第三节点C传输非期望的信号干扰，相应地，一种实施例中，当第四晶体管T4为N型晶体管时，在该阶段扫描信号VScan应为低电平；另一种实施例中，当第四晶体管T4为P型晶体管时，在该阶段扫描信号VScan应为高电平。本实施例公开的像素电路驱动过程的其它阶段与上述实施例相同，在此不再赘述。
相对于由数据线Data提供参考电平Vref的实施例中，本实施例虽然需要单独为第五晶体管T5配置一数据传输线以提供参考电平Vref，但是，可以简化数据线Data的时序控制，无需频繁变换数据线Data所传输的信号，更利于控制器的时序控制。
实施例三：
请参考图6a和图6b，为本实施例公开的一种像素电路结构原理图，上述实施例中，第二电容C2的一端直接连接至驱动晶体管T1的控制极，本实施例中，第二电容C2采用间接连接的方式连接至驱动晶体管T1的控制极，第二电容C2与驱动晶体管T1的控制极相连的一端连接至第三节点C，通过第一电容C1的耦合作用，实现第二电容C2的该端与驱动晶体管T1的控制极电连接。本实施例公开的像素电路中，其它元器件的连接方式与上述实施例相同，在此不再赘述。
图6a所示的像素电路中，各晶体管(驱动晶体管T1、第二晶体管T2、第三晶体管T3和第四晶体管T4)为N型薄膜晶体管；图6b所示的像素电路中，各晶体管(驱动晶体管T1、第二晶体管T2、第三晶体管T3和第四晶体管T4)为P型薄膜晶体管。
请参考图4a和图4b，分别为图6a和图6b所示像素电路的工作时序图，下文结合图6a和图4a为例对本实施像素电路的工作过程予以说明。需要说明的是，当各晶体管为P型晶体管时，例如在图6b所示的电路中，其各控制信号的高、低状态与图6a所示电路的信号状态反相，在下文中，若未特别说明，均遵循此原则。
在暗数据写入阶段，发光控制信号VEM为有效电平(例如高电平)，扫描信号VScan为有效电平(例如高电平)，第一控制信号VCM为低电平。于是，第二晶体管T2由第一控制信号VCM控制在截止状态，第三晶体管T3响应发光控制信号VEM的有效电平导通并处于导通状态，第四晶体管T4响应扫描信号VScan的有效电平导通，此时，由于数据线Data上传输的为暗数据电压，于是，该暗数据电压通过导通的第四晶体管T4传输到第三节点C，进而通过电容耦合到第二节点B，从而使得像素电路的发光元件OLED被关闭。同样地，在优选的实施例中，当具有多行像素电路时，每行像素电路对应的扫描信号VScan的有效电平也可以依次到来，于是，每行像素被依次写入暗数据，从而每行像素的发光元件被 依次关闭，直到最后一行像素完成暗数据的写入，所有的发光元件都被关闭，而且保证了每行的像素电路具有相同的发光时间。
在初始化阶段：发光控制信号VEM保持为有效电平(例如高电平)，第一控制信号VCM变为有效电平(例如高电平)，扫描信号VScan为有效电平(例如高电平)，此时，数据线上传输的为参考电平Vref；于是，第三晶体管T3响应发光控制信号VEM的有效电平(例如高电平)处于导通状态，第四晶体管T4响应扫描信号VScan的有效电平(例如高电平)处于导通状态，第二晶体管T2响应第一控制信号VCM的有效电平(例如高电平)处于导通状态；于是，数据线上传输的参考电平Vref通过导通的第四晶体管T4传输到第三节点C以初始化第三节点C电位，即第三节点C的电位为VC＝Vref；第一节点A和第二节点B通过导通的第二晶体管T2连通，第一电平端VDD通过导通的第三晶体管T3向连通的第一节点A和第二节点B传输第一电平端VDD的电位(如高电平VH)，以初始化第一节点A和第二节点B的电位，此时，第一节点A和第二节点B的电位为VA＝VB＝VH；于是完成了各节点电位的初始化过程。需要说明的是，在优选的实施例中，当具有多行像素电路时，每行像素电路对应的扫描信号VScan的有效电平可以同时到来，各像素电路同时完成初始化过程。需要说明的是，在另一种实施例中，请参考图6b，第一节点A和第二节点B的初始化电位由第二电平端VSS的电位(如低电平VL)提供，此时，第一节点A和第二节点B的电位为VA＝VB＝VL。
在阈值补偿阶段：第一控制信号VCM保持为有效电平(例如高电平)，扫描信号VScan保持为有效电平(例如高电平)，发光控制信号VEM变为低电平，此时，数据线上传输的依旧为参考电平Vref；于是，第三晶体管T3由发光控制信号VEM控制在截止状态，第四晶体管T4保持导通状态，于是，第三节点C的电位保持为Vref；第一节点A和第二节点B通过导通的第二晶体管T2连通，此时，驱动晶体管T1形成了二极管的连接形式，第一节点A和第二节点B的电位通过二极管形式的连接驱动晶体管T1向第二电平端VSS放电至驱动晶体管T1截止，此时第一节点A和第二节点B的电位为VA＝VB＝VOLED+VTH，其中，VTH和VOLED分别为驱动晶体管T1的阈值电压和发光元件OLED的阳极电位，从而完成了第二节点B根据驱动晶体管T1和发光元件OLED的阈值电压调整电位的过程，此时，VC1＝VB-VC＝VOLED+VTH-Vref，其中，VC1为第一电容元件 C1两端的压差。需要说明的是，在另一种实施例中，请参考图6b，第一节点A和第二节点B的电位通过第一电平端VDD提供的电位充电至驱动晶体管T1截止，以完成驱动晶体管T1和发光元件OLED的阈值电压补偿的过程。需要说明的是，在优选的实施例中，当具有多行像素电路时，每行像素电路对应的扫描信号VScan的有效电平可以同时到来，各像素电路同时完成阈值补偿过程。
在发光阶段，扫描信号VScan保持为有效电平(例如高电平)，第一控制信号VCM变为低电平，发光控制信号VEM变为有效电平(例如高电平)，此时，数据线上传输的为发光数据电压VData；于是，第三晶体管T3和第四晶体管T4为导通状态，数据线上的发光数据电压VData通过导通的第四晶体管T4传输至第三节点C，于是，第三节点C的电位由Vref变为VData，在第一电容C1的耦合作用下，第二节点B的电位变为VOLED+VTH-Vref+VData，驱动晶体管T1响应第二节点B的电位导通驱动发光元件OLED发光，此时流过发光元件OLED的电流为：
Figure PCTCN2016077393-appb-000003
其中，μn、Cox、W、L分别为驱动晶体管T1的有效迁移率、单位面积栅电容、沟道宽度和沟道长度。从式(3-1)可以看出，最终流过发光元件OLED的电流与驱动晶体管T1的阈值电压以及OLED本身的阈值电压都无关，从而本实施例中的像素电路可以很好的补偿显示的不均匀性。
需要说明的是，本实施例公开的像素电路中，并未示出第五晶体管T5，在可替换的实施例中，也可以采用第五晶体管T5来传输参考电平Vref。当然，在包含第五晶体管T5的实施例中，当第五晶体管T5传输参考电平Vref时，第四晶体管T4也应由扫描信号VScan控制在截止状态，具体可参见上述实施例，在此不再赘述。
依据上述实施例公开的像素电路，本实施例还公开了一种像素电路驱动方法，像素电路的每一驱动周期包括暗数据写入阶段、初始化及阈 值补偿阶段和发光阶段，驱动方法包括：
在暗数据写入阶段，第四晶体管T4响应扫描信号VScan的有效电平导通向第三节点C传输暗数据电压，将发光元件OLED控制在不发光状态；
在初始化和阈值补偿阶段，第三节点C接收参考电平Vref以初始化第三节点C电位；第二节点B根据驱动晶体管T1和发光元件OLED的阈值电压调整电位并通过第一电容C1存储该电位；
在发光阶段，第四晶体管T4响应扫描信号VScan的有效电平导通向第三节点C传输发光数据电压VData，并通过电容耦合至第二节点B；第三晶体管T3响应发光控制信号VEM的有效电平导通，驱动晶体管T1响应第二节点B的电位导通驱动发光元件OLED发光。
实施例四：
本实施例还公开了一种显示装置，请参考图7，为本实施例还公开的显示装置结构原理图，该显示装置包括：
显示面板100，显示面板100包括排列成n行m列矩阵的上述实施例提供的像素电路Pixel[1][1]……Pixel[n][m]，其中，n和m为大于0的整数，Pixel[n][m]表征第n行m列的像素电路；与每个像素相连的第一方向(例如横向)的多条扫描线Gate[1]……Gate[n]，其中，Gate[n]表示第n行像素电路对应的扫描线，用于向提供向本行像素电路提供扫描控制信号，例如扫描信号VScan等；和第二方向(例如纵向)的多条数据线Data[1]……Data[m]，其中，Data[m]表示第m列像素电路对应的数据线，用于提供各像素电路的数据信号，包括：暗数据电压和发光数据电压VDATA。显示面板可以是液晶显示面板、有机发光显示面板、电子纸显示面板等，而对应的显示装置可以是液晶显示器、有机发光显示器、电子纸显示器等。
需要说明的是，在本实施例中，像素电路所需的第一控制信号VCM和发光控制信号VEM也可以通过全局线的方式来提供，譬如，第一控制线CM，用于向像素电路矩阵中各像素电路同时提供第一控制信号VCM；发光控制线EM，用于向像素电路矩阵中各像素电路同时提供发光控制信号VEM。当然，在另一种实施例中，比如第一电平端和第二电平端所需的电源线等也可以通过全局线的方式提供，本领域技术人员可以依据 具体像素电路的需求来调整。
栅极驱动电路200，用于产生扫描脉冲信号，并通过沿第一方向形成的各行扫描线Gate[1]……Gate[n]向像素电路提供所需的扫描控制信号。
数据驱动电路300，数据驱动电路300的信号输出端耦合到显示面板100中与其对应的数据线Data[1]……Data[m]上，数据驱动电路300产生的数据信号通过数据线Data[1]……Data[m]传输到对应的像素单元内以实现图像灰度。
控制器400，控制器400用于向栅极驱动电路、数据驱动电路以及第一控制线CM和发光控制线EM提供控制时序。
在优选的实施例中，
在暗数据写入阶段，各行扫描线按行依次向各像素电路提供扫描信号VScan的有效电平，各像素电路按行依次接收暗数据电压；在初始化和阈值补偿阶段，第一控制线CM和发光控制线EM同时向各像素电路提供第一控制信号VCM相应的电平和发光控制信号VEM相应的电平；各像素电路同时响应本行扫描线提供的扫描信号VScan有效电平提取各自驱动晶体管T1和发光元件(OLED)的阈值电压；在发光阶段，第一控制线CM将各相应的晶体管(如第二晶体管T2，或者第二晶体管T2和第四晶体管T4)控制在截止状态，发光控制线EM同时向各像素电路提供发光控制信号VEM的有效电平，各行扫描线按行依次向各像素电路提供扫描信号VScan的有效电平，各像素电路按行依次接收发光数据电压VData，各像素电路按行依次开始发光。
以上应用了具体个例对本发明进行阐述，只是用于帮助理解本发明，并不用以限制本发明。对于本发明所属技术领域的技术人员，依据本发明的思想，还可以做出若干简单推演、变形或替换。

Claims (10)

  1. 一种像素电路，其特征在于，包括：
    用于串联在第一电平端(VDD)和第二电平端(VSS)之间的驱动晶体管(T1)和发光元件(OLED)，以及第二晶体管(T2)、第三晶体管(T3)、第四晶体管(T4)、第一电容(C1)和第二电容(C2)；
    驱动晶体管(T1)的第一极连接至第三晶体管(T3)的第二极形成第一节点(A)；驱动晶体管(T1)的第二极连接至发光元件(OLED)的第一端；驱动晶体管(T1)的控制极连接至第一电容(C1)的一端形成第二节点(B)；第一电容(C1)的另一端连接至第四晶体管(T4)的第二极形成第三节点(C)；
    第三晶体管(T3)的控制极用于输入发光控制信号(VEM)；第三晶体管(T3)的第一极和发光元件(OLED)的第二端用于分别连接至第一电平端(VDD)和第二电平端(VSS)；
    第二晶体管(T2)的第一极连接至第一节点(A)，第二晶体管(T2)的第二极连接至第二节点(B)，第二晶体管(T2)的控制极用于输入第一控制信号(VCM)；
    第四晶体管(T4)的第一极用于连接至数据线(Data)，用于输入数据信号或者还用于参考电平(Vref)；第四晶体管(T4)的控制极用于输入扫描信号(VScan)；
    第二电容(C2)连接至驱动晶体管(T1)的控制极和发光元件(OLED)的第二端之间。
  2. 如权利要求1所述的像素电路，其特征在于，所述数据信号包括：暗数据电压和发光数据电压(VData)；所述暗数据电压为能够使得发光元件(OLED)不发光的电压，所述发光数据电压(VData)为驱动发光元件(OLED)发光的电压；
    在第一阶段，第四晶体管(T4)响应扫描信号(VScan)的有效电平导通向第三节点(C)传输暗数据电压；
    在第二阶段，第二晶体管(T2)响应第一控制信号(VCM)的有效电平连通第一节点(A)和第二节点(B)；第三晶体管(T3)响应发光控制信号(VEM)的有效电平导通向第一节点(A)和第二节点(B)传输第一电平端(VDD)或第二电平端(VSS)的电位，初始化第一节点(A)和第二节点(B)；第三节点(C)接收参考电平(Vref)以初始化 第三节点(C)电位；各点电位完成初始化之后，发光控制信号(VEM)将第三晶体管(T3)控制在截止状态，第一节点(A)和第二节点(B)根据驱动晶体管(T1)和发光元件(OLED)的阈值电压通过导通的驱动晶体管(T1)调整电位，并存储在第一电容(C1)中；
    在第三阶段，第二晶体管(T2)由第一控制信号(VCM)控制在截止状态；第三晶体管(T3)响应发光控制信号(VEM)的有效电平导通，第四晶体管(T4)响应扫描信号(VScan)的有效电平导通向第三节点(C)传输发光数据电压(VData)；发光数据电压(VData)通过电容耦合至第二节点(B)，驱动晶体管(T1)响应第二节点(B)的电位导通驱动发光元件(OLED)发光。
  3. 如权利要求2所述的像素电路，其特征在于，
    所述参考电平(Vref)由数据线(Data)提供，在第二阶段，第四晶体管(T4)响应扫描信号(VScan)的有效电平导通向第三节点(C)传输参考电平(Vref)以初始化第三节点(C)电位。
  4. 如权利要求2所述的像素电路，其特征在于，驱动晶体管(T1)和发光元件(OLED)，以及第二晶体管(T2)、第三晶体管(T3)和第四晶体管(T4)为N型晶体管；各晶体管导通的有效电平为高电平；
    所述暗数据电压为低电平；
    第三晶体管(T3)的第一极用于连接至第一电平端(VDD)，发光元件(OLED)的第二端用于连接至第二电平端(VSS)。
  5. 如权利要求4所述的像素电路，其特征在于，还包括：第五晶体管(T5)；
    第五晶体管(T5)的第一极用于输入参考电平(Vref)，第五晶体管(T5)的第二极连接至第三节点(C)，第五晶体管(T5)的控制极用于输入第一控制信号(VCM)；
    在第二阶段，第五晶体管(T5)响应第一控制信号(VCM)的有效电平导通向第三节点(C)传输参考电平(Vref)以初始化第三节点(C)电位。
  6. 如权利要求2所述的像素电路，其特征在于，驱动晶体管(T1)和发光元件(OLED)，以及第二晶体管(T2)、第三晶体管(T3)和第四晶体管(T4)为P型晶体管；各晶体管导通的有效电平为低电平；
    所述暗数据电压为高电平；
    第三晶体管(T3)的第一极用于连接至第二电平端(VSS)，发光元件(OLED)的第二端用于连接至第一电平端(VDD)。
  7. 如权利要求6所述的像素电路，其特征在于，还包括：第五晶体管(T5)；
    第五晶体管(T5)的第一极用于输入参考电平(Vref)，第五晶体管(T5)的第二极连接至第三节点(C)，第五晶体管(T5)的控制极用于输入第一控制信号(VCM)；
    在第二阶段，第五晶体管(T5)响应第一控制信号(VCM)的有效电平导通向第三节点(C)传输参考电平(Vref)以初始化第三节点(C)电位。
  8. 一种显示装置，其特征在于，包括：
    像素电路矩阵，所述像素电路矩阵包括排列成n行m列矩阵的如权利要求2-7任意一项所述的像素电路，所述n和m为大于0的整数；
    栅极驱动电路，用于产生扫描脉冲信号，并通过沿第一方向形成的各行扫描线向像素电路提供所需的扫描信号；
    数据驱动电路，用于产生代表灰度信息的数据电压信号，并通过沿第二方向形成的各数据线向像素电路提供数据信号；
    第一控制线(CM)，用于向像素电路矩阵中各像素电路同时提供第一控制信号(VCM)；
    发光控制线(EM)，用于向像素电路矩阵中各像素电路同时提供发光控制信号(VEM)；
    控制器，用于向栅极驱动电路、数据驱动电路以及第一控制线(CM)和发光控制线(EM)提供控制时序。
  9. 如权利要求8所述的显示装置，其特征在于，所述显示装置的一个驱动周期包括：暗数据写入阶段、初始化和阈值补偿阶段、发光阶段；
    在暗数据写入阶段，各行扫描线按行依次向各像素电路提供扫描信号(VScan)的有效电平，各像素电路按行依次接收暗数据电压；
    在初始化和阈值补偿阶段，第一控制线(CM)和发光控制线(EM)同时向各像素电路提供第一控制信号(VCM)相应的电平和发光控制信号(VEM)相应的电平；各像素电路同时响应本行扫描线提供的扫描信号(VScan)有效电平提取各自驱动晶体管(T1)和发光元件(OLED) 的阈值电压；
    在发光阶段，第一控制线(CM)将各相应的晶体管控制在截止状态，发光控制线(EM)同时向各像素电路提供发光控制信号(VEM)的有效电平，各行扫描线按行依次向各像素电路提供扫描信号(VScan)的有效电平，各像素电路按行依次接收发光数据电压(VData)，各像素电路按行依次开始发光。
  10. 一种像素电路驱动方法，其特征在于，所述像素电路的每一驱动周期包括暗数据写入阶段、初始化及阈值补偿阶段和发光阶段，所述驱动方法包括：
    在暗数据写入阶段，第四晶体管(T4)响应扫描信号(VScan)的有效电平导通向第三节点(C)传输暗数据电压，将发光元件(OLED)控制在不发光状态；
    在初始化和阈值补偿阶段，第三节点(C)接收参考电平(Vref)以初始化第三节点(C)电位；第二节点(B)根据驱动晶体管(T1)和发光元件(OLED)的阈值电压调整电位并通过第一电容(C1)存储该电位；
    在发光阶段，第四晶体管(T4)响应扫描信号(VScan)的有效电平导通向第三节点(C)传输发光数据电压(VData)，并通过电容耦合至第二节点(B)；第三晶体管(T3)响应发光控制信号(VEM)的有效电平导通，驱动晶体管(T1)响应第二节点(B)的电位导通驱动发光元件(OLED)发光。
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