WO2016169369A1 - 一种显示装置及其像素电路 - Google Patents

一种显示装置及其像素电路 Download PDF

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Publication number
WO2016169369A1
WO2016169369A1 PCT/CN2016/076554 CN2016076554W WO2016169369A1 WO 2016169369 A1 WO2016169369 A1 WO 2016169369A1 CN 2016076554 W CN2016076554 W CN 2016076554W WO 2016169369 A1 WO2016169369 A1 WO 2016169369A1
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Prior art keywords
transistor
control signal
scan control
voltage
pixel circuit
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PCT/CN2016/076554
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English (en)
French (fr)
Inventor
张盛东
王翠翠
冷传利
Original Assignee
北京大学深圳研究生院
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Priority to US15/550,982 priority Critical patent/US20180033365A1/en
Publication of WO2016169369A1 publication Critical patent/WO2016169369A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
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    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
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    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0216—Interleaved control phases for different scan lines in the same sub-field, e.g. initialization, addressing and sustaining in plasma displays that are not simultaneous for all scan lines
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G09G2310/0218—Addressing of scan or signal lines with collection of electrodes in groups for n-dimensional addressing
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    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
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    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • G—PHYSICS
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    • G09G2320/064—Adjustment of display parameters for control of overall brightness by time modulation of the brightness of the illumination source

Definitions

  • the present application relates to the field of display technologies, and in particular, to a display device and a pixel circuit thereof.
  • OLED Organic Light-Emitting Diode
  • PMOLED Passive Matrix OLED
  • AMOLED Active Matrix OLED
  • PMOLED Passive Matrix OLED
  • AMOLED Active Matrix OLED
  • PMOLED Passive Matrix OLED
  • AMOLED Active Matrix OLED
  • PMOLED has low manufacturing cost, it has crosstalk and requires a large driving current, so it has shortcomings such as short service life and high power consumption, and cannot meet large-area, high-resolution display requirements.
  • AMOLEDs avoid problems such as duty cycle and crosstalk, requiring less drive current, lower power consumption, and longer lifetime.
  • AMOLED is easier to meet the needs of large area, high resolution, high gray level display.
  • a conventional AMOLED pixel circuit is composed of two thin film transistors (TFTs) and a storage capacitor.
  • the pixel circuit includes a driving transistor 11, a switching transistor 12, a storage capacitor 13, and a light emitting device OLED14.
  • the signal on the control signal line 15 controls the switching transistor 12, and the data signal on the sampled data signal line 16 is supplied to the gate of the driving transistor 11, so that the driving transistor 11 generates the current required by the OLED 14, thereby generating the desired gradation,
  • the gray scale information is stored in the storage capacitor 13, and the storage capacitor 13 holds the sampled data information until the next frame.
  • the current flowing through the OLED 14 in the pixel circuit can be expressed as:
  • ⁇ n and C ox are the effective field effect mobility of the driving transistor 11 and the gate capacitance per unit area, respectively, and W and L are the effective channel width and the channel length of the TFT device, respectively.
  • V G is the gate potential of the driving transistor 11
  • V OLED is the bias voltage at both ends of the OLED 14 during light emission
  • V TH is the threshold voltage of the driving transistor 11.
  • the present application provides a display device and a pixel circuit thereof, which can compensate for driving transistors and hair
  • the threshold voltage offset of the optical device can also solve the problem of display unevenness caused by the difference in threshold voltages of the driving transistors across the display panel.
  • the present application provides a pixel circuit, including:
  • the one frame period of the pixel circuit sequentially includes an initialization phase, a threshold extraction phase, a data writing phase, and an illumination phase; the pixel circuit includes:
  • first transistor and a light emitting device connected in series between a high potential and a low potential, wherein the first transistor is configured to provide a driving current for the light emitting device during the light emitting phase, and the light emitting device is configured to emit light having a intensity associated with the current flowing;
  • the high potential is provided by the first voltage source signal terminal, and the low potential is provided by the second voltage source signal terminal;
  • a second transistor connected between the data signal terminal and the control electrode of the first transistor, the control electrode of the second transistor is connected to the first scan control signal end, and the first scan control signal terminal is used for input control of the pixel circuit gating a first scan control signal, the second transistor is configured to be turned on under the control of the first scan control signal, and the data voltage of the data signal end is applied to the control electrode of the first transistor to control the first transistor to provide data and data to the light emitting device The drive voltage associated with the data voltage at the signal terminal;
  • the storage unit comprises a first capacitor, a second capacitor and a third transistor, wherein the first capacitor and the second capacitor are connected in series at the control pole of the first transistor And a low potential, and in the initialization phase and the threshold extraction phase, providing a reference voltage for the gate of the first transistor;
  • the first pole of the third transistor is connected to the series node of the first capacitor and the second capacitor, the second pole Connected to the series node of the first transistor and the light emitting device, and in an initialization phase, an initial voltage is coupled to the second electrode of the third transistor, the control electrode of the third transistor is coupled to the second scan control signal terminal, the second scan
  • the control signal terminal is for inputting a second scan control signal, and the second scan
  • the second transistor is configured to be turned on in the initialization phase, the threshold extraction phase, and the data write phase under the control of the first scan control signal, the reference voltage being provided by the data signal terminal, and a reference voltage is coupled to the control electrode of the first transistor by a second transistor; the initial voltage is provided by the first voltage source signal terminal, and the initial voltage is coupled to the third transistor through the first transistor The second pole.
  • the reference voltage is provided by a data signal terminal, and the second transistor is configured to couple a reference voltage input to the data signal terminal to a control electrode of the first transistor during an initialization phase and a threshold extraction phase;
  • the pixel The circuit further includes a fourth transistor having a first pole connected to the series node of the first transistor and the light emitting device, a second pole connected to the third voltage source signal end, and a control pole connected to the third scan control signal end;
  • the third scan The control signal terminal is used to input a third scan control signal, and the third scan control signal controls the fourth transistor guide in the initialization phase Passing to couple an initial voltage on the signal terminal of the third voltage source to the series node of the first transistor and the light emitting device.
  • the first transistor is configured to couple an initial voltage input by the first voltage source signal terminal to a series node of the first transistor and the light emitting device in an initialization phase
  • the pixel circuit further including a fifth a transistor having a first electrode connected to the fourth voltage source signal terminal, a second electrode connected to the control electrode of the first transistor, a control electrode connected to the fourth scan control signal terminal, and a fourth scan control signal terminal for inputting the fourth scan a control signal; a fifth transistor for coupling a reference voltage on the signal source of the fourth voltage source to the gate of the first transistor during the initialization phase and the threshold extraction phase.
  • the pixel circuit further includes:
  • a fourth transistor having a first electrode connected to the series node of the first transistor and the light emitting device, a second electrode connected to the third voltage source signal terminal, a control electrode connected to the third scan control signal terminal, and a third scan control signal terminal For inputting a third scan control signal; the fourth transistor is configured to couple an initial voltage on the signal end of the third voltage source to a series node of the first transistor and the light emitting device in an initialization phase;
  • a fifth transistor having a first electrode connected to the fourth voltage source signal terminal, a second electrode connected to the control electrode of the first transistor, a control electrode connected to the fourth scan control signal terminal, and a fourth scan control signal terminal for inputting Four scan control signals; a fifth transistor for coupling a reference voltage on the signal source of the fourth voltage source to the gate of the first transistor during the initialization phase and the threshold extraction phase.
  • the initial voltage and the reference voltage are provided by a data signal terminal, and the second transistor is configured to couple an initial voltage input to the data signal terminal to a control electrode of the first transistor during an initialization phase, in a threshold extraction phase a reference voltage input to the data signal terminal is coupled to the control electrode of the first transistor;
  • the pixel circuit further includes a fourth transistor having a first pole connected to the series node of the first transistor and the light emitting device, and the second pole connected to the a control pole of a transistor, the control electrode is connected to the third scan control signal end; the third scan control signal end is used for inputting a third scan control signal, and the third scan control signal controls the fourth transistor to be turned on during the initialization phase to An initial voltage on the gate of a transistor is coupled to the series node of the first transistor and the light emitting device.
  • the initial voltage and the reference voltage are provided by a data signal terminal, and the second transistor is configured to couple a reference voltage input to the data signal terminal to a control electrode of the first transistor in a threshold extraction phase;
  • the pixel The circuit further includes a fourth transistor having a first pole connected to the series node of the first transistor and the light emitting device, a second pole connected to the data signal end, a control pole connected to the third scan control signal end, and a third scan control signal end
  • the third scan control signal controls the fourth transistor to be turned on during the initialization phase to couple the initial voltage of the data signal terminal to the series node of the first transistor and the light emitting device;
  • the initial voltage and the reference voltage are provided by the data signal terminal, and the second transistor is used. Coupling a reference voltage input to the data signal terminal to a control electrode of the first transistor during a threshold extraction phase; the pixel circuit further includes a fourth transistor having a first electrode connected to the series node of the first capacitor and the second capacitor The second pole is connected to the data signal end, the control pole is connected to the third scan control signal end; the third scan control signal end is used for inputting the third scan control signal, and the third scan control signal controls the fourth transistor to be turned on during the initialization phase.
  • the initial voltage of the data signal terminal is coupled to the series node of the first capacitor and the second capacitor.
  • the initial voltage is smaller than a threshold voltage of the light emitting device
  • a difference between the reference voltage and a threshold voltage of the first transistor is smaller than a threshold voltage of the light emitting device
  • a maximum value of the data voltage is different from the first transistor
  • the difference in threshold voltage is less than the threshold voltage of the light emitting device.
  • the present application provides a display device, including:
  • a display panel comprising any one of the above pixel circuits arranged in an array of M columns * N rows, wherein M and N are positive integers;
  • a gate driving circuit for providing a first scan control signal and a second scan control signal for the pixel circuit;
  • the gate driving circuit includes N first scan control signal lines, N second scan control signal lines, and an nth
  • the first scan control signal line is connected to the first scan control signal end of the nth row of pixel circuits, and the nth second scan control signal line is connected to the second scan control signal end of the nth row of pixel circuits; wherein n is greater than An integer equal to 1 being less than or equal to N;
  • the first scan control signal line is for providing a first scan control signal for a pixel circuit of a corresponding row; and the second scan control signal line is for providing a second pixel circuit for a corresponding row Scanning a control signal;
  • the first power line is configured to provide an initial voltage for an initial stage of the pixel circuit of the corresponding row;
  • a data driving circuit for supplying a voltage signal and a first power voltage control signal to the M data signal lines and the X first power voltage signal lines; wherein the mth data signal line is connected to the data of the mth column pixel circuit At the signal end, m is an integer greater than or equal to 1 less than or equal to M; the data signal line is used to provide a reference voltage for the pixel circuit of the corresponding column in the initialization phase and the threshold extraction phase, and to provide a gray-scale related data voltage for the data writing phase .
  • the second transistor is configured to be turned on in an initial stage, a threshold extraction stage, and a data writing stage under control of the first scan control signal, the reference voltage being provided by the data signal line, and being in the first scan
  • the reference signal is passed through the second transistor under the action of the control signal Press-coupled to the control electrode of the first transistor;
  • the initial voltage is provided by the first voltage source signal terminal, and the initial voltage is coupled to the second electrode of the third transistor and the series connection of the first capacitor and the second capacitor through the first transistor node;
  • a constant power signal of the second power line and the fifth power line that may exist is uniformly provided by an external constant voltage circuit
  • the pixel circuit further includes:
  • a fourth transistor having a first electrode connected to the series node of the first transistor and the light emitting device, a second electrode connected to the third voltage source signal terminal, a control electrode connected to the third scan control signal terminal, and a third scan control signal terminal For inputting a third scan control signal; the fourth transistor is configured to couple an initial voltage on the signal end of the third voltage source to a series node of the first transistor and the light emitting device in an initialization phase;
  • a fifth transistor having a first electrode connected to the fourth voltage source signal terminal, a second electrode connected to the control electrode of the first transistor, a control electrode connected to the fourth scan control signal terminal, and a fourth scan control signal terminal for inputting a fourth scan control signal; the fifth transistor is configured to couple the reference voltage on the signal source of the fourth voltage source to the control electrode of the first transistor during the initialization phase and the threshold extraction phase;
  • nth a scan control signal line is connected to the first scan control signal end of the nth row of pixel circuits
  • the nth second scan control signal line is connected to the second scan control signal end of the nth row of pixel circuits
  • the nth third scan The control signal line is connected to the third scan control signal end of the pixel circuit of the nth row
  • the nth fourth scan control signal line is connected to the fourth scan control signal end of the pixel circuit of the nth row, where n is greater than or equal to 1 and less than or equal to An integer of N;
  • the first scan control signal line is configured to provide a first scan control signal for a pixel circuit of a corresponding row
  • the second scan control signal line is configured to provide a second scan control signal for a pixel circuit of a corresponding row
  • the third scan control signal line is configured to provide a
  • a data driving circuit for supplying a required voltage signal to the M data signal lines, wherein the mth data signal line is connected to the data signal end of the mth column pixel circuit, wherein m is an integer greater than or equal to 1 and less than or equal to M;
  • the data signal lines are used to provide reference voltage and gray scale related data voltages for the circuits in the initialization phase and the threshold extraction phase and the data write phase, respectively, for the pixel circuits of the respective columns.
  • the constant power signals of the first power line, the second power line, the third power line, the fourth power line and the fifth power line that may be present are uniformly provided by an external constant voltage circuit.
  • the gate driving circuit does not include the third scan control signal line and the fourth scan control signal.
  • a fourth scan control signal end of the pixel circuit of the nth row is connected to the first scan control signal line of the pixel circuit of the nth row
  • a third scan control signal end of the pixel circuit of the nth row is connected to the pixel circuit of the nab row
  • a is an integer greater than or equal to 1 and less than n
  • b is an integer greater than or equal to 1 and less than na.
  • the pixel circuit further includes:
  • a fourth transistor having a first electrode connected to the series node of the first transistor and the light emitting device, a second electrode connected to the data signal line, a control electrode connected to the third scan control signal end, and a third scan control signal terminal for inputting The third scan control signal; the first supply voltage signal no longer provides an initialization voltage for the circuit, and the initialization voltage is changed to the source drive circuit for the circuit.
  • a fourth transistor for coupling an initial voltage on the data signal line to a series node of the first transistor and the light emitting device and a series node of the first capacitor and the second capacitor in an initialization phase;
  • the fourth transistor has a first pole connected to the series node of the first capacitor and the second capacitor, a second pole connected to the data signal line, a control pole connected to the third scan control signal end, and a third scan control signal
  • the terminal is used for inputting a third scan control signal; the first power supply voltage signal no longer provides an initialization voltage for the circuit, and the initialization voltage is changed to the source drive circuit for the circuit.
  • a fourth transistor for coupling an initial voltage on the data signal line to a series node of the first transistor and the light emitting device and a series node of the first capacitor and the second capacitor in an initialization phase;
  • the fourth transistor has a first electrode connected to the series node of the first transistor and the light emitting device, a second electrode connected to the control electrode of the first transistor, and a control electrode connected to the third scan control signal end;
  • the scan control signal terminal is used to input a third scan control signal;
  • the first power supply voltage signal no longer provides an initialization voltage to the circuit, and the initialization voltage is changed to the source drive circuit for the circuit.
  • a fourth transistor for coupling an initial voltage on the data signal line to a series node of the first transistor and the light emitting device and a series node of the first capacitor and the second capacitor in an initialization phase;
  • a gate driving circuit for providing scan control signals for N first scan control signal lines, N second scan control signal lines, and N third scan control signal lines;
  • the nth first scan control signal line is connected to the nth a first scan control signal end of the row pixel circuit
  • the nth second scan control signal line is connected to the second scan control signal end of the nth row pixel circuit
  • the nth third scan control signal line is connected to the nth row of pixels a third scan control signal end of the circuit
  • n is an integer greater than or equal to 1 and less than or equal to N;
  • the first scan control signal line is configured to provide a first scan control signal for a pixel circuit of a corresponding row, the second scan control signal line for providing a second scan control signal for a pixel circuit of a corresponding row, the third The scan control signal line is configured to provide a third scan control signal for the pixel circuit of the corresponding row;
  • a data driving circuit for supplying a required voltage signal to the M data signal lines, wherein the mth data signal line is connected to the data signal end of the mth column pixel circuit, wherein m is an integer greater than or equal to 1 and less than or equal to M;
  • the data signal line is used for the pixel circuit of the corresponding column
  • the threshold extraction phase and the data write phase respectively provide the circuit with an initialization voltage, a reference voltage, and a grayscale related data voltage.
  • the constant power signals of the first power line, the second power line, the third power line, the fourth power line and the fifth power line that may exist are uniformly provided by an external constant voltage circuit;
  • the pixel circuit generates the threshold voltage information of the driving tube by the source level following form, and the threshold voltage of the driving tube is generated across the first capacitor by the partial pressure of the first capacitor and the second capacitor a reference voltage related to the gray scale information, the reference voltage remains unchanged during the illumination process, so that the drive current flowing through the light emitting device is independent of the threshold voltages of the driving transistor and the light emitting device, thereby compensating for the threshold voltage deviation of the driving transistor and the light emitting device Move to solve the problem of display unevenness caused by different threshold voltages of the driving transistors across the display panel.
  • the scanning control signal overlaps to reduce the line programming time of the circuit, and the high-precision and high-frame rate display panel is required while obtaining high precision;
  • the pixel circuit adopts group programming and packet illumination to reduce the circuit complexity and increase the illumination time.
  • FIG. 1 is a structural diagram of a pixel circuit in the prior art
  • FIG. 2 is a structural diagram of a pixel circuit in the first embodiment of the present application.
  • FIG. 3 is a waveform diagram of driving signals of a pixel circuit in Embodiment 1 of the present application.
  • FIG. 4 is a structural diagram of a pixel circuit in Embodiment 2 of the present application.
  • FIG. 5 is a waveform diagram of driving signals of a pixel circuit in Embodiment 2 of the present application.
  • FIG. 6 is a structural diagram of a pixel circuit in Embodiment 3 of the present application.
  • FIG. 7 is a waveform diagram of driving signals of a pixel circuit in Embodiment 3 of the present application.
  • FIG. 8 is a structural diagram of a display device composed of a pixel circuit according to Embodiment 3 of the present application.
  • FIG. 9 is a structural diagram of a pixel circuit in Embodiment 4 of the present application.
  • FIG. 10 is a waveform diagram of driving signals of a pixel circuit in Embodiment 4 of the present application.
  • FIG. 11 is a structural diagram of a pixel circuit in Embodiment 5 of the present application.
  • FIG. 12 is a waveform diagram of driving signals of a pixel circuit in Embodiment 5 of the present application.
  • FIG. 13 is a structural diagram of a pixel circuit in Embodiment 6 of the present application.
  • FIG. 14 is a waveform diagram of driving signals of a pixel circuit in Embodiment 6 of the present application.
  • FIG. 15 is a structural diagram of a pixel circuit in Embodiment 7 of the present application.
  • FIG. 16 is a waveform diagram of driving signals of a pixel circuit in Embodiment 7 of the present application.
  • FIG. 17 is a schematic diagram of driving of all pixel circuits in a group according to Embodiment 8 of the present application.
  • 18 is a schematic diagram of driving when all pixel circuits in the eighth embodiment of the present application are divided into two groups;
  • 19 is a schematic diagram of driving when all pixel circuits in the eighth embodiment of the present application are divided into four groups;
  • FIG. 20 is a structural diagram of a pixel circuit in Embodiment 8 of the present application.
  • FIG. 21 is a waveform diagram of driving signals of a pixel circuit in Embodiment 8 of the present application.
  • Figure 22 is a structural diagram of a display device in Embodiment 8 of the present application.
  • FIG. 23 is a structural diagram of a pixel circuit in Embodiment 9 of the present application.
  • FIG. 25 is a structural diagram of a pixel circuit in Embodiment 10 of the present application.
  • 26 is a structural diagram of a pixel circuit in another embodiment of the present application.
  • Figure 27 is a structural diagram of a display device in a tenth embodiment of the present application.
  • the transistor used in the embodiment of the present application may be a transistor of any structure, such as a Field Effect Transistor (FET) or a Bipolar Junction Transistor (BJT).
  • FET Field Effect Transistor
  • BJT Bipolar Junction Transistor
  • the control electrode refers to the gate
  • the first electrode refers to the drain
  • the second electrode refers to the source
  • the control electrode refers to the base
  • the first electrode refers to the collector
  • the second electrode refers to the emitter. pole.
  • a transistor is used as a switch
  • the transistor in the display device is usually a TFT device.
  • the embodiment of the present application mainly uses a TFT as an example for description.
  • the organic light emitting diode OLED is used as the light emitting device
  • the transistor used in the present application is an N-type tube unless otherwise specified.
  • the embodiment provides a pixel circuit including a first transistor 21, a second transistor 22, a third transistor 23, a first capacitor 26, a second capacitor 27, and a light emitting device 25.
  • the first transistor 21 and the light emitting device 25 are sequentially connected in series between the first voltage source signal terminal V DD[n] and the second voltage source signal terminal V SS .
  • the control electrode of the first transistor 21 is connected to the second electrode of the second transistor 22, the first electrode of the first transistor 21 is connected to the signal terminal of the first voltage source, and the second electrode of the first transistor 21 is connected to the anode of the light emitting device 25. ;
  • the control electrode of the second transistor 22 is connected to the first scan control signal terminal V SCAN[n] for receiving the first scan control signal of the current row, and the first pole of the second transistor 22 is connected to the data signal terminal Data Line for The second electrode of the second transistor 22 is connected to the control electrode of the first transistor 21 at the data information (data voltage) on the data line Data Receiver.
  • the second transistor 22 is responsive to the first scan control signal of the current row to pass the reference voltage and the data voltage associated with the gray scale information.
  • the control electrode of the third transistor 23 is connected to the second scan control signal line V EM[n] for receiving the second scan control signal of the current row, and the first electrode of the third transistor 23 is connected to the anode of the light emitting device 25, The second pole of the three transistor 23 is coupled to the second pole of the first capacitor 26.
  • the third transistor 23 is operative to be turned on in the initialization phase, the threshold extraction phase, and the illumination phase in response to the second scan control signal of the current row.
  • the first pole of the first capacitor 26 is connected to the control electrode of the first transistor 21, the second pole is connected to the first pole of the second capacitor 27, and the second pole of the second capacitor 27 is connected to the second voltage source signal terminal V SS .
  • the voltage difference generated across the first capacitor 26 is the threshold voltage information of the driving transistor (first transistor 21), and the data writing phase is divided by the first capacitor 26 and the second capacitor 27
  • the information about the threshold voltage of the drive tube is stored at both ends of the first capacitor 26 to form a reference voltage, and the light-emitting phase couples voltage information across the OLED (light-emitting device 25) to the first transistor 21 by bootstrap.
  • the control electrode maintains the reference voltage across the first capacitor 26 unchanged.
  • the second pole of the second capacitor 27 is connected to the second voltage source signal terminal V SS .
  • the second pole of the second capacitor 27 may also be connected to a separate Five voltage source signal terminals.
  • the waveform of the driving signal of the pixel circuit in this embodiment is shown in FIG. 3.
  • one frame time T can be divided into four phases: an initialization phase, a threshold extraction phase, and a data writing phase.
  • the illuminating phase for convenience of explanation, the second transistor of the first transistor 21 and the second transistor 22 are connected to the first node A, and the first pole of the first capacitor 26 and the first pole of the second capacitor 27 are connected to the first pole
  • the two nodes B, the second pole of the first transistor 21 and the anode of the light emitting device 25 are connected to the third node C.
  • the current pixel is gated, and the first scan control signal input by the first scan control signal terminal V SCAN[n] of the current pixel changes from a low level to a high level, and the second scan control signal terminal V EM[n] inputs
  • the second scan control signal is kept high, all the transistors are turned on, and the signal input from the first voltage source signal terminal V DD[n] is converted from the high level V DDH to the low level V DDL .
  • the voltage on the data signal data line is the reference voltage V REF , then the first node A in FIG. 2 is charged to the reference voltage V REF .
  • V DDL Initial voltage
  • V TH_OLED the threshold voltage of the light-emitting device 25
  • the first scan control signal input by the first scan control signal terminal V SCAN[n] of the current pixel is maintained at a high level, and the second scan control signal input by the second scan control signal terminal V EM[n] is switched from a high level It is low, thereby turning off the third transistor 23, and therefore, the second node B and the third node C are turned off; the signal input from the first voltage source signal terminal V DD[n] is kept at a high level.
  • the voltage change on the Data Line data line is the data voltage V DATA related to the gradation.
  • the first node A also changes to V DATA . Since the first capacitor 26 and the second capacitor 27 are connected in series, the voltage at point B is Refresh to:
  • C1 and C2 are capacitance values of the first capacitor 26 and the second capacitor 27, respectively.
  • the data voltage should satisfy [V DATA ] max –V TH_T1 ⁇ V TH_OLED , where [V DATA ] max is the maximum value in the data voltage. In this way, the OLED does not emit light throughout the programming process, increasing the contrast of the display.
  • the reference voltage generated between the first capacitor 25 and the threshold voltage information and the gray scale information of the driving tube is:
  • the first scan control signal input by the current pixel first scan control signal terminal V SCAN[n] changes from a high level to a low level, and the second transistor 22 is turned off.
  • the second scan control signal input from the second scan control signal terminal V EM[n] changes from a low level to a high level, and the third transistor 23 is turned on.
  • the second node B and the third node C are connected.
  • the third node C starts to rise to the anode voltage V OLED corresponding to the illuminating when the OLED emits light, then the first node A The corresponding voltage is also raised to maintain the voltage difference between the first node A and the second node B unchanged, so the current flowing through the OLED does not change, and the expression of the current is as follows:
  • the pixel circuit provided in this embodiment can compensate for the threshold voltage drift of the driving transistor and the light emitting device, and can also solve the display unevenness caused by different threshold voltages of the driving transistors of the pixel circuits in the display panel, and the properly designed reference voltage V REF
  • the OLED device can be made to emit light during non-lighting periods, increasing contrast.
  • the threshold voltage of the TFT changes to a negative value
  • the conventional voltage-type compensation circuit that uses the diode connection to discharge to generate the threshold voltage information can no longer provide compensation, and the pixel circuit in the present embodiment can adopt the source-level follow-up form. It is advantageous to compensate for both the positive and negative threshold voltages at the same time, which is extremely advantageous in a display device using a depletion transistor as a drive tube.
  • this embodiment provides another pixel circuit, which is mainly different from the first embodiment in that a fourth transistor 24 is added, and the fourth transistor 24 is in the circuit under the control of the third scan signal.
  • the second node B and the third node C are initialized; the first voltage source signal terminal V DD input is no longer a pulse signal, but a constant high level, and initialization is completed by the fourth transistor 24.
  • the control electrode of the fourth transistor 24 is connected to the third scan control signal terminal V R[n] , the first electrode is connected to the anode of the light emitting device 25, and the second electrode is connected to the third voltage source signal terminal V CM for response.
  • the third scan control signal initializes the voltages of the second node B and the third node C to a certain low level in the initialization phase.
  • the driving signal waveform diagram of the pixel circuit is as shown in FIG. 5.
  • the one frame time T is also divided into four phases: an initialization phase, a threshold extraction phase, a data writing phase, and an illumination phase.
  • the working principle of each stage is similar to that of the first embodiment, and will not be described here.
  • the second pole of the second capacitor 27 can also be connected to a separate fifth voltage source signal terminal.
  • the pixel circuits provided in this embodiment have the same connection relationship and the same driving process, and are not described herein again.
  • the pixel circuits on the entire panel can share the signals input from the signal terminals of the same first voltage source, which is easier to control.
  • this embodiment provides another pixel circuit, which is mainly different from the second embodiment in that a fifth transistor 28 is added, and the control electrode of the fifth transistor 28 is connected to the fourth scan signal terminal V SN[n ] , the first pole is connected to the fourth voltage source signal terminal for inputting a constant reference voltage V REF , and the second pole is connected to the gate electrode of the first transistor 21 .
  • the fifth transistor 28 provides a constant reference voltage V REF for the gate of the driving transistor during the circuit initialization phase and the threshold extraction phase under the control of the fourth scan signal, which is beneficial in that the line programming time can be greatly reduced.
  • the pixel circuit is more suitable for large area, high resolution, high frame rate displays.
  • the waveform of the driving signal of the pixel circuit in this embodiment is as shown in FIG. 7.
  • One frame time T is also divided into four phases: an initialization phase, a threshold extraction phase, a data writing phase, and an illumination phase.
  • the working principle of each stage is similar to that of the first embodiment, and will not be described here.
  • the second pole of the second capacitor 27 can also be connected to a separate fifth voltage source signal terminal.
  • the initialization of the circuit is completed by the initial voltage input by the signal source of the first voltage source, and the fourth transistor 24 is not needed.
  • the signal input by the signal terminal of the first voltage source is a pulse signal;
  • the driving process of the pixel circuit in this embodiment is not described herein.
  • the embodiment further provides a display device including a display panel, a gate driving circuit 30 and a data driving circuit 40 .
  • the display panel includes a plurality of pixel arrays, wherein the pixel arrays are arranged in a matrix by M columns*N rows of pixel circuits 50, wherein M and N are positive integers, and the pixel circuit 50 adopts the pixel circuit provided in this embodiment.
  • the gate driving circuit 30 provides a scan control signal for the N first scan control signal lines, the N second scan control signal lines, the N third scan control signal lines, and the N fourth scan control signal lines;
  • the first scan control signal line is connected to the first scan control signal end of the nth row of pixel circuits, and the nth second scan control signal line is connected to the second scan control signal end of the nth row of pixel circuits, the nth third The scan control signal line is connected to the third scan control signal end of the pixel circuit of the nth row, and the nth fourth scan control signal line is connected to the fourth scan control signal end of the pixel circuit of the nth row; wherein n is greater than or equal to 1 An integer less than or equal to N.
  • the data driving circuit 40 supplies a voltage signal to the M data signal lines, and the mth data signal line is connected to the data signal end of the mth column pixel circuit, where m is an integer greater than or equal to 1 and less than or equal to M.
  • the pixel circuits 50 of the same row are connected to the same first scan control signal line 31, second scan control signal line 32, third scan control signal line 34, and fourth scan control signal line 35.
  • a scan control signal line 31, a second scan control signal line 32, a third scan control signal line 34 and a fourth scan control signal line 35 may provide a first scan control signal and a second scan required for the pixel circuit of the current row. a control signal, a third scan control signal, and a fourth scan control signal.
  • the pixel circuits of the same column are all connected to the same data signal line 41. When the fourth scan control signal changes from low level to high level, the line is gated, and then the current line of the gate is operated.
  • the data signal line 41 supplies the pixel circuit with a reference level V REF and a gray scale related data voltage V DATA during the data writing phase.
  • the pixel array is given in the form of a 3*3 matrix, and the actual pixel array may be selectively arranged according to the situation; the switch tube in this embodiment may also be P. Type tube, but it is necessary to make corresponding changes to the circuit connection relationship and drive signal according to the characteristics of the P-type tube, and will not be described here.
  • the display device and the pixel circuit provided by the embodiment do not affect the row programming time of the circuit in the initialization phase and the threshold extraction phase.
  • the row programming time of each row includes only the data writing time (the time required for the voltage division of the two capacitors).
  • the threshold extraction is performed in the row under the control of the fourth scan control signal, which occupies the illumination time (the threshold extraction time is much smaller than the illumination time), and thus does not affect the high frame rate and the high resolution. The precision of threshold extraction.
  • the fourth scan control signal line is not included, and the fourth scan control signal end of the nth row of pixel circuits is connected to the first scan control signal line of the n-1th row of pixel circuits.
  • FIG. 9 and FIG. 10 are respectively a structural diagram and a driving waveform diagram of the pixel circuit in the embodiment.
  • the pixel circuit is different from the third embodiment in that the gate electrode of the fifth transistor is connected to the first scan signal line of the previous row.
  • the row circuit is initialized and thresholded using the first scan signal of the previous row.
  • the row programming time of each row includes the initialization and threshold extraction time (the time of data writing is less than the sum of the initialization and threshold extraction times).
  • the specific driving process is the same as that of the third embodiment, the only difference is that the first scanning signal of the previous row works at this time each time the fourth scanning signal works.
  • the gate drive circuit only needs to generate the first scan control signal, the second scan control signal, and the third scan control signal.
  • the advantage of this is that the complexity of the peripheral circuit can be reduced, and the scanning control signal of the pixel circuit is also reduced, and the aperture ratio is larger.
  • the initialization of the pixel circuit is controlled by a signal input from the signal source of the first voltage source, the first voltage source signal being a pulse signal; and the pixel circuit not including the initialization transistor, ie, the fourth transistor 24.
  • the pixel circuit includes only the first scan control signal and the second scan control signal.
  • the difference between this embodiment and the fourth embodiment is that the fourth scan control signal end of the pixel circuit of the nth row is connected to the first scan control signal line of the pixel circuit of the n-3th row.
  • FIG. 11 is a structural diagram of a pixel circuit of the display device in the embodiment.
  • the main difference between the pixel circuit and the pixel circuit in the third embodiment is that the control electrode of the fifth transistor 28 is connected to the first scan control signal line of the pixel circuit of the n-3th row, and the fifth transistor 28 is The first scan control signal of the pixel circuit of the n-3th row provides a constant reference level V REF for the gate of the drive transistor during circuit initialization and threshold extraction, which is beneficial in utilizing each
  • the overlap of the first scan signals can greatly reduce the line time.
  • the equivalent line time is reduced to 1/4 of the line programming time in the first embodiment and the second embodiment.
  • the threshold extraction time is twice the line time, making the pixel circuit more suitable for large area, high resolution, high frame rate displays.
  • the control electrode of the fifth transistor 28 is connected to the first scan control signal line of the n-3th row, the first electrode is connected to the fourth voltage source signal terminal, and the second electrode is connected to the control electrode of the first transistor 21 for In response to the first scan control signal of row n-3, a stable reference level V REF is provided for the gate of the drive transistor during the initialization and threshold extraction phases.
  • the waveform of the driving signal of the pixel circuit in this embodiment is as shown in FIG. 12, and one frame time T is also divided into four phases: an initialization phase, a threshold extraction phase, a data writing phase, and an illumination phase.
  • the working principle of each stage is similar to that of the first embodiment, and will not be described here.
  • the second pole of the second capacitor 27 can also be connected to a separate fifth voltage source signal terminal, and the fifth voltage source signal terminal is connected to the fifth power source line of the gate drive circuit.
  • the initialization of the pixel circuit is completed by the signal input from the signal source of the first voltage source, and the fourth transistor 24 is not needed.
  • the signal input by the signal source of the first voltage source is a pulse signal;
  • the driving manner of the pixel circuit in the embodiment is not described herein.
  • the main advantage of the embodiment is that while obtaining the reduced row programming time, one scanning control signal line can be reduced, making the peripheral circuit simpler.
  • the display panel is similar to the fourth embodiment, and details are not described herein again. Only the control electrode of the fifth transistor of the pixel circuit of the nth row is connected to the first scan signal line V SCAN[n-3] of the n-3th row instead of the first scan signal line V of the n-1th row. SCAN[n-1] .
  • the fourth scan control signal end of the nth row of pixel circuits may be connected to the first scan control signal line of the n-th row of pixel circuits, where a is an integer greater than or equal to 1 and less than n.
  • the present embodiment provides another display device, which differs from the third embodiment in that the gate driving circuit does not include the third scan control signal line and the fourth scan control signal line, and the fourth scan control of the nth row of pixel circuits
  • the signal end is connected to the first scan control signal line of the pixel circuit of the nath row
  • the third scan control signal end of the pixel circuit of the nth row is connected to the first scan control signal line of the pixel circuit of the nab row
  • a is An integer greater than or equal to 1 and less than n
  • b is an integer greater than or equal to 1 and less than na.
  • the first scan control signal of the n-th row pixel circuit and the first scan control signal of the n-a-b row pixel circuit have a high level superposition period, which is an initialization phase of the nth row pixel circuit.
  • FIG. 13 is a structural diagram of a pixel circuit of the display device in the embodiment.
  • the main difference between the pixel circuit in this embodiment and the pixel circuit in the third embodiment is that the control electrodes of the fourth transistor 24 and the fifth transistor 28 are both connected to the first scan control signal line of the pixel circuit of the previous row, such as The current row is the nth row, the fourth transistor 24 is connected to the first scan control signal line of the pixel circuit of the n-5th row, and the gate of the fifth transistor 28 is connected to the pixel circuit of the n-3th row.
  • the fourth transistor 24 is initialized in the circuit by the first scan control signal provided by the first scan control signal line V SCAN[n-5] of the pixel circuit of the n-5th row.
  • the phase provides the initialized low level V LL to the connected second node B and the second node C, and the fifth transistor 28 is provided in the first scan control signal line V SCAN[n-3] of the pixel circuit of the n-3th row.
  • the first scan control signal acts to provide a constant reference level V REF for the gate of the drive transistor during the circuit initialization phase and the threshold extraction phase. This is advantageous in that the third scan control signal of the current row can be removed.
  • Line and fourth scan control letter The line greatly reduces the complexity of the peripheral circuit; by using the overlap of the first scan signals, the line time can be greatly reduced, and in the case where the data write time is constant, the equivalent line time is reduced to the embodiment.
  • the control electrode of the fourth transistor 24 is connected to the first scan control signal line of the n-5th row, the first electrode is connected to the anode of the light emitting device, and the second electrode is connected to the second electrode of the first transistor 21, the fourth transistor 24 initializing the circuit under the action of the first scan control signal of the n-5th row;
  • the control electrode of the fifth transistor 28 is connected to the first scan control signal line of the n-3th row, and the first pole is connected to the fourth a power supply line, the second pole being coupled to the control electrode of the first transistor 21 for responding to the first scan control signal of the n-3th row, providing a stable reference level for the control electrode of the drive tube during the initialization phase and the threshold extraction phase V REF .
  • the waveform of the driving signal of the pixel circuit in this embodiment is as shown in FIG. 14.
  • One frame time T is also divided into four phases: an initialization phase, a threshold extraction phase, a data writing phase, and an illumination phase.
  • the working principle of each stage is similar to that of the first embodiment, and will not be described here.
  • the present embodiment is more effective in utilizing the first scan signal of the preceding row, so that the row scan signal of the circuit includes only the first scan signal and the second scan signal, and the pixel for the progressive illumination
  • peripheral circuits are simplified to the utmost. With the overlap of the first scan signals, the row programming time can be reduced while obtaining a longer threshold extraction time, making the pixel circuit more suitable for the needs of large area, high resolution and high frame rate displays.
  • the display devices provided by the above embodiments are all implemented in the form of progressive illumination, and the peripheral circuits are relatively complicated. Both embodiments described below adopt a form of concentrated illumination.
  • the seventh embodiment adopts a common centralized illumination mode, and the initialization and threshold extraction processes of all the pixel circuits on the entire panel are performed simultaneously, after all the pixel circuits on the panel complete initialization and threshold extraction, in order to make the whole programming process
  • the OLED does not emit light, the signal provided by the first power line V DD becomes a low level, and the third transistors of all the pixel circuits are turned off, and data writing is started line by line. When the data writing is completed, the first power source is turned on.
  • the signal provided by line V DD is switched from low level to high level, the third transistor of all pixel circuits on the panel is turned on, and the pixel circuit enters the illumination mode. Due to the centralized initialization and threshold extraction, and the form of concentrated illumination, all of the pixel circuits on the entire panel require only a first power line V DD and a second scan control signal line.
  • the disadvantage of concentrated illumination is that the illumination time is short, the illumination current required for the illumination device to emit light is large, and the larger illumination current degrades the illumination device more significantly.
  • the driving method of the group programming is given in the eighth embodiment.
  • all the pixel circuits on the panel are divided into groups c (c is an integer greater than or equal to 1 less than N) from top to bottom, and the programming and illumination of the circuit are modularized in groups. That is, the initialization and threshold extraction are performed simultaneously in the group, and the data is written line by line. After the data is written, the group emits light; when one group is programmed, the illumination of other groups is not affected, so that the time of illumination can be made large. The increase is in scope.
  • FIG. 15 is a structural diagram of a pixel circuit of the display device in the embodiment.
  • the main difference between the pixel circuit in this embodiment and the first embodiment is that the signal provided by the first power line V DD and the signal provided by the second scanning signal line V EM no longer distinguish which line, and all the lines share the same The first power line V DD and the second scan signal line V EM .
  • the first pole of the first transistor 21 is connected to the first power line V DD , the second pole is connected to the anode of the light emitting device; the gate of the third transistor 23 is connected to the unified second scan control line V EM , first The pole is connected to the anode of the light emitting device, the second pole is connected to the second pole of the first capacitor, and the third transistor 23 is turned on in the initialization phase, the threshold extraction phase and the light emitting phase in response to the control signal provided by the second scan control line V EM .
  • the waveform of the driving signal of the pixel circuit in this embodiment is as shown in FIG. 16.
  • One frame time T is also divided into four phases: an initialization phase, a threshold extraction phase, a data writing phase, and an illumination phase.
  • the first scan signal line V SCAN of all the rows on the panel is at a high level
  • the first power line V DD is switched from a high level to a low level
  • the second scan control signal line V EM is at a high level
  • all on the panel
  • the second transistor 22 and the third transistor 23 are both turned on, and the first node A of all the pixel circuits is charged to the reference voltage V REF , at which time the second node B and the third node C are connected by the third transistor 23, the second node B and the third node C are discharged to a certain low level V LL , V LL ⁇ V TH_OLED provided by the second power line V DD .
  • V TH_OLED is the threshold voltage of the light emitting device 25, therefore, the light emitting device 25 does not emit light, and all the pixel circuits on the panel are initialized.
  • the first scan signal line V SCAN of all the rows on the panel is kept at a high level, the first power line V DD is switched from a low level to a high level, and the second scan control signal line V EM is at a high level, the second transistor 22 and the third transistor 23 are both turned on, the first node A of all the pixel circuits is kept as the reference voltage V REF , at which time the second node B and the third node C are connected by the switch tube, and the first power line V DD is paired with the second node B and the third node C are charged until the first transistor 21 is turned off, and charging of point B and point C is stopped.
  • the second scan control signal line V EM is switched from a high level to a low level, and the third transistor of all the pixel circuits on the panel is turned off, and therefore, the second node B and the third node C are disconnected; the first power line V DD transitions from a high level to a low level to prevent OLEDs from illuminating during prolonged programming and to place the OLED in a negative bias state to reduce degradation of the OLED; all pixel circuits on the panel begin to write data line by line.
  • the first scan control signal line V SCAN[n] of the current line transitions from a low level to a high level, the first transistor 21 of the current line is turned on, and data writing to the current line is started, and the data line is on the Data Line.
  • the voltage is the current line grayscale related to the data voltage V DATA . Since the first capacitor 26 and the second capacitor 27 are connected in series, the voltage of the second node B in FIG. 15 is finally refreshed to:
  • the reference voltage generated between the first capacitor 25 and the threshold voltage information and the gray scale information of the driving tube is:
  • the first scan control signal line V SCAN of all the rows becomes the low level, then all the second transistors 22 are turned off; the first power supply line V DD is converted from the low level to the high level.
  • Level, the second scan control signal line V EM changes from low level to high level, then the third transistor 23 of all the pixel circuits is turned on, the second node B and the third node C are connected, and the third node C follows The OLED light emission starts to rise to the anode voltage V OLED corresponding to the light emission.
  • the OLED can be made to emit light during the entire programming process to obtain a high-contrast display; the OLED is in a negative bias state during the data writing phase, which can reduce the OLED. Degraded.
  • all the pixel circuits on the panel are divided into groups c (c is an integer greater than or equal to 1 less than N) from top to bottom, and one group is one module.
  • groups c c is an integer greater than or equal to 1 less than N
  • programming and illumination of all pixel circuits are simultaneously When a group is programmed, it does not affect the illumination of other groups.
  • all the pixel circuits share the first power line and the second scan control signal line.
  • the display device provided in this embodiment is the same as that in the seventh embodiment.
  • Fig. 17 is a view schematically showing the programming and illuminating of the pixel circuit on the panel in the seventh embodiment in the case of no grouping, wherein 1 is an initialization phase, 2 is a threshold extraction phase, 3 is a data writing phase, and 4 is an illuminating phase. If the initialization of the pixel circuit, the threshold extraction and the time of data writing are not changed, after the grouping is adopted, the programming and illumination of all the pixel circuits on the panel are as shown in FIGS. 18 and 19, wherein FIG. 18 is to divide the pixel circuit into In the case of two groups, Fig. 19 shows a case where the pixel circuits are divided into four groups.
  • the description will be made in two groups. All the pixel circuits on the panel are divided into two groups, the first power line of the first group is V DD1 , and the second scan control signal line is V EM1 . The first power line of the second group is V DD2 and the second scan control signal line is V EM2 .
  • the connection relationship in the circuit does not change, and the data line of the pixel circuit on the entire panel does not change.
  • the driving signal waveform diagram of the pixel circuit in this embodiment is as shown in FIG. 21.
  • the driving process of the pixel circuit includes the following four stages: an initialization phase, a threshold extraction phase, a data writing phase, and an illumination phase.
  • the initialization and threshold extraction of all pixel circuits is Simultaneously, each row of pixel circuits in the group is performed row by row when data is written. After each row in the group completes data writing, the group enters the illumination mode; at most one group at a time is programmed, and a group of programming does not affect Glow to other groups.
  • the working principle of each stage is similar to that of the seven cases. The difference is that the programming of all the pixel circuits on the panel in the seventh embodiment is performed simultaneously. In the eighth embodiment, the programming of the pixel circuits in the same group is performed simultaneously. No longer.
  • the second pole of the second capacitor 27 can also be connected to a separate fifth voltage source signal terminal.
  • FIG. 22 shows a display device composed of the pixel circuit of the present embodiment, the display device including a display panel, a gate drive circuit 30, and a data drive circuit 40.
  • the display panel includes a plurality of pixel arrays, wherein the pixel arrays are arranged in a matrix by M columns * N rows of pixel circuits 50, wherein M and N are both positive integers, and the pixel circuit 50 employs a pixel circuit provided by 24.
  • the pixel circuits 50 of the same row are all connected to the same set of first scan control signal lines 31, and the first scan control signal lines 31 can provide the required first scan control signals for the pixel circuits of the current row. .
  • the pixel circuits of the same column are connected to the same data signal line 41, and the data signal line 41 can provide the reference voltage V REF required for the initialization phase and the threshold extraction phase; when the first scan control signal line changes from a low level to a high level Usually, the line is strobed, and then the data is written to the current line.
  • the data signal line 41 can provide the gradation-related data voltage V DATA required for the data writing phase.
  • the first set of first power line 37 and second scan control signal line 38 provide a first set of signals V DD1 and a second scan control signal V EM1 , respectively, which are also provided by the data drive circuit.
  • the second set of first power line 39 and second scan control signal line 310 provide a second set of signals V DD2 and a second scan control signal V EM2 , respectively .
  • the pixel array is given in the form of a 4*4 matrix, and the actual pixel array may be selectively arranged according to the situation; the switch tube in this embodiment may also be a P. Type tube, but it is necessary to make corresponding changes to the circuit connection relationship and drive signal according to the characteristics of the P-type tube.
  • the embodiment provides another pixel circuit.
  • the initial voltage and the reference voltage are provided by the data signal end, and the second transistor is used to couple the initial voltage input by the data signal end to the first node A in the initialization phase.
  • the reference voltage input to the data signal terminal is coupled to the first node A during the threshold extraction phase;
  • the pixel circuit further includes a fourth transistor having a first pole connected to the third node C and a second pole connected to the first node A, the control pole Connected to the third scan control signal terminal;
  • the third scan control signal terminal is configured to input a third scan control signal, and the third scan control signal controls the fourth transistor to be turned on during the initialization phase to couple the initial voltage on the first node A Go to the third node C.
  • the main difference between this embodiment and the second embodiment is that the initial voltage is provided by the data signal terminal instead of the third voltage source signal terminal.
  • the waveform of the driving signal of the pixel circuit is as shown in FIG. 24.
  • One frame time T is also divided into four phases: an initialization phase, a threshold extraction phase, a data writing phase, and an illumination phase.
  • the working principle of each stage is similar to that of the first embodiment, and will not be described here.
  • the second pole of the second capacitor 27 can also be connected to a separate fifth voltage source signal terminal.
  • this embodiment provides another pixel circuit.
  • the initial voltage and the reference voltage are provided by the data signal terminal, and the second transistor is used to couple the reference voltage input to the data signal terminal to the first node A in the threshold extraction phase.
  • the pixel circuit further includes a fourth transistor having a first electrode connected to the third node C, a second electrode connected to the data signal terminal, a control electrode connected to the third scan control signal terminal, and a third scan control signal terminal for inputting A third scan control signal, the third scan control signal controlling the fourth transistor to be turned on during the initialization phase to couple the initial voltage of the data signal terminal to the third node C.
  • the main difference between this embodiment and the second embodiment is that the initial voltage is provided by the data signal terminal instead of the third voltage source signal terminal.
  • the waveform of the driving signal of the pixel circuit is as shown in FIG. 24.
  • One frame time T is also divided into four phases: an initialization phase, a threshold extraction phase, a data writing phase, and an illumination phase.
  • the driving process is the same as that in Embodiment 9, and will not be described again here.
  • the first pole of the fourth transistor 24 can also be connected to the second node B, and the second pole is connected to The data signal end can also be used for initialization.
  • the waveform of the driving signal of the pixel circuit is the same as that of FIG. 24, and the driving process is the same as that of Embodiment 9, and details are not described herein again.
  • the present embodiment further provides a display device.
  • the display device includes a display panel, a gate driving circuit 30, and a data driving circuit 40.
  • the display panel includes a plurality of pixel arrays, wherein the pixel arrays are arranged in a matrix by M columns*N rows of pixel circuits 50, wherein M and N are positive integers, and the pixel circuit 50 adopts the pixel circuit provided in this embodiment.
  • the gate driving circuit 30 provides a scan control signal for the N first scan control signal lines, the N second scan control signal lines, and the N third scan control signal lines; the nth first scan control signal line is connected to the a first scan control signal end of the n-line pixel circuit, the nth second scan control signal line is connected to the second scan control signal end of the n-th row pixel circuit, and the nth third scan control signal line is connected to the n-th row a third scan control signal terminal of the pixel circuit; wherein n is an integer greater than or equal to 1 and less than or equal to N.
  • the data driving circuit 40 supplies a voltage signal to the M data signal lines, and the mth data signal line is connected to the data signal end of the mth column pixel circuit, where m is an integer greater than or equal to 1 and less than or equal to M.
  • the pixel circuits 50 of the same row are connected to the same first scan control signal line 31, the second scan control signal line 32, and the third scan control signal line 34.
  • the first scan control signal line 31, The second scan control signal line 32, the third scan control signal line 34 can provide the first scan control signal, the second scan control signal, and the third scan control signal for the pixel circuit of the current row.
  • the pixel circuits of the same column are all connected to the same data signal line 41.
  • the first scan control signal changes from a low level to a high level, the line is gated, and then the current line of the gate is operated.
  • the data signal line 41 supplies the pixel circuit with an initialization voltage V LL at the data writing stage, and the reference level V REF is the data voltage V DATA associated with the gradation.
  • the first power voltage signal and the second power voltage signal are uniformly provided by a peripheral constant voltage circuit.
  • the pixel array is given in the form of a 3*3 matrix, and the actual pixel array may be selectively arranged according to the situation; the switch tube in this embodiment may also be P. Type tube, but it is necessary to make corresponding changes to the circuit connection relationship and drive signal according to the characteristics of the P-type tube, and will not be described here.

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Abstract

一种显示装置及其像素电路。像素电路通过源级跟随的形式产生驱动晶体管（21）的阈值电压信息，通过第一电容（26）和第二电容（27）的分压在第一电容（26）两端产生驱动晶体管（21）的阈值电压和灰度信息有关的基准电压，发光过程中基准电压保持不变，使得流过发光器件（25）的驱动电流与驱动晶体管（21）和发光器件（25）的阈值电压无关，从而补偿驱动晶体管（21）和发光器件（25）的阈值电压偏移，解决显示不均匀的问题。显示装置采用逐行发光方式时，采用扫描控制信号交叠的形式，以减少电路的行编程时间，在获得高精度的同时满足高分辨率、高帧频显示面板的需求；显示装置采用集中发光方式时，像素电路采用分组编程、分组发光的方式，以减小电路复杂度的同时增加发光时间。

Description

一种显示装置及其像素电路 技术领域
本申请涉及显示技术领域，具体涉及一种显示装置及其像素电路。
背景技术
有机发光二极管(OLED，Organic Light-Emitting Diode)显示因具有高亮度、高发光效率、宽视角、低功耗、低制造成本等优点,近年来被人们广泛研究，并迅速应用到新一代的显示器件中。OLED显示按像素驱动方式可以分为PMOLED(Passive Matrix OLED，无源矩阵OLED)和AMOLED(Active Matrix OLED，有源矩阵OLED)两种。PMOLED虽然制造成本低，但其具有交叉串扰、需要的驱动电流大，因而存在使用寿命短、功耗高等缺点，不能满足大面积、高分辨率的显示要求。相比之下，AMOLED避免了占空比和交叉串扰等问题，所需要的驱动电流较小、功耗较低，因而寿命更长。AMOLED更容易满足大面积、高分辨率、高灰度级显示的需要。
传统的AMOLED像素电路由两个薄膜晶体管(TFT，Thin Film Transistor)和一个存储电容构成，如图1所示，该像素电路包括驱动晶体管11、开关晶体管12、存储电容13和发光器件OLED14，扫描控制信号线15上的信号控制开关晶体管12，采样数据信号线16上的数据信号，提供给驱动晶体管11的栅极，使得驱动晶体管11产生OLED14所需要的电流，从而产生所需要的灰度，并将该灰度信息存储在存储电容13中，存储电容13保持采样到的数据信息直到下一帧。该像素电路中流过OLED14的电流可以表示为：
Figure PCTCN2016076554-appb-000001
其中，μn和Cox分别为驱动晶体管11的有效场效应迁移率和单位面积的栅电容，W和L分别为TFT器件的有效沟道宽度和沟道长度。VG为驱动晶体管11的栅极电位，VOLED为OLED 14发光过程中两端的偏压，VTH为驱动晶体管11的阈值电压。这种电路结构虽然简单，但是当驱动晶体管11的阈值电压VTH漂移、OLED 14随着时间而退化造成VOLED增加或采用多晶硅材料导致面板各处驱动晶体管阈值电压不均匀时，流过OLED14的电流会随着时间或空间位置的变化而变化，从而导致显示的不均匀问题。
发明内容
本申请提供一种显示装置及其像素电路，能够补偿驱动晶体管和发 光器件的阈值电压偏移，还能够解决因显示面板各处驱动晶体管阈值电压不同而导致的显示不均匀问题。
根据本申请的第一方面，本申请提供了一种像素电路，包括：
所述像素电路的一帧周期依次包括初始化阶段、阈值提取阶段、数据写入阶段和发光阶段；所述像素电路包括：
串联在高电位和低电位之间的第一晶体管和发光器件，第一晶体管用于在发光阶段导通为发光器件提供驱动电流，发光器件用于发射强度与流过电流相关的光；所述高电位由第一电压源信号端提供，所述低电位由第二电压源信号端提供；
第二晶体管，其连接在数据信号端和第一晶体管的控制极之间，第二晶体管的控制极连接到第一扫描控制信号端，第一扫描控制信号端用于输入控制该像素电路选通的第一扫描控制信号，第二晶体管用于在第一扫描控制信号的控制下导通，将数据信号端的数据电压施加到第一晶体管的控制极，以控制第一晶体管为发光器件提供与数据信号端的数据电压相关的驱动电流；
存储单元，其连接在第一晶体管的控制极和第二电压源信号端之间，或连接在第一晶体管的控制极和第五电压源信号端之间，第二电压源信号端和第五电压源信号端用于提供一低电位，用于存储数据信号端的数据电压；存储单元包括第一电容、第二电容和第三晶体管，第一电容和第二电容串联在第一晶体管的控制极和低电位之间，并在初始化阶段和阈值提取阶段，为第一晶体管的控制极提供一参考电压；第三晶体管的第一极连接在第一电容和第二电容的串联节点，第二极连接在第一晶体管和发光器件的串联节点上，并在初始化阶段，将一初始电压耦合到第三晶体管的第二极，第三晶体管的控制极连接到第二扫描控制信号端，第二扫描控制信号端用于输入第二扫描控制信号，第二扫描控制信号在数据写入阶段控制第三晶体管截止。
在第一种实施例中，第二晶体管用于在第一扫描控制信号的控制下在初始化阶段、阈值提取阶段和数据写入阶段导通，所述参考电压由数据信号端提供，并在第一扫描控制信号的作用下，通过第二晶体管将参考电压耦合到第一晶体管的控制极；所述初始电压由第一电压源信号端提供，并通过第一晶体管将初始电压耦合到第三晶体管的第二极。
在第二种实施例中，所述参考电压由数据信号端提供，第二晶体管用于在初始化阶段和阈值提取阶段将数据信号端输入的参考电压耦合到第一晶体管的控制极；所述像素电路还包括第四晶体管，其第一极连接到第一晶体管和发光器件的串联节点上，第二极连接到第三电压源信号端，控制极连接到第三扫描控制信号端；第三扫描控制信号端用于输入第三扫描控制信号，第三扫描控制信号在初始化阶段控制第四晶体管导 通，以将第三电压源信号端上的初始电压耦合到第一晶体管和发光器件的串联节点上。
在第三种实施例中，所述第一晶体管用于在初始化阶段将第一电压源信号端输入的初始电压耦合到第一晶体管和发光器件的串联节点上，所述像素电路还包括第五晶体管，其第一极连接到第四电压源信号端，第二极连接到第一晶体管的控制极，控制极连接到第四扫描控制信号端；第四扫描控制信号端用于输入第四扫描控制信号；第五晶体管用于在初始化阶段和阈值提取阶段将第四电压源信号端上的参考电压耦合到第一晶体管的控制极。
在第四种实施例中，所述像素电路还包括：
第四晶体管，其第一极连接到第一晶体管和发光器件的串联节点上，第二极连接到第三电压源信号端，控制极连接到第三扫描控制信号端；第三扫描控制信号端用于输入第三扫描控制信号；第四晶体管用于在初始化阶段将第三电压源信号端上的初始电压耦合到第一晶体管和发光器件的串联节点上；
第五晶体管，其第一极连接到第四电压源信号端，第二极连接到第一晶体管的控制极，控制极连接到第四扫描控制信号端；第四扫描控制信号端用于输入第四扫描控制信号；第五晶体管用于在初始化阶段和阈值提取阶段将第四电压源信号端上的参考电压耦合到第一晶体管的控制极。
在第五种实施例中，所述初始电压和参考电压由数据信号端提供，第二晶体管用于在初始化阶段将数据信号端输入的初始电压耦合到第一晶体管的控制极，在阈值提取阶段将数据信号端输入的参考电压耦合到第一晶体管的控制极；所述像素电路还包括第四晶体管，其第一极连接到第一晶体管和发光器件的串联节点上，第二极连接到第一晶体管的控制极，控制极连接到第三扫描控制信号端；第三扫描控制信号端用于输入第三扫描控制信号，第三扫描控制信号在初始化阶段控制第四晶体管导通，以将第一晶体管控制极上的初始电压耦合到第一晶体管和发光器件的串联节点上。
在第六种实施例中，所述初始电压和参考电压由数据信号端提供，第二晶体管用于在阈值提取阶段将数据信号端输入的参考电压耦合到第一晶体管的控制极；所述像素电路还包括第四晶体管，其第一极连接到第一晶体管和发光器件的串联节点上，第二极连接到数据信号端，控制极连接到第三扫描控制信号端；第三扫描控制信号端用于输入第三扫描控制信号，第三扫描控制信号在初始化阶段控制第四晶体管导通，以将数据信号端的初始电压耦合到第一晶体管和发光器件的串联节点上；
或者，所述初始电压和参考电压由数据信号端提供，第二晶体管用 于在阈值提取阶段将数据信号端输入的参考电压耦合到第一晶体管的控制极；所述像素电路还包括第四晶体管，其第一极连接到第一电容和第二电容的串联节点上，第二极连接到数据信号端，控制极连接到第三扫描控制信号端；第三扫描控制信号端用于输入第三扫描控制信号，第三扫描控制信号在初始化阶段控制第四晶体管导通，以将数据信号端的初始电压耦合到第一电容和第二电容的串联节点上。
进一步，所述初始电压小于所述发光器件的阈值电压，所述参考电压与第一晶体管的阈值电压的差小于所述发光器件的阈值电压，所述数据电压中的最大值与第一晶体管的阈值电压的差小于所述发光器件的阈值电压。
根据本申请的第二方面，本申请提供了一种显示装置，包括：
显示面板，其包括以M列*N行阵列式排布的上述任意一种像素电路，M和N为正整数；
栅极驱动电路，其用于为像素电路提供第一扫描控制信号和第二扫描控制信号；栅极驱动电路包括N根第一扫描控制信号线、N根第二扫描控制信号线、第n根第一扫描控制信号线连接到第n行像素电路的第一扫描控制信号端，第n根第二扫描控制信号线连接到第n行像素电路的第二扫描控制信号端；其中，n为大于等于1小于等于N的整数；所述第一扫描控制信号线用于为相应行的像素电路提供第一扫描控制信号；所述第二扫描控制信号线用于为相应行的像素电路提供第二扫描控制信号；所述第一电源线用于为相应行的像素电路在初始化阶段提供初始电压；
数据驱动电路，其用于为M根数据信号线和X根第一电源电压信号线提供电压信号和第一电源电压控制信号；其中，第m根数据信号线连接到第m列像素电路的数据信号端，m为大于等于1小于等于M的整数；所述数据信号线用于为相应列的像素电路在初始化阶段和阈值提取阶段提供参考电压以及为数据写入阶段提供灰度有关的数据电压。其中，X为大于等于1小于等于N的正整数，X的大小取决于面板上同时进行初始化和阈值提取的像素电路的多少；如果每次有x行像素电路进行初始化，则X＝N/x；如果X＝N，则该面板上的像素电路是逐行发光的；如果X＝1，则面板上所有的像素电路是同时发光的，如果X为大于1小于N的正整数，则面板上所有的像素电路被分成了X组，每组内的像素电路同时完成初始化，阈值提取和发光过程；所述第一电源电压信号线为像素电路提供第一电压源信号。
所述像素电路中，第二晶体管用于在第一扫描控制信号的控制下在初始阶段、阈值提取阶段和数据写入阶段导通，所述参考电压由数据信号线提供，并在第一扫描控制信号的作用下，通过第二晶体管将参考电 压耦合到第一晶体管的控制极；所述初始电压由第一电压源信号端提供，并通过第一晶体管将初始电压耦合到第三晶体管的第二极以及第一电容和第二电容的串联节点；
第二电源线以及可能存在的第五电源线上恒定的电源信号由外部恒压电路统一提供；
在第二种实施例中，所述像素电路还包括：
第四晶体管，其第一极连接到第一晶体管和发光器件的串联节点上，第二极连接到第三电压源信号端，控制极连接到第三扫描控制信号端；第三扫描控制信号端用于输入第三扫描控制信号；第四晶体管用于在初始化阶段将第三电压源信号端上的初始电压耦合到第一晶体管和发光器件的串联节点上；
第五晶体管，其第一极连接到第四电压源信号端，第二极连接到第一晶体管的控制极，控制极连接到第四扫描控制信号端；第四扫描控制信号端用于输入第四扫描控制信号；第五晶体管用于在初始化阶段和阈值提取阶段将第四电压源信号端上的参考电压耦合到第一晶体管的控制极；
栅极驱动电路，为N根第一扫描控制信号线、N根第二扫描控制信号线、N根第三扫描控制信号线、N根第四扫描控制信号线提供扫描控制信号，第n根第一扫描控制信号线连接到第n行像素电路的第一扫描控制信号端，第n根第二扫描控制信号线连接到第n行像素电路的第二扫描控制信号端，第n根第三扫描控制信号线连接到第n行像素电路的第三扫描控制信号端，第n根第四扫描控制信号线连接到第n行像素电路的第四扫描控制信号端其中，n为大于等于1小于等于N的整数；所述第一扫描控制信号线用于为相应行的像素电路提供第一扫描控制信号，所述第二扫描控制信号线用于为相应行的像素电路提供第二扫描控制信号，所述第三扫描控制信号线用于为相应行的像素电路提供第三扫描控制信号，所述第四扫描控制信号线用于为相应行的像素电路提供第四扫描控制信号；
数据驱动电路，为M根数据信号线提供所需要的电压信号，其中第m根数据信号线连接到第m列像素电路的数据信号端，其中，m为大于等于1小于等于M的整数；所述数据信号线用于为相应列的像素电路在初始化阶段和阈值提取阶段以及数据写入阶段分别为电路提供参考电压和灰度有关的数据电压。
所述第一电源线、第二电源线、第三电源线，第四电源线和可能存在的第五电源线上恒定的电源信号由外部恒压电路统一提供。
在第四种实施例中，根据上述第二种实施例提供的显示装置，进一步，所述栅极驱动电路不包括第三扫描控制信号线和第四扫描控制信号 线，第n行像素电路的第四扫描控制信号端连接到第n-a行像素电路的第一扫描控制信号线上，第n行像素电路的第三扫描控制信号端连接到第n-a-b行像素电路的第一扫描控制信号线上，其中，a为大于等于1小于n的整数，b为大于等于1小于n-a的整数。
在第四种实施例中，所述像素电路还包括：
第四晶体管，其第一极连接到第一晶体管和发光器件的串联节点上，第二极连接到数据信号线，控制极连接到第三扫描控制信号端；第三扫描控制信号端用于输入第三扫描控制信号；第一电源电压信号不再为电路提供初始化电压，初始化电压改有源极驱动电路为电路提供。第四晶体管用于在初始化阶段将数据信号线上的初始电压耦合到第一晶体管和发光器件的串联节点以及第一电容和第二电容的串联节点上；
或者所述第四晶体管，其第一极连接到第一电容和第二电容的串联节点上，第二极连接到数据信号线，控制极连接到第三扫描控制信号端；第三扫描控制信号端用于输入第三扫描控制信号；第一电源电压信号不再为电路提供初始化电压，初始化电压改有源极驱动电路为电路提供。第四晶体管用于在初始化阶段将数据信号线上的初始电压耦合到第一晶体管和发光器件的串联节点以及第一电容和第二电容的串联节点上；
或者所述第四晶体管，其第一极连接到第一晶体管和发光器件的串联节点上，第二极连接到第一晶体管的控制极，其控制极连接到第三扫描控制信号端；第三扫描控制信号端用于输入第三扫描控制信号；第一电源电压信号不再为电路提供初始化电压，初始化电压改有源极驱动电路为电路提供。第四晶体管用于在初始化阶段将数据信号线上的初始电压耦合到第一晶体管和发光器件的串联节点以及第一电容和第二电容的串联节点上；
栅极驱动电路，为N根第一扫描控制信号线、N根第二扫描控制信号线、N根第三扫描控制信号线提供扫描控制信号；第n根第一扫描控制信号线连接到第n行像素电路的第一扫描控制信号端，第n根第二扫描控制信号线连接到第n行像素电路的第二扫描控制信号端，第n根第三扫描控制信号线连接到第n行像素电路的第三扫描控制信号端；其中，n为大于等于1小于等于N的整数；
所述第一扫描控制信号线用于为相应行的像素电路提供第一扫描控制信号，所述第二扫描控制信号线用于为相应行的像素电路提供第二扫描控制信号，所述第三扫描控制信号线用于为相应行的像素电路提供第三扫描控制信号；
数据驱动电路，为M根数据信号线提供所需要的电压信号，其中第m根数据信号线连接到第m列像素电路的数据信号端，其中，m为大于等于1小于等于M的整数；所述数据信号线用于为相应列的像素电路在 初始化阶段，阈值提取阶段和数据写入阶段分别为电路提供初始化电压，参考电压和灰度有关的数据电压。
所述第一电源线、第二电源线、第三电源线，第四电源线和可能存在的第五电源线上恒定的电源信号由外部恒压电路统一提供；
本申请提供的显示装置及其像素电路，像素电路通过源级跟随的形式产生驱动管的阈值电压信息，通过第一电容和第二电容的分压在第一电容两端产生驱动管的阈值电压和灰度信息有关的基准电压，发光过程中，该基准电压保持不变，使得流过发光器件的驱动电流与驱动晶体管和发光器件的阈值电压无关，从而补偿驱动晶体管和发光器件的阈值电压偏移，解决显示面板各处驱动晶体管阈值电压不同而导致的显示不均匀问题。显示装置采用逐行发光方式时，采用扫描控制信号交叠的形式，以减少电路的行编程时间，在获得高精度的同时满足高分辨率、高帧频显示面板的需求；采用集中发光方式时，像素电路采用分组编程、分组发光的方式，以减小电路复杂度的同时增加发光时间。
附图说明
图1为现有技术中一种像素电路的结构图；
图2为本申请实施例一中像素电路的结构图；
图3为本申请实施例一中像素电路的驱动信号波形图；
图4为本申请实施例二中像素电路的结构图；
图5为本申请实施例二中像素电路的驱动信号波形图；
图6为本申请实施例三中像素电路的结构图；
图7为本申请实施例三中像素电路的驱动信号波形图；
图8为本申请实施例三中像素电路组成的显示装置的结构图；
图9为本申请实施例四中像素电路的结构图；
图10为本申请实施例四中像素电路的驱动信号波形图；
图11为本申请实施例五中像素电路的结构图；
图12为本申请实施例五中像素电路的驱动信号波形图；
图13为本申请实施例六中像素电路的结构图；
图14为本申请实施例六中像素电路的驱动信号波形图；
图15为本申请实施例七中像素电路的结构图；
图16为本申请实施例七中像素电路的驱动信号波形图；
图17为本申请实施例八中所有像素电路作为一组时驱动示意图；
图18为本申请实施例八中所有像素电路分为两组时驱动示意图；
图19为本申请实施例八中所有像素电路分为四组时驱动示意图；
图20为本申请实施例八中像素电路的结构图；
图21为本申请实施例八中像素电路的驱动信号波形图；
图22为本申请实施例八中显示装置的结构图；
图23为本申请实施例九中像素电路的结构图；
图24为本申请实施例九中像素电路的驱动信号波形图；
图25为本申请实施例十中像素电路的结构图；
图26为本申请另一种实施例中像素电路的结构图；
图27为本申请实施例十中显示装置的结构图。
具体实施方式
首先对本申请中用到的一些术语进行说明。本申请实施例中使用的晶体管可以是任何结构的晶体管，如场效应晶体管(FET，Field Effect Transistor)，或者双极型晶体管(BJT，Bipolar Junction Transistor)。当晶体管为FET时，控制极指栅极，第一电极指漏极，第二电极指源极；当晶体管为BJT时，控制极指基极，第一电极指集电极，第二电极指发射极。当晶体管作为开关使用时，其漏极和源极可以互换。显示装置中的晶体管通常采用TFT器件，本申请实施例主要以TFT为例进行说明。在本申请实施例中，以有机发光二极管OLED为发光器件，除特别说明外，本申请中所用的晶体管为N型管。
下面通过具体实施方式结合附图对本申请作进一步详细说明。
实施例一
请参考图2，本实施例提供了一种像素电路，包括第一晶体管21、第二晶体管22、第三晶体管23、第一电容26、第二电容27和发光器件25，
第一晶体管21和发光器件25顺次串联在第一电压源信号端VDD[n]和第二电压源信号端VSS之间。第一晶体管21的控制极连接至第二晶体管22的第二极，第一晶体管21的第一极连接至第一电压源信号端，第一晶体管21的第二极连接至发光器件25的阳极；
第二晶体管22的控制极连接至第一扫描控制信号端VSCAN[n]，用于接收当前行的第一扫描控制信号，第二晶体管22的第一极连接至数据信号端Data Line，用于接收数据信号端Data Line上的数据信息(数据电压)，第二晶体管22的第二极连接至第一晶体管21的控制极。第二晶体管22用于响应当前行的第一扫描控制信号，以传递参考电压及与灰度信息有关的数据电压。
第三晶体管23的控制极连接至第二扫描控制信号线VEM[n]，用于接收当前行的第二扫描控制信号，第三晶体管23的第一极连接至发光器件25的阳极，第三晶体管23的第二极连接至第一电容26的第二极。第三晶体管23用于响应当前行的第二扫描控制信号，在初始化阶段、阈值提取阶段和发光阶段打开。
第一电容26的第一极连接至第一晶体管21的控制极，第二极连接至第二电容27的第一极；第二电容27的第二极连接至第二电压源信号 端VSS。阈值提取阶段，第一电容26两端产生的电压差为驱动管(第一晶体管21)的阈值电压信息，数据写入阶段通过第一电容26和第二电容27的分压形式将与灰度信息和驱动管的阈值电压有关的信息存储在第一电容26的两端，以形成基准电压，发光阶段通过自举的形式将OLED(发光器件25)两端的电压信息耦合到第一晶体管21的控制极，保持第一电容26两端的基准电压不变。需要说明的是，本实施例中，第二电容27的第二极连接在第二电压源信号端VSS，在其他实施例中，第二电容27的第二极也可以连接在单独的第五电压源信号端。
本实施例中像素电路的驱动信号波形图如图3所示，该像素电路工作过程中一帧时间T(一帧周期)可分为四个阶段：初始化阶段、阈值提取阶段、数据写入阶段和发光阶段，为了方便说明，设第一晶体管21控制极和第二晶体管22的第二极连接于第一节点A，第一电容26第二极和第二电容27的第一极连接于第二节点B，第一晶体管21的第二极和发光器件25的阳极连接于第三节点C。
(1)初始化阶段
当前像素被选通，当前像素的第一扫描控制信号端VSCAN[n]输入的第一扫描控制信号从低电平变为高电平，第二扫描控制信号端VEM[n]输入的第二扫描控制信号保持为高电平，则所有晶体管都开启，第一电压源信号端VDD[n]输入的信号从高电平VDDH转换为低电平VDDL。数据信号端Data Line上的电压为参考电压VREF，则图2中第一节点A被充电至参考电压VREF。由于第三晶体管23被打开，此时第二节点B和第三节点C被开关管(第三晶体管23)连通，第二节点B和第三节点C被放电至某一低电平VDDL(初始电压)，VDDL＜VTH_OLED，其中VTH_OLED为发光器件25的阈值电压，因此，发光器件25不发光，电路完成了初始化。
(2)阈值提取阶段
当前像素的第一扫描控制信号和第二扫描控制信号保持为高电平，则所有晶体管都开启，第一电压源信号端VDD[n]输入的信号从低电平转换为高电平。数据信号端Data Line上的电压保持为参考电压VREF，因此，第一节点A保持参考电压VREF，第二节点B和第三节点C通过第一晶体管21和第三晶体管23被第一电压源信号端VDD[n]充电，直至第一晶体管21关断，此时B点和C点的电压为：VB＝VC＝VREF-VTH_T1，VREF-VTH_T1＜VTH_OLED，其中VTH_T1为第一晶体管21的阈值电压，此时，发光器件25不发光。
(3)数据写入阶段
当前像素的第一扫描控制信号端VSCAN[n]输入的第一扫描控制信号保持为高电平，第二扫描控制信号端VEM[n]输入的第二扫描控制信号从高电平转换为低电平，从而关断第三晶体管23，因此，第二节点B和第 三节点C断开；第一电压源信号端VDD[n]输入的信号保持为高电平。数据信号端Data Line上的电压变化为与灰度有关的数据电压VDATA，图2中第一节点A也变化为VDATA，由于第一电容26和第二电容27串联，因此B点的电压刷新至：
Figure PCTCN2016076554-appb-000002
其中，C1和C2分别为第一电容26和第二电容27的电容值。
为了保证在编程的过程中OLED不发光，因此，数据电压应该满足[VDATA]max–VTH_T1＜VTH_OLED，其中[VDATA]max为数据电压中的最大值。这样，在整个编程过程中OLED都不发光，增加了显示器的对比度。
经过数据写入以后，第一电容25两端产生的与驱动管的阈值电压信息和灰度信息有关的基准电压为：
Figure PCTCN2016076554-appb-000003
(4)发光阶段
当前像素第一扫描控制信号端VSCAN[n]输入的第一扫描控制信号从高电平变为低电平，则第二晶体管22关断。第二扫描控制信号端VEM[n]输入的第二扫描控制信号从低电平变为高电平，则第三晶体管23打开。第二节点B和第三节点C连通，由于此时的第一节点A开始悬空，则第三节点C随着OLED发光开始抬高至发光时所对应的阳极电压VOLED，则第一节点A也抬高了相应的电压而维持第一节点A和第二节点B之间的电压差保持不变，所以流过OLED的电流不变，该电流的表达式如下：
Figure PCTCN2016076554-appb-000004
Figure PCTCN2016076554-appb-000005
从公式(4)可以看出流过OLED的电流与第一晶体管21的阈值电压VTH_T1和OLED两端的第二阈值电压VTH_OLED无关，只跟当前像素点灰度有关的数据电压VDATA、已知的参考电压VREF、第一电容26电容值C1和第二电容27电容值C2有关。通过合理设计参考电压VREF，可以使得在整个编程过程中OLED都不发光，以获得高对比度的显示器。
本实施例中提供的像素电路能够补偿驱动晶体管和发光器件的阈值电压漂移，还可以解决显示面板各处像素电路的驱动晶体管阈值电压不同而导致的显示不均匀问题，合理设计的参考电压VREF可以使OLED器件在非发光周期不发光，增加了对比度。此外，当TFT阈值电压变化为负值时，传统的采用二极管连接进行放电从而产生阈值电压信息的电压型补偿电路无法再提供补偿，而本实施中的像素电路由于采用源级跟随的形式，可以同时补偿正负阈值电压，因此更优越，这一点在采用耗尽型晶体管作为驱动管的显示装置中极为有利。
实施例二
如图4所示，本实施例提供了另一种像素电路，其与实施例一的主要区别在于增加了一个第四晶体管24，第四晶体管24在第三扫描信号的控制作用下对电路中的第二节点B和第三节点C进行初始化；此时的第一电压源信号端VDD输入的不再是脉冲信号，而是恒定的高电平，初始化由第四晶体管24完成。
第四晶体管24的控制极连接至第三扫描控制信号端VR[n]上，第一极连接至发光器件25的阳极，第二极连接至第三电压源信号端VCM，用于响应第三扫描控制信号，在初始化阶段将第二节点B和第三节点C的电压初始化到某一低电平。
本实施例中，像素电路的驱动信号波形图如图5所示，一帧时间T也分为四个阶段：初始化阶段、阈值提取阶段、数据写入阶段和发光阶段。各个阶段的工作原理与实施例一类似，此处不再赘述。
在其他实施例中，第二电容27的第二极也可以连接在单独的第五电压源信号端。本实施例中提供的像素电路与实施例二相比，其他的器件的连接关系一致，驱动过程也一致，此处不再赘述。
本实施例中，由于引入了第三扫描控制信号和第四晶体管，使得整个面板上的像素电路可以共用同一第一电压源信号端输入的信号，更易于控制。
实施例三
请参考图6，本实施例提供了另一种像素电路，其与实施例二的主要区别在于增加了第五晶体管28，第五晶体管28的控制极连接在第四扫描信号端VSN[n]，第一极连接至第四电压源信号端，用于输入恒定的参考电压VREF，第二极连接至第一晶体管21的控制极。第五晶体管28在第四扫描信号的控制作用下在电路初始化阶段和阈值提取阶段为驱动管的栅极提供恒定的参考电压VREF，这样做的有益之处是可以大大减少行编程时间，使的该像素电路更适合大面积、高分辨率、高帧频的显示器。
本实施例中像素电路的驱动信号波形图如图7所示，一帧时间T也分为四个阶段：初始化阶段、阈值提取阶段、数据写入阶段和发光阶段。各个阶段的工作原理与实施例一类似，此处不再赘述。
在其他实施例中，第二电容27的第二极也可以连接在单独的第五电压源信号端。
在其他实施例中，电路的初始化由第一电压源信号端输入的初始电压完成，而不需要第四晶体管24，此时第一电压源信号端输入的信号为脉冲信号；结合实施例一和实施例三，可知该实施例中像素电路的驱动过程，此处不再赘述。
请参考图8，本实施例还提供了一种显示装置，包括显示面板、栅极驱动电路30和数据驱动电路40。显示面板包括若干像素阵列，其中像素阵列由M列*N行像素电路50按矩阵的形式排列而成，其中M和N均为正整数，像素电路50采用本实施例中提供的像素电路。
栅极驱动电路30为包括N根第一扫描控制信号线、N根第二扫描控制信号线、N根第三扫描控制信号线和N根第四扫描控制信号线提供扫描控制信号；第n根第一扫描控制信号线连接到第n行像素电路的第一扫描控制信号端，第n根第二扫描控制信号线连接到第n行像素电路的第二扫描控制信号端，第n根第三扫描控制信号线连接到第n行像素电路的第三扫描控制信号端，第n根第四扫描控制信号线连接到第n行像素电路的第四扫描控制信号端；其中，n为大于等于1小于等于N的整数。
数据驱动电路40，为M根数据信号线提供电压信号，第m根数据信号线连接到第m列像素电路的数据信号端，其中，m为大于等于1小于等于M的整数。
像素阵列中，同一行的像素电路50均连接到同一根第一扫描控制信 号线31、第二扫描控制信号线32、第三扫描控制信号线34和第四扫描控制信号线35上，该第一扫描控制信号线31、第二扫描控制信号线32，第三扫描控制信号线34和第四扫描控制信号线35可以为当前行的像素电路提供所需要的第一扫描控制信号、第二扫描控制信号，第三扫描控制信号和第四扫描控制信号。同一列的像素电路均连接至同一根数据信号线41上，当第四扫描控制信号从低电平转变为高电平时表示该行被选通，接下来对选通的当前行进行操作。数据信号线41在数据写入阶段为像素电路提供参考电平VREF与灰度有关的数据电压VDATA。
需要说明的是，本实施例中，为了方便说明，像素阵列以3*3矩阵的形式给出，实际的像素阵列可以根据情况进行选择布置；本实施例中的开关管也可以是可以为P型管，但是需要根据P型管的特性对电路连接关系及驱动信号做相应的改变，此处不再赘述。
本实施例提供的显示装置及其像素电路，其初始化阶段和阈值提取阶段不影响电路的行编程时间，每行的行编程时间只包括数据写入时间(两电容的分压所需的时间)，阈值提取是在第四扫描控制信号的控制作用下在行内完成的，其占用的是发光时间(阈值提取时间远远小于发光时间)，因此在获得高帧频和高分辨率的同时不影响阈值提取的精度。
实施例四
本实施例中不包括第四扫描控制信号线，第n行像素电路的第四扫描控制信号端连接到第n-1行像素电路的第一扫描控制信号线上。
请参考图9和图10，分别为本实施例中的像素电路的结构图和驱动波形图。本实施例中，像素电路与实施例三的不同之处在于，第五晶体管的控制极连接至上一行的第一扫描信号线上。利用上一行的第一扫描信号对本行电路进行初始化和阈值提取，此时，每行的行编程时间包括初始化和阈值提取的时间(数据写入的时间小于初始化和阈值提取的时间之和)。其具体的驱动过程与实施例三相同，唯一不同的是当每次第四扫描信号工作的时候此时为上一行的第一扫描信号工作。栅极驱动电路只需要产生第一扫描控制信号、第二扫描控制信号和第三扫描控制信号。与实施例三相比，这样做的好处是可以减小外围电路的复杂度，同时也减少了像素电路的扫描控制信号，开口率更大。
在其他实施例中，像素电路的初始化是由第一电压源信号端输入的信号控制完成的，第一电压源信号为脉冲信号；像素电路不包括初始化晶体管，即第四晶体管24。因此，在实施例中，像素电路只包括第一扫描控制信号和第二扫描控制信号。
实施例五
本实施例与实施例四的区别在于，第n行像素电路的第四扫描控制信号端连接到第n-3行像素电路的第一扫描控制信号线上。
请参考图11，分别为本实施例中显示装置的像素电路的结构图。本实施例中，像素电路与实施例三中的像素电路的主要区别是第五晶体管28的控制极连接至第n-3行的像素电路的第一扫描控制信号线上，第五晶体管28在第n-3行的像素电路的第一扫描控制信号作用下，在电路初始化和阈值提取的过程给为驱动管的栅极提供恒定的参考电平VREF，这样做的有益之处在于利用每行第一扫描信号的交叠，可以大大减少行时间，在数据写入时间不变的情况下，此时等效的行时间减少为实施例一和实施例二中行编程时间的1/4，此时阈值提取时间为两倍的行时间，使得该像素电路更适合大面积，高分辨率，高帧频的显示器。
第五晶体管28的控制极连接至第n-3行的第一扫描控制信号线上，第一极连接至第四电压源信号端，第二极连接至第一晶体管21的控制极，用于响应第n-3行的第一扫描控制信号，在初始化和阈值提取阶段为驱动管的控制极提供稳定的参考电平VREF。
本实施例中像素电路的驱动信号波形图如图12所示，一帧时间T也分为四个阶段：初始化阶段、阈值提取阶段、数据写入阶段和发光阶段。各个阶段的工作原理与实施例一类似，此处不再赘述。
在其他实施例中，第二电容27的第二极也可以连接在单独的第五电压源信号端，第五电压源信号端连接到栅极驱动电路的第五电源线。
在其他实施例中，像素电路的初始化由第一电压源信号端输入的信号完成，而不需要第四晶体管24，此时所需的第一电压源信号端输入的信号为脉冲信号；结合实施例一和实施例五，可知该实施例中像素电路的驱动方式，此处不再赘述。
相比于实施例三，本实施例的主要优势在于，在获得减少的行编程时间的同时，可以减少一根扫描控制信号线，使外围电路更简单。其显示面板跟实施例四相近，此处不再赘述。只是此时第n行像素电路的第五晶体管的控制极连接至第n-3行的第一扫描信号线VSCAN[n-3]上而非第n-1行的第一扫描信号线VSCAN[n-1]上。
当然，在具体实施例中，第n行像素电路的第四扫描控制信号端可以连接到第n-a行像素电路的第一扫描控制信号线上，其中，a为大于等于1小于n的整数。
实施例六
本实施例提供了另一种显示装置，其与实施例三的区别在于，栅极驱动电路不包括第三扫描控制信号线和第四扫描控制信号线，第n行像素电路的第四扫描控制信号端连接到第n-a行像素电路的第一扫描控制信号线上，第n行像素电路的第三扫描控制信号端连接到第n-a-b行像素电路的第一扫描控制信号线上，其中，a为大于等于1小于n的整数，b为大于等于1小于n-a的整数。为了保证每一行像素电路具有初始化 阶段，第n-a行像素电路的第一扫描控制信号和第n-a-b行像素电路的第一扫描控制信号具有一段高电平叠加期，该高电平叠加期即为第n行像素电路的初始化阶段。
请参考图13，为本实施例中显示装置的像素电路的结构图。本实施例中的像素电路与实施例三中的像素电路的主要区别是第四晶体管24和第五晶体管28的控制极都连接至前面某行的像素电路的第一扫描控制信号线上，如，当前行是第n行，第四晶体管24控制极连接至第n-5行的像素电路的第一扫描控制信号线上，第五晶体管28的控制极连接至第n-3行的像素电路的第一扫描控制信号线上，第四晶体管24在第n-5行的像素电路的第一扫描控制信号线VSCAN[n-5]提供的第一扫描控制信号的作用下，在电路初始化阶段给连通的第二节点B和第二节点C提供初始化的低电平VLL，第五晶体管28在第n-3行的像素电路的第一扫描控制信号线VSCAN[n-3]提供的第一扫描控制信号的作用下，在电路初始化阶段和阈值提取阶段为驱动管的栅极提供恒定的参考电平VREF，这样做的有益之处在于可以去掉当前行的第三扫描控制信号线和第四扫描控制信号线，大大减小了外围电路的复杂度；利用行第一扫描信号的交叠，可以大大减少行时间，在数据写入时间不变的情况下，此时等效的行时间减少为实施例一和实施例二中行编程时间的1/4，此时阈值提取时间为两倍的行时间，使得该像素电路更适合大面积，高分辨率，高帧频的显示器。
第四晶体管24的控制极连接至第n-5行的第一扫描控制信号线上，第一极连接至发光器件的阳极，第二极连接至第一晶体管21的第二极，第四晶体管24在第n-5行的第一扫描控制信号的作用下为电路进行初始化；第五晶体管28的控制极连接至第n-3行的第一扫描控制信号线，第一极连接至第四电源线，第二极连接至第一晶体管21的控制极，用于响应第n-3行的第一扫描控制信号，在初始化阶段和阈值提取阶段为驱动管的控制极提供稳定的参考电平VREF。
本实施例中像素电路的驱动信号波形图如图14所示，一帧时间T也分为四个阶段：初始化阶段、阈值提取阶段、数据写入阶段和发光阶段。各个阶段的工作原理与实施例一类似，此处不再赘述。
本实施例相比于实施例三有益之处是更充分的利用了前面行的第一扫描信号，使电路的行扫描信号只包括第一扫描信号和第二扫描信号，对于逐行发光的像素电路来讲，外围电路得到了最大限度的简化。利用第一扫描信号的交叠，可以在获得较长阈值提取时间的同时减少行编程时间，使得像素电路更适合大面积，高分辨率和高帧频的显示器的需求。
以上实施例提供的显示装置均采用逐行发光的形式来实现，外围电路相对复杂，以下介绍的两实施例均采用集中发光的形式。实施例七采 用的是普通的集中发光形式，整个面板上所有的像素电路的初始化和阈值提取过程是同时进行的，当面板上所有的像素电路完成初始化和阈值提取以后，为了使整个编程过程中OLED不发光，第一电源线VDD提供的信号变为低电平，所有的像素电路的第三晶体管都关断，逐行开始进行数据的写入，当数据写入完成以后，第一电源线VDD提供的信号从低电平转换为高电平，面板上所有的像素电路的第三晶体管都打开，像素电路进入发光模式。由于采用了集中初始化和阈值提取，以及集中发光的形式，整个面板上所有的像素电路只需要一根第一电源线VDD和第二扫描控制信号线。集中发光的缺点是：发光时间短，发光器件发光时所需要的发光电流较大，而较大的发光电流会使发光器件退化更明显。为了增加发光时间，实施例八给出了分组编程的驱动方式。如果采用分组发光的形式，首先，面板上所有的像素电路从上到下分成c(c为大于等于1小于N的整数)组，此时电路的编程和发光是按组为模块化进行的，即组内同时进行初始化和阈值提取，并进行数据的逐行写入，完成数据写入以后，该组进行发光；一组进行编程的时候不影响其他组的发光，这样可以使发光的时间大幅度增加。
实施例七：
请参考图15，为本实施例中显示装置的像素电路的结构图。本实施例中的像素电路与实施例一的主要区别在于，第一电源线VDD提供的信号和第二扫描信号线VEM提供的信号不再区分是哪一行的，所有的行共用相同的第一电源线VDD和第二扫描信号线VEM。
第一晶体管21的第一极连接至第一电源线上VDD，第二极连接至发光器件的阳极；第三晶体管23的控制极连接至统一的第二扫描控制线VEM上，第一极连接至发光器件的阳极，第二极连接至第一电容的第二极，第三晶体管23响应第二扫描控制线VEM提供的控制信号，在初始化阶段、阈值提取阶段和发光阶段导通。
本实施例中像素电路的驱动信号波形图如图16所示，一帧时间T也分为四个阶段：初始化阶段、阈值提取阶段、数据写入阶段和发光阶段。
(1)初始化阶段
面板上所有行的第一扫描信号线VSCAN都为高电平，第一电源线VDD从高电平转换为低电平，第二扫描控制信号线VEM为高电平，面板上所有的第二晶体管22和第三晶体管23都打开，所有像素电路的第一节点A被充电至参考电压VREF，此时第二节点B和第三节点C被第三晶体管23连通，第二节点B和第三节点C被放电至第二电源线VDD提供的某一低电平VLL，VLL＜VTH_OLED。其中VTH_OLED为发光器件25的阈值电压，因此，发光器件25不发光，面板上所有的像素电路都完成了初始化。
(2)阈值提取阶段
面板上所有行的第一扫描信号线VSCAN保持为高电平，第一电源线VDD从低电平转换为高电平，第二扫描控制信号线VEM为高电平，第二晶体管22和第三晶体管23都打开，所有像素电路的第一节点A保持为参考电压VREF，此时第二节点B和第三节点C被开关管连通，第一电源线VDD对第二节点B和第三节点C充电直至第一晶体管21关断，停止对B点和C点充电，此时第二节点B和第三节点C的电压为：VB＝VC＝VREF-VTH_T1，VREF-VTH_T1＜VTH_OLED，其中VTH_T1为第一晶体管21的阈值电压，因此发光器件25不发光，此时面板上所有的像素电路完成了阈值提取。
(3)数据写入阶段：
第二扫描控制信号线VEM为从高电平转换为低电平，面板上所有像素电路的第三晶体管关断，因此，第二节点B和第三节点C断开；第一电源线VDD从高电平转换为低电平，以防止在长时间编程过程中OLED发光并使得OLED处于负偏置状态以减少OLED的退化；面板上所有的像素电路开始逐行进行数据的写入。当当前行的第一扫描控制信号线VSCAN[n]从低电平转换为高电平时，当前行的第一晶体管21打开，开始对当前行进行数据写入，此时数据线Data Line上的电压为当前行灰度有关的数据电压VDATA。由于第一电容26和第二电容27串联，图15中的第二节点B的电压最后刷新至：
Figure PCTCN2016076554-appb-000006
经过数据写入以后，第一电容25两端产生的与驱动管的阈值电压信息和灰度信息有关的基准电压为：
Figure PCTCN2016076554-appb-000007
(4)发光阶段：
逐行进行数据写入之后，所有行的第一扫描控制信号线VSCAN都变为低电平，则所有的第二晶体管22都关断；第一电源线VDD从低电平转换为高电平，第二扫控制信号线VEM从低电平变为高电平，则所有像素电路的第三晶体管23都打开，第二节点B和第三节点C连通，第三节点C随着OLED发光开始抬高至发光时所对应的阳极电压VOLED，由于此时所有的第一节点A开始悬空，第一节点A也抬高了相应的电压， 第一节点A和第二节点B之间的电压差保持不变，所以流过OLED的电流不变，该电流的表达式如下：
Figure PCTCN2016076554-appb-000008
从公式(7)可以看出流过OLED的电流与第一晶体管21的阈值电压VTH_T1和OLED两端的阈值电压VTH_OLED无关，只跟当前像素点灰度有关的数据电压VDATA、已知的参考电压VREF、第一电容26电容值C1和第二电容27电容值C2有关，因此，可以补偿驱动管的阈值电压VTH_T1和OLED阈值电压VTH_OLED的变化，也可以补偿整个显示面板上各处驱动晶体管的阈值电压不同而导致的显示不均匀问题。通过合理设计参考电压VREF和第一电源线VDD，可以使得在整个编程过程中OLED都不发光，以获得高对比度的显示器；OLED在数据写入阶段处于负偏置状态，可以减少OLED的退化。
实施例八
本实施例中，面板上所有的像素电路从上到下被分成c(c为大于等于1小于N的整数)组，一组为一个模块，同一组内，所有像素电路的编程和发光是同时进行的，某一组进行编程的时候，不影响其他组的发光。同一组内，所有的像素电路共用第一电源线和第二扫描控制信号线。
当c取值为1时，本实施例提供的显示装置与实施例七相同。
图17示意性的表示了未分组时，即实施例七中面板上像素电路的编程和发光情况，其中1为初始化阶段，2为阈值提取阶段，3为数据写入阶段，4为发光阶段。如果不改变像素电路的初始化、阈值提取和数据写入的时间，采用分组的形式以后，面板上所有像素电路的编程和发光情况如图18和图19所示，其中图18为将像素电路分成两组的情况，图19为将像素电路分成四组的情况。
本实施例中，以分成两组的形式进行说明。面板上所有的像素电路分成2组，第一组的第一电源线为VDD1，第二扫描控制信号线为VEM1。第二组的第一电源线为VDD2，第二扫描控制信号线为VEM2。请参考图20和图21，与实施例七相比，电路中连接关系没有发生变化，整个面板上像素电路的数据线没有发生变化。
本实施例中像素电路的驱动信号波形图如图21所示，同一组内，像素电路的驱动过程包括以下四个阶段：初始化阶段、阈值提取阶段、数据写入阶段和发光阶段。同组内，所有像素电路的初始化和阈值提取是 同时进行的，组内各行像素电路在数据写入时逐行进行，当组内各行完成数据写入之后，该组进入发光模式；每次最多只有一组在编程，一组的编程不会影响到其他组进行发光。各个阶段的工作原理与实施七例类似，不同的是实施例七中面板上所有的像素电路的编程是同时进行的，该实施例八中同组内的像素电路的编程是同时进行的，因此不再赘述。
在其他实施例中，第二电容27的第二极也可以连接在单独的第五电压源信号端。
图22给出了一种由本实施例中的像素电路组成的显示装置，该显示装置包括显示面板、栅极驱动电路30及数据驱动电路40。显示面板包括若干像素阵列，其中像素阵列由M列*N行像素电路50按矩阵的形式排列而成，其中M和N均为正整数，像素电路50采用24提供的像素电路。一般地，像素阵列中，同一行的像素电路50均连接到同一组第一扫描控制信号线31，该第一扫描控制信号线31可以为当前行的像素电路提供所需要的第一扫描控制信号。同一列的像素电路均连接至同一数据信号线41上，数据信号线41可以提供初始化阶段和阈值提取阶段所需要的参考电压VREF；当第一扫描控制信号线从低电平转变为高电平时表示该行被选通，接下来对当前行进行数据写入的操作。数据信号线41可以提供数据写入阶段所需要的灰度有关的数据电压VDATA。第一组的第一电源线37和第二扫描控制信号线38，分别为第一组提供信号VDD1和第二扫描控制信号VEM1，该信号也由数据驱动电路提供。第二组的第一电源线39和第二扫描控制信号线310，分别为第二组提供信号VDD2和第二扫描控制信号VEM2。
需要说明的是，本实施例中，为了方便说明，像素阵列以4*4矩阵的形式给出，实际的像素阵列可以根据情况进行选择布置；本实施例中的开关管也可以是可以为P型管，但是需要根据P型管的特性对电路连接关系及驱动信号做相应的改变。
实施例九
请参考图23，本实施例提供了另一种像素电路，初始电压和参考电压由数据信号端提供，第二晶体管用于在初始化阶段将数据信号端输入的初始电压耦合到第一节点A，在阈值提取阶段将数据信号端输入的参考电压耦合到第一节点A；像素电路还包括第四晶体管，其第一极连接到第三节点C，第二极连接到第一节点A，控制极连接到第三扫描控制信号端；第三扫描控制信号端用于输入第三扫描控制信号，第三扫描控制信号在初始化阶段控制第四晶体管导通，以将第一节点A上的初始电压耦合到第三节点C上。
本实施例与实施例二的主要区别在于，初始电压由数据信号端提供，而非由第三电压源信号端提供。
本实施例中，像素电路的驱动信号波形图如图24所示，一帧时间T也分为四个阶段：初始化阶段、阈值提取阶段、数据写入阶段和发光阶段。各个阶段的工作原理与实施例一类似，此处不再赘述。
在其他实施例中，第二电容27的第二极也可以连接在单独的第五电压源信号端。
实施例十
请参考图25，本实施例提供了另一种像素电路，初始电压和参考电压由数据信号端提供，第二晶体管用于在阈值提取阶段将数据信号端输入的参考电压耦合到第一节点A；像素电路还包括第四晶体管，其第一极连接到第三节点C上，第二极连接到数据信号端，控制极连接到第三扫描控制信号端；第三扫描控制信号端用于输入第三扫描控制信号，第三扫描控制信号在初始化阶段控制第四晶体管导通，以将数据信号端的初始电压耦合到第三节点C上。
本实施例与实施例二的主要区别在于，初始电压由数据信号端提供，而非由第三电压源信号端提供。
本实施例中，像素电路的驱动信号波形图如图24所示，一帧时间T也分为四个阶段：初始化阶段、阈值提取阶段、数据写入阶段和发光阶段。其驱动过程与实施例九相同，这里将不再赘述。
由于在初始化阶段，第三晶体管23处于打开状态，所以，在某些实施例中，如图26所示，第四晶体管24的第一极也可以连接到第二节点B，第二极连接到数据信号端，同样可以实现初始化的作用。该实施例中，像素电路的驱动信号波形图与图24相同，驱动过程与实施例九相同，这里不再赘述。
本实施例还相应提供了一种显示装置，请参考图27，本显示装置，包括显示面板、栅极驱动电路30和数据驱动电路40。显示面板包括若干像素阵列，其中像素阵列由M列*N行像素电路50按矩阵的形式排列而成，其中M和N均为正整数，像素电路50采用本实施例中提供的像素电路。
栅极驱动电路30为包括N根第一扫描控制信号线、N根第二扫描控制信号线、N根第三扫描控制信号线提供扫描控制信号；第n根第一扫描控制信号线连接到第n行像素电路的第一扫描控制信号端，第n根第二扫描控制信号线连接到第n行像素电路的第二扫描控制信号端，第n根第三扫描控制信号线连接到第n行像素电路的第三扫描控制信号端；其中，n为大于等于1小于等于N的整数。
数据驱动电路40，为M根数据信号线提供电压信号，第m根数据信号线连接到第m列像素电路的数据信号端，其中，m为大于等于1小于等于M的整数。
像素阵列中，同一行的像素电路50均连接到同一根第一扫描控制信号线31、第二扫描控制信号线32、第三扫描控制信号线34上，该第一扫描控制信号线31、第二扫描控制信号线32，第三扫描控制信号线34可以为当前行的像素电路提供所需要的第一扫描控制信号、第二扫描控制信号，第三扫描控制信号。同一列的像素电路均连接至同一根数据信号线41上，当第一扫描控制信号从低电平转变为高电平时表示该行被选通，接下来对选通的当前行进行操作。数据信号线41在数据写入阶段为像素电路提供初始化电压VLL，参考电平VREF与灰度有关的数据电压VDATA。
第一电源电压信号和第二电源电压信号由外围恒压电路统一提供。
需要说明的是，本实施例中，为了方便说明，像素阵列以3*3矩阵的形式给出，实际的像素阵列可以根据情况进行选择布置；本实施例中的开关管也可以是可以为P型管，但是需要根据P型管的特性对电路连接关系及驱动信号做相应的改变，此处不再赘述。
以上内容是结合具体的实施方式对本申请所作的进一步详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请发明构思的前提下，还可以做出若干简单推演或替换。

Claims (10)

  1. 一种像素电路，其特征在于，所述像素电路的一帧周期依次包括初始化阶段、阈值提取阶段、数据写入阶段和发光阶段；所述像素电路包括：
    串联在高电位和低电位之间的第一晶体管和发光器件，第一晶体管用于在发光阶段导通为发光器件提供驱动电流，发光器件用于发射强度与流过电流相关的光；所述高电位由第一电压源信号端提供，所述低电位由第二电压源信号端提供；
    第二晶体管，其连接在数据信号端和第一晶体管的控制极之间，第二晶体管的控制极连接到第一扫描控制信号端，第一扫描控制信号端用于输入控制该像素电路选通的第一扫描控制信号，第二晶体管用于在第一扫描控制信号的控制下导通，将数据信号端的数据电压施加到第一晶体管的控制极，以控制第一晶体管为发光器件提供与数据信号端的数据电压相关的驱动电流；
    存储单元，其连接在第一晶体管的控制极和第二电压源信号端之间，或连接在第一晶体管的控制极和第五电压源信号端之间，第二电压源信号端和第五电压源信号端用于提供一低电位，用于存储数据信号端的数据电压；存储单元包括第一电容、第二电容和第三晶体管，第一电容和第二电容串联在第一晶体管的控制极和低电位之间，并在初始化阶段和阈值提取阶段，为第一晶体管的控制极提供一参考电压；第三晶体管的第一极连接在第一电容和第二电容的串联节点，第二极连接在第一晶体管和发光器件的串联节点上，并在初始化阶段，将一初始电压耦合到第三晶体管的第二极，第三晶体管的控制极连接到第二扫描控制信号端，第二扫描控制信号端用于输入第二扫描控制信号，第二扫描控制信号在数据写入阶段控制第三晶体管截止。
  2. 如权利要求1所述的像素电路，其特征在于，第二晶体管用于在第一扫描控制信号的控制下在初始化阶段、阈值提取阶段和数据写入阶段导通，所述参考电压由数据信号端提供，并在第一扫描控制信号的作用下，通过第二晶体管将参考电压耦合到第一晶体管的控制极；所述初始电压由第一电压源信号端提供，并通过第一晶体管将初始电压耦合到第三晶体管的第二极。
  3. 如权利要求1所述的像素电路，其特征在于，所述参考电压由数据信号端提供，第二晶体管用于在初始化阶段和阈值提取阶段将数据信号端输入的参考电压耦合到第一晶体管的控制极；所述像素电路还包括第四晶体管，其第一极连接到第一晶体管和发光器件的串联节点上，第二极连接到第三电压源信号端，控制极连接到第三扫描控制信号端；第三扫描控制信号端用于输入第三扫描控制信号，第三扫描控制信号在初 始化阶段控制第四晶体管导通，以将第三电压源信号端上的初始电压耦合到第一晶体管和发光器件的串联节点上。
  4. 如权利要求1所述的像素电路，其特征在于，所述第一晶体管用于在初始化阶段将第一电压源信号端输入的初始电压耦合到第一晶体管和发光器件的串联节点上，所述像素电路还包括第五晶体管，其第一极连接到第四电压源信号端，第二极连接到第一晶体管的控制极，控制极连接到第四扫描控制信号端；第四扫描控制信号端用于输入第四扫描控制信号；第五晶体管用于在初始化阶段和阈值提取阶段将第四电压源信号端上的参考电压耦合到第一晶体管的控制极。
  5. 如权利要求1所述的像素电路，其特征在于，所述像素电路还包括：
    第四晶体管，其第一极连接到第一晶体管和发光器件的串联节点上，第二极连接到第三电压源信号端，控制极连接到第三扫描控制信号端；第三扫描控制信号端用于输入第三扫描控制信号；第四晶体管用于在初始化阶段将第三电压源信号端上的初始电压耦合到第一晶体管和发光器件的串联节点上；
    第五晶体管，其第一极连接到第四电压源信号端，第二极连接到第一晶体管的控制极，控制极连接到第四扫描控制信号端；第四扫描控制信号端用于输入第四扫描控制信号；第五晶体管用于在初始化阶段和阈值提取阶段将第四电压源信号端上的参考电压耦合到第一晶体管的控制极。
  6. 如权利要求1所述的像素电路，其特征在于，所述初始电压和参考电压由数据信号端提供，第二晶体管用于在初始化阶段将数据信号端输入的初始电压耦合到第一晶体管的控制极，在阈值提取阶段将数据信号端输入的参考电压耦合到第一晶体管的控制极；
    所述像素电路还包括第四晶体管，其第一极连接到第一晶体管和发光器件的串联节点上，第二极连接到第一晶体管的控制极，控制极连接到第三扫描控制信号端；第三扫描控制信号端用于输入第三扫描控制信号，第三扫描控制信号在初始化阶段控制第四晶体管导通，以将第一晶体管控制极上的初始电压耦合到第一晶体管和发光器件的串联节点上以及第一电容和第二电容的节点上；
    或者，所述第四晶体管，其第一极连接到第一晶体管和发光器件的串联节点上，第二极连接到数据信号端，控制极连接到第三扫描控制信号端；第三扫描控制信号端用于输入第三扫描控制信号，第三扫描控制信号在初始化阶段控制第四晶体管导通，以将数据信号端的初始电压耦合到第一晶体管和发光器件的串联节点上；
    或者，所述第四晶体管，其第一极连接到第一电容和第二电容的串 联节点上，第二极连接到数据信号端，控制极连接到第三扫描控制信号端；第三扫描控制信号端用于输入第三扫描控制信号，第三扫描控制信号在初始化阶段控制第四晶体管导通，以将数据信号端的初始电压耦合到第一电容和第二电容的串联节点上。
  7. 一种显示装置，其特征在于，包括：
    显示面板，其包括以M列*N行阵列式排布的像素电路，所述像素电路采用如权利要求1所述的像素电路，M和N为正整数；
    栅极驱动电路，其用于为N根第一扫描控制信号和N根第二扫描控制信号提供电压扫描控制信号；
    数据驱动电路，其用于为M根数据信号线和X根第一电源电压信号线提供电压信号和第一电源电压控制信号；其中，第m根数据信号线连接到第m列像素电路的数据信号端，m为大于等于1小于等于M的整数；所述数据信号线用于为相应列的像素电路在初始化阶段和阈值提取阶段提供参考电压以及为数据写入阶段提供灰度有关的数据电压；其中，X为大于等于1小于等于N的正整数，X的大小取决于面板上同时进行初始化和阈值提取的像素电路的多少；如果每次有x行像素电路进行初始化，则X＝N/x；如果X＝N，则该面板上的像素电路是逐行发光的；如果X＝1，则面板上所有的像素电路是同时发光的，如果X为大于1小于N的正整数，则面板上所有的像素电路被分成了X组，每组内的像素电路同时完成初始化，阈值提取和发光过程；所述第一电源电压信号线为像素电路提供第一电压源信号；
    所述像素电路中，第二晶体管用于在第一扫描控制信号的控制下在初始阶段、阈值提取阶段和数据写入阶段导通，所述参考电压由数据信号线提供，并在第一扫描控制信号的作用下，通过第二晶体管将参考电压耦合到第一晶体管的控制极；所述初始电压由第一电压源信号端提供，并通过第一晶体管将初始电压耦合到第三晶体管的第二极以及第一电容和第二电容的串联节点；
    第二电源线以及可能存在的第五电源线上恒定的电源信号由外部恒压电路统一提供。
  8. 如权利要求7所述的显示装置，其特征在于，所述像素电路还包括：
    第四晶体管和第五晶体管；
    第四晶体管，其第一极连接到第一晶体管和发光器件的串联节点上，第二极连接到第三电压源信号端，控制极连接到第三扫描控制信号端；第三扫描控制信号端用于输入第三扫描控制信号；第四晶体管用于在初始化阶段将第三电压源信号端上的初始电压耦合到第一晶体管和发光器件的串联节点上；
    第五晶体管，其第一极连接到第四电压源信号端，第二极连接到第一晶体管的控制极，控制极连接到第四扫描控制信号端；第四扫描控制信号端用于输入第四扫描控制信号；第五晶体管用于在初始化阶段和阈值提取阶段将第四电压源信号端上的参考电压耦合到第一晶体管的控制极；
    栅极驱动电路，为N根第一扫描控制信号线、N根第二扫描控制信号线、N根第三扫描控制信号线、N根第四扫描控制信号线提供扫描控制信号；第n根第一扫描控制信号线连接到第n行像素电路的第一扫描控制信号端，第n根第二扫描控制信号线连接到第n行像素电路的第二扫描控制信号端，第n根第三扫描控制信号线连接到第n行像素电路的第三扫描控制信号端，第n根第四扫描控制信号线连接到第n行像素电路的第四扫描控制信号端；其中，n为大于等于1小于等于N的整数；
    所述第一扫描控制信号线用于为相应行的像素电路提供第一扫描控制信号，所述第二扫描控制信号线用于为相应行的像素电路提供第二扫描控制信号，所述第三扫描控制信号线用于为相应行的像素电路提供第三扫描控制信号，所述第四扫描控制信号线用于为相应行的像素电路提供第四扫描控制信号，所述第三电源线用于为每一行像素电路提供初始电压，所述第四电源线用于为每一行像素电路提供参考电压；
    数据驱动电路，为M根数据信号线提供所需要的电压信号，其中第m根数据信号线连接到第m列像素电路的数据信号端，其中，m为大于等于1小于等于M的整数；所述数据信号线用于为相应列的像素电路在初始化阶段和阈值提取阶段以及数据写入阶段分别为电路提供参考电压和灰度有关的数据电压；
    所述第一电源线、第二电源线、第三电源线，第四电源线和第五电源线上恒定的电源信号由外部恒压电路统一提供。
  9. 如权利要求8所述的显示装置，其特征在于，所述栅极驱动电路不包括第三扫描控制信号线和第四扫描控制信号线，第n行像素电路的第四扫描控制信号端连接到第n-a行像素电路的第一扫描控制信号线上，第n行像素电路的第三扫描控制信号端连接到第n-a-b行像素电路的第一扫描控制信号线上，其中，a为大于等于1小于n的整数，b为大于等于1小于n-a的整数。
  10. 如权利要求7所述的显示装置，其特征在于，所述像素电路还包括：
    第四晶体管，其第一极连接到第一晶体管和发光器件的串联节点上，第二极连接到数据信号线，控制极连接到第三扫描控制信号端；第三扫描控制信号端用于输入第三扫描控制信号；第一电源电压信号不再为电路提供初始化电压，初始化电压改有源极驱动电路为电路提供；第四晶 体管用于在初始化阶段将数据信号线上的初始电压耦合到第一晶体管和发光器件的串联节点以及第一电容和第二电容的串联节点上；
    或者所述第四晶体管，其第一极连接到第一电容和第二电容的串联节点上，第二极连接到数据信号线，控制极连接到第三扫描控制信号端；第三扫描控制信号端用于输入第三扫描控制信号；第一电源电压信号不再为电路提供初始化电压，初始化电压改有源极驱动电路为电路提供；第四晶体管用于在初始化阶段将数据信号线上的初始电压耦合到第一晶体管和发光器件的串联节点以及第一电容和第二电容的串联节点上；
    或者所述第四晶体管，其第一极连接到第一晶体管和发光器件的串联节点上，第二极连接到第一晶体管的控制极，其控制极连接到第三扫描控制信号端；第三扫描控制信号端用于输入第三扫描控制信号；第一电源电压信号不再为电路提供初始化电压，初始化电压改有源极驱动电路为电路提供；第四晶体管用于在初始化阶段将数据信号线上的初始电压耦合到第一晶体管和发光器件的串联节点以及第一电容和第二电容的串联节点上；
    栅极驱动电路，为N根第一扫描控制信号线、N根第二扫描控制信号线、N根第三扫描控制信号线提供扫描控制信号；第n根第一扫描控制信号线连接到第n行像素电路的第一扫描控制信号端，第n根第二扫描控制信号线连接到第n行像素电路的第二扫描控制信号端，第n根第三扫描控制信号线连接到第n行像素电路的第三扫描控制信号端；其中，n为大于等于1小于等于N的整数；
    所述第一扫描控制信号线用于为相应行的像素电路提供第一扫描控制信号，所述第二扫描控制信号线用于为相应行的像素电路提供第二扫描控制信号，所述第三扫描控制信号线用于为相应行的像素电路提供第三扫描控制信号；
    数据驱动电路，为M根数据信号线提供所需要的电压信号，其中第m根数据信号线连接到第m列像素电路的数据信号端，其中，m为大于等于1小于等于M的整数；所述数据信号线用于为相应列的像素电路在初始化阶段，阈值提取阶段和数据写入阶段分别为电路提供初始化电压，参考电压和灰度有关的数据电压；
    所述第一电源线、第二电源线、第三电源线，第四电源线和可能存在的第五电源线上恒定的电源信号由外部恒压电路统一提供。
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CN103310732A (zh) * 2013-06-09 2013-09-18 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示装置
CN105096819A (zh) * 2015-04-21 2015-11-25 北京大学深圳研究生院 一种显示装置及其像素电路

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CN108320712A (zh) * 2018-04-27 2018-07-24 江苏集萃有机光电技术研究所有限公司 像素电路及显示装置

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