WO2018032899A1 - 像素电路及其驱动方法、显示面板和显示装置 - Google Patents

像素电路及其驱动方法、显示面板和显示装置 Download PDF

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Publication number
WO2018032899A1
WO2018032899A1 PCT/CN2017/091925 CN2017091925W WO2018032899A1 WO 2018032899 A1 WO2018032899 A1 WO 2018032899A1 CN 2017091925 W CN2017091925 W CN 2017091925W WO 2018032899 A1 WO2018032899 A1 WO 2018032899A1
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Prior art keywords
transistor
module
light emitting
scan
voltage
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PCT/CN2017/091925
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English (en)
French (fr)
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冯佑雄
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US15/736,690 priority Critical patent/US10504440B2/en
Publication of WO2018032899A1 publication Critical patent/WO2018032899A1/zh

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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
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Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a pixel circuit and a driving method thereof, a display panel, and a display device.
  • OLEDs are current-driven devices that require a constant current to control light emission.
  • the drive transistors in each OLED pixel circuit may have different threshold voltages due to process recipes and device aging, etc., resulting in each OLED exhibiting different brightness for the same data signal. This can result in uneven brightness between different display areas.
  • Embodiments of the present disclosure provide a pixel circuit that seeks to mitigate, alleviate or eliminate at least one of the above problems.
  • a pixel circuit including a light emitting module, a driving module, a compensation module, and an initialization module.
  • the initialization module is coupled to the first voltage terminal, the first scan line, and the third scan line and configured to be responsive to the first scan signal on the first scan line and the third scan on the third scan line
  • the signal is initialized with the first voltage supplied by the first voltage terminal to the driving module and the light emitting module.
  • the compensation module is coupled to the second scan line, the data line, and the second voltage terminal and configured to write a data voltage on the data line to the second responsive to a second scan signal on the second scan line
  • the driving module performs threshold voltage compensation on the driving module.
  • the drive module is coupled to the second voltage terminal and the illumination control line and is configured to generate a current dependent on the written data voltage in response to an illumination control signal on the illumination control line.
  • the light emitting module is coupled between the driving module and the first voltage terminal and configured to be illuminated by the generated current.
  • the initialization module includes: a first transistor having a gate connected to the first scan line, a first pole connected to the first voltage terminal, and a second connected to the first node And a second transistor having a gate connected to the third scan line, a first pole connected to the first voltage terminal, and a second pole connected to the second node.
  • the driving module includes: a fifth transistor having a source, a drain and a gate connected to the second node; a sixth transistor having a gate connected to the light emission control line, a first electrode connected to the second voltage terminal, and a fifth transistor connected a second pole of the source; and a seventh transistor having a gate connected to the light emission control line, a first pole connected to the drain of the fifth transistor, and connected to the first The second pole of a node.
  • the compensation module includes: a third transistor having a gate connected to the second scan line, a first pole connected to the drain of the fifth transistor, and a connection to the a second pole of the second node; a fourth transistor having a gate connected to the second scan line, a first pole connected to the data line, and the source connected to the fifth transistor a second pole; and a capacitor having a first end connected to the second voltage terminal and a second end connected to the second node.
  • the lighting module includes an organic light emitting diode having a first end coupled to the first node and a second end coupled to the first voltage terminal.
  • the fifth transistor is a P-type transistor
  • the first end of the organic light emitting diode is an anode
  • the second end of the organic light emitting diode is a cathode
  • the fifth transistor is an N-type transistor
  • the first end of the organic light emitting diode is a cathode
  • the second end of the organic light emitting diode is an anode
  • the first scan line and the third scan line are configured to transmit the same signal such that the first scan signal is identical to the third scan signal.
  • a display panel including: a plurality of scanning lines arranged in a first direction; a plurality of light emission control lines arranged in the first direction; a plurality of data lines in a second direction intersecting the first direction; and a pixel array including a plurality of pixel circuits disposed at intersections of the respective scan lines, the respective light emission control lines, and the respective data lines, each of the pixel circuits And connecting to a corresponding one of the three scan lines and each of the illumination control lines and including a light emitting module, a driving module, a compensation module, and an initialization module.
  • the initialization module is coupled to the first voltage terminal and the first and third scan lines of the corresponding three scan lines and configured to be responsive to the first scan signal and the third scan on the first scan line
  • the third scan signal on the line initializes the drive module and the light emitting module with a first voltage supplied by the first voltage terminal.
  • the compensation module is connected to the second scan of the corresponding three scan lines Depicting a line, a data line, and a second voltage terminal and configured to write a data voltage on the data line to the drive module and to the drive module in response to a second scan signal on the second scan line Perform threshold voltage compensation.
  • the driving module is coupled to the second voltage terminal and the corresponding one of the light emission control lines and configured to generate the data voltage dependent on the writing in response to the light emission control signal on the corresponding one of the light emission control lines Current.
  • the light emitting module is coupled between the driving module and the first voltage terminal and configured to be illuminated by the generated current.
  • a display device including the display panel as described above.
  • a method of driving a pixel circuit includes an initialization module connected to the first voltage terminal, the first scan line and the third scan line, a compensation module connected to the second scan line, the data line and the second voltage terminal, and connected to the second voltage terminal And a driving module of the illumination control line, and a light emitting module connected between the driving module and the first voltage end.
  • the method includes: utilizing, by the initialization module, a first voltage supplied by the first voltage terminal in response to a first scan signal on the first scan line and a third scan signal on the third scan line Initializing the driving module and the lighting module; writing, by the compensation module, a data voltage on the data line to the driving module in response to a second scanning signal on the second scanning line
  • the driving module performs threshold voltage compensation; and supplies, by the driving module, a current dependent on the written data voltage to the lighting module in response to an emission control signal on the lighting control line to drive the The light module emits light.
  • the initialization module includes a first transistor and a second transistor
  • the compensation module includes a third transistor, a fourth transistor, and a capacitor
  • the driving module includes a fifth transistor, a sixth transistor, and a seventh transistor
  • the light emitting module comprises an organic light emitting diode.
  • the initializing the driving module and the light emitting module includes applying the first voltage to a gate of the fifth transistor and both ends of the light emitting diode through the first and second transistors, respectively.
  • Writing the data voltage to the driving module and performing threshold voltage compensation on the driving module includes using the fourth, fifth, and third transistors to threshold voltages of the data voltage and the fifth transistor Writing to the gate of the fifth transistor.
  • Supplying the current to the light emitting module includes providing a current path through which the current flows, the current path including the sixth, fifth, and seventh transistors and the organic light emitting diodes connected in series.
  • the applying the first voltage to the gate of the fifth transistor and the two ends of the organic light emitting diode through the first and second transistors, respectively, respectively comprise The first and second transistors are turned on during successive two periods.
  • FIG. 1 schematically illustrates a block diagram of a pixel circuit in accordance with an embodiment of the present disclosure
  • FIG. 2 schematically illustrates a block diagram of a pixel circuit in accordance with an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram showing a circuit diagram of the pixel circuit of FIG. 1;
  • FIG. 4 is a schematic diagram showing a circuit diagram of the pixel circuit of FIG. 2;
  • FIG. 5 schematically illustrates a timing diagram for the pixel circuit of FIG. 4
  • Figure 6 schematically illustrates a timing diagram for the pixel circuit of Figure 3;
  • FIG. 7 schematically illustrates a block diagram of a display device in accordance with an embodiment of the present disclosure.
  • FIG. 1 schematically illustrates a block diagram of a pixel circuit in accordance with an embodiment of the present disclosure.
  • the pixel circuit includes an initialization module 10 , a compensation module 20 , a driving module 30 , and a lighting module 40 .
  • the initialization module 10 is connected to the first voltage terminal VSS, the first scan line S[2n], and the third scan line S[2n-1].
  • the initialization module 10 is configured to be supplied with the first voltage terminal VSS in response to the first scan signal on the first scan line S[2n] and the third scan signal on the third scan line S[2n-1]
  • a voltage initializes the drive module 30 and the illumination module 40.
  • the first scan line S[2n] and the third scan line S[2n-1] are configured to transmit the same signal such that the first scan signal is identical to the third scan signal. Therefore, the first scan line S[2n] and the third scan line S[2n-1] are shown in FIG. 1 as a single signal terminal indicated by "S[2n]/S[2n-1]".
  • the compensation module 20 is connected to the second scan line S[2n+1], the data line D[m], and the second voltage terminal VDD.
  • the compensation module 20 is configured to write the data voltage on the data line D[m] to the driving module 30 and perform threshold voltage compensation on the driving module 30 in response to the second scan signal on the second scan line S[2n+1] .
  • the drive module 30 is connected to the second voltage terminal VDD and the light emission control line EM[n].
  • the drive module 30 is configured to generate a current dependent on the written data voltage in response to the illumination control signal on the illumination control line EM[n].
  • the light emitting module 40 is connected between the driving module 30 and the first voltage terminal VSS.
  • the light emitting module 40 is configured to be illuminated by the generated current.
  • threshold voltage compensation is performed by the compensation module 20, and the light flows through
  • the current of the module 40 can be controlled such that it is independent of the threshold voltage of the drive module 30, thereby eliminating the effect of the threshold voltage on the brightness of the light module 40 and improving the brightness uniformity of the display.
  • FIG. 2 schematically illustrates a block diagram of a pixel circuit in accordance with an embodiment of the present disclosure.
  • first scan line S[2n] and the third scan line S[2n-1] are shown as separate signal terminals, which can transmit different scan signals, such as Will be described later.
  • the separated first scan line S[2n] and third scan line S[2n-1] may also be used to transmit the same scan signal.
  • FIG. 3 and 4 schematically illustrate circuit diagrams of the pixel circuits of Figs. 1 and 2, respectively.
  • the initialization module 10 includes a first transistor T1 and a second transistor T2.
  • the first transistor T1 has a gate connected to the first scan line S[2n] (indicated by "S[2n]/S[2n-1]” in FIG. 3), and first connected to the first voltage terminal VSS a pole, and a second pole connected to the first node N1.
  • the second transistor T2 has a gate connected to the third scan line S[2n-1] (indicated by "S[2n]/S[2n-1]" in FIG. 3), connected to the first voltage terminal VSS a first pole and a second pole connected to the second node N2.
  • the driving module 30 includes a fifth transistor T5 (which functions as a driving transistor), a sixth transistor T6, and a seventh transistor T7.
  • the fifth transistor T5 has a source, a drain, and a gate connected to the second node N2.
  • the sixth transistor T6 has a gate connected to the light emission control line EM[n], a first electrode connected to the second voltage terminal VDD, and a second electrode connected to the source of the fifth transistor T5.
  • the seventh transistor T7 has a gate connected to the light emission control line EM[n], a first electrode connected to the drain of the fifth transistor T5, and a second electrode connected to the first node N1.
  • the compensation module 20 includes a third transistor T3, a fourth transistor T4, and a capacitor C.
  • the third transistor T3 has a gate connected to the second scan line S[2n+1], a first pole connected to the drain of the fifth transistor T5, and a second pole connected to the second node N2.
  • the fourth transistor T4 has a gate connected to the second scan line S[2n+1], a first pole connected to the data line D[m], and a second pole connected to the source of the fifth transistor T5.
  • the capacitor C has a first end connected to the second voltage terminal VDD and a second end connected to the second node N2.
  • the light emitting module 40 includes an organic light emitting diode L having a first end connected to the first node N1 and a second end connected to the first voltage terminal VSS.
  • the fifth transistor T5 is a P-type transistor
  • the first end of the organic light emitting diode L is an anode
  • the second end of the organic light emitting diode L is a cathode
  • the fifth transistor T5 is an N-type crystal
  • the first end of the organic light emitting diode L is a cathode
  • the second end of the organic light emitting diode L is an anode.
  • the first, second, third, fourth, sixth, and seventh transistors T1, T2, T3, T4, T6, T7 act as switching transistors, which are typically fabricated such that their first poles Used interchangeably with the second pole.
  • FIG. 5 schematically illustrates a timing diagram for the pixel circuit of FIG.
  • the operation of the pixel circuit of FIG. 4 will be described in detail below with reference to FIG. It is assumed that in the pixel circuit of FIG. 4: 1) each transistor is a P-type transistor; 2) a first voltage terminal VSS supplies a low-level voltage; and 3) a second voltage terminal VDD supplies a high-level voltage.
  • a low level is indicated by "0”
  • a high level is indicated by "1".
  • the operation of the pixel circuit includes an initialization phase P1, a data write and threshold voltage compensation phase P2, and an illumination phase P3.
  • the initialization module 10 is supplied with the first voltage terminal VSS in response to the first scan signal on the first scan line S[2n] and the third scan signal on the third scan line S[2n-1].
  • the first voltage initializes the drive module 30 and the lighting module 40.
  • the initialization phase P1 may include a first sub-phase P1 1 and a second sub-phase P1 2 .
  • the second transistor T2 is turned on to transfer the low level of the first voltage terminal VSS to the second node N2, thereby initializing the gate voltage of the fifth transistor T5 to clear the influence of the data voltage of the previous image frame.
  • initialization is only required by the voltage supplied from a single first voltage terminal VSS, thereby reducing the amount of power required in the pixel circuit. This facilitates the simplification of the circuit.
  • the compensation module 20 writes the data voltage on the data line D[m] to the drive module 30 in response to the second scan signal on the second scan line S[2n+1]
  • the threshold voltage compensation is performed on the drive module 30.
  • the fourth transistor T4 is turned on to transfer the data voltage Vdata on the data line D[m] to the first The source of the five transistor T5.
  • Vds is the drain-source voltage of the fifth transistor T5, and Vth is the threshold voltage of the fifth transistor T5. Therefore, the gate voltage Vg of the fifth transistor T5 is Vdata+Vth.
  • data writing can be realized by the fourth, fifth and third transistors T4, T5, T3 without charging and discharging of a large-sized capacitor.
  • This allows a pixel circuit with a reduced footprint and thus an improved PPI (Pixels Per Inch).
  • the driving module 30 supplies a current dependent on the written data voltage Vdata to the lighting module 40 in response to the lighting control signal on the lighting control line EM[n] to drive the lighting module 40 to emit light.
  • the sixth transistor T6 and the seventh transistor T7 are turned on.
  • the fifth transistor T5 operates in a saturated state and generates a drive current I as follows:
  • K is a parameter associated with the fifth transistor T5, which can be regarded as a constant.
  • the current I for driving the light emission of the organic light emitting diode L is independent of the threshold voltage Vth of the fifth transistor T5, thereby eliminating the threshold voltage Vth of the driving transistor (ie, the fifth transistor T5) from the organic light emitting diode.
  • the effect of the brightness of L improves the brightness uniformity of the display.
  • FIG. 6 schematically illustrates a timing diagram for the pixel circuit of FIG.
  • the initialization phase P1 need not be further divided into the first sub-phase P1 1 and the second sub-phase. P1 2 .
  • the first scan line S[2n] and the third scan line S[2n-1] may also be configured to transmit the same signal, and thus the timing diagram of FIG. Also applicable to the pixel circuit of FIG.
  • each transistor is described as a P-type transistor.
  • the control signal shown in Figure 5 or Figure 6 needs to be flipped to drive the corresponding transistor.
  • FIG. 7 schematically illustrates a block diagram of a display device 700 in accordance with an embodiment of the present disclosure.
  • the display device 700 includes a display panel 710, a first scan driver 702, a second scan driver 704, a data driver 706, and a power source 708.
  • Display panel 710 includes a pixel array that includes n x m pixel circuits P. Each pixel circuit P includes an OLED.
  • the display panel 710 includes 2n+1 scan lines S1, S2, . . . , S2n, S2n+1 arranged in a first direction (row direction in the drawing) to transmit a scan signal; Two directions (column directions in the figure) are arranged to transmit m data lines D1, D2, ..., Dm of data signals; n light-emitting control lines EM1, EM2 arranged in a first direction to transmit light-emission control signals, ..., EMn; and m first wires (not shown) and m second wires (not shown) for applying the first and second voltages VDD and VSS.
  • n and m are natural numbers.
  • the first scan driver 702 is connected to the scan lines S1, S2, . . . , S2n, S2n+1 to apply a scan signal to the display panel 710.
  • the second scan driver 704 is connected to the illumination control lines EM1, EM2, . . . , EMn, EMn+1 to apply the illumination control signals to the display panel 710.
  • the data driver 706 is connected to the data lines D1, D2, . . . , Dm to apply the data signals to the display panel 710.
  • the data driver 706 supplies the data signal to the pixel circuit P of the display panel 710 during the data writing phase.
  • the power source 708 applies the first voltage VSS and the second voltage VDD to each of the pixel circuits P in the display panel 710.
  • the display device 700 can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.

Abstract

一种像素电路（P）、显示面板（710）、显示装置（700）和驱动像素电路（P）的方法，像素电路（P）包括：发光模块（40）、驱动模块（30）、补偿模块（20）以及初始化模块（10）。初始化模块（10）被配置成响应于第一和第三扫描信号而利用第一电压对驱动模块（30）和发光模块（40）进行初始化。补偿模块（20）被配置成响应于第二扫描信号而将数据电压写入驱动模块（30）并对驱动模块（30）进行阈值电压补偿。驱动模块（30）被配置成响应于发光控制信号而生成依赖于写入的数据电压的电流。发光模块（40）被配置成受生成的电流驱动而发光。

Description

像素电路及其驱动方法、显示面板和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种像素电路及其驱动方法、显示面板和显示装置。
背景技术
现有的有机发光显示器存在一些问题。有机发光二极管(OLED)属于电流驱动型器件，其需要稳定的电流来控制光发射。由于工艺制程和器件老化等原因，各OLED像素电路中的驱动晶体管可能具有不同的阈值电压，导致每个OLED针对相同的数据信号呈现不同的亮度。这可以造成不同显示区域之间的亮度不均匀。
发明内容
本公开的实施例提供一种像素电路，其寻求减轻、缓解或消除上述问题中的至少一个。
根据本公开的一方面，提供了一种像素电路，其包括发光模块、驱动模块、补偿模块以及初始化模块。所述初始化模块连接到第一电压端、第一扫描线和第三扫描线并且被配置成响应于所述第一扫描线上的第一扫描信号和所述第三扫描线上的第三扫描信号而利用所述第一电压端供应的第一电压对所述驱动模块和所述发光模块进行初始化。所述补偿模块连接到第二扫描线、数据线和第二电压端并且被配置成响应于所述第二扫描线上的第二扫描信号而将所述数据线上的数据电压写入所述驱动模块并对所述驱动模块进行阈值电压补偿。所述驱动模块连接到所述第二电压端和发光控制线并且被配置成响应于所述发光控制线上的发光控制信号而生成依赖于写入的所述数据电压的电流。所述发光模块连接在所述驱动模块与所述第一电压端之间并且被配置成受生成的所述电流驱动而发光。
在一些实施例中，所述初始化模块包括：第一晶体管，具有连接到所述第一扫描线的栅极、连接到所述第一电压端的第一极、以及连接到第一节点的第二极；和第二晶体管，具有连接到所述第三扫描线的栅极、连接到所述第一电压端的第一极、以及连接到第二节点的第二极。
在一些实施例中，所述驱动模块包括：第五晶体管，具有源极、 漏极和连接到所述第二节点的栅极；第六晶体管，具有连接到所述发光控制线的栅极、连接到所述第二电压端的第一极、以及连接到所述第五晶体管的所述源极的第二极；和第七晶体管，具有连接到所述发光控制线的栅极、连接到所述第五晶体管的所述漏极的第一极、以及连接到所述第一节点的第二极。
在一些实施例中，所述补偿模块包括：第三晶体管，具有连接到所述第二扫描线的栅极、连接到所述第五晶体管的所述漏极的第一极、以及连接到所述第二节点的第二极；第四晶体管，具有连接到所述第二扫描线的栅极、连接到所述数据线的第一极、以及连接到所述第五晶体管的所述源极的第二极；和电容，具有连接到所述第二电压端的第一端和连接到所述第二节点的第二端。
在一些实施例中，所述发光模块包括有机发光二极管，其具有连接到所述第一节点的第一端和连接到所述第一电压端的第二端。
在一些实施例中，所述第五晶体管为P型晶体管，所述有机发光二极管的所述第一端为阳极，并且所述有机发光二极管的所述第二端为阴极。
在一些实施例中，所述第五晶体管为N型晶体管，所述有机发光二极管的所述第一端为阴极，并且所述有机发光二极管的所述第二端为阳极。
在一些实施例中，所述第一扫描线和所述第三扫描线被配置成传输相同的信号使得所述第一扫描信号与所述第三扫描信号相同。
根据本公开的另一方面，提供了一种显示面板，其包括：布置在第一方向上的多条扫描线；布置在所述第一方向上的多条发光控制线；布置在与所述第一方向交叉的第二方向上的多条数据线；以及像素阵列，包括布置在各扫描线、各发光控制线和各数据线的交叉处的多个像素电路，各像素电路中的每一个连接到各扫描线中的对应三条扫描线和各发光控制线中的对应一条发光控制线并且包括发光模块、驱动模块、补偿模块以及初始化模块。所述初始化模块连接到第一电压端和所述对应三条扫描线中的第一和第三扫描线并且被配置成响应于所述第一扫描线上的第一扫描信号和所述第三扫描线上的第三扫描信号而利用所述第一电压端供应的第一电压对所述驱动模块和所述发光模块进行初始化。所述补偿模块连接到所述对应三条扫描线中的第二扫 描线、数据线和第二电压端并且被配置成响应于所述第二扫描线上的第二扫描信号而将所述数据线上的数据电压写入所述驱动模块并对所述驱动模块进行阈值电压补偿。所述驱动模块连接到所述第二电压端和所述对应一条发光控制线并且被配置成响应于所述对应一条发光控制线上的发光控制信号而生成依赖于写入的所述数据电压的电流。所述发光模块连接在所述驱动模块与所述第一电压端之间并且被配置成受生成的所述电流驱动而发光。
根据本公开的又另一方面，提供了一种显示装置，其包括如上所述的显示面板。
根据本公开的再另一方面，提供了一种驱动像素电路的方法。所述像素电路包括连接到第一电压端、第一扫描线和第三扫描线的初始化模块、连接到第二扫描线、数据线和第二电压端的补偿模块、连接到所述第二电压端和发光控制线的驱动模块、以及连接在所述驱动模块与所述第一电压端之间的发光模块。所述方法包括：由所述初始化模块响应于所述第一扫描线上的第一扫描信号和所述第三扫描线上的第三扫描信号而利用所述第一电压端供应的第一电压对所述驱动模块和所述发光模块进行初始化；由所述补偿模块响应于所述第二扫描线上的第二扫描信号而将所述数据线上的数据电压写入所述驱动模块并对所述驱动模块进行阈值电压补偿；以及由所述驱动模块响应于所述发光控制线上的发光控制信号而将依赖于写入的所述数据电压的电流供应给所述发光模块以驱动所述发光模块发光。
在一些实施例中，所述初始化模块包括第一晶体管和第二晶体管，所述补偿模块包括第三晶体管、第四晶体管以及电容，所述驱动模块包括第五晶体管、第六晶体管和第七晶体管，并且所述发光模块包括有机发光二极管。所述对所述驱动模块和所述发光模块进行初始化包括分别通过所述第一和第二晶体管将所述第一电压施加到所述第五晶体管的栅极和所述发光二极管的两端。所述将所述数据电压写入所述驱动模块并对所述驱动模块进行阈值电压补偿包括通过所述第四、第五和第三晶体管将所述数据电压和所述第五晶体管的阈值电压写入所述第五晶体管的栅极。将所述电流供应给所述发光模块包括提供所述电流流过其的电流路径，所述电流路径包括串联连接的所述第六、第五和第七晶体管和所述有机发光二极管。
在一些实施例中，所述分别通过所述第一和第二晶体管将所述第一电压施加到所述第五晶体管的所述栅极和所述有机发光二极管的所述两端包括分别在接连的两个时间段期间导通所述第一和第二晶体管。
根据在下文中所描述的实施例，本公开的这些和其它方面将是清楚明白的，并且将参考在下文中所描述的实施例而被阐明。
附图说明
在下面结合附图对于示例性实施例的描述中，本公开的更多细节、特征和优点被公开，在附图中：
图1示意性地图示出根据本公开实施例的像素电路的框图；
图2示意性地图示出根据本公开实施例的像素电路的框图；
图3示意性地图示出图1的像素电路的电路图；
图4示意性地图示出图2的像素电路的电路图；
图5示意性地图示出用于图4的像素电路的时序图；
图6示意性地图示出用于图3的像素电路的时序图；并且
图7示意性地图示出根据本公开实施例的显示装置的框图。
具体实施方式
将理解的是，尽管术语第一、第二、第三等等在本文中可以用来描述各种元件、部件和/或部分，但是这些元件、部件和/或部分不应当由这些术语限制。这些术语仅用来将一个元件、部件或部分与另一个元件、部件或部分相区分。因此，下面讨论的第一元件、部件或部分可以被称为第二元件、部件或部分而不偏离本公开的教导。
本文中使用的术语仅出于描述特定实施例的目的并且不意图限制本公开。如本文中使用的，单数形式“一个”、“一”和“该”意图也包括复数形式，除非上下文清楚地另有指示。将进一步理解的是，术语“包括”和/或“包含”当在本说明书中使用时指定所述及特征、整体、步骤、操作、元件和/或部件的存在，但不排除一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组的存在或添加一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组。如本文中使用的，术语“和/或”包括相关联的列出项目中的一个或多个的任意和全部组合。
将理解的是，当元件被称为“连接到另一个元件”或“耦合到另 一个元件”时，其可以直接连接到另一个元件或直接耦合到另一个元件，或者可以存在中间元件。相反，当元件被称为“直接连接到另一个元件或层”、“直接耦合到另一个元件或层”时，没有中间元件存在。
除非另有定义，本文中使用的所有术语(包括技术术语和科学术语)具有与本公开所属领域的普通技术人员所通常理解的相同含义。将进一步理解的是，诸如那些在通常使用的字典中定义的之类的术语应当被解释为具有与其在相关领域和/或本说明书上下文中的含义相一致的含义，并且将不在理想化或过于正式的意义上进行解释，除非本文中明确地如此定义。
下面将结合附图详细描述本公开的实施例。
图1示意性地图示出根据本公开实施例的像素电路的框图。如图1所示，该像素电路包括初始化模块10、补偿模块20、驱动模块30以及发光模块40。
初始化模块10连接到第一电压端VSS、第一扫描线S[2n]和第三扫描线S[2n-1]。该初始化模块10被配置成响应于第一扫描线S[2n]上的第一扫描信号和第三扫描线S[2n-1]上的第三扫描信号而利用第一电压端VSS供应的第一电压对驱动模块30和发光模块40进行初始化。
在该实施例中，第一扫描线S[2n]和第三扫描线S[2n-1]被配置成传输相同的信号使得第一扫描信号与第三扫描信号相同。因此，第一扫描线S[2n]和第三扫描线S[2n-1]在图1中被示出为由“S[2n]/S[2n-1]”指示的单个信号端。
补偿模块20连接到第二扫描线S[2n+1]、数据线D[m]和第二电压端VDD。补偿模块20被配置成响应于第二扫描线S[2n+1]上的第二扫描信号而将数据线D[m]上的数据电压写入驱动模块30并对驱动模块30进行阈值电压补偿。
驱动模块30连接到第二电压端VDD和发光控制线EM[n]。驱动模块30被配置成响应于发光控制线EM[n]上的发光控制信号而生成依赖于写入的数据电压的电流。
发光模块40连接在驱动模块30与第一电压端VSS之间。发光模块40被配置成受生成的所述电流驱动而发光。
如稍后将描述的，通过补偿模块20执行阈值电压补偿，流过发光 模块40的电流可以被控制使得其与驱动模块30的阈值电压无关，从而消除了阈值电压对发光模块40的亮度的影响，并且提高了显示器的亮度均匀性。
图2示意性地图示出根据本公开实施例的像素电路的框图。
该实施例不同于图1的实施例，在于第一扫描线S[2n]和第三扫描线S[2n-1]被示出为分开的信号端，其可以传输不同的扫描信号，如稍后将描述的。可替换地，分开的第一扫描线S[2n]和第三扫描线S[2n-1]也可以用来传输相同的扫描信号。
图3和图4分别示意性地图示出图1和图2的像素电路的电路图。
初始化模块10包括第一晶体管T1和第二晶体管T2。第一晶体管T1具有连接到第一扫描线S[2n](在图3中由“S[2n]/S[2n-1]”指示)的栅极、连接到第一电压端VSS的第一极、以及连接到第一节点N1的第二极。第二晶体管T2具有连接到第三扫描线S[2n-1](在图3中由“S[2n]/S[2n-1]”指示)的栅极、连接到第一电压端VSS的第一极、以及连接到第二节点N2的第二极。
驱动模块30包括第五晶体管T5(其充当驱动晶体管)、第六晶体管T6以及第七晶体管T7。第五晶体管T5具有源极、漏极和连接到第二节点N2的栅极。第六晶体管T6具有连接到发光控制线EM[n]的栅极、连接到第二电压端VDD的第一极、以及连接到第五晶体管T5的源极的第二极。第七晶体管T7具有连接到发光控制线EM[n]的栅极、连接到第五晶体管T5的漏极的第一极、以及连接到第一节点N1的第二极。
补偿模块20包括第三晶体管T3、第四晶体管T4以及电容C。第三晶体管T3具有连接到第二扫描线S[2n+1]的栅极、连接到第五晶体管T5的漏极的第一极、以及连接到第二节点N2的第二极。第四晶体管T4具有连接到第二扫描线S[2n+1]的栅极、连接到数据线D[m]的第一极、以及连接到第五晶体管T5的源极的第二极。电容C具有连接到第二电压端VDD的第一端和连接到第二节点N2的第二端。
发光模块40包括有机发光二极管L，其具有连接到第一节点N1的第一端和连接到第一电压端VSS的第二端。在其中第五晶体管T5为P型晶体管的实施例中，有机发光二极管L的第一端为阳极，并且有机发光二极管L的第二端为阴极。在其中第五晶体管T5为N型晶 体管的实施例中，有机发光二极管L的第一端为阴极，并且有机发光二极管L的第二端为阳极。
在各实施例中，第一、第二、第三、第四、第六和第七晶体管T1、T2、T3、T4、T6、T7充当开关晶体管，其典型地被制作使得它们的第一极和第二极可互换地使用。
图5示意性地图示出用于图4的像素电路的时序图。以下结合图5对图4的像素电路的操作进行详细描述。假定在图4的像素电路中：1)各个晶体管为P型晶体管；2)第一电压端VSS供应低电平电压；并且3)第二电压端VDD供应高电平电压。在下文中，以“0”表示低电平，并且以“1”表示高电平。
该像素电路的操作包括初始化阶段P1、数据写入和阈值电压补偿阶段P2以及发光阶段P3。
在初始化阶段P1期间，初始化模块10响应于第一扫描线S[2n]上的第一扫描信号和第三扫描线S[2n-1]上的第三扫描信号而利用第一电压端VSS供应的第一电压对驱动模块30和发光模块40进行初始化。具体地，初始化阶段P1可以包括第一子阶段P11和第二子阶段P12。
在第一子阶段P11，S[2n]＝1，S[2n+1]＝1，S[2n-1]＝0，EM[n]＝1。第一晶体管T1导通以将第一电压端VSS的低电平传输至第一节点N1。此时，跨有机发光二极管L两端的电压为零，使得发光二极管L被初始化以清除上一图像帧的数据电压的影响。
在第二子阶段P12，S[2n-1]＝1，S[2n+1]＝1，S[2n-1]＝0，EM[n]＝1。
第二晶体管T2导通以将第一电压端VSS的低电平传输至第二节点N2，从而初始化第五晶体管T5的栅极电压以清除上一图像帧的数据电压的影响。
在初始化阶段P1中，只需要由单个第一电压端VSS供应的电压来实现初始化，从而减少了像素电路中需要的电源的数量。这有利于电路的简化。
在数据写入和阈值电压补偿阶段P2期间，补偿模块20响应于第二扫描线S[2n+1]上的第二扫描信号而将数据线D[m]上的数据电压写入驱动模块30并对驱动模块30进行阈值电压补偿。
具体地，S[2n]＝1，S[2n+1]＝0，S[2n-1]＝1，EM[n]＝1。
第四晶体管T4导通以将数据线D[m]上的数据电压Vdata传输至第 五晶体管T5的源极。第三晶体管T3导通以使第五晶体管T5的漏极和栅极导通，在该情况下第五晶体管T5操作于其中Vds＝Vth的二极管模式下。Vds为第五晶体管T5的漏-源电压，并且Vth为第五晶体管T5的阈值电压。因此，第五晶体管T5的栅极电压Vg＝Vdata+Vth。
在此阶段P2中，数据写入可以通过第四、第五和第三晶体管T4、T5、T3来实现，而无需大尺寸电容的充放电。这允许具有减小的占用面积(footprint)的像素电路并且因此提高的PPI(Pixels Per Inch)。
在发光阶段P3期间，驱动模块30响应于发光控制线EM[n]上的发光控制信号而将依赖于写入的数据电压Vdata的电流供应给发光模块40以驱动所述发光模块40发光。
具体地，S[2n]＝1，S[2n+1]＝1，S[2n-1]＝1，EM[n]＝0。
第六晶体管T6和第七晶体管T7导通。第五晶体管T5(驱动晶体管)的栅-源电压Vgs＝Vg-Vs＝Vdata+Vth-VDD。第五晶体管T5操作于饱和状态并且生成驱动电流I如下：
I＝K(Vgs-Vth)2
＝K(Vdata+Vth-VDD-Vth)2
＝K(Vdata-VDD)2              (1)
其中，K为关联于第五晶体管T5的参数，其可以视为常数。
由等式(1)可知，用于驱动有机发光二极管L发光的电流I与第五晶体管T5的阈值电压Vth无关，从而消除了驱动晶体管(即第五晶体管T5)的阈值电压Vth对有机发光二极管L的亮度的影响，提高了显示器的亮度均一性。
上面参照图5描述了图4的像素电路的操作。图6示意性地图示出用于图3的像素电路的时序图。如图6所示，由于第一扫描线S[2n]和第三扫描线S[2n-1]传输相同的信号，因此初始化阶段P1无需再划分为第一子阶段P11和第二子阶段P12。
将理解的是，对于图4的像素电路而言，第一扫描线S[2n]和第三扫描线S[2n-1]也可以被配置成传输相同的信号，并且因此图6的时序图也适用于图4的像素电路。此外，在上面的描述中，各个晶体管被描述为P型晶体管。在N型晶体管的情况下，图5或图6所示的控制信号需要进行翻转以驱动对应的晶体管。
图7示意性地图示出根据本公开实施例的显示装置700的框图。 参见图7，显示装置700包括显示面板710、第一扫描驱动器702、第二扫描驱动器704、数据驱动器706和电源708。
显示面板710包括像素阵列，其包括n×m个像素电路P。每个像素电路P包括OLED。显示面板710包括以第一方向(在图中为行方向)布置以传送扫描信号的2n+1条扫描线S1，S2，...，S2n，S2n+1；以与第一方向交叉的第二方向(在图中为列方向)布置以传送数据信号的m条数据线D1，D2，...，Dm；以第一方向布置以传送发光控制信号的n条发光控制线EM1，EM2，...，EMn；以及用于施加第一和第二电压VDD和VSS的m条第一电线(未示出)和m条第二电线(未示出)。n和m是自然数。
第一扫描驱动器702连接至扫描线S1，S2，...，S2n，S2n+1，以将扫描信号施加至显示面板710。
第二扫描驱动器704连接至发光控制线EM1，EM2，...，EMn，EMn+1，以将发光控制信号施加至显示面板710。
数据驱动器706连接至数据线D1，D2，...，Dm，以将数据信号施加至显示面板710。这里，数据驱动器706在数据写入阶段期间将数据信号供给显示面板710的像素电路P。
电源708将第一电压VSS和第二电压VDD施加至显示面板710中的每个像素电路P。
该显示装置700可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
鉴于前面的描述并结合阅读附图，对前述本公开的示例性实施例的各种修改和改动对于相关领域的技术人员可以变得清楚明白。任何和所有修改仍将落入本公开的非限制性和示例性实施例的范围内。此外，属于本公开的这些实施例所属领域的技术人员，在得益于前面的描述和相关附图所给出的教导后，将会想到在此描述的本公开的其他实施例。

Claims (20)

  1. 一种像素电路，包括发光模块、驱动模块、补偿模块以及初始化模块，其中：
    所述初始化模块连接到第一电压端、第一扫描线和第三扫描线并且被配置成响应于所述第一扫描线上的第一扫描信号和所述第三扫描线上的第三扫描信号而利用所述第一电压端供应的第一电压对所述驱动模块和所述发光模块进行初始化；
    所述补偿模块连接到第二扫描线、数据线和第二电压端并且被配置成响应于所述第二扫描线上的第二扫描信号而将所述数据线上的数据电压写入所述驱动模块并对所述驱动模块进行阈值电压补偿；
    所述驱动模块连接到所述第二电压端和发光控制线并且被配置成响应于所述发光控制线上的发光控制信号而生成依赖于写入的所述数据电压的电流；并且
    所述发光模块连接在所述驱动模块与所述第一电压端之间并且被配置成受生成的所述电流驱动而发光。
  2. 根据权利要求1所述的像素电路，其中所述初始化模块包括：
    第一晶体管，具有连接到所述第一扫描线的栅极、连接到所述第一电压端的第一极、以及连接到第一节点的第二极；和
    第二晶体管，具有连接到所述第三扫描线的栅极、连接到所述第一电压端的第一极、以及连接到第二节点的第二极。
  3. 根据权利要求2所述的像素电路，其中所述驱动模块包括：
    第五晶体管，具有源极、漏极和连接到所述第二节点的栅极；
    第六晶体管，具有连接到所述发光控制线的栅极、连接到所述第二电压端的第一极、以及连接到所述第五晶体管的所述源极的第二极；和
    第七晶体管，具有连接到所述发光控制线的栅极、连接到所述第五晶体管的所述漏极的第一极、以及连接到所述第一节点的第二极。
  4. 根据权利要求3所述的像素电路，其中所述补偿模块包括：
    第三晶体管，具有连接到所述第二扫描线的栅极、连接到所述第五晶体管的所述漏极的第一极、以及连接到所述第二节点的第二极；
    第四晶体管，具有连接到所述第二扫描线的栅极、连接到所述数 据线的第一极、以及连接到所述第五晶体管的所述源极的第二极；和
    电容，具有连接到所述第二电压端的第一端和连接到所述第二节点的第二端。
  5. 根据权利要求3所述的像素电路，其中所述发光模块包括有机发光二极管，其具有连接到所述第一节点的第一端和连接到所述第一电压端的第二端。
  6. 根据权利要求5所述的像素电路，其中所述第五晶体管为P型晶体管，其中所述有机发光二极管的所述第一端为阳极，并且其中所述有机发光二极管的所述第二端为阴极。
  7. 根据权利要求5所述的像素电路，其中所述第五晶体管为N型晶体管，其中所述有机发光二极管的所述第一端为阴极，并且其中所述有机发光二极管的所述第二端为阳极。
  8. 根据权利要求1-7中任一项所述的像素电路，其中所述第一扫描线和所述第三扫描线被配置成传输相同的信号使得所述第一扫描信号与所述第三扫描信号相同。
  9. 一种显示面板，包括：
    布置在第一方向上的多条扫描线；
    布置在所述第一方向上的多条发光控制线；
    布置在与所述第一方向交叉的第二方向上的多条数据线；以及
    像素阵列，包括布置在各扫描线、各发光控制线和各数据线的交叉处的多个像素电路，各像素电路中的每一个连接到各扫描线中的对应三条扫描线和各发光控制线中的对应一条发光控制线并且包括发光模块、驱动模块、补偿模块以及初始化模块，其中：
    所述初始化模块连接到第一电压端和所述对应三条扫描线中的第一和第三扫描线并且被配置成响应于所述第一扫描线上的第一扫描信号和所述第三扫描线上的第三扫描信号而利用所述第一电压端供应的第一电压对所述驱动模块和所述发光模块进行初始化；
    所述补偿模块连接到所述对应三条扫描线中的第二扫描线、数据线和第二电压端并且被配置成响应于所述第二扫描线上的第二扫描信号而将所述数据线上的数据电压写入所述驱动模块并对所述驱动模块进行阈值电压补偿；
    所述驱动模块连接到所述第二电压端和所述对应一条发光控制线并且被配置成响应于所述对应一条发光控制线上的发光控制信号而生成依赖于写入的所述数据电压的电流；并且
    所述发光模块连接在所述驱动模块与所述第一电压端之间并且被配置成受生成的所述电流驱动而发光。
  10. 根据权利要求9所述的显示面板，其中所述初始化模块包括：
    第一晶体管，具有连接到所述第一扫描线的栅极、连接到所述第一电压端的第一极、以及连接到第一节点的第二极；和
    第二晶体管，具有连接到所述第三扫描线的栅极、连接到所述第一电压端的第一极、以及连接到第二节点的第二极。
  11. 根据权利要求10所述的显示面板，其中所述驱动模块包括：
    第五晶体管，具有源极、漏极和连接到所述第二节点的栅极；
    第六晶体管，具有连接到所述对应一条发光控制线的栅极、连接到所述第二电压端的第一极、以及连接到所述第五晶体管的所述源极的第二极；和
    第七晶体管，具有连接到所述对应一条发光控制线的栅极、连接到所述第五晶体管的所述漏极的第一极、以及连接到所述第一节点的第二极。
  12. 根据权利要求11所述的显示面板，其中所述补偿模块包括：
    第三晶体管，具有连接到所述第二扫描线的栅极、连接到所述第五晶体管的所述漏极的第一极、以及连接到所述第二节点的第二极；
    第四晶体管，具有连接到所述第二扫描线的栅极、连接到所述数据线的第一极、以及连接到所述第五晶体管的所述源极的第二极；和
    电容，具有连接所述第二电压端的第一端和连接到所述第二节点的第二端。
  13. 根据权利要求11所述的显示面板，其中所述发光模块包括有机发光二极管，其具有连接到所述第一节点的第一端和连接到所述第一电压端的第二端。
  14. 根据权利要求13所述的显示面板，其中所述第五晶体管为P型晶体管，其中所述有机发光二极管的所述第一端为阳极，并且其中所述有机发光二极管的所述第二端为阴极。
  15. 根据权利要求13所述的显示面板，其中所述第五晶体管为N 型晶体管，其中所述有机发光二极管的所述第一端为阴极，并且其中所述有机发光二极管的所述第二端为阳极。
  16. 根据权利要求9-15中任一项所述的显示面板，其中所述第一扫描线和所述第三扫描线被配置成传输相同的信号使得所述第一扫描信号与所述第三扫描信号相同。
  17. 一种显示装置，包括如权利要求9-16中任一项所述的显示面板。
  18. 一种驱动像素电路的方法，所述像素电路包括连接到第一电压端、第一扫描线和第三扫描线的初始化模块、连接到第二扫描线、数据线和第二电压端的补偿模块、连接到所述第二电压端和发光控制线的驱动模块、以及连接在所述驱动模块与所述第一电压端之间的发光模块，所述方法包括：
    由所述初始化模块响应于所述第一扫描线上的第一扫描信号和所述第三扫描线上的第三扫描信号而利用所述第一电压端供应的第一电压对所述驱动模块和所述发光模块进行初始化；
    由所述补偿模块响应于所述第二扫描线上的第二扫描信号而将所述数据线上的数据电压写入所述驱动模块并对所述驱动模块进行阈值电压补偿；以及
    由所述驱动模块响应于所述发光控制线上的发光控制信号而将依赖于写入的所述数据电压的电流供应给所述发光模块以驱动所述发光模块发光。
  19. 根据权利要求18所述的方法，其中所述初始化模块包括第一晶体管和第二晶体管，其中所述补偿模块包括第三晶体管、第四晶体管以及电容，其中所述驱动模块包括第五晶体管、第六晶体管和第七晶体管，其中所述发光模块包括有机发光二极管，并且其中：
    所述对所述驱动模块和所述发光模块进行初始化包括分别通过所述第一和第二晶体管将所述第一电压施加到所述第五晶体管的栅极和所述发光二极管的两端；
    所述将所述数据电压写入所述驱动模块并对所述驱动模块进行阈值电压补偿包括通过所述第四、第五和第三晶体管将所述数据电压和所述第五晶体管的阈值电压写入所述第五晶体管的栅极；并且
    将所述电流供应给所述发光模块包括提供所述电流流过其的电流 路径，所述电流路径包括串联连接的所述第六、第五和第七晶体管和所述有机发光二极管。
  20. 根据权利要求19所述的方法，其中所述分别通过所述第一和第二晶体管将所述第一电压施加到所述第五晶体管的所述栅极和所述有机发光二极管的所述两端包括分别在接连的两个时间段期间导通所述第一和第二晶体管。
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