WO2015032141A1 - 像素电路及显示器 - Google Patents

像素电路及显示器 Download PDF

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Publication number
WO2015032141A1
WO2015032141A1 PCT/CN2013/089018 CN2013089018W WO2015032141A1 WO 2015032141 A1 WO2015032141 A1 WO 2015032141A1 CN 2013089018 W CN2013089018 W CN 2013089018W WO 2015032141 A1 WO2015032141 A1 WO 2015032141A1
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WIPO (PCT)
Prior art keywords
transistor
module
pixel
gate
light
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PCT/CN2013/089018
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English (en)
French (fr)
Inventor
陈俊生
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Priority to US14/368,633 priority Critical patent/US9666131B2/en
Publication of WO2015032141A1 publication Critical patent/WO2015032141A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0443—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0465—Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0254—Control of polarity reversal in general, other than for liquid crystal displays
    • G09G2310/0256—Control of polarity reversal in general, other than for liquid crystal displays with the purpose of reversing the voltage across a light emitting or modulating element within a pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0238—Improving the black level

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a pixel circuit and a display. Background technique
  • the pixel compensation circuit in the prior art is a 6T1C circuit (a circuit composed of 6 thin film transistors and 1 capacitor), and the circuit diagram is as shown in FIG. 1.
  • VDD is a high voltage level signal
  • VSS is a low voltage level.
  • FIG. 2 is a circuit schematic diagram of two pixels arranged horizontally, which constitutes a pixel unit in a horizontal or vertical direction, which is required in the vertical direction.
  • the number of components arranged is: 1 data signal line, 12 TFTs, 2 capacitors, 2 gate control signal lines, 1 illumination control signal end Emission, 1 high voltage level signal terminal VDD, 1 initialization Voltage level signal terminal Vinit.
  • Embodiments of the present invention provide a pixel circuit for reducing pixel circuit size, thereby reducing pixel pitch, increasing the number of pixels in a unit area, and improving picture display quality.
  • the present invention also provides a display.
  • a pixel circuit includes: a first pixel sub-circuit and a second pixel sub-circuit, and an initialization module and a data voltage connected to the first pixel sub-circuit and the second pixel sub-circuit Write module,
  • the initialization module is connected to the reset signal end and the low potential end for initializing the first pixel sub-circuit and the second pixel sub-circuit under the control of the reset signal input by the reset signal terminal;
  • the data voltage writing module is connected to the data voltage and the gate signal end, and is configured to first write the first data voltage to the first pixel sub-circuit and the second pixel sub-circuit under the control of the signal input by the gate signal end, and The driving module of the first pixel sub-circuit compensates, then writes the second data voltage to the second pixel sub-circuit, and compensates the driving module of the second pixel sub-circuit.
  • the pixel circuit provided by the embodiment of the present invention includes: a first pixel sub-circuit and a second pixel sub-circuit, and an initialization module and a data voltage writing module connected to the first pixel sub-circuit and the second pixel sub-circuit.
  • the pixel circuit composed of the first pixel sub-circuit, the second pixel sub-circuit, and the initialization module and the data voltage writing module can reduce the pixel circuit size, thereby reducing the pixel pitch, and increasing the number of pixels in a unit area. , improve the display quality of the screen.
  • the first pixel sub-circuit includes a first driving module, a first lighting module, a first threshold compensation module, and a first lighting control module,
  • the initialization module is connected to the first threshold compensation module, and is configured to initialize the first threshold compensation module under the control of the initialization signal output by the initialization module;
  • the first threshold compensation module is connected to the first driving module, and is configured to perform threshold voltage compensation on the first driving module.
  • the first illuminating module is connected to the first illuminating control module for performing illuminating display under the action of the first illuminating control module.
  • the first pixel sub-circuit composed of the first driving module, the first lighting module, the first threshold compensation module and the first lighting control module is simple and easy to implement in the design of the pixel circuit.
  • the first threshold compensation module includes a first storage capacitor, a third transistor, and a fifth transistor; the first driving module includes a fourth transistor; and the first lighting control module includes a sixth crystal a body tube and a seventh transistor; the first light emitting module includes a first light emitting diode.
  • the first pixel sub-circuit consisting of the storage capacitor, the transistor and the light-emitting diode is easy to implement in the design of the pixel circuit.
  • one end of the first storage capacitor is connected to a high voltage level signal line, and the other end is connected to a source of the third transistor;
  • a gate of the third transistor is connected to a signal terminal of the gate, and a drain of the third transistor is connected to a drain of the fourth transistor;
  • a gate of the fifth transistor is connected to a switch control signal line, a source of the fifth transistor is connected to a drain of the sixth transistor, a drain of the fifth transistor is a source of the fourth transistor Extremely connected
  • a gate of the fourth transistor is connected to the initialization module
  • a gate of the sixth transistor is connected to an emission control signal line, and a source of the sixth transistor is connected to a signal line of a high voltage level;
  • a gate of the seventh transistor is connected to the light emission control signal line, a source of the seventh transistor is connected to a drain of the fourth transistor, and a drain of the seventh transistor is connected to the first light emitting diode;
  • the anode of the first light emitting diode is connected to the drain of the seventh transistor, and the cathode of the first light emitting diode is connected to the low voltage level signal line.
  • the connection relationship between the storage capacitor, the transistor, and the light emitting diode is facilitated in the design of the pixel circuit.
  • the second pixel sub-circuit includes a second driving module, a second lighting module, a second threshold compensation module, and a second lighting control module.
  • the initialization module is connected to the second threshold compensation module, and is configured to initialize the second threshold compensation module under the control of the initialization signal output by the initialization module;
  • the second threshold compensation module is connected to the second driving module, and is configured to perform threshold voltage compensation on the second driving module.
  • the second illuminating module is connected to the second illuminating control module for performing illuminating display under the action of the second illuminating control module.
  • the second pixel sub-circuit composed of the second driving module, the second lighting module, the second threshold compensation module and the second lighting control module is simple and easy to implement in the design of the pixel circuit.
  • the second threshold compensation module includes a second storage capacitor and a tenth transistor; the second driving module includes a ninth transistor; and the second illumination control module includes a sixth transistor and an eighth crystal
  • the second light emitting module includes a second light emitting diode.
  • the second pixel sub-circuit consisting of the storage capacitor, the transistor and the light-emitting diode is easy to implement in the design of the pixel circuit.
  • one end of the second storage capacitor is connected to the high voltage level signal line, and the other end is connected to the source of the tens transistor;
  • a gate of the tenth transistor is connected to a gate signal terminal, and a drain of the tenth transistor is connected to a drain of the ninth transistor;
  • a gate of the ninth transistor is connected to a source of the tenth transistor, and a source of the ninth transistor is connected to the data voltage writing module;
  • a gate of the sixth transistor is connected to the light emission control signal line, a source of the sixth transistor is connected to a high voltage level signal line, and a drain of the sixth transistor is connected to a source of the ninth transistor ;
  • a gate of the eighth transistor is connected to the light emission control signal line, a source of the eighth transistor is connected to a drain of the ninth transistor, and a drain of the eighth transistor is connected to a second light emitting diode;
  • the anode of the second light emitting diode is connected to the drain of the eighth transistor, and the cathode of the second light emitting diode is connected to the low voltage level signal line.
  • the connection relationship between the storage capacitor, the transistor, and the light emitting diode is facilitated in the design of the pixel circuit.
  • the initialization module includes a first transistor and an eleventh transistor, wherein a gate of the first transistor is connected to a reset signal line, and a drain of the first transistor and a first pixel sub-circuit a threshold compensation module is connected, a source of the first transistor is connected to a low potential end; a gate of the eleventh transistor is connected to a reset signal line, and a drain of the eleventh transistor and a second pixel sub-circuit The second threshold compensation module is connected, and the source of the eleventh transistor is connected to the low potential end.
  • the initialization module includes a first transistor and an eleventh transistor, and the first transistor and the eleventh transistor function as a switching device of an initialization module in the pixel circuit, which is convenient for implementation in the circuit design.
  • the data voltage writing module includes a second transistor, a gate of the second transistor is connected to a gate signal end, a source of the second transistor is connected to a data signal line, and the second transistor is The drain is coupled to the first threshold compensation module of the first pixel sub-circuit and to the second drive module of the second pixel sub-circuit.
  • the data voltage writing module includes a second transistor, and the second transistor functions as a pixel circuit
  • the data voltage is written into the switching device of the module, which is convenient for implementation in the circuit design.
  • the data voltage written in the data voltage writing module includes a first data voltage and a second data voltage, wherein the first data voltage is used to drive the first threshold compensation module to perform threshold voltage on the first driving module.
  • the second data voltage is used to drive the second threshold compensation module to perform threshold voltage compensation on the second driving module.
  • the data signal is a stepped timing signal, it is possible to input two different voltage values from one data signal line.
  • the first light emitting diode and the second light emitting diode are both organic light emitting diodes.
  • the organic light emitting diode is used as the first light emitting module in the pixel circuit and the light emitting diode in the second light emitting module, which is convenient in the circuit design.
  • the transistors are all P-type thin film transistors.
  • a P-type thin film transistor is used as a thin film transistor in a pixel circuit, and it is easy to implement in a circuit design.
  • the display provided by the embodiment of the invention includes a plurality of pixels, a data signal line and a gate control signal line, wherein each of the two pixels constitutes a pixel unit, and further includes the pixel circuit connected to each pixel unit.
  • the display since the display includes the above-described pixel circuit connected to each pixel unit, the display has the advantages of the pixel circuit, and the picture display quality can be improved.
  • two pixels in each pixel unit share one data signal line.
  • two pixels in each pixel unit share a gate control signal line.
  • FIG. 1 is a schematic diagram of a 6T1C AMOLED pixel compensation circuit in a single pixel in the prior art
  • FIG. 2 is a schematic diagram of a 12T2C AMOLED pixel compensation circuit in two pixels in the prior art
  • FIG. 3 is an 11T2C AMOLED according to an embodiment of the present invention
  • FIG. 4 is a timing diagram of an operation of an 11T2C AMOLED pixel circuit according to an embodiment of the present invention
  • FIG. 5 is an initialization stage of an 11T2C AMOLED pixel circuit according to an embodiment of the present invention
  • Cylindrical circuit diagram is an initialization stage of an 11T2C AMOLED pixel circuit according to an embodiment of the present invention.
  • FIG. 6 is a circuit diagram of a 11T2C AMOLED pixel circuit in a first threshold compensation stage according to an embodiment of the present invention
  • FIG. 7 is a circuit diagram of a 11T2C AMOLED pixel circuit in a second threshold compensation stage according to an embodiment of the present invention.
  • FIG. 8 is a circuit diagram of a 11T2C AMOLED pixel circuit in an illumination stage according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram showing the arrangement of individual pixels in the prior art.
  • FIG. 10 is a schematic diagram showing a horizontal arrangement of pixel units composed of any two pixels according to an embodiment of the present invention.
  • FIG. 11 is another schematic diagram of another horizontal arrangement of pixel units composed of any two pixels according to an embodiment of the present invention.
  • FIG. 12 is a schematic diagram of a vertical arrangement of pixel units composed of any two pixels according to an embodiment of the present invention.
  • FIG. 13 is a schematic diagram showing another vertical arrangement of pixel units composed of any two pixels according to an embodiment of the present invention. detailed description
  • Embodiments of the present invention provide a pixel circuit and a display for reducing the size of a pixel circuit, thereby reducing pixel pitch, increasing the number of pixels in a unit area, and improving picture display quality.
  • the pixel circuit provided by the embodiment of the present invention is an active matrix light emitting diode pixel circuit. Since the active matrix light emitting diode pixel circuit can compensate the driving module of the pixel, the active matrix light emitting in the embodiment of the present invention
  • the diode pixel circuit can also be referred to as an active matrix light emitting diode pixel compensation circuit.
  • an active matrix light emitting diode pixel compensation circuit includes: a first pixel sub-circuit and a second pixel sub-circuit, and the first pixel sub-circuit and the second pixel The sub-circuit is connected to the initialization module 31 and the data voltage writing module 32,
  • the initialization module 31 is connected to the reset signal end (corresponding to the first gate control signal Gate (ND) and the low potential end (corresponding to the AMOLED pixel circuit initialization voltage level signal Vinit) of the AMOLED pixel circuit, and is used for inputting at the reset signal end. Reset signal control for the first pixel subcircuit and The two-pixel sub-circuit is initialized;
  • the data voltage writing module 32 is connected to the data signal line (corresponding to the AMOLED pixel circuit data signal Data) and the gate signal end (corresponding to the AMOLED pixel compensation circuit gate control signal Gate (N)) for inputting at the gate signal end.
  • the first data voltage is first written to the first pixel sub-circuit and the second pixel sub-circuit, and the driving module of the first pixel sub-circuit is compensated, and then the second pixel sub-circuit is written into the second The data voltage is compensated for the drive module of the second pixel sub-circuit.
  • the first pixel sub-circuit includes a first driving module 331, a first lighting module 341, a first threshold compensation module 351, and a first lighting control module 361.
  • the initialization module 31 is connected to the first threshold compensation module 351 for initializing the first threshold compensation module 351 under the control of the initialization signal output by the initialization module 31;
  • the first threshold compensation module 351 is connected to the first driving module 331 for performing threshold voltage compensation on the first driving module 331;
  • the first illuminating module 341 is connected to the first illuminating control module 361 for performing illuminating display under the action of the first illuminating control module 361.
  • the first threshold compensation module 351 includes a first storage capacitor C1, a third transistor T3, and a fifth transistor T5; the first driving module 331 includes a fourth transistor T4; the first lighting control module 361 A sixth transistor T6 and a seventh transistor T7 are included; the first light emitting module 341 includes a first light emitting diode OLED1.
  • a C1 end of the first storage capacitor is connected to a high voltage level signal line (corresponding to a high voltage level signal VDD), and the other end is connected to a source of the third transistor T3;
  • the gate of the third transistor T3 is connected to the gate signal end (corresponding to the AMOLED pixel compensation circuit gate control signal Gate(N)), the drain of the third transistor T3 and the drain of the fourth transistor T4. Extremely connected
  • the gate of the fifth transistor T5 is connected to a switch control signal line (corresponding to the AMOLED pixel compensation circuit switch control signal SW), and the source of the fifth transistor T5 is connected to the drain of the sixth transistor T6.
  • a drain of the fifth transistor T5 is connected to a source of the fourth transistor T4;
  • a gate of the fourth transistor T4 is connected to the initialization module 31;
  • the light emission control signal EM is connected, and the source of the sixth transistor T6 is connected to the high voltage level signal line (corresponding to the high voltage level signal VDD );
  • a gate of the seventh transistor T7 is connected to an emission control signal line (corresponding to an AMOLED pixel circuit illumination control signal EM), and a source of the seventh transistor T7 is connected to a drain of the fourth transistor T4, the a drain of the seven-transistor T7 is connected to the first light-emitting diode OLED1;
  • the anode of the first light emitting diode OLED1 is connected to the drain of the seventh transistor T7, and the cathode of the first light emitting diode OLED1 is connected to a low voltage level signal line (corresponding to the low voltage level signal VSS).
  • the second pixel sub-circuit includes a second driving module 332, a second lighting module 342, a second threshold compensation module 352, and a second lighting control module 362.
  • the initialization module 31 is connected to the second threshold compensation module 352 for initializing the second threshold compensation module 352 under the control of the initialization signal output by the initialization module 31.
  • the second threshold compensation module 352 is connected to the second driving module 332 for performing threshold voltage compensation on the second driving module 332.
  • the second illuminating module 342 is connected to the second illuminating control module 362 for performing illuminating display under the action of the second illuminating control module 362.
  • the second threshold compensation module 352 includes a second storage capacitor C2 and a tenth transistor T10; the second driving module 332 includes a ninth transistor T9; and the second lighting control module 362 includes a sixth transistor T6. And an eighth transistor T8; the second light emitting module 342 includes a second light emitting diode OLED2.
  • one end of the second storage capacitor C2 is connected to a high voltage level signal line (corresponding to a high voltage level signal VDD), and the other end is connected to a source of the tenth transistor T10;
  • the gate of the tenth transistor T10 is connected to the gate signal end (corresponding to the AMOLED pixel compensation circuit gate control signal Gate(N)), and the drain of the tenth transistor T10 and the drain of the ninth transistor T9 Extremely connected
  • a gate of the ninth transistor T9 is connected to a source of the tenth transistor T10, and a source of the ninth transistor T9 is connected to the data voltage writing module 32;
  • a gate of the sixth transistor T6 is connected to an emission control signal line (corresponding to an AMOLED pixel circuit illumination control signal EM), and a source of the sixth transistor T6 and a high voltage level signal line (corresponding to a high voltage level signal VDD) Connected, the drain of the sixth transistor T6 is connected to the source of the ninth transistor T9; a gate of the eighth transistor T8 is connected to an emission control signal line (corresponding to an AMOLED pixel circuit illumination control signal EM), and a source of the eighth transistor T8 is connected to a drain of the ninth transistor T9, the The drain of the eight transistor T8 is connected to the second light emitting diode OLED2;
  • the anode of the second light emitting diode OLED2 is connected to the drain of the eighth transistor T8, and the cathode of the second light emitting diode OLED2 is connected to a low voltage level signal line (corresponding to the low voltage level signal VSS).
  • the sixth transistor T6 is a switching transistor shared by the first illumination control module 361 and the second illumination control module 362.
  • the illumination control modules 361 and 362 can simultaneously control the illumination of the OLED 1 and the OLED 2, and can also separately control the illumination of the OLED 1 and the OLED 2 . .
  • the initialization module 31 includes a first transistor T1 and an eleventh transistor T11, wherein a gate of the first transistor T1 and a reset signal line (corresponding to a first-level gate control signal Gate of the AMOLED pixel circuit) N-1) is connected, the drain of the first transistor T1 is connected to the first threshold compensation module 351 of the first pixel sub-circuit, and the source and the low potential end of the first transistor T1 (corresponding to the initialization of the AMOLED pixel circuit) The voltage level signal Vinit is connected; the gate of the eleventh transistor T11 is connected to a reset signal line (corresponding to a first-level gate control signal Gate (N-1) of the AMOLED pixel circuit), and the eleventh transistor Til The drain is connected to the second threshold compensation module 352 of the second pixel sub-circuit, and the source of the eleventh transistor T11 is connected to the low potential terminal (corresponding to the AMOLED pixel circuit initialization voltage level signal Vinit).
  • a gate of the first transistor T1 and a reset signal line
  • the data voltage writing module 32 includes a second transistor T2, and a gate of the second transistor T2 is connected to a gate signal end (corresponding to an AMOLED pixel compensation circuit gate control signal Gate(N)).
  • the source of the second transistor T2 is connected to the data signal line (corresponding to the AMOLED pixel circuit data signal Data), the drain of the second transistor T2 and the source of the fifth transistor T5 and the second pixel sub-circuit
  • the second driving module 332 is connected.
  • the value of N in the gate control signal Gate ( N ) and the gate control signal Gate ( N-1 ) of the previous stage may be selected according to the number of gate control signal lines in the pixel compensation circuit and actual needs.
  • the data voltage input in the data voltage writing module 32 includes a first data voltage and a second data voltage, wherein the first data voltage is used to drive the first threshold compensation module 351 to perform the first driving module 331 The threshold voltage is compensated, and the second data voltage is used to drive the second threshold compensation module 352 to perform threshold voltage compensation on the second driving module 332.
  • the first LED OLED1 and the second LED OLED2 are both Light-emitting diodes.
  • the transistors T1, ⁇ 2, ⁇ 3, ⁇ 4, ⁇ 5, ⁇ 6, ⁇ 7, ⁇ 8, ⁇ 9, T10 and Til are ⁇ -type thin film transistors.
  • the gate control signal Gate (N) and the light emission control signal EM are at a high level; the upper gate control signal Gate (N-1) and the switch control signal SW are low.
  • the first transistor T1, the fifth transistor T5, and the eleventh transistor Til in FIG. 3 are turned on; the second transistor T2, the third transistor T3, the sixth transistor T6, the seventh transistor T7, and the eighth transistor
  • the ⁇ 8 and the tenth transistor T10 are turned off, and therefore, the cylindrical circuit diagram of Fig. 3 is as shown in Fig. 5.
  • the storage capacitors C1 and C2 respectively store the data signal Data input by the previous frame, the two capacitors are all connected to the initialization voltage level signal Vinit having a low potential, and the storage capacitors C1 and C2 are both paired with the initialization voltage level signal. Vinit discharges and discharges to the initialization voltage ⁇ .
  • the upper gate control signal Gate (N-1) and the illumination control signal EM are at a high level; the gate control signal Gate (N) and the switch control signal SW are low.
  • the second transistor T2, the third transistor ⁇ 3, the fifth transistor ⁇ 5, and the tenth transistor T10 in FIG. 3 are turned on; the first transistor T1, the sixth transistor ⁇ 6, the seventh transistor ⁇ 7, and the eighth transistor ⁇ 8 And the eleventh transistor T11 is turned off, therefore, the cylindrical circuit diagram of FIG. 3 is as shown in FIG. 6.
  • the data level signal Data is input to the first voltage value VI.
  • the threshold voltage of T4 and the voltage value V is stored in the storage capacitor C1
  • the ninth transistor T9 is equivalent to the diode, and the voltage of the second node P2 becomes: V Vl - Vth ( T9 ), where Vth ( T9 ) is
  • the threshold voltage of the nine-transistor T9 stores the voltage value V in the storage capacitor C2 while charging the two capacitors C1 and C2.
  • the upper gate control signal Gate (Nl), the switch control signal SW, and the illumination control signal EM are at a high level; the gate control signal Gate (N) of the current stage is at a low level.
  • the second transistor T2, the third transistor ⁇ 3, and the tenth transistor T10 in FIG. 3 are turned on; the first transistor T1, the eleventh transistor T11, the fifth transistor ⁇ 5, the seventh transistor ⁇ 7, the eighth transistor ⁇ 8, and The sixth transistor ⁇ 6 is turned off, and therefore, the cylindrical circuit diagram of Fig. 3 is as shown in Fig. 7.
  • the data level signal Data is input to the second voltage value V2.
  • the ninth transistor T9 is equivalent to the diode, and the voltage of the second node P2 becomes: V ⁇ VS-Vth (T9), where Vth (T9) is the ninth transistor.
  • T9 threshold power Press and store the voltage value in storage capacitor C2.
  • the upper-stage gate control signal Gate (N-1) and the gate-level gate control signal Gate(N) are at a high level; the light-emission control signal EM and the switch control signal SW is at a low level, at this time, the fifth transistor T5, the sixth transistor ⁇ 6, the seventh transistor ⁇ 7, and the eighth transistor ⁇ 8 in FIG. 3 are turned on; the first transistor T1, the second transistor ⁇ 2, the third transistor ⁇ 3, the first The ten transistor T10 and the eleventh transistor T11 are turned off, and therefore, the cylindrical circuit diagram of FIG. 3 is as shown in FIG.
  • the fourth transistor ⁇ 4 and the ninth transistor ⁇ 9 are driving transistors of the OLED, and the current is controlled as follows:
  • the sources of the fourth transistor ⁇ 4 and the ninth transistor ⁇ 9 are both connected to the high voltage level signal VDD, wherein the high voltage power
  • the voltage value of the flat signal VDD is a constant value
  • the current flowing through the first light emitting diode OLED1 is:
  • the current Id1 flowing through the first light emitting diode OLED1 and the current Id2 flowing through the second light emitting diode OLED2 and the threshold voltage Vth (T4) of the fourth transistor T4 and the threshold voltage Vth of the ninth transistor T9 (T9) is irrelevant, so it can play a compensating role.
  • the AMOLED pixel circuit provided by the embodiment of the present invention includes 11 thin film transistors and two capacitors, that is, an 11T2C AMOLED pixel circuit.
  • a display provided by the embodiment of the present invention includes a plurality of pixels, a data signal line, and a gate control signal line, wherein each of the two pixels constitutes a pixel unit, and further includes an embodiment of the present invention connected to each pixel unit.
  • 11T2C AMOLED pixel circuit 11T2C AMOLED pixel circuit.
  • the pixel arrangement of a single pixel in the prior art is as shown in FIG. 9.
  • the compensation circuit in a single pixel is a 6T1C AMOLED pixel compensation circuit in the prior art. If two pixels are put together to form a pixel unit, then The compensation circuit of the pixel unit in the prior art is a 12T2C AMOLED pixel compensation circuit in the prior art.
  • the arrangement of pixel units including 2 pixels provided by the embodiment of the present invention is as shown in FIG. 10-13, wherein two pixels in any pixel unit arranged in the horizontal direction share a data signal line Data (m), vertical Two pixels in any one of the pixel units arranged in the direction share a gate control signal line Gate ( N ), wherein two pixels in any one of the pixel units arranged in the horizontal direction are horizontal Any two pixels above, such as: Pixell and Pixel 2 or Pixel 2 and Pixel 3, the two pixels arranged vertically in the pixel unit are any two pixels in the vertical direction.
  • m data signal line Data
  • N gate control signal line Gate
  • the two pixels in any one of the pixel units arranged in the horizontal direction share a data signal line Data ( m ) including: the data signal line Data ( m ) is located in two horizontally arranged Pixel 1 Between Pixel 2 and Pixel 2, or data signal line Data (m) is located on one side of Pixel 1 and Pixel 2 in two horizontal directions.
  • the data signal line Data (m) in the embodiment of the present invention is not Limited to one side of the Pixel 1, it may be located on one side of any of the two horizontally arranged pixels.
  • a common control signal line Gate ( N ) is shared by two pixels in any of the pixel units arranged in the vertical direction.
  • the gate control signal line Gate ( N ) is located in a pixel unit. Between any two pixels arranged in the vertical direction or the gate control signal line Gate (N) is located on one side of any one of any two pixels constituting the vertical direction of one pixel unit.
  • the AMOLED pixel circuit includes: a first pixel sub-circuit and a second pixel sub-circuit, and is connected to the first pixel sub-circuit and the second pixel sub-circuit
  • the initialization module and the data voltage writing module the initialization module is connected to the reset signal end and the low potential end, and is configured to initialize the first pixel sub-circuit and the second pixel sub-circuit under the control of the reset signal input by the reset signal end;
  • the data voltage writing module is connected to the data voltage and the gate signal end for writing a first data voltage to the first pixel sub-circuit under the control of the signal input by the gate signal terminal, and for the first pixel sub-circuit
  • the driving module compensates, then writes a second data voltage to the second pixel sub-circuit, and compensates the driving module of the second pixel sub-circuit, and the AMOLED pixel circuit can reduce the pixel circuit size, thereby reducing the pixel pitch. Increase the number of pixels

Abstract

一种像素电路及显示器，用以减小像素电路尺寸，进而减小像素间距，提高单位面积内所拥有的像素数目，提升画面显示品质。所述像素电路包括：第一像素子电路和第二像素子电路，以及与第一像素子电路和第二像素子电路连接的初始化模块（31）和数据电压写入模块（32）；初始化模块（31）连接复位信号端和低电位端，用于在复位信号端输入的复位信号控制下对第一像素子电路和第二像素子电路进行初始化；数据电压写入模块（32）连接数据电压和门信号端，用于在门信号端输入的信号控制下先对第一像素子电路和第二像素子电路写入第一数据电压，并对第一像素子电路的驱动模块进行补偿，然后对第二像素子电路写入第二数据电压，并对第二像素子电路的驱动模块进行补偿。

Description

像素电路及显示器
技术领域
本发明涉及显示器技术领域， 尤其涉及一种像素电路及显示器。 背景技术
目前高端中小尺寸有源矩阵有机发光二极管 （ Active Matrix Organic Light Emitting Diode, AMOLED )产品背板多使用低温多晶石圭 ( Low Temperature Poly-Silicon, LTPS )工艺技术， 然而由于 LTPS工艺的波动性会导致薄膜晶体 管（ Thin Film Transistor, TFT )器件的阈值电压漂移， 从而使得驱动有机发光 二极管 （Organic Light Emitting Diode, OLED ) 器件的电流不稳定导致画面显 示品质降低。 现有技术中的像素补偿电路为 6T1C电路（由 6个薄膜晶体管和 1个电容组成的电路）， 电路图如图 1所示， 图中， VDD为高电压电平信号， VSS为低电压电平信号， Data为数据信号， Gate为栅极控制信号， Reset为初 始化控制信号， Vinit为初始化电压电平信号， Emission (即 EM )为控制 OLED 发光的信号， 由 OLED面板的 emission电路提供此电压。 然而， 需要将 6个薄 膜晶体管和 1个电容在一个像素中布置下去是不容易的，需要 TFT器件做得非 常小， 所以 TFT器件的性能要求也相对较高， 会导致像素间距（Pixel Pitch ) 无法进一步降低。
如图 2所示， 现有技术中的 6T1C电路在 2个像素里的水平方向所需要布 置的元器件数目为： 2条数据信号线： Data vl和 Data v2、 12个 TFT、 2个电 容、 1条栅极控制信号线 Gate、 1个发光控制信号端 Emission, 1个高电压电 平信号端 VDD、 1个初始化电压电平信号端 Vinit, 1个初始化控制信号端 Reset, 图 1中有两个有机发光二极管 OLED1和 OLED2,其阴极均与低电压电平信号 VSS相连， 图 2为水平排列的 2个像素的电路原理图， 其在水平或者垂直方向 组成一个像素单元，在垂直方向所需要布置的元器件数目为： 1条数据信号线、 12个 TFT、 2个电容、 2条栅极控制信号线、 1个发光控制信号端 Emission, 1 个高电压电平信号端 VDD、 1个初始化电压电平信号端 Vinit。
综上所述， 现有技术中在 2个像素中需要布置 12个 TFT和 2个电容。 发明内容
本发明实施例提供了一种像素电路， 用以减小像素电路尺寸， 进而减小像 素间距， 提高单位面积内所拥有的像素数目， 提升画面显示品质。 本发明还提 供了一种显示器。 根据本发明一实施例， 提供的一种像素电路， 包括： 第一像素子电路和第 二像素子电路， 以及与所述第一像素子电路和第二像素子电路连接的初始化模 块和数据电压写入模块，
所述初始化模块连接复位信号端和低电位端， 用于在复位信号端输入的复 位信号控制下对第一像素子电路和第二像素子电路进行初始化；
所述数据电压写入模块连接数据电压和门信号端， 用于在门信号端输入的 信号控制下先对第一像素子电路和第二像素子电路写入第一数据电压， 并对所 述第一像素子电路的驱动模块进行补偿， 然后对第二像素子电路写入第二数据 电压， 并对第二像素子电路的驱动模块进行补偿。
由本发明实施例提供的所述像素电路， 包括： 第一像素子电路和第二像素 子电路， 以及与所述第一像素子电路和第二像素子电路连接的初始化模块和数 据电压写入模块， 所述由第一像素子电路、 第二像素子电路以及初始化模块和 数据电压写入模块组成的像素电路能够减小像素电路尺寸， 进而减小像素间 距， 提高单位面积内所拥有的像素数目， 提升画面显示品质。
可选地， 所述第一像素子电路包括第一驱动模块、 第一发光模块、 第一阈 值补偿模块和第一发光控制模块，
初始化模块连接所述第一阈值补偿模块， 用于在初始化模块输出的初始化 信号控制下对第一阈值补偿模块进行初始化；
所述第一阈值补偿模块连接第一驱动模块， 用于对第一驱动模块进行阈值 电压补偿；
所述第一发光模块连接第一发光控制模块， 用于在第一发光控制模块作用 下进行发光显示。
这样， 由第一驱动模块、 第一发光模块、 第一阈值补偿模块和第一发光控 制模块组成的第一像素子电路在像素电路的设计中简单便于实施。
可选地， 所述第一阈值补偿模块包括第一存储电容、 第三晶体管和第五晶 体管； 所述第一驱动模块包括第四晶体管； 所述第一发光控制模块包括第六晶 体管和第七晶体管； 所述第一发光模块包括第一发光二极管。
这样， 由存储电容、 晶体管和发光二极管组成的第一像素子电路在像素电 路的设计中筒单便于实施。
可选地， 所述第一存储电容的一端与高电压电平信号线相连， 另一端与第 三晶体管的源极相连；
所述第三晶体管的栅极与门信号端相连， 所述第三晶体管的漏极与所述第 四晶体管的漏极相连；
所述第五晶体管的栅极与开关控制信号线相连， 所述第五晶体管的源极与 所述第六晶体管的漏极相连， 所述第五晶体管的漏极与所述第四晶体管的源极 相连；
所述第四晶体管的栅极与所述初始化模块相连；
所述第六晶体管的栅极与发光控制信号线连接， 所述第六晶体管的源极与 高电压电平信号线相连；
所述第七晶体管的栅极与发光控制信号线连接， 所述第七晶体管的源极与 所述第四晶体管的漏极相连， 所述第七晶体管的漏极与第一发光二极管相连； 所述第一发光二极管的阳极与第七晶体管的漏极相连， 所述第一发光二极 管的阴极与低电压电平信号线相连。
这样， 所述存储电容、 晶体管及发光二极管的连接关系在像素电路的设计 中筒单便于实施。
可选地， 所述第二像素子电路包括第二驱动模块、 第二发光模块、 第二阈 值补偿模块和第二发光控制模块，
所述初始化模块连接第二阈值补偿模块， 用于在初始化模块输出的初始化 信号控制下对第二阈值补偿模块进行初始化；
所述第二阈值补偿模块连接第二驱动模块， 用于对第二驱动模块进行阈值 电压补偿；
所述第二发光模块连接第二发光控制模块， 用于在第二发光控制模块作用 下进行发光显示。
这样， 由第二驱动模块、 第二发光模块、 第二阈值补偿模块和第二发光控 制模块组成的第二像素子电路在像素电路的设计中简单便于实施。
可选地， 所述第二阈值补偿模块包括第二存储电容和第十晶体管； 所述第 二驱动模块包括第九晶体管； 所述第二发光控制模块包括第六晶体管和第八晶 体管； 所述第二发光模块包括第二发光二极管。
这样， 由存储电容、 晶体管和发光二极管组成的第二像素子电路在像素电 路的设计中筒单便于实施。
可选地， 所述第二存储电容的一端与高电压电平信号线相连， 另一端与第 十晶体管的源极相连；
所述第十晶体管的栅极与门信号端相连， 所述第十晶体管的漏极与所述第 九晶体管的漏极相连；
所述第九晶体管的栅极与所述第十晶体管的源极相连， 所述第九晶体管的 源极与所述数据电压写入模块相连；
所述第六晶体管的栅极与发光控制信号线连接， 所述第六晶体管的源极与 高电压电平信号线相连， 所述第六晶体管的漏极与所述第九晶体管的源极相 连；
所述第八晶体管的栅极与发光控制信号线连接， 所述第八晶体管的源极与 所述第九晶体管的漏极相连， 所述第八晶体管的漏极与第二发光二极管相连； 所述第二发光二极管的阳极与第八晶体管的漏极相连， 所述第二发光二极 管的阴极与低电压电平信号线相连。
这样， 所述存储电容、 晶体管及发光二极管的连接关系在像素电路的设计 中筒单便于实施。
可选地， 所述初始化模块包括第一晶体管和第十一晶体管， 其中， 所述第 一晶体管的栅极与复位信号线相连， 所述第一晶体管的漏极与第一像素子电路 的第一阈值补偿模块相连， 所述第一晶体管的源极与低电位端相连； 所述第十 一晶体管的栅极与复位信号线相连， 所述第十一晶体管的漏极与第二像素子电 路的第二阈值补偿模块相连， 所述第十一晶体管的源极与低电位端相连。
这样， 所述初始化模块包括第一晶体管和第十一晶体管， 第一晶体管和第 十一晶体管作为像素电路中的初始化模块的开关器件， 在电路设计中方便筒单 便于实施。
可选地， 所述数据电压写入模块包括第二晶体管， 所述第二晶体管的栅极 与门信号端相连， 所述第二晶体管的源极与数据信号线相连， 所述第二晶体管 的漏极与第一像素子电路的第一阈值补偿模块和和第二像素子电路的第二驱 动模块相连。
这样， 所述数据电压写入模块包括第二晶体管， 第二晶体管作为像素电路 中的数据电压写入模块的开关器件， 在电路设计中方便筒单便于实施。
可选地， 所述数据电压写入模块中写入的数据电压包括第一数据电压和第 二数据电压， 其中， 第一数据电压用于驱动第一阈值补偿模块对第一驱动模块 进行阈值电压补偿， 第二数据电压用于驱动第二阈值补偿模块对第二驱动模块 进行阈值电压补偿。
这样， 由于数据信号为阶梯形的时序信号， 可以实现由一条数据信号线输 入两个不同的电压值。
可选地， 所述第一发光二极管和第二发光二极管均为有机发光二极管。 这样， 用有机发光二极管作为像素电路中的第一发光模块和第二发光模块 中的发光二极管， 在电路设计中方便筒单。
可选地， 所述晶体管均为 P型薄膜晶体管。
这样， 用 P型薄膜晶体管作为像素电路中的薄膜晶体管， 在电路设计中方 便筒单便于实施。
本发明实施例提供的显示器， 包括多个像素、 数据信号线以及栅极控制信 号线， 其中， 每两个像素组成一像素单元， 还包括与各像素单元连接的上面所 述的像素电路。
这样， 由于所述显示器包括与各像素单元连接的上面所述的像素电路， 该 显示器具有所述像素电路的优点， 能够很好的提升画面显示品质。
可选地， 所述每一像素单元中的两个像素共用一条数据信号线。
这样， 每一像素单元中的两个像素共用一条数据信号线， 故两个像素可以 省略一条数据信号线， 数据信号线的排列方法筒单易行。
可选地， 所述每一像素单元中的两个像素共用一条栅极控制信号线。
这样， 每一像素单元中的两个像素共用一条栅极控制信号线， 故两个像素 可以省略一条栅极控制信号线， 栅极控制信号线的排列方法筒单易行。 附图说明
图 1为现有技术中的单个像素中的 6T1C AMOLED像素补偿电路示意图； 图 2为现有技术中的 2个像素中的 12T2C AMOLED像素补偿电路示意图； 图 3为本发明实施例提供的 11T2C AMOLED像素电路示意图；
图 4为本发明实施例提供的 11T2C AMOLED像素电路工作的时序图； 图 5为本发明实施例提供的 11T2C AMOLED像素电路在初始化工作阶段 的筒化电路图；
图 6为本发明实施例提供的 11T2C AMOLED像素电路在第一阈值补偿阶 段的筒化电路图；
图 7为本发明实施例提供的 11T2C AMOLED像素电路在第二阈值补偿阶 段的筒化电路图；
图 8为本发明实施例提供的 11T2C AMOLED像素电路在发光阶段的筒化 电路图；
图 9为现有技术中的单个像素的排列示意图；
图 10为本发明实施例提供的由任意两个像素组成的像素单元的一种水平 排列示意图；
图 11为本发明实施例提供的由任意两个像素组成的像素单元的另一种水 平排列示意图；
图 12为本发明实施例提供的由任意两个像素组成的像素单元的一种垂直 排列示意图；
图 13为本发明实施例提供的由任意两个像素组成的像素单元的另一种垂 直排列示意图。 具体实施方式
本发明实施例提供了一种像素电路及显示器， 用以减小像素电路尺寸， 进 而减小像素间距， 提高单位面积内所拥有的像素数目， 提升画面显示品质。
其中， 本发明实施例提供的像素电路为有源矩阵发光二极管像素电路， 由 于有源矩阵发光二极管像素电路能够起到对像素的驱动模块进行补偿的作用， 故本发明实施例中有源矩阵发光二极管像素电路也可称为有源矩阵发光二极 管像素补偿电路。
下面给出本发明实施例提供的技术方案的详细介绍。
如图 3所示，本发明实施例提供的一种有源矩阵发光二极管像素补偿电路， 包括： 第一像素子电路和第二像素子电路， 以及与所述第一像素子电路和第二 像素子电路连接的初始化模块 31和数据电压写入模块 32,
所述初始化模块 31连接复位信号端（对应 AMOLED像素电路上一级栅极 控制信号 Gate ( N-D )和低电位端（对应 AMOLED像素电路初始化电压电平 信号 Vinit ), 用于在复位信号端输入的复位信号控制下对第一像素子电路和第 二像素子电路进行初始化；
所述数据电压写入模块 32连接数据信号线（对应 AMOLED像素电路数据 信号 Data )和门信号端（对应 AMOLED像素补偿电路本级栅极控制信号 Gate ( N ) ), 用于在门信号端输入的信号控制下先对第一像素子电路和第二像素子 电路写入第一数据电压， 并对所述第一像素子电路的驱动模块进行补偿， 然后 对第二像素子电路写入第二数据电压， 并对第二像素子电路的驱动模块进行补 偿。
在图 3所示的电路中， 为了区别导线间的交叉相连和不相连， 将相连的交 叉点以实心圓点表示， 不相连的交叉点以空心圓点表示。
可选地， 所述第一像素子电路包括第一驱动模块 331、 第一发光模块 341、 第一阈值补偿模块 351和第一发光控制模块 361 ,
初始化模块 31连接所述第一阈值补偿模块 351 , 用于在初始化模块 31输 出的初始化信号控制下对第一阈值补偿模块 351进行初始化；
所述第一阈值补偿模块 351连接第一驱动模块 331 , 用于对第一驱动模块 331进行阈值电压补偿；
所述第一发光模块 341连接第一发光控制模块 361 , 用于在第一发光控制 模块 361作用下进行发光显示。
可选地， 所述第一阈值补偿模块 351包括第一存储电容 Cl、 第三晶体管 T3和第五晶体管 T5; 所述第一驱动模块 331包括第四晶体管 T4; 所述第一发 光控制模块 361包括第六晶体管 T6和第七晶体管 T7; 所述第一发光模块 341 包括第一发光二极管 0LED1。
可选地， 所述第一存储电容的 C1一端与高电压电平信号线 （对应高电压 电平信号 VDD )相连， 另一端与第三晶体管 T3的源极相连；
所述第三晶体管 T3的栅极与门信号端 （对应 AMOLED像素补偿电路本 级栅极控制信号 Gate ( N ) )相连， 所述第三晶体管 T3的漏极与所述第四晶体 管 T4的漏极相连；
所述第五晶体管 T5的栅极与开关控制信号线（对应 AMOLED像素补偿 电路开关控制信号 SW )相连， 所述第五晶体管 T5的源极与所述第六晶体管 T6的漏极相连，所述第五晶体管 T5的漏极与所述第四晶体管 T4的源极相连； 所述第四晶体管 T4的栅极与所述初始化模块 31相连；
所述第六晶体管 T6的栅极与发光控制信号线（对应 AMOLED像素电路 发光控制信号 EM )连接， 所述第六晶体管 T6的源极与高电压电平信号线（对 应高电压电平信号 VDD )相连；
所述第七晶体管 T7的栅极与发光控制信号线（对应 AMOLED像素电路 发光控制信号 EM )连接， 所述第七晶体管 T7的源极与所述第四晶体管 T4的 漏极相连， 所述第七晶体管 T7的漏极与第一发光二极管 OLED1相连；
所述第一发光二极管 OLED1的阳极与第七晶体管 T7的漏极相连，所述第 一发光二极管 OLED1的阴极与低电压电平信号线（对应低电压电平信号 VSS ) 相连。
可选地， 所述第二像素子电路包括第二驱动模块 332、 第二发光模块 342、 第二阈值补偿模块 352和第二发光控制模块 362,
初始化模块 31连接所述第二阈值补偿模块 352, 用于在初始化模块 31输 出的初始化信号控制下对第二阈值补偿模块 352进行初始化；
所述第二阈值补偿模块 352连接第二驱动模块 332, 用于对第二驱动模块 332进行阈值电压补偿；
所述第二发光模块 342连接第二发光控制模块 362, 用于在第二发光控制 模块 362作用下进行发光显示。
可选地， 所述第二阈值补偿模块 352包括第二存储电容 C2和第十晶体管 T10; 所述第二驱动模块 332包括第九晶体管 T9; 所述第二发光控制模块 362 包括第六晶体管 T6和第八晶体管 T8; 所述第二发光模块 342包括第二发光二 极管 OLED2。
可选地， 所述第二存储电容 C2的一端与高电压电平信号线 （对应高电压 电平信号 VDD )相连， 另一端与第十晶体管 T10的源极相连；
所述第十晶体管 T10的栅极与门信号端（对应 AMOLED像素补偿电路本 级栅极控制信号 Gate ( N ) )相连， 所述第十晶体管 T10的漏极与所述第九晶 体管 T9的漏极相连；
所述第九晶体管 T9的栅极与所述第十晶体管 T10的源极相连， 所述第九 晶体管 T9的源极与所述数据电压写入模块 32相连；
所述第六晶体管 T6的栅极与发光控制信号线（对应 AMOLED像素电路 发光控制信号 EM )连接， 所述第六晶体管 T6的源极与高电压电平信号线（对 应高电压电平信号 VDD )相连， 所述第六晶体管 T6的漏极与所述第九晶体管 T9的源极相连； 所述第八晶体管 T8的栅极与发光控制信号线（对应 AMOLED像素电路 发光控制信号 EM )连接， 所述第八晶体管 T8的源极与所述第九晶体管 T9的 漏极相连， 所述第八晶体管 T8的漏极与第二发光二极管 OLED2相连；
所述第二发光二极管 OLED2的阳极与第八晶体管 T8的漏极相连，所述第 二发光二极管 OLED2的阴极与低电压电平信号线（对应低电压电平信号 VSS ) 相连。
其中， 第六晶体管 T6是第一发光控制模块 361和第二发光控制模块 362 共用的开关晶体管，发光控制模块 361和 362既可以同时控制 OLED1和 OLED2 的发光， 也可以分开控制 OLED1和 OLED2的发光。
可选地， 所述初始化模块 31包括第一晶体管 T1和第十一晶体管 T11 , 其 中， 所述第一晶体管 T1的栅极与复位信号线 （对应 AMOLED像素电路上一 级栅极控制信号 Gate ( N-1 ) )相连， 所述第一晶体管 T1的漏极与第一像素子 电路的第一阈值补偿模块 351相连，所述第一晶体管 T1的源极与低电位端（对 应 AMOLED像素电路初始化电压电平信号 Vinit )相连； 所述第十一晶体管 T11的栅极与复位信号线（对应 AMOLED像素电路上一级栅极控制信号 Gate ( N-1 ) )相连， 所述第十一晶体管 Til的漏极与第二像素子电路的第二阈值补 偿模块 352相连， 所述第十一晶体管 T11的源极与低电位端 （对应 AMOLED 像素电路初始化电压电平信号 Vinit )相连。
可选地， 所述数据电压写入模块 32包括第二晶体管 T2, 所述第二晶体管 T2的栅极与门信号端 （对应 AMOLED像素补偿电路本级栅极控制信号 Gate ( N ) )相连， 所述第二晶体管 T2的源极与数据信号线（对应 AMOLED像素 电路数据信号 Data )相连， 所述第二晶体管 T2的漏极与所述第五晶体管 T5 的源极和第二像素子电路的第二驱动模块 332相连。
其中， 本级栅极控制信号 Gate ( N )、 上一级栅极控制信号 Gate ( N-1 ) 中 N的取值可以根据像素补偿电路中栅极控制信号线的数量及实际需要进行选 择。
可选地， 所述数据电压写入模块 32中输入的数据电压包括第一数据电压 和第二数据电压， 其中， 第一数据电压用于驱动第一阈值补偿模块 351对第一 驱动模块 331进行阈值电压补偿， 第二数据电压用于驱动第二阈值补偿模块 352对第二驱动模块 332进行阈值电压补偿。
可选地， 所述第一发光二极管 OLED1和第二发光二极管 OLED2均为有 机发光二极管。
可选地， 所述晶体管 Tl、 Τ2、 Τ3、 Τ4、 Τ5、 Τ6、 Τ7、 Τ8、 Τ9、 T10和 Til均为 Ρ型薄膜晶体管。
下面结合图 3-图 8, 具体说明本发明实施例提供的 AMOLED像素补偿电 路的工作原理。
如图 4所示， 在 I阶段， 本级栅极控制信号 Gate ( N )和发光控制信号 EM 为高电平； 上一级栅极控制信号 Gate ( N-1 )和开关控制信号 SW为低电平， 此时， 图 3中的第一晶体管 Tl、 第五晶体管 Τ5和第十一晶体管 Til打开； 第 二晶体管 T2、 第三晶体管 Τ3、 第六晶体管 Τ6、 第七晶体管 Τ7、 第八晶体管 Τ8和第十晶体管 T10关闭， 因此， 图 3的筒化电路图如图 5所示。 由于存储 电容 C1和 C2分别存储上一帧画面输入的数据信号 Data, 此时 2个电容全部 连接在具有低电位的初始化电压电平信号 Vinit上， 存储电容 C1和 C2均对初 始化电压电平信号 Vinit放电， 放电到初始化电压 ν 。
如图 4所示， 在 II阶段， 上一级栅极控制信号 Gate ( N-1 )和发光控制信 号 EM为高电平； 本级栅极控制信号 Gate ( N )和开关控制信号 SW为低电平， 此时， 图 3中的第二晶体管 T2、 第三晶体管 Τ3、 第五晶体管 Τ5和第十晶体 管 T10打开； 第一晶体管 Tl、 第六晶体管 Τ6、 第七晶体管 Τ7、 第八晶体管 Τ8和第十一晶体管 T11关闭， 因此， 图 3的筒化电路图如图 6所示。 数据电 平信号 Data输入第一电压值 VI , 此时第四晶体管 T4相当于二极管， 第一节 点 P1的电压变为： V=Vl-Vth ( T4 ), 其中， Vth ( T4 ) 为第四晶体管 T4的阈 值电压， 并将电压值 V存储在存储电容 C1中， 第九晶体管 T9相当于二极管， 第二节点 P2的电压变为： V Vl-Vth ( T9 ), 其中， Vth ( T9 ) 为第九晶体管 T9的阈值电压， 并将电压值 V存储在存储电容 C2中， 同时对 2个电容 C1和 C2进行充电。
如图 4所示， 在 III阶段， 上一级栅极控制信号 Gate ( N-l )、 开关控制信 号 SW和发光控制信号 EM为高电平； 本级栅极控制信号 Gate ( N )为低电平， 此时， 图 3中的第二晶体管 T2、 第三晶体管 Τ3和第十晶体管 T10打开； 第一 晶体管 Tl、 第十一晶体管 Tll、 第五晶体管 Τ5、 第七晶体管 Τ7、 第八晶体管 Τ8和第六晶体管 Τ6关闭， 因此， 图 3的筒化电路图如图 7所示。 数据电平信 号 Data输入第二电压值 V2, 此时第九晶体管 T9相当于二极管， 第二节点 P2 的电压变为： V^ VS-Vth ( T9 ), 其中， Vth ( T9 )为第九晶体管 T9的阈值电 压， 并将电压值 存储在存储电容 C2中。
如图 4所示， 在 IV阶段即发光阶段， 上一级栅极控制信号 Gate ( N-1 )和 本级栅极控制信号 Gate ( N )为高电平；发光控制信号 EM和开关控制信号 SW 为低电平， 此时， 图 3中的第五晶体管 T5、 第六晶体管 Τ6、 第七晶体管 Τ7 和第八晶体管 Τ8打开； 第一晶体管 Tl、 第二晶体管 Τ2、 第三晶体管 Τ3、 第 十晶体管 T10和第十一晶体管 T11关闭，因此，图 3的筒化电路图如图 8所示。 第四晶体管 Τ4和第九晶体管 Τ9为 OLED的驱动晶体管， 其对电流的控制方 式如下： 第四晶体管 Τ4和第九晶体管 Τ9的源极均与高电压电平信号 VDD相 连， 其中， 高电压电平信号 VDD的电压数值为恒定值， 流经第一发光二极管 OLED1的电流为：
Idl= * [VDD- (Vl-Vth (T4) )-Vth (T4)f = * (VDD-V1)2 其中， k为预设常数， 流经第二发光二极管 OLED2的电流为：
Id2=- VDD-(V2-Vth(T9))-Vth(T9)]2 =^-* [VDD-V2]2
2
从上面的方程可以看出， 流经第一发光二极管 OLED1的电流 Idl和流经 第二发光二极管 OLED2的电流 Id2与第四晶体管 T4的阈值电压 Vth ( T4 )和 第九晶体管 T9的阈值电压 Vth ( T9 )无关， 因此可以起到补偿作用。
综上所述，本发明实施例提供的 AMOLED像素电路包括 11个薄膜晶体管 和 2个电容， 即为 11T2C AMOLED像素电路。
本发明实施例提供的一种显示器， 包括多个像素、 数据信号线以及栅极控 制信号线， 其中， 每两个像素组成一像素单元， 还包括与各像素单元连接的本 发明实施例提供的 11T2C AMOLED像素电路。
下面具体介绍包含 2个像素的像素单元的排列方式：
现有技术中的单个像素的像素排列方式如图 9所示，单个像素中的补偿电 路为现有技术中的 6T1C AMOLED像素补偿电路，如果将两个像素放到一起组 成一个像素单元， 则现有技术中的像素单元的补偿电路为现有技术中的 12T2C AMOLED像素补偿电路。
本发明实施例提供的包含 2个像素的像素单元的排列方式如图 10-13所 示， 其中， 水平方向排列的任一像素单元中的两个像素共用一条数据信号线 Data ( m ), 垂直方向排列的任一像素单元中的两个像素共用一条栅极控制信号 线 Gate ( N ), 其中， 水平方向排列的任一像素单元中的两个像素为水平方向 上的任意两个像素， 如： 像素 Pixell与 Pixel 2或者 Pixel 2与 Pixel 3 , 像素单 元中垂直方向排列的两个像素为垂直方向上的任意两个像素。
如图 10和 11所示， 所述水平方向排列的任一像素单元中的两个像素共用 一条数据信号线 Data ( m ) 包括： 数据信号线 Data ( m )位于两个水平方向排 列的 Pixel 1和 Pixel 2之间， 或数据信号线 Data ( m )位于两个水平方向排列 的 Pixel 1和 Pixel 2中的 Pixel 1的一侧， 当然， 本发明实施例中的数据信号线 Data ( m )不限于位于 Pixel 1的一侧， 可以位于两个水平方向排列的像素中的 任一像素的一侧。
如图 12和 13所示， 所述垂直方向排列的任一像素单元中的两个像素共用 一条栅极控制信号线 Gate ( N ) 包括： 栅极控制信号线 Gate ( N )位于组成一 像素单元的垂直方向排列的任意两个像素之间或栅极控制信号线 Gate ( N )位 于组成一像素单元的垂直方向排列的任意两个像素中的任一像素的一侧。 综上所述， 本发明实施例提供的技术方案中， 所述 AMOLED像素电路包 括： 第一像素子电路和第二像素子电路， 以及与所述第一像素子电路和第二像 素子电路连接的初始化模块和数据电压写入模块， 所述初始化模块连接复位信 号端和低电位端， 用于在复位信号端输入的复位信号控制下对第一像素子电路 和第二像素子电路进行初始化； 所述数据电压写入模块连接数据电压和门信号 端， 用于在门信号端输入的信号控制下先对第一像素子电路写入第一数据电 压， 并对所述第一像素子电路的驱动模块进行补偿， 然后对第二像素子电路写 入第二数据电压， 并对第二像素子电路的驱动模块进行补偿， 所述 AMOLED 像素电路能够减小像素电路尺寸， 进而减小像素间距， 提高单位面积内所拥有 的像素数目， 提升画面显示品质。 离本发明的精神和范围。 这样， 倘若本发明实施例的这些修改和变型属于本发 明权利要求及其等同技术的范围之内， 则本发明也意图包含这些改动和变型在 内。

Claims

权 利 要 求 书
1、 一种像素电路， 其特征在于， 包括： 第一像素子电路和第二像素子电 路， 以及与所述第一像素子电路和第二像素子电路连接的初始化模块和数据 电压写入模块，
所述初始化模块连接复位信号端和低电位端， 用于在复位信号端输入的 复位信号控制下对第一像素子电路和第二像素子电路进行初始化；
所述数据电压写入模块连接数据电压和门信号端， 用于在门信号端输入 的信号控制下先对第一像素子电路和第二像素子电路写入第一数据电压， 并 对所述第一像素子电路的驱动模块进行补偿， 然后对第二像素子电路写入第 二数据电压， 并对第二像素子电路的驱动模块进行补偿。
2、 根据权利要求 1所述的电路， 其特征在于， 所述第一像素子电路包括 第一驱动模块、 第一发光模块、 第一阈值补偿模块和第一发光控制模块， 所述初始化模块连接所述第一阈值补偿模块， 用于在初始化模块输出的 初始化信号控制下对第一阈值补偿模块进行初始化；
所述第一阈值补偿模块连接第一驱动模块， 用于对第一驱动模块进行阈 值电压补偿；
所述第一发光模块连接第一发光控制模块， 用于在第一发光控制模块作 用下进行发光显示。
3、 根据权利要求 2所述的电路， 其特征在于， 所述第二像素子电路包括 第二驱动模块、 第二发光模块、 第二阈值补偿模块和第二发光控制模块， 所述初始化模块连接所述第二阈值补偿模块， 用于在初始化模块输出的 初始化信号控制下对第二阈值补偿模块进行初始化；
所述第二阈值补偿模块连接第二驱动模块， 用于对第二驱动模块进行阈 值电压补偿；
所述第二发光模块连接第二发光控制模块， 用于在第二发光控制模块作 用下进行发光显示。
4、 根据权利要求 2或 3所述的电路， 其特征在于， 所述第一阈值补偿模 块包括第一存储电容、 第三晶体管和第五晶体管； 所述第一驱动模块包括第 四晶体管； 所述第一发光控制模块包括第六晶体管和第七晶体管； 所述第一 发光模块包括第一发光二极管。
5、 根据权利要求 4所述的电路， 其特征在于， 所述第一存储电容的一端 与高电压电平信号线相连， 另一端与第三晶体管的源极相连；
所述第三晶体管的栅极与门信号端相连， 所述第三晶体管的漏极与所述 第四晶体管的漏极相连；
所述第五晶体管的栅极与开关控制信号线相连， 所述第五晶体管的源极 与所述第六晶体管的漏极相连， 所述第五晶体管的漏极与所述第四晶体管的 源极相连；
所述第四晶体管的栅极与所述初始化模块相连；
所述第六晶体管的栅极与发光控制信号线连接， 所述第六晶体管的源极 与高电压电平信号线相连；
所述第七晶体管的栅极与发光控制信号线连接， 所述第七晶体管的源极 与所述第四晶体管的漏极相连， 所述第七晶体管的漏极与第一发光二极管相 连；
所述第一发光二极管的阳极与第七晶体管的漏极相连， 所述第一发光二 极管的阴极与低电压电平信号线相连。
6、 根据权利要求 3所述的电路， 其特征在于， 所述第二阈值补偿模块包 括第二存储电容和第十晶体管； 所述第二驱动模块包括第九晶体管； 所述第 二发光控制模块包括第六晶体管和第八晶体管； 所述第二发光模块包括第二 发光二极管。
7、 根据权利要求 6所述的电路， 其特征在于， 所述第二存储电容的一端 与高电压电平信号线相连， 另一端与第十晶体管的源极相连；
所述第十晶体管的栅极与门信号端相连， 所述第十晶体管的漏极与所述 第九晶体管的漏极相连；
所述第九晶体管的栅极与所述第十晶体管的源极相连， 所述第九晶体管 的源极与所述数据电压写入模块相连；
所述第六晶体管的栅极与发光控制信号线连接， 所述第六晶体管的源极 与高电压电平信号线相连， 所述第六晶体管的漏极与所述第九晶体管的源极 相连；
所述第八晶体管的栅极与发光控制信号线连接， 所述第八晶体管的源极 与所述第九晶体管的漏极相连， 所述第八晶体管的漏极与第二发光二极管相 连； 所述第二发光二极管的阳极与第八晶体管的漏极相连， 所述第二发光二 极管的阴极与低电压电平信号线相连。
8、 根据权利要求 3所述的电路， 其特征在于， 所述初始化模块包括第一 晶体管和第十一晶体管， 其中， 所述第一晶体管的栅极与复位信号线相连， 所述第一晶体管的漏极与第一像素子电路的第一阈值补偿模块相连， 所述第 一晶体管的源极与低电位端相连； 所述第十一晶体管的栅极与复位信号线相 连， 所述第十一晶体管的漏极与第二像素子电路的第二阈值补偿模块相连， 所述第十一晶体管的源极与低电位端相连。
9、 根据权利要求 3所述的电路， 其特征在于， 所述数据电压写入模块包 括第二晶体管， 所述第二晶体管的栅极与门信号端相连， 所述第二晶体管的 源极与数据信号线相连， 所述第二晶体管的漏极与第一像素子电路的第一阈 值补偿模块和第二像素子电路的第二驱动模块相连。
10、 根据权利要求 9所述的电路， 其特征在于， 所述数据电压写入模块 中写入的数据电压包括第一数据电压和第二数据电压， 其中， 第一数据电压 用于驱动第一阈值补偿模块对第一驱动模块进行阈值电压补偿， 第二数据电 压用于驱动第二阈值补偿模块对第二驱动模块进行阈值电压补偿。
11、 根据权利要求 4或 6所述的电路， 其特征在于， 所述第一发光二极 管和第二发光二极管均为有机发光二极管。
12、 根据权利要求 4、 6、 8-9任一权项所述的电路， 其特征在于， 所述 晶体管均为 P型薄膜晶体管。
13、 一种显示器， 包括多个像素、 数据信号线以及栅极控制信号线， 其 特征在于， 每两个像素组成一像素单元， 还包括与各像素单元连接的权利要 求 1-12任一权项所述的像素电路。
14、 根据权利要求 13所述的显示器， 其特征在于， 所述每一像素单元中 的两个像素共用一条数据信号线。
15、 根据权利要求 13或 14所述的显示器， 其特征在于， 所述每一像素 单元中的两个像素共用一条栅极控制信号线。
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