WO2022110940A1 - 像素电路及其驱动方法、显示面板 - Google Patents

像素电路及其驱动方法、显示面板 Download PDF

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Publication number
WO2022110940A1
WO2022110940A1 PCT/CN2021/114926 CN2021114926W WO2022110940A1 WO 2022110940 A1 WO2022110940 A1 WO 2022110940A1 CN 2021114926 W CN2021114926 W CN 2021114926W WO 2022110940 A1 WO2022110940 A1 WO 2022110940A1
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Prior art keywords
module
transistor
signal
driving
light
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PCT/CN2021/114926
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English (en)
French (fr)
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米磊
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合肥维信诺科技有限公司
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Priority to KR1020227046366A priority Critical patent/KR20230017321A/ko
Publication of WO2022110940A1 publication Critical patent/WO2022110940A1/zh
Priority to US17/990,070 priority patent/US11887540B2/en

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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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Definitions

  • the embodiments of the present application relate to the field of display technology, for example, to a pixel circuit, a driving method thereof, and a display panel.
  • the pixel circuit in the display panel plays a very important role in driving the light-emitting element to emit light stably.
  • the pixel circuit is configured to drive the light-emitting element to emit light under the control of the scanning signal and the light-emitting control signal, and the scanning signal and the light-emitting control signal are provided by a gate driver circuit (Gate Driver in Panel, GIP) located in the non-display area of the display panel.
  • GIP Gate Driver in Panel
  • the pixel circuit needs to have a correspondingly arranged GIP circuit with a complicated structure, so that the display panel has a problem of a large frame.
  • Embodiments of the present application provide a pixel circuit, a driving method thereof, and a display panel, so as to simplify the structure of the GIP circuit and reduce the frame of the display panel.
  • a pixel circuit comprising:
  • the driving module is configured to generate a driving current in response to the data signal, so as to drive the light-emitting element to emit light;
  • a first initialization module the first initialization module is controlled by a first scan signal and a second scan signal; the first initialization module is set to be valid for the first scan signal and the second scan signal when the The control terminal of the drive module is initialized;
  • the data writing module is controlled by a third scan signal; when the second scan signal and the third scan signal are valid, the first initialization module is set to cooperate with the data writing module Write the data signal into the control terminal of the driving module.
  • the present application also provides a display panel, including: a plurality of pixel circuits according to any embodiment of the present application.
  • the present application also provides a driving method for a pixel circuit, which is applicable to the pixel circuit described in any embodiment of the present application; the driving method includes:
  • the first scan signal and the second scan signal are valid to control the first initialization module to initialize the control terminal of the drive module;
  • the second scanning signal and the third scanning signal are valid to control the first initialization module to cooperate with the data writing module to write the data signal into the control terminal of the driving module;
  • the driving module In the light-emitting stage, the driving module generates a driving current in response to the data signal to drive the light-emitting element to emit light.
  • the first initialization module of the pixel circuit is controlled by the first scan signal and the second scan signal
  • the data writing module is controlled by the third scan signal, which realizes threshold voltage compensation while writing data.
  • the waveform shapes of the first scan signal, the second scan signal and the third scan signal are the same, and the delay time interval is the same. Therefore, the scanning signal can be multiplexed by the upper and lower scanning signals.
  • the scanning signal of the current stage is the third scanning signal
  • the scanning signal of the upper stage is the second scanning signal
  • the scanning signals of the upper two stages are the first scanning signal.
  • the two scan signals can multiplex the scan signals of the previous stage
  • the first scan signal can multiplex the scan signals of the two previous stages.
  • the pixel circuit of the embodiment of the present application can output the scan signal by only one group of GIP circuits, which is beneficial to simplify the structure of the GIP circuit.
  • the embodiments of the present application are beneficial to simplify the way of providing scan signals, thereby simplifying the structure of the GIP circuit and reducing the frame width of the display panel.
  • FIG. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a driving sequence of a pixel circuit according to an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of another pixel circuit according to an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of another pixel circuit according to an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of another pixel circuit according to an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of another pixel circuit according to an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of another pixel circuit according to an embodiment of the present application.
  • FIG. 8 is a schematic flowchart of a method for driving a pixel circuit according to an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a display panel according to an embodiment of the present application.
  • Embodiments of the present application provide a pixel circuit, which is applicable to an N-type metal-oxide-semiconductor (N-Metal-Oxide-Semiconductor, NMOS) pixel circuit structure.
  • the pixel circuit includes a driving module 100 , a first initialization module 200 and a data writing module 300 .
  • the driving module 100 is configured to generate a driving current in response to the data signal, so as to drive the light-emitting element D to emit light.
  • the first initialization module 200 is connected to the first scan signal Scan1 and the second scan signal Scan2.
  • the first initialization module 200 is configured to initialize the control terminal of the driving module 100 when the first scan signal Scan1 and the second scan signal Scan2 are valid.
  • the data writing module 300 is connected to the third scan signal Scan3. When the second scan signal Scan2 and the third scan signal Scan3 are valid, the first initialization module 200 is configured to cooperate with the data writing module 300 to write the data signal to the control terminal of the driving module 100 .
  • the driving module 100 , the first initialization module 200 and the data writing module 300 are all composed of transistors, and whether the first scan signal Scan1 , the second scan signal Scan2 and the third scan signal Scan3 are valid depends on the type of the transistors.
  • the transistor connected to the scan signal is an N-type transistor, which is valid when the scan signal is at a high level.
  • the transistor connected to the scan signal is a P-type transistor, and it is valid when the scan signal is at a low level.
  • the signal for initializing the control terminal of the driving module 100 is the first initialization signal Vref1.
  • the driving module 100 includes a control terminal, a first terminal and a second terminal.
  • the first initialization module 200 includes a first control terminal, a second control terminal, an initialization signal input terminal, a data signal input terminal and an output terminal.
  • the first control terminal of the first initialization module 200 is connected to the first scan signal Scan1, the second control terminal is connected to the second scan signal Scan2, the initialization signal input terminal is connected to the first initialization signal Vref1, and the data signal input terminal is connected to the driving module 100.
  • the first terminal is electrically connected to the output terminal, and the output terminal is electrically connected to the control terminal of the driving module 100 .
  • the data writing module 300 includes a control terminal, an input terminal and an output terminal.
  • the control terminal of the data writing module 300 is connected to the third scan signal Scan3, the input terminal is connected to the data signal Data, and the output terminal is electrically connected to the second terminal of the driving module 100. connect.
  • the transistors in the driving module 100 , the first initialization module 200 and the data writing module 300 are all N-type transistors.
  • the working process of the pixel circuit includes the first stage t1, the second stage t2, the third stage t3 (second initialization stage), the fourth stage t4 (data writing stage), the fifth stage t5, the sixth stage t6 and the first stage Seven stages t7 (light-emitting stage). Only the third stage t3 (second initialization stage), the fourth stage t4 (data writing stage) and the seventh stage t7 (light-emitting stage) will be described below.
  • the first scan signal Scan1 and the second scan signal Scan2 are both at high level, which controls the input terminal and output terminal of the initialization signal of the first initialization module 200 to be turned on, thereby controlling the first
  • the initialization signal Vref1 is written into the control terminal of the driving module 100 to realize the initialization of the control terminal of the driving module 100, so that the driving module 100 is in a conducting state at the initial moment of the fourth stage t4.
  • the first scan signal Scan1 is at a low level
  • the second scan signal Scan2 and the third scan signal Scan3 are both at a high level
  • the second scan signal Scan2 controls the first initialization module 200
  • the input end and output end of the data signal are turned on, so that the first end and the control end of the driving module 100 are controlled to be turned on.
  • the third scan signal Scan3 controls the conduction of the input terminal and the output terminal of the data writing module 300 , thereby controlling the writing of the data signal to the second terminal of the driving module 100 .
  • the driving module 100 Since the driving module 100 is in the on state, the data signal is written to the driver sequentially through the second terminal of the driving module 100 , the first terminal of the driving module 100 , the data input terminal of the first initialization module 200 , and the output terminal of the first initialization module 200 .
  • the control terminal of the module 100 is turned off until the potential of the control terminal of the driving module 100 reaches Vdata+Vth, where Vdata is the data voltage and Vth is the threshold voltage of the driving module 100 .
  • Vdata the data voltage
  • Vth is the threshold voltage of the driving module 100 .
  • the threshold voltage Vth will be subtracted, so that the finally obtained driving current is not affected by the threshold voltage of the driving module 100 , thereby realizing threshold voltage compensation.
  • the first initialization module 200 cooperates with the data writing module 300 to write the data signal into the control terminal of the driving module 100, thereby realizing threshold voltage compensation.
  • the first scan signal Scan1, the second scan signal Scan2 and the third scan signal Scan3 are all low level
  • the first end of the driving module 100 is connected to the first power supply signal ELVDD
  • the driving module The second terminal of 100 is connected to the anode of the light-emitting element D
  • the cathode of the light-emitting element D is connected to the second power supply signal ELVSS
  • the driving module 100 generates a driving current in response to the data signal of the control terminal to drive the light-emitting element D to emit light.
  • the first initialization module 200 of the pixel circuit in the embodiment of the present application is controlled by the first scan signal Scan1 and the second scan signal Scan2, and the data writing module 300 is controlled by the third scan signal Scan3.
  • the module 100 simultaneously implements threshold voltage compensation.
  • the waveform shapes of the first scan signal Scan1 , the second scan signal Scan2 and the third scan signal Scan3 are the same, and the delay time intervals are the same. Therefore, the scanning signal can be multiplexed by the upper and lower scanning signals.
  • the scanning signal of the current stage is the third scanning signal Scan3, the scanning signal of the upper stage is the second scanning signal Scan2, and the scanning signals of the upper two stages are the first scanning signal Scan1.
  • the second scan signal Scan2 can multiplex the scan signals of the previous stage
  • the first scan signal Scan1 can multiplex the scan signals of the two previous stages.
  • the pixel circuit of the embodiment of the present application can output the scan signal by only one group of GIP circuits, which is beneficial to simplify the structure of the GIP circuit.
  • the embodiments of the present application are beneficial to simplify the way of providing scan signals, thereby simplifying the structure of the GIP circuit and reducing the frame width of the display panel.
  • the driving module 100 includes a driving transistor DTFT, the gate of the driving transistor DTFT is used as the control terminal of the driving module 100 , and the source of the driving transistor DTFT is used as the second terminal of the driving module 100 , the drain of the driving transistor DTFT serves as the first terminal of the driving module 100 .
  • the driving transistor DTFT is an N-type transistor, and the first power signal ELVDD is multiplexed into the first initialization signal Vref1.
  • the N-type transistor is turned on when its gate is at a high level, and correspondingly, the first initialization signal Vref1 should be set to a high level.
  • the first power supply signal ELVDD is at a high level, the first power supply signal ELVDD can be multiplexed into the first initialization signal Vref1. In this way, the first initialization signal Vref1 can be omitted, thereby facilitating the simplification of the structure of the driving circuit and the design of the signal wiring.
  • the pixel circuit further includes a first lighting control module 400 and a second lighting control module 500 .
  • the control terminal of the first lighting control module 400 is connected to the lighting control signal EM
  • the first terminal of the first lighting control module 400 is connected to the first power supply signal ELVDD
  • the second terminal of the first lighting control module 400 is connected to the first terminal of the driving module 100 .
  • One end is electrically connected.
  • the control terminal of the second lighting control module 500 is connected to the lighting control signal EM
  • the first terminal of the second lighting control module 500 is electrically connected to the second terminal of the driving module 100
  • the second terminal of the second lighting control module 500 is connected to the lighting element D Electrical connection.
  • the first scan signal Scan1 , the second scan signal Scan2 and the third scan signal Scan3 are all low level, and the light-emitting control signal EM is high level.
  • the light-emitting control signal EM controls the first end and the second end of the first light-emitting control module 400 to conduct, the first power signal ELVDD is written into the first end of the driving module 100 through the first light-emitting control module 400, and the light-emitting control signal EM controls the first end of the driving module 100.
  • the first end and the second end of the two light-emitting control modules 500 are connected to each other, so that the second end of the driving module 100 and the anode of the light-emitting element D are connected to each other.
  • the cathode of the light-emitting element D is connected to the second power supply signal ELVSS, and the driving module 100 generates a driving current in response to the data signal at the control terminal thereof, so as to drive the light-emitting element D to emit light.
  • the first light emission control module 400 and the second light emission control module 500 of the pixel circuit provided by the embodiment of the present application are controlled by the same light emission control signal EM.
  • the first lighting control module 400 needs to be turned on in the second initialization stage, and at the same time, the second lighting control module 500 needs to be turned on. Therefore, the control logic of the above-mentioned pixel circuit is relatively complicated, and the first light-emitting control module 400 and the second light-emitting control module 500 need to be controlled by different light-emitting control signals EM.
  • two sets of GIP circuits for outputting light-emitting control signals are required.
  • the structure of the pixel circuit provided by the embodiment of the present application does not need to set the first lighting control module 400 to be turned on in the second initialization stage, so that the first lighting control module 400 and the second lighting control module 500 can be turned on and off at the same time .
  • the control logic for the initialization of the control terminal of the driving module 100 in the embodiment of the present application is simple, and only one set of GIP circuits for outputting light-emitting control signals is required. Therefore, the embodiments of the present application only need one set of GIP circuits for outputting scanning signals, and only one set of GIP circuits for outputting light-emitting control signals EM, which simplifies the structure of the GIP circuit, thereby helping to reduce the frame of the display panel. .
  • the pixel circuit further includes a storage module 600, the first end of the storage module 600 is electrically connected to the control terminal of the drive module 100, the second end of the storage module 600 is electrically connected to the light-emitting element D, and the storage module 600 is configured as a storage driver
  • the potential of the control terminal of the module 100 ensures that the driving module 100 can generate a stable driving current in the light-emitting stage.
  • the pixel circuit further includes a second initialization module 700, the control terminal of the second initialization module 700 is connected to the first scan signal Scan1, the first terminal of the second initialization module 700 is connected to the second initialization signal Vref2, and the second initialization module The second end of 700 is electrically connected to the light-emitting element D.
  • the second initialization signal Vref2 is a DC reset signal.
  • the first scan signal Scan1 controls the first end and the second end of the second initialization module 700 in the high level stage
  • the second initialization signal Vref2 is written into the anode of the light-emitting element D through the second initialization module 700 .
  • the anode potential of the light-emitting element D is maintained at the potential of the second initialization signal Vref2.
  • the seventh stage t7 (light-emitting stage), the first terminal and the second terminal of the second lighting control module 500 are turned on, and the second initialization signal Vref2 is written into the second terminal of the driving module 100 .
  • the size of the drive current is determined by the following formula:
  • ⁇ is the mobility of the driving transistor DTFT
  • Cox is the parasitic capacitance Cst of the driving transistor DTFT
  • W/L is the width-length ratio of the driving transistor DTFT
  • Vgs is the gate-source voltage difference of the driving transistor DTFT.
  • the second initialization module 700 can be set to be controlled by the first scan signal.
  • the second initialization module 700 in the embodiment of the present application initializes the anode of the light-emitting element D and simultaneously initializes the second end of the driving module 100, which is beneficial to improve the accuracy of the driving current and improve the display of the display panel. quality.
  • the first initialization module 200 includes a first transistor T1 and a second transistor T2.
  • the gate of the first transistor T1 is connected to the first scan signal Scan1, and the first electrode of the first transistor T1 is connected to the first initialization signal Vref1.
  • the gate of the second transistor T2 is connected to the second scan signal Scan2, the first pole of the second transistor T2 is electrically connected to the second pole of the first transistor T1, and the second pole of the second transistor T2 is connected to the control terminal of the driving module 100 electrical connection.
  • the first transistor T1 and the second transistor T2 are both N-type transistors. When the first scan signal Scan1 and the second scan signal Scan2 are both at a high level, the first transistor T1 and the second transistor T2 are turned on, and the first initialization signal Vref1 Write to the gate of the drive transistor DTFT.
  • the first initialization module 200 is set to include a first transistor T1 and a second transistor T2, so that the function of the first initialization module 200 to initialize the gate of the driving transistor DTFT is realized.
  • the first initialization module 200 only includes two transistors, and the circuit structure is simple and easy to implement.
  • the first transistor T1 is a low temperature polysilicon transistor or an oxide transistor
  • the second transistor T2 is an oxide transistor.
  • the oxide transistor has a better function of preventing leakage current, thereby reducing the gate leakage current of the driving transistor DTFT and improving the display stability.
  • both the first transistor T1 and the second transistor T2 are oxide transistors, so as to reduce the leakage of the gate of the driving transistor DTFT through the second transistor T2 and the first transistor T1.
  • the first transistor T1 is a low temperature polysilicon transistor
  • the second transistor T2 is an oxide transistor. Since the first transistor T1 and the second transistor T2 are connected in series, when the leakage current on the second transistor T2 is small, the entire branch will be The leakage current is smaller, thereby reducing the gate leakage of the driving transistor DTFT.
  • the first pole of the second transistor T2 is also electrically connected to the first terminal of the driving module 100 .
  • the data writing module 300 includes a third transistor T3, the gate of the third transistor T3 is connected to the third scan signal Scan3, the first electrode of the third transistor T3 is connected to the data signal Data, and the second electrode of the third transistor T3 is connected to the drive.
  • the second end of the module 100 is electrically connected.
  • the first scan signal Scan1 When the first scan signal Scan1 is at a low level, the second scan signal Scan2 and the third scan signal Scan3 are at a high level, the first scan signal Scan1 controls the first transistor T1 to turn off, and the second scan signal Scan2 controls the second transistor T2 When turned on, the third scan signal Scan3 controls the third transistor T3 to be turned on.
  • the data signal Data is written into the gate of the driving transistor DTFT through the third transistor T3, the source of the driving transistor DTFT, the drain of the driving transistor DTFT, and the second transistor T2.
  • the first initialization module 200 is set to include a first transistor T1 and a second transistor T2. On the basis of realizing the function of the first initialization module 200 to initialize the gate of the driving transistor DTFT, the coordinated data writing is realized.
  • the module 300 functions to write a data signal into the gate of the drive transistor DTFT.
  • the first initialization module 200 only includes two transistors, and the circuit structure is simple and easy to implement.
  • the first lighting control module 400 includes a fourth transistor T4.
  • the gate of the fourth transistor T4 is connected to the light-emitting control signal EM
  • the first electrode of the fourth transistor T4 is connected to the first power signal ELVDD
  • the second electrode of the fourth transistor T4 is electrically connected to the drain of the driving transistor DTFT.
  • the second light-emitting control module 500 includes a fifth transistor T5, the gate of the fifth transistor T5 is connected to the light-emitting control signal EM, the first electrode of the fifth transistor T5 is electrically connected to the source electrode of the driving transistor DTFT, and the first electrode of the fifth transistor T5 is electrically connected to the source electrode of the driving transistor DTFT.
  • the diode is electrically connected to the light-emitting element D.
  • Both the fourth transistor T4 and the fifth transistor T5 are N-type transistors.
  • the light-emitting control signal EM controls the fourth transistor T4 and the fifth transistor T5 to be turned off, and the pixel circuit enters the initialization stage (including the first initialization stage and the second initialization stage) and the data writing stage.
  • the pixel circuit When the light-emitting control is at a high level, the pixel circuit enters the light-emitting stage, the light-emitting control signal EM controls the fourth transistor T4 and the fifth transistor T5 to be turned on, and the first power signal ELVDD is written into the drain of the driving transistor DTFT through the fourth transistor T4, The driving current flows into the light-emitting element D through the fifth transistor T5, and the light-emitting element D emits light.
  • the first lighting control module 400 includes a fourth transistor T4, and the second lighting control module 500 includes a fifth transistor T5.
  • the circuit structure is simple and easy to implement.
  • the second initialization module 700 includes a sixth transistor T6.
  • the gate of the sixth transistor T6 is connected to the first scan signal Scan1, the first electrode of the sixth transistor T6 is connected to the second initialization signal Vref2, and the second electrode of the sixth transistor T6 is electrically connected to the anode of the light emitting element D.
  • the storage module 600 includes a capacitor Cst, a first terminal of the capacitor Cst is electrically connected to the gate of the driving transistor DTFT, and a second terminal of the capacitor Cst is electrically connected to the second electrode of the sixth transistor T6.
  • the sixth transistor T6 is an N-type transistor.
  • the sixth transistor T6 is controlled to be turned on, and the second initialization signal Vref2 is written into the anode of the light-emitting element D to initialize the anode of the light-emitting element D.
  • the second initialization signal Vref2 is written into the anode of the light-emitting element D.
  • the second end of the capacitor Cst stores the second initialization potential.
  • the storage module 600 includes a capacitor Cst
  • the second initialization module 700 includes a sixth transistor T6.
  • the circuit structure is simple and easy to implement.
  • the pixel circuit includes a driving module 100 , a first initialization module 200 , a data writing module 300 , a first lighting control module 400 , a second lighting control module 500 , a storage module 600 and a second initialization module 700 .
  • the driving module 100 includes a driving transistor DTFT
  • the first initialization module 200 includes a first transistor T1 and a second transistor T2
  • the data writing module 300 includes a third transistor T3
  • the first light emission control module 400 includes a fourth transistor T4
  • the control module 500 includes a fifth transistor T5, the storage module 600 includes a capacitor Cst
  • the second initialization module 700 includes a sixth transistor T6.
  • the control signals of the pixel circuit include a first scan signal Scan1, a second scan signal Scan2, a third scan signal Scan3, an emission control signal EM, a second initialization signal Vref2, a first power supply signal ELVDD and a second power supply signal ELVSS.
  • the second initialization signal Vref2 is a DC reset signal
  • the first power supply signal ELVDD and the second power supply signal ELVSS are DC power supply signals, and provide the current required by the light-emitting element D to emit light.
  • the light-emitting element D is an organic light-emitting diode (Organic Light-Emitting Diode, OLED).
  • the pixel circuit has a 7T1C circuit structure.
  • the driving transistor DTFT, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are all N-type transistors, and the second transistor
  • the transistor T2 is an oxide transistor to reduce the gate leakage current of the driving transistor DTFT, and the other transistors are low temperature polysilicon transistors.
  • the connection relationship between the plurality of transistors and the capacitor Cst is such that both ends of the capacitor Cst are connected to the gate of the driving transistor DTFT and the anode of the light-emitting element D, respectively.
  • the third transistor T3 is controlled by the third scan signal Scan3, and writes the data signal to the source of the driving transistor DTFT.
  • the fourth transistor T4 and the fifth transistor T5 are both controlled by the light-emitting control signal EM, and jointly determine whether the light-emitting element D emits light.
  • the sixth transistor T6 is controlled by the first scan signal Scan1, and resets the anode of the light-emitting element D to the potential of the second initialization signal Vref2.
  • the second transistor T2 is controlled by the second scan signal Scan2, the first electrode of the second transistor T2 is connected to the drain of the driving transistor DTFT, and the second electrode of the second transistor T2 is connected to the gate of the driving transistor DTFT.
  • the first transistor T1 is controlled by the first scan signal Scan1, and the first transistor T1 and the second transistor T2 work together to reset the gate of the driving transistor DTFT to the potential of the first power supply signal ELVDD.
  • the first scan signal Scan1, the second scan signal Scan2, and the third scan signal Scan3 are all low level, and the light emission control signal EM changes from high level to low level,
  • the fourth transistor T4 and the fifth transistor T5 are turned off, the light-emitting element D finishes emitting light, and the pixel circuit enters the preparation stage before data writing.
  • the second scan signal Scan2, the third scan signal Scan3 and the light-emitting control signal EM are all low level, the first scan signal Scan1 changes from low level to high level, and the first scan signal Scan1 changes from low level to high level.
  • the six transistors T6 and the first transistor T1 are turned on, the second initialization signal Vref2 is written into the anode of the light-emitting element D through the sixth transistor T6, and the anode of the light-emitting element D is reset to the potential of the second initialization signal Vref2.
  • the first scan signal Scan1 maintains a high level
  • the third scan signal Scan3 and the light-emitting control signal EM maintain a low level
  • the second scan signal Scan2 changes from a low level to a high level flat
  • the second transistor T2 is turned on
  • the first transistor T1 and the second transistor T2 work together to reset the gate of the driving transistor DTFT to the potential of the first power supply signal ELVDD to ensure that the driving transistor DTFT is turned on at the beginning of the next stage state.
  • the second initialization signal Vref2 is still written to the anode of the light-emitting element D through the sixth transistor T6.
  • the light emission control signal EM remains at a low level
  • the first scan signal Scan1 changes from a high level to a low level
  • the first transistor T1 and the sixth transistor T6 are turned off.
  • the second scan signal Scan2 maintains a high level
  • the second transistor T2 is kept on
  • the source and drain of the driving transistor DTFT are short-circuited.
  • the third scan signal Scan3 changes from a low level to a high level, and the third transistor T3 is turned on.
  • the third transistor T3 and the second transistor T2 work together to discharge the gate potential of the driving transistor DTFT from the potential of the first power supply signal ELVDD to Vdata+Vth, and the driving transistor DTFT changes from on to to disconnect.
  • the first scan signal Scan1 and the light-emitting control signal EM maintain a low level
  • the second scan signal Scan2 changes from a high level to a low level
  • the second transistor T2 is turned off.
  • the third scan signal Scan3 remains at a high level
  • the third transistor T3 remains on
  • the source potential of the driving transistor DTFT is the potential of the data signal Data.
  • the first scan signal Scan1 , the second scan signal Scan2 and the light emission control signal EM keep the low level, the third scan signal Scan3 changes from the high level to the low level, and the third transistor T3 is turned off.
  • the first scan signal Scan1 , the second scan signal Scan2 and the third scan signal Scan3 maintain a low level.
  • the light-emitting control signal EM changes from a low level to a high level, the fourth transistor T4 and the fifth transistor T5 are turned on, and the light-emitting element D enters the light-emitting stage.
  • the magnitude of the drive current is determined by the following equation.
  • ⁇ is the mobility of the driving transistor DTFT
  • Cox is the parasitic capacitance Cst of the driving transistor DTFT
  • W/L is the width-length ratio of the driving transistor DTFT
  • Vgs is the gate-source voltage difference of the driving transistor DTFT. Since the gate voltage of the driving transistor DTFT is Vdata+Vth, in the process of calculating the driving current, the threshold voltage Vth will be subtracted, so that the finally obtained driving current is not affected by the threshold voltage of the driving module 100, thereby realizing Threshold voltage compensation.
  • the source voltage of the driving transistor DTFT is initialized to the potential of the second initialization voltage in the first initialization stage, instead of directly using the second power supply signal ELVSS for calculation, the voltage drop on the second power supply signal ELVSS (IR The calculation error caused by drop) maintains the stability of the source voltage of the driving transistor DTFT and the accuracy of the calculation of the driving current.
  • the embodiments of the present application are conducive to simplifying the structure of the GIP circuit, thereby reducing the frame of the display panel. analyse as below:
  • the scanning signal can be multiplexed by the upper and lower scanning signals.
  • the scanning signal of the current stage is the third scanning signal Scan3
  • the scanning signal of the upper stage is the second scanning signal Scan2
  • the scanning signals of the upper two stages are the first scanning signal Scan1.
  • the second scan signal Scan2 can multiplex the scan signals of the previous stage
  • the first scan signal Scan1 can multiplex the scan signals of the two previous stages.
  • the pixel circuit of the embodiment of the present application can output the scan signal by only one group of GIP circuits.
  • control logic of the pixel circuit is generally complicated, and the first lighting control module 400 and the second lighting control module 500 need to be controlled by using different lighting control signals EM.
  • two sets of GIP circuits for outputting the lighting control signal EM are required.
  • the control logic for the initialization of the control terminal of the driving module 100 in the embodiment of the present application is simple, and only one set of GIP circuits for outputting the light-emitting control signal EM is required.
  • the embodiments of the present application provide a brand-new 7T1C full NMOS pixel circuit, which is not only conducive to simplifying the structure of the GIP circuit and reducing the frame of the display panel, but also realizes threshold voltage compensation and avoids the The calculation error caused by the IR drop of the two power supply signals ELVSS, and the gate leakage current of the driving transistor DTFT is reduced.
  • the embodiment of the present application also provides a driving method for a pixel circuit, and the driving method is applicable to the pixel circuit provided by any embodiment of the present application.
  • the driving method includes the following steps:
  • the first scan signal and the second scan signal are valid to control the first initialization module to initialize the control terminal of the driving module.
  • the second scanning signal and the third scanning signal are valid to control the first initialization module to cooperate with the data writing module to write the data signal into the control terminal of the driving module.
  • the driving module in the light-emitting stage, the driving module generates a driving current in response to the data signal to drive the light-emitting element to emit light.
  • the scanning signal can be multiplexed by the upper and lower scanning signals.
  • the scanning signal of the current stage is the third scanning signal
  • the scanning signal of the upper stage is the second scanning signal
  • the scanning signals of the upper two stages are the first scanning signal.
  • the two scan signals can multiplex the scan signals of the previous stage
  • the first scan signal can multiplex the scan signals of the two previous stages.
  • the pixel circuit of the embodiment of the present application can output the scan signal by only one group of GIP circuits, which is beneficial to simplify the structure of the GIP circuit.
  • An embodiment of the present application also provides a display panel, the display panel includes: a plurality of pixel circuits as provided in any embodiment of the present application, and the technical principles thereof are similar, and details are not repeated here.
  • the display panel includes a display area 710 and a non-display area 720 .
  • the display panel further includes a plurality of pixel circuits 711 and a plurality of scan driving circuits 721 .
  • the plurality of pixel circuits 711 in the display area 710 are arranged in an array, and the plurality of scan driving circuits 721 in the non-display area 720 are connected in cascade.
  • the scan signal output by the n-th scan driving circuit 721 is used as the third scan signal of the pixel circuit 711 in the n-th row; signal; the scan signal output by the n-2th level scan drive circuit 721 is used as the first scan signal of the nth row of pixel circuits 711 ; wherein, n is a positive integer, and n ⁇ 3.
  • the third scan signal line 714 of the pixel circuit 711 in the nth row is electrically connected to the scan driver circuit 721 of the nth stage, and the second scan signal line 713 of the pixel circuit 711 of the nth row is electrically connected to the scan driver circuit of the n ⁇ 1st stage.
  • 721 is electrically connected, and the first scan signal line 712 of the pixel circuit 711 of the nth row is electrically connected to the scan driving circuit 721 of the n-2th level.
  • the embodiments of the present application are arranged in this way, so as to realize the effect that the first scan signal, the second scan signal and the third scan signal share a set of GIP circuits for outputting the scan signal.
  • the pixel circuits 711 in the third row and the rows below the third row can multiplex the scan driving circuits 721 of the upper row and the upper two rows, and the pixel circuits 711 of the first row and the second row need to be additionally A two-stage scan drive circuit 721 is provided. Therefore, the number of stages of the scan driving circuits 721 on the display panel is at least two more stages than the number of rows of the pixel circuits 711 .
  • the display panel further includes a light-emitting driving circuit 722 connected in cascade, and the light-emitting driving circuit 722 is disposed in the non-display area 720 of the display panel.
  • the light-emission control signal output by the n-th stage light-emission driving circuit 722 is used as the light-emission control signal of the pixel circuit 711 in the n-th row. That is, the light emission control signal line 715 of the pixel circuit 711 of the nth row is electrically connected to the light emission driving circuit 722 of the nth stage.
  • the embodiments of the present application are set in this way, and the effect of using a set of GIP circuits for outputting light-emitting control signals is achieved.

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Abstract

一种像素电路及其驱动方法、显示面板，像素电路包括：驱动模块（100），驱动模块（100）设置为响应数据信号而产生驱动电流，以驱动发光元件（D）发光；第一初始化模块（200），第一初始化模块（200）由第一扫描信号（Scan1）和第二扫描信号（Scan2）控制；第一初始化模块（200）设置为在第一扫描信号（Scan1）和第二扫描信号（Scan2）有效时，对驱动模块（100）的控制端进行初始化；数据写入模块（300），数据写入模块（300）由第三扫描信号（Scan3）控制；在第二扫描信号（Scan2）和第三扫描信号（Scan3）有效时，第一初始化模块（200）设置为配合数据写入模块（300）将数据信号写入驱动模块（100）的控制端。

Description

像素电路及其驱动方法、显示面板
本申请要求在2020年11月26日提交中国专利局、申请号为202011354699.3的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及显示技术领域，例如涉及一种像素电路及其驱动方法、显示面板。
背景技术
随着显示技术的不断发展，显示面板的应用范围越来越广泛，人们对显示面板的要求也越来越高。
显示面板中的像素电路在驱动发光元件稳定发光方面起到了非常重要的作用。像素电路设置为在扫描信号和发光控制信号的控制下驱动发光元件发光，而扫描信号和发光控制信号由位于显示面板的非显示区的门驱动电路(Gate Driver in Panel，GIP)提供。然而，像素电路需要对应设置的GIP电路的结构复杂，使得显示面板存在边框较大的问题。
发明内容
本申请实施例提供一种像素电路及其驱动方法、显示面板，以简化GIP电路的结构，减小显示面板的边框。
本申请实施例提供了如下技术方案：
一种像素电路，包括：
驱动模块，所述驱动模块设置为响应数据信号而产生驱动电流，以驱动发光元件发光；
第一初始化模块，所述第一初始化模块由第一扫描信号和第二扫描信号控制；所述第一初始化模块设置为在所述第一扫描信号和所述第二扫描信号有效 时，对所述驱动模块的控制端进行初始化；
数据写入模块，所述数据写入模块由第三扫描信号控制；在所述第二扫描信号和所述第三扫描信号有效时，所述第一初始化模块设置为配合所述数据写入模块将所述数据信号写入所述驱动模块的控制端。
本申请还提供了一种显示面板，包括：多个如本申请任意实施例所述的像素电路。
本申请还提供了一种像素电路的驱动方法，适用于本申请任意实施例所述的像素电路；所述驱动方法包括：
初始化阶段，所述第一扫描信号和所述第二扫描信号有效，以控制所述第一初始化模块对所述驱动模块的控制端进行初始化；
数据写入阶段，所述第二扫描信号和所述第三扫描信号有效，以控制所述第一初始化模块配合所述数据写入模块将数据信号写入所述驱动模块的控制端；
发光阶段，所述驱动模块响应所述数据信号而产生驱动电流，以驱动发光元件发光。
本申请实施例设置像素电路的第一初始化模块由第一扫描信号和第二扫描信号控制，数据写入模块由第三扫描信号控制，在数据写入的同时实现了阈值电压补偿。以及在像素电路的驱动过程中，第一扫描信号、第二扫描信号和第三扫描信号的波形形状一致，延迟的时间间隔相同。因此，扫描信号可以采用上下级扫描信号复用，例如，本级扫描信号为第三扫描信号，上一级扫描信号为第二扫描信号，上两级扫描信号为第一扫描信号，那么，第二扫描信号可以复用上一级的扫描信号，第一扫描信号可以复用上两级的扫描信号。这样，本申请实施例的像素电路可以仅由一组GIP电路来输出扫描信号，从而有利于简化GIP电路的结构。综上所述，本申请实施例在实现阈值电压补偿的基础上，有利于简化扫描信号的提供方式，从而有利于简化GIP电路的结构、减小显示面板的边框宽度。
附图说明
图1为本申请实施例提供的一种像素电路的结构示意图。
图2为本申请实施例提供的一种像素电路的驱动时序示意图。
图3为本申请实施例提供的另一种像素电路的结构示意图。
图4为本申请实施例提供的又一种像素电路的结构示意图。
图5为本申请实施例提供的又一种像素电路的结构示意图。
图6为本申请实施例提供的又一种像素电路的结构示意图。
图7为本申请实施例提供的又一种像素电路的结构示意图。
图8为本申请实施例提供的一种像素电路的驱动方法的流程示意图。
图9为本申请实施例提供的一种显示面板的结构示意图。
具体实施方式
下面结合附图和实施例对本申请作详细说明。
本申请实施例提供了一种像素电路，该像素电路可适用于N型金属-氧化物-半导体(N-Metal-Oxide-Semiconductor，NMOS)像素电路结构。参见图1，该像素电路包括驱动模块100、第一初始化模块200和数据写入模块300。驱动模块100设置为响应数据信号而产生驱动电流，以驱动发光元件D发光。第一初始化模块200与第一扫描信号Scan1和第二扫描信号Scan2连接。第一初始化模块200设置为在第一扫描信号Scan1和第二扫描信号Scan2有效时，对驱动模块100的控制端进行初始化。数据写入模块300与第三扫描信号Scan3连接。在第二扫描信号Scan2和第三扫描信号Scan3有效时，第一初始化模块200设置为配合数据写入模块300将数据信号写入驱动模块100的控制端。
其中，驱动模块100、第一初始化模块200和数据写入模块300均由晶体管构成，第一扫描信号Scan1、第二扫描信号Scan2和第三扫描信号Scan3是否有效与晶体管的类型有关。扫描信号连接的晶体管为N型晶体管，扫描信号为高电平时有效。扫描信号连接的晶体管的为P型晶体管，扫描信号为低电平时有 效。对驱动模块100的控制端进行初始化的信号为第一初始化信号Vref1。
驱动模块100包括控制端、第一端和第二端。第一初始化模块200包括第一控制端、第二控制端、初始化信号输入端、数据信号输入端和输出端。第一初始化模块200的第一控制端接入第一扫描信号Scan1，第二控制端接入第二扫描信号Scan2，初始化信号输入端接入第一初始化信号Vref1，数据信号输入端与驱动模块100的第一端电连接，输出端与驱动模块100的控制端电连接。数据写入模块300包括控制端、输入端和输出端，数据写入模块300的控制端接入第三扫描信号Scan3，输入端接入数据信号Data，输出端与驱动模块100的第二端电连接。
参阅图2，驱动模块100、第一初始化模块200和数据写入模块300中的晶体管均为N型晶体管。该像素电路的工作过程包括第一阶段t1、第二阶段t2、第三阶段t3(第二初始化阶段)、第四阶段t4(数据写入阶段)、第五阶段t5、第六阶段t6和第七阶段t7(发光阶段)。下面仅对其中的第三阶段t3(第二初始化阶段)、第四阶段t4(数据写入阶段)和第七阶段t7(发光阶段)进行说明。
在第三阶段t3(第二初始化阶段)，第一扫描信号Scan1和第二扫描信号Scan2均为高电平，控制第一初始化模块200的初始化信号输入端和输出端导通，从而控制第一初始化信号Vref1写入驱动模块100的控制端，实现了对驱动模块100的控制端的初始化，以使驱动模块100在第四阶段t4的初始时刻处于导通状态。
在第四阶段t4(数据写入阶段)，第一扫描信号Scan1为低电平，第二扫描信号Scan2和第三扫描信号Scan3均为高电平，第二扫描信号Scan2控制第一初始化模块200的数据信号输入端和输出端导通，从而控制驱动模块100的第一端和控制端导通。第三扫描信号Scan3控制数据写入模块300的输入端和输出端导通，从而控制数据信号写入驱动模块100的第二端。由于驱动模块100处于导通状态，数据信号依次通过驱动模块100的第二端、驱动模块100的第一端、第一初始化模块200的数据输入端、第一初始化模块200的输出端写入驱 动模块100的控制端，直至驱动模块100的控制端的电位达到在Vdata+Vth，驱动模块100断开，其中，Vdata为数据电压，Vth为驱动模块100的阈值电压。在后续计算驱动电流的过程中，阈值电压Vth会被减去，使得最终获得的驱动电流不受驱动模块100的阈值电压的影响，从而实现了阈值电压补偿。由此，实现了第一初始化模块200配合数据写入模块300将数据信号写入驱动模块100的控制端，实现了阈值电压补偿。
在第七阶段t7(发光阶段)，第一扫描信号Scan1、第二扫描信号Scan2和第三扫描信号Scan3均为低电平，驱动模块100的第一端接入第一电源信号ELVDD，驱动模块100的第二端与发光元件D的阳极接通，发光元件D的阴极接入第二电源信号ELVSS，驱动模块100响应其控制端的数据信号而产生驱动电流，以驱动发光元件D发光。
由此可见，本申请实施例设置像素电路的第一初始化模块200由第一扫描信号Scan1和第二扫描信号Scan2控制，数据写入模块300由第三扫描信号Scan3控制，在数据信号写入驱动模块100的同时实现了阈值电压补偿。以及在像素电路的驱动过程中，第一扫描信号Scan1、第二扫描信号Scan2和第三扫描信号Scan3的波形形状一致，延迟的时间间隔相同。因此，扫描信号可以采用上下级扫描信号复用，例如，本级扫描信号为第三扫描信号Scan3，上一级扫描信号为第二扫描信号Scan2，上两级扫描信号为第一扫描信号Scan1，那么，第二扫描信号Scan2可以复用上一级的扫描信号，第一扫描信号Scan1可以复用上两级的扫描信号。这样，本申请实施例的像素电路可以仅由一组GIP电路来输出扫描信号，从而有利于简化GIP电路的结构。综上所述，本申请实施例在实现阈值电压补偿的基础上，有利于简化扫描信号的提供方式，从而有利于简化GIP电路的结构、减小显示面板的边框宽度。
参见图1，在本申请的一种实施方式中，驱动模块100包括驱动晶体管DTFT，驱动晶体管DTFT的栅极作为驱动模块100的控制端，驱动晶体管DTFT的源极作为驱动模块100的第二端，驱动晶体管DTFT的漏极作为驱动模块100的 第一端。驱动晶体管DTFT为N型晶体管，第一电源信号ELVDD复用为第一初始化信号Vref1。其中，N型晶体管在其栅极为高电平时导通，对应的，第一初始化信号Vref1应设置为高电平。又由于第一电源信号ELVDD为高电平，因此可以采用第一电源信号ELVDD复用为第一初始化信号Vref1。这样设置，可以省去第一初始化信号Vref1，从而有利于简化驱动电路的结构，以及简化信号走线的设计。
参见图1和图2，像素电路还包括第一发光控制模块400和第二发光控制模块500。第一发光控制模块400的控制端接入发光控制信号EM，第一发光控制模块400的第一端接入第一电源信号ELVDD，第一发光控制模块400的第二端与驱动模块100的第一端电连接。第二发光控制模块500的控制端接入发光控制信号EM，第二发光控制模块500的第一端与驱动模块100的第二端电连接，第二发光控制模块500的第二端与发光元件D电连接。
像素电路在第七阶段t7(发光阶段)，第一扫描信号Scan1、第二扫描信号Scan2和第三扫描信号Scan3均为低电平，发光控制信号EM为高电平。发光控制信号EM控制第一发光控制模块400的第一端和第二端导通，第一电源信号ELVDD通过第一发光控制模块400写入驱动模块100的第一端，发光控制信号EM控制第二发光控制模块500的第一端和第二端导通，从而使得驱动模块100的第二端和发光元件D的阳极导通。发光元件D的阴极接入第二电源信号ELVSS，驱动模块100响应其控制端的数据信号而产生驱动电流，以驱动发光元件D发光。
由此可见，本申请实施例提供的像素电路的第一发光控制模块400和第二发光控制模块500由同一个发光控制信号EM来控制。然而，对于一般的像素电路，若要实现第一电源信号ELVDD复用为第一初始化信号Vref1，需要在第二初始化阶段导通第一发光控制模块400，与此同时，第二发光控制模块500不能导通，因此，上述像素电路控制逻辑较为复杂，第一发光控制模块400和第二发光控制模块500需要采用不同的发光控制信号EM来控制。对应地，需要 两套输出发光控制信号的GIP电路。
本申请实施例所提供的像素电路的结构，无需设置采用第一发光控制模块400在第二初始化阶段导通，使得第一发光控制模块400和第二发光控制模块500可以同时导通和关断。本申请实施例对驱动模块100的控制端的初始化的控制逻辑简单，且仅需要一套输出发光控制信号的GIP电路。因此，本申请实施例在仅需一套输出扫描信号的GIP电路的基础上，仅需一套输出发光控制信号EM的GIP电路，简化了GIP电路的结构，从而有利于减小显示面板的边框。
参见图1，像素电路还包括存储模块600，存储模块600的第一端与驱动模块100的控制端电连接，存储模块600的第二端与发光元件D电连接，存储模块600设置为存储驱动模块100的控制端的电位，以确保驱动模块100能够在发光阶段产生稳定的驱动电流。
参见图3，像素电路还包括第二初始化模块700，第二初始化模块700的控制端接入第一扫描信号Scan1，第二初始化模块700第一端接入第二初始化信号Vref2，第二初始化模块700的第二端与发光元件D电连接。其中，与第一初始化信号Vref1类似，第二初始化信号Vref2为直流复位信号。
结合图2和图3，在像素电路的驱动过程中的第二阶段t2(第一初始化阶段)，第一扫描信号Scan1在高电平阶段控制第二初始化模块700的第一端和第二端导通，第二初始化信号Vref2通过第二初始化模块700写入发光元件D的阳极。且在存储模块600的作用下，发光元件D的阳极电位保持为第二初始化信号Vref2的电位。
在第七阶段t7(发光阶段)，第二发光控制模块500的第一端和第二端导通，第二初始化信号Vref2写入驱动模块100的第二端。驱动电流的大小由下式决定：
I＝1/2*μ*Cox*W/L*(Vgs-Vth) 2＝1/2*μ*Cox*W/L*(Vdata-Vref2) 2
其中，μ为驱动晶体管DTFT的迁移率，Cox为驱动晶体管DTFT的寄生电容Cst，W/L为驱动晶体管DTFT的宽长比，Vgs为驱动晶体管DTFT的栅源电压差。
由此可见，基于本申请实施例提供的像素电路的结构，可以设置第二初始化模块700由第一扫描信号控制。本申请实施例中的第二初始化模块700在对发光元件D的阳极进行初始化的同时，实现了对驱动模块100的第二端进行初始化，有利于提升驱动电流的准确性，提升显示面板的显示品质。
参见图4，第一初始化模块200包括第一晶体管T1和第二晶体管T2。第一晶体管T1的栅极接入第一扫描信号Scan1，第一晶体管T1的第一极接入第一初始化信号Vref1。第二晶体管T2的栅极接入第二扫描信号Scan2，第二晶体管T2的第一极与第一晶体管T1的第二极电连接，第二晶体管T2的第二极与驱动模块100的控制端电连接。
第一晶体管T1和第二晶体管T2均为N型晶体管，当第一扫描信号Scan1和第二扫描信号Scan2均为高电平时，第一晶体管T1和第二晶体管T2导通，第一初始化信号Vref1写入驱动晶体管DTFT的栅极。
本申请实施例设置第一初始化模块200包括第一晶体管T1和第二晶体管T2，实现了第一初始化模块200对驱动晶体管DTFT的栅极进行初始化的功能。第一初始化模块200仅包括两个晶体管，电路结构简单，易于实现。
第一晶体管T1为低温多晶硅晶体管或氧化物晶体管，第二晶体管T2为氧化物晶体管。其中，与低温多晶硅晶体管相比，氧化物晶体管具有更好的防漏电流的作用，从而减小驱动晶体管DTFT的栅极漏电流，提升显示的稳定性。示例性地，第一晶体管T1和第二晶体管T2均为氧化物晶体管，从而减小驱动晶体管DTFT的栅极通过第二晶体管T2和第一晶体管T1漏电。或者，第一晶体管T1为低温多晶硅晶体管，第二晶体管T2为氧化物晶体管，由于第一晶体管T1和第二晶体管T2为串联连接，当第二晶体管T2上漏电流较小时，使得整条支路上的漏电流较小，从而起到了减小驱动晶体管DTFT的栅极漏电的作用。
参见图5，第二晶体管T2的第一极还与驱动模块100的第一端电连接。数据写入模块300包括第三晶体管T3，第三晶体管T3的栅极接入第三扫描信号Scan3，第三晶体管T3的第一极接入数据信号Data，第三晶体管T3的第二极与 驱动模块100的第二端电连接。
当第一扫描信号Scan1为低电平，第二扫描信号Scan2和第三扫描信号Scan3为高电平时，第一扫描信号Scan1控制第一晶体管T1断开，第二扫描信号Scan2控制第二晶体管T2导通，第三扫描信号Scan3控制第三晶体管T3导通。数据信号Data通过第三晶体管T3、驱动晶体管DTFT的源极、驱动晶体管DTFT的漏极、第二晶体管T2写入驱动晶体管DTFT栅极。
本申请实施例设置第一初始化模块200包括第一晶体管T1和第二晶体管T2，在实现了第一初始化模块200对驱动晶体管DTFT的栅极进行初始化的功能的基础上，实现了配合数据写入模块300将数据信号写入驱动晶体管DTFT的栅极的功能。另外，第一初始化模块200仅包括两个晶体管，电路结构简单，易于实现。
参见图6，第一发光控制模块400包括第四晶体管T4。第四晶体管T4的栅极接入发光控制信号EM，第四晶体管T4的第一极接入第一电源信号ELVDD，第四晶体管T4的第二极与驱动晶体管DTFT的漏极电连接。第二发光控制模块500包括第五晶体管T5，第五晶体管T5的栅极接入发光控制信号EM，第五晶体管T5的第一极与驱动晶体管DTFT的源极电连接，第五晶体管T5的第二极与发光元件D电连接。
第四晶体管T4和第五晶体管T5均为N型晶体管。当发光控制信号EM为低电平时，发光控制信号EM控制第四晶体管T4和第五晶体管T5断开，像素电路进入初始化阶段(包括第一初始化阶段和第二初始化阶段)和数据写入阶段。当发光控制为高电平时，像素电路进入发光阶段，发光控制信号EM控制第四晶体管T4和第五晶体管T5导通，第一电源信号ELVDD通过第四晶体管T4写入驱动晶体管DTFT的漏极，驱动电流通过第五晶体管T5流入发光元件D，发光元件D发光。
本申请实施例设置第一发光控制模块400包括第四晶体管T4，第二发光控制模块500包括第五晶体管T5，电路结构简单，易于实现。
参见图7，第二初始化模块700包括第六晶体管T6。第六晶体管T6的栅极接入第一扫描信号Scan1，第六晶体管T6的第一极接入第二初始化信号Vref2，第六晶体管T6的第二极与发光元件D的阳极电连接。存储模块600包括电容Cst，电容Cst的第一端与驱动晶体管DTFT的栅极电连接，电容Cst的第二端与第六晶体管T6的第二极电连接。
第六晶体管T6为N型晶体管。当第一扫描信号Scan1为高电平时，控制第六晶体管T6导通，第二初始化信号Vref2写入发光元件D的阳极，对发光元件D的阳极进行初始化，同时，第二初始化信号Vref2写入电容Cst的第二端，电容Cst存储第二初始化电位。
本申请实施例设置存储模块600包括电容Cst，第二初始化模块700包括第六晶体管T6，电路结构简单，易于实现。
参见图7，像素电路包括驱动模块100、第一初始化模块200、数据写入模块300、第一发光控制模块400、第二发光控制模块500、存储模块600和第二初始化模块700。驱动模块100包括驱动晶体管DTFT，第一初始化模块200包括第一晶体管T1和第二晶体管T2，数据写入模块300包括第三晶体管T3，第一发光控制模块400包括第四晶体管T4，第二发光控制模块500包括第五晶体管T5，存储模块600包括电容Cst，第二初始化模块700包括第六晶体管T6。像素电路的控制信号包括第一扫描信号Scan1、第二扫描信号Scan2、第三扫描信号Scan3、发光控制信号EM、第二初始化信号Vref2、第一电源信号ELVDD和第二电源信号ELVSS。
其中，第二初始化信号Vref2为直流复位信号，第一电源信号ELVDD和第二电源信号ELVSS为直流电源信号，提供发光元件D发光需要的电流。发光元件D为有机发光二极管(Organic Light-Emitting Diode，OLED)。该像素电路为7T1C电路结构，驱动晶体管DTFT、第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5和第六晶体管T6均为N型晶体管，且第二晶体管T2为氧化物晶体管，以减小驱动晶体管DTFT的栅极漏电流，其 余晶体管为低温多晶硅晶体管。
多个晶体管和电容Cst的连接关系为，电容Cst两端分别连接驱动晶体管DTFT的栅极和发光元件D的阳极。第三晶体管T3由第三扫描信号Scan3控制，将数据信号写入驱动晶体管DTFT的源极。第四晶体管T4和第五晶体管T5均由发光控制信号EM控制，共同决定发光元件D是否发光。第六晶体管T6由第一扫描信号Scan1控制，将发光元件D的阳极复位至第二初始化信号Vref2的电位。第二晶体管T2由第二扫描信号Scan2控制，第二晶体管T2的第一极连接驱动晶体管DTFT的漏极，第二晶体管T2的第二极连接驱动晶体管DTFT的栅极。第一晶体管T1由第一扫描信号Scan1控制，第一晶体管T1和第二晶体管T2共同作用，将驱动晶体管DTFT的栅极复位至第一电源信号ELVDD的电位。
结合图7和图2，在第一阶段t1，第一扫描信号Scan1、第二扫描信号Scan2、第三扫描信号Scan3均为低电平，发光控制信号EM由高电平变为低电平，第四晶体管T4和第五晶体管T5断开，发光元件D结束发光，像素电路进入数据写入前的准备阶段。
在第二阶段t2(第一初始化阶段)，第二扫描信号Scan2、第三扫描信号Scan3和发光控制信号EM均为低电平，第一扫描信号Scan1由低电平变为高电平，第六晶体管T6和第一晶体管T1导通，第二初始化信号Vref2通过第六晶体管T6写入发光元件D的阳极，发光元件D的阳极复位至第二初始化信号Vref2的电位。
在第三阶段t3(第二初始化阶段)，第一扫描信号Scan1保持高电平，第三扫描信号Scan3和发光控制信号EM保持低电平，第二扫描信号Scan2由低电平变为高电平，第二晶体管T2导通，第一晶体管T1和第二晶体管T2共同作用将驱动晶体管DTFT的栅极复位至第一电源信号ELVDD的电位，以确保驱动晶体管DTFT在下一阶段开始时为导通状态。与此同时，第二初始化信号Vref2仍然通过第六晶体管T6写入发光元件D的阳极。
在第四阶段t4(数据写入阶段)，发光控制信号EM保持低电平，第一扫描信号Scan1由高电平变为低电平，第一晶体管T1和第六晶体管T6断开。第二扫描信号Scan2保持高电平，第二晶体管T2保持导通，将驱动晶体管DTFT的源极和漏极短接。第三扫描信号Scan3由低电平变为高电平，第三晶体管T3导通。由于驱动晶体管DTFT处于导通状态，第三晶体管T3和第二晶体管T2共同作用，将驱动晶体管DTFT的栅极电位由第一电源信号ELVDD的电位放电至Vdata+Vth，驱动晶体管DTFT由导通变为断开。
在第五阶段t5，第一扫描信号Scan1和发光控制信号EM保持低电平，第二扫描信号Scan2由高电平变为低电平，第二晶体管T2断开。第三扫描信号Scan3保持高电平，第三晶体管T3保持导通，驱动晶体管DTFT的源极电位为数据信号Data的电位。
在第六阶段t6，第一扫描信号Scan1、第二扫描信号Scan2和发光控制信号EM保持低电平，第三扫描信号Scan3由高电平变为低电平，第三晶体管T3断开。
在第七阶段t7(发光阶段)，第一扫描信号Scan1、第二扫描信号Scan2和第三扫描信号Scan3保持低电平。发光控制信号EM由低电平变为高电平，第四晶体管T4和第五晶体管T5导通，发光元件D进入发光阶段。驱动电流的大小由下式决定。
I＝1/2*μ*Cox*W/L*(Vgs-Vth) 2＝1/2*μ*Cox*W/L*(Vdata-Vref2) 2
其中，μ为驱动晶体管DTFT的迁移率，Cox为驱动晶体管DTFT的寄生电容Cst，W/L为驱动晶体管DTFT的宽长比，Vgs为驱动晶体管DTFT的栅源电压差。由于驱动晶体管DTFT的栅极电压为Vdata+Vth，因此在计算驱动电流的过程中，阈值电压Vth会被减去，使得最终获得的驱动电流不受驱动模块100的阈值电压的影响，从而实现了阈值电压补偿。另外，由于驱动晶体管DTFT的源极电压在第一初始化阶段中初始化为第二初始化电压的电位，而非直接采用第二电源信号ELVSS进行计算，避免了第二电源信号ELVSS上的电压降落 (IR drop)带来的计算误差，维持了驱动晶体管DTFT的源极电压的稳定和驱动电流计算的准确性。
本申请实施例有利于简化GIP电路的结构，从而有利于减小显示面板的边框。分析如下：
一方面，在像素电路的驱动过程中，第一扫描信号Scan1、第二扫描信号Scan2和第三扫描信号Scan3的波形形状一致，延迟的时间间隔相同。因此，扫描信号可以采用上下级扫描信号复用，例如，本级扫描信号为第三扫描信号Scan3，上一级扫描信号为第二扫描信号Scan2，上两级扫描信号为第一扫描信号Scan1，那么，第二扫描信号Scan2可以复用上一级的扫描信号，第一扫描信号Scan1可以复用上两级的扫描信号。这样，本申请实施例的像素电路可以仅由一组GIP电路来输出扫描信号。
另一方面，像素电路控制逻辑一般较为复杂，第一发光控制模块400和第二发光控制模块500需要采用不同的发光控制信号EM来控制。对应地，需要两套输出发光控制信号EM的GIP电路。本申请实施例对驱动模块100的控制端的初始化的控制逻辑简单，且仅需要一套输出发光控制信号EM的GIP电路。
综上所述，本申请实施例提供了一种全新的7T1C的全NMOS像素电路，该像素电路不仅有利于简化GIP电路的结构，减小显示面板的边框，还能够实现阈值电压补偿、避免第二电源信号ELVSS的IR drop带来的计算误差、以及降低驱动晶体管DTFT的栅极漏电流。
本申请实施例还提供了一种像素电路的驱动方法，该驱动方法适用于本申请任意实施例所提供的像素电路。参见图8，该驱动方法包括以下步骤：
S110、初始化阶段，第一扫描信号和第二扫描信号有效，以控制第一初始化模块对驱动模块的控制端进行初始化。
S120、数据写入阶段，第二扫描信号和第三扫描信号有效，以控制第一初始化模块配合数据写入模块将数据信号写入驱动模块的控制端。
S130、发光阶段，驱动模块响应数据信号而产生驱动电流，以驱动发光元件发光。
本申请实施例设置在像素电路的驱动过程中，第一扫描信号、第二扫描信号和第三扫描信号的波形形状一致，延迟的时间间隔相同。因此，扫描信号可以采用上下级扫描信号复用，例如，本级扫描信号为第三扫描信号，上一级扫描信号为第二扫描信号，上两级扫描信号为第一扫描信号，那么，第二扫描信号可以复用上一级的扫描信号，第一扫描信号可以复用上两级的扫描信号。这样，本申请实施例的像素电路可以仅由一组GIP电路来输出扫描信号，从而有利于简化GIP电路的结构。
本申请实施例还提供了一种显示面板，该显示面板包括：多个如本申请任意实施例所提供的像素电路，其技术原理类似，这里不再赘述。
参见图9，显示面板包括显示区710和非显示区720。显示面板还包括多个像素电路711和多个扫描驱动电路721。位于显示区710内的多个像素电路711呈阵列排布，位于非显示区720内的多个扫描驱动电路721级联连接。
其中，第n级扫描驱动电路721输出的扫描信号作为第n行像素电路711的第三扫描信号；第n-1级扫描驱动电路721输出的扫描信号作为第n行像素电路711的第二扫描信号；第n-2级扫描驱动电路721输出的扫描信号作为第n行像素电路711的第一扫描信号；其中，n为正整数，且n≥3。
也就是说，第n行像素电路711的第三扫描信号线714与第n级扫描驱动电路721电连接，第n行像素电路711的第二扫描信号线713与第n-1级扫描驱动电路721电连接，第n行像素电路711的第一扫描信号线712与第n-2级扫描驱动电路721电连接。
本申请实施例这样设置，实现了第一扫描信号、第二扫描信号和第三扫描信号共用一套输出扫描信号的GIP电路的效果。
需要说明的是，在第3行以及位于第3行以下的各行像素电路711可以复 用上一行和上两行的扫描驱动电路721，对于第1行和第2行的像素电路711，需要另外设置两级扫描驱动电路721。因此，该显示面板上的扫描驱动电路721的级数比像素电路711的行数多至少多两级。
参见图9，在本申请的一种实施方式中，可选地，显示面板还包括级联连接的发光驱动电路722，发光驱动电路722设置于显示面板的非显示区720。第n级发光驱动电路722输出的发光控制信号作为第n行像素电路711的发光控制信号。也就是说，第n行像素电路711的发光控制信号线715与第n级发光驱动电路722电连接。本申请实施例这样设置，实现了使用一套输出发光控制信号的GIP电路的效果。

Claims (20)

  1. 一种像素电路，包括：
    驱动模块，所述驱动模块设置为响应数据信号而产生驱动电流，以驱动发光元件发光；
    第一初始化模块，所述第一初始化模块由第一扫描信号和第二扫描信号控制；所述第一初始化模块设置为在所述第一扫描信号和所述第二扫描信号有效时，对所述驱动模块的控制端进行初始化；
    数据写入模块，所述数据写入模块由第三扫描信号控制；在所述第二扫描信号和所述第三扫描信号有效时，所述第一初始化模块设置为配合所述数据写入模块将所述数据信号写入所述驱动模块的控制端。
  2. 根据权利要求1所述的像素电路，其中，所述第一初始化模块包括：
    第一晶体管，所述第一晶体管的栅极接入所述第一扫描信号，所述第一晶体管的第一极接入第一初始化信号；
    第二晶体管，所述第二晶体管的栅极接入所述第二扫描信号，所述第二晶体管的第一极与所述第一晶体管的第二极电连接，所述第二晶体管的第二极与所述驱动模块的控制端电连接。
  3. 根据权利要求2所述的像素电路，其中，所述第一晶体管为低温多晶硅晶体管或氧化物晶体管，所述第二晶体管为氧化物晶体管。
  4. 根据权利要求2所述的像素电路，其中，所述第二晶体管的第一极还与所述驱动模块的第一端电连接；
    所述数据写入模块包括第三晶体管，所述第三晶体管的栅极接入所述第三扫描信号，所述第三晶体管的第一极接入所述数据信号，所述第三晶体管的第二极与所述驱动模块的第二端电连接。
  5. 根据权利要求1所述的像素电路，还包括：
    第一发光控制模块，所述第一发光控制模块的控制端接入发光控制信号，所述第一发光控制模块的第一端接入第一电源信号，所述第一发光控制模块的第二端与所述驱动模块的第一端电连接；
    第二发光控制模块，所述第二发光控制模块的控制端接入所述发光控制信号，所述第二发光控制模块的第一端与所述驱动模块的第二端电连接，所述第二发光控制模块的第二端与所述发光元件电连接。
  6. 根据权利要求5所述的像素电路，其中，所述驱动模块包括驱动晶体管，所述驱动晶体管为N型晶体管，所述第一电源信号复用为第一初始化信号。
  7. 根据权利要求1所述的像素电路，还包括：
    存储模块，所述存储模块的第一端与所述驱动模块的控制端电连接，所述存储模块的第二端与所述发光元件电连接；
    第二初始化模块，所述第二初始化模块的控制端接入所述第一扫描信号，所述第二初始化模块第一端接入第二初始化信号，所述第二初始化模块的第二端与所述发光元件电连接。
  8. 根据权利要求1所述的像素电路，其中，所述驱动模块包括控制端、第一端和第二端，所述第一初始化模块包括第一控制端、第二控制端、初始化信号输入端、数据信号输入端和输出端，所述第一初始化模块的第一控制端接入所述第一扫描信号，所述第一初始化模块的第二控制端接入所述第二扫描信号，所述初始化信号输入端接入第一初始化信号，所述数据信号输入端与所述驱动模块的第一端电连接，所述第一初始化模块的输出端与所述驱动模块的控制端电连接；所述数据写入模块包括控制端、输入端和输出端，所述数据写入模块的控制端接入所述第三扫描信号，所述数据写入模块的输入端接入数据信号，所述数据写入模块的输出端与所述驱动模块的第二端电连接。
  9. 根据权利要求1所述的像素电路，其中，所述第一扫描信号、所述第二扫描信号和所述第三扫描信号的波形形状一致，延迟的时间间隔相同，所述像素电路的扫描信号采用上下级扫描信号复用。
  10. 根据权利要求6所述的像素电路，其中，所述驱动晶体管的栅极作为所述驱动模块的控制端，所述驱动晶体管的源极作为所述驱动模块的第二端，所述驱动晶体管的漏极作为所述驱动模块的第一端。
  11. 根据权利要求7所述的像素电路，其中，所述存储模块设置为存储所述驱动模块的控制端的电位，以确保所述驱动模块能够在发光阶段产生稳定的驱动电流。
  12. 根据权利要求7所述的像素电路，其中，所述第二初始化信号为直流复位信号。
  13. 根据权利要求6所述的像素电路，其中，所述第一发光控制模块包括第四晶体管，所述第四晶体管的栅极接入所述发光控制信号，所述第四晶体管的第一极接入所述第一电源信号，所述第四晶体管的第二极与所述驱动晶体管的漏极电连接；所述第二发光控制模块包括第五晶体管，所述第五晶体管的栅极接入所述发光控制信号，所述第五晶体管的第一极与所述驱动晶体管的源极电连接，所述第五晶体管的第二极与所述发光元件电连接。
  14. 根据权利要求7所述的像素电路，其中，所述驱动模块包括驱动晶体管，所述第二初始化模块包括第六晶体管，所述第六晶体管的栅极接入所述第一扫描信号，所述第六晶体管的第一极接入所述第二初始化信号，所述第六晶体管的第二极与所述发光元件的阳极电连接；所述存储模块包括电容，所述电容的第一端与所述驱动晶体管的栅极电连接，所述电容的第二端与所述第六晶体管的第二极电连接。
  15. 根据权利要求5所述的像素电路，其中，所述第一电源信号为直流电源信号。
  16. 一种显示面板，包括：多个如权利要求1-15任一项所述的像素电路。
  17. 根据权利要求16所述的显示面板，其中，多个所述像素电路呈阵列排布；
    所述显示面板还包括级联连接的多个扫描驱动电路；第n级所述扫描驱动电路输出的扫描信号作为第n行所述像素电路的第三扫描信号；
    第n-1级所述扫描驱动电路输出的扫描信号作为所述第n行所述像素电路的第二扫描信号；
    第n-2级所述扫描驱动电路输出的扫描信号作为所述第n行所述像素电路的第一扫描信号；其中，n为正整数，且n≥3。
  18. 根据权利要求16所述的显示面板，其中，所述显示面板包括显示区和非显示区，所述显示面板还包括多个扫描驱动电路；位于所述显示区内的多个所述像素电路呈阵列排布，位于所述非显示区内的多个扫描驱动电路级联连接。
  19. 根据权利要求18所述的显示面板，还包括级联连接的发光驱动电路，所述发光驱动电路设置于所述显示面板的非显示区，第n级发光驱动电路输出的发光控制信号作为第n行像素电路的发光控制信号；其中，n为正整数。
  20. 一种像素电路的驱动方法，所述像素电路包括：驱动模块、第一初始化模块和数据写入模块；所述第一初始化模块由第一扫描信号和第二扫描信号控制，所述数据写入模块由第三扫描信号控制；
    所述驱动方法包括：
    初始化阶段，所述第一扫描信号和所述第二扫描信号有效，以控制所述第一初始化模块对所述驱动模块的控制端进行初始化；
    数据写入阶段，所述第二扫描信号和所述第三扫描信号有效，以控制所述第一初始化模块配合所述数据写入模块将数据信号写入所述驱动模块的控制端；
    发光阶段，所述驱动模块响应所述数据信号而产生驱动电流，以驱动发光元件发光。
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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112509517B (zh) * 2020-11-26 2022-07-12 合肥维信诺科技有限公司 像素电路的驱动方法、显示面板
CN113436583B (zh) * 2021-06-30 2022-10-14 昆山国显光电有限公司 显示面板及其驱动方法
WO2023133753A1 (zh) * 2022-01-13 2023-07-20 京东方科技集团股份有限公司 驱动电路、驱动方法和显示装置
CN114495799A (zh) * 2022-03-04 2022-05-13 昆山国显光电有限公司 像素电路和显示面板
CN114743498A (zh) * 2022-04-02 2022-07-12 合肥维信诺科技有限公司 显示面板及其控制方法、显示装置
KR20230143650A (ko) * 2022-04-05 2023-10-13 삼성디스플레이 주식회사 픽셀 회로 및 이를 포함하는 표시 장치

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104465715A (zh) * 2014-12-30 2015-03-25 上海天马有机发光显示技术有限公司 像素电路、驱动方法、显示面板及显示装置
KR20160129987A (ko) * 2015-04-30 2016-11-10 삼성디스플레이 주식회사 화소 및 이를 이용한 유기전계발광 표시장치
KR20180011434A (ko) * 2016-07-22 2018-02-01 삼성디스플레이 주식회사 표시 장치 및 그 구동 방법
CN107799535A (zh) * 2016-09-02 2018-03-13 三星显示有限公司 显示装置及其制造方法
KR20180032722A (ko) * 2016-09-22 2018-04-02 삼성디스플레이 주식회사 표시 장치
CN108877674A (zh) * 2018-07-27 2018-11-23 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示装置
CN109559686A (zh) * 2019-01-18 2019-04-02 京东方科技集团股份有限公司 像素电路、驱动方法、电致发光显示面板及显示装置
CN111986612A (zh) * 2020-08-31 2020-11-24 云谷（固安）科技有限公司 像素驱动电路、像素驱动电路的驱动方法和显示面板
CN112509517A (zh) * 2020-11-26 2021-03-16 合肥维信诺科技有限公司 像素电路及其驱动方法、显示面板
CN113097247A (zh) * 2019-12-23 2021-07-09 苹果公司 具有像素内补偿和氧化物驱动晶体管的电子显示器

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104658484B (zh) 2015-03-18 2018-01-16 上海和辉光电有限公司 显示装置、像素驱动电路及其驱动方法
CN104809989A (zh) * 2015-05-22 2015-07-29 京东方科技集团股份有限公司 一种像素电路、其驱动方法及相关装置
CN106448560B (zh) * 2016-12-21 2019-03-12 上海天马有机发光显示技术有限公司 有机发光显示面板及其驱动方法、有机发光显示装置
KR102555440B1 (ko) * 2017-11-01 2023-07-12 엘지디스플레이 주식회사 게이트 구동부 및 이를 포함하는 유기 발광 표시 장치
US10490128B1 (en) 2018-06-05 2019-11-26 Apple Inc. Electronic devices having low refresh rate display pixels with reduced sensitivity to oxide transistor threshold voltage
CN111243522A (zh) * 2018-11-29 2020-06-05 上海和辉光电有限公司 一种显示装置及其驱动方法
CN109461407B (zh) * 2018-12-26 2020-10-16 上海天马微电子有限公司 一种有机发光显示面板及有机发光显示装置
CN110033737B (zh) * 2019-05-31 2021-10-26 上海天马有机发光显示技术有限公司 一种扫描电路、显示面板及显示装置
CN110148384B (zh) * 2019-06-28 2021-08-03 上海天马有机发光显示技术有限公司 一种阵列基板、显示面板和像素驱动电路的驱动方法
CN111383596A (zh) * 2020-03-25 2020-07-07 昆山国显光电有限公司 像素电路、显示面板和像素电路的驱动方法
CN111710300B (zh) * 2020-06-30 2021-11-23 厦门天马微电子有限公司 一种显示面板、驱动方法及显示装置
CN111754920A (zh) * 2020-07-17 2020-10-09 武汉华星光电半导体显示技术有限公司 像素驱动电路及其驱动方法、显示面板

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104465715A (zh) * 2014-12-30 2015-03-25 上海天马有机发光显示技术有限公司 像素电路、驱动方法、显示面板及显示装置
KR20160129987A (ko) * 2015-04-30 2016-11-10 삼성디스플레이 주식회사 화소 및 이를 이용한 유기전계발광 표시장치
KR20180011434A (ko) * 2016-07-22 2018-02-01 삼성디스플레이 주식회사 표시 장치 및 그 구동 방법
CN107799535A (zh) * 2016-09-02 2018-03-13 三星显示有限公司 显示装置及其制造方法
KR20180032722A (ko) * 2016-09-22 2018-04-02 삼성디스플레이 주식회사 표시 장치
CN108877674A (zh) * 2018-07-27 2018-11-23 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示装置
CN109559686A (zh) * 2019-01-18 2019-04-02 京东方科技集团股份有限公司 像素电路、驱动方法、电致发光显示面板及显示装置
CN113097247A (zh) * 2019-12-23 2021-07-09 苹果公司 具有像素内补偿和氧化物驱动晶体管的电子显示器
CN111986612A (zh) * 2020-08-31 2020-11-24 云谷（固安）科技有限公司 像素驱动电路、像素驱动电路的驱动方法和显示面板
CN112509517A (zh) * 2020-11-26 2021-03-16 合肥维信诺科技有限公司 像素电路及其驱动方法、显示面板

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