WO2016155183A1 - 像素电路、显示装置及其驱动方法 - Google Patents

像素电路、显示装置及其驱动方法 Download PDF

Info

Publication number
WO2016155183A1
WO2016155183A1 PCT/CN2015/086471 CN2015086471W WO2016155183A1 WO 2016155183 A1 WO2016155183 A1 WO 2016155183A1 CN 2015086471 W CN2015086471 W CN 2015086471W WO 2016155183 A1 WO2016155183 A1 WO 2016155183A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
phase
transistor
gate
driving
Prior art date
Application number
PCT/CN2015/086471
Other languages
English (en)
French (fr)
Inventor
尹静文
王俪蓉
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US15/021,332 priority Critical patent/US20170047007A1/en
Publication of WO2016155183A1 publication Critical patent/WO2016155183A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G09G3/3241—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
    • G09G3/325—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror the data current flowing through the driving transistor during a setting phase, e.g. by using a switch for connecting the driving transistor to the data driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0245—Clearing or presetting the whole screen independently of waveforms, e.g. on power-on
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness
    • G09G2320/0646—Modulation of illumination source brightness and image signal correlated to each other

Definitions

  • the present invention relates to the field of organic light emitting diode display, and in particular to a pixel circuit, a display device including the pixel circuit, and a driving method of the display device.
  • Organic light-emitting displays are one of the hotspots in the field of flat panel display research today. Compared with liquid crystal displays, organic light-emitting diodes have the advantages of low energy consumption, low production cost, self-luminous, wide viewing angle and fast response. At present, in the display fields of mobile phones, PDAs, digital cameras, etc., organic light-emitting diode display panels have been replaced by conventional liquid crystal display panels.
  • the pixel drive circuit design is the core technology content of the active matrix organic light emitting diode display panel (AMOLED), which has important research significance.
  • organic light-emitting diodes are current-driven and require a constant current to control illumination.
  • FIG. 1 Shown in FIG. 1 is a conventional 2T1C pixel circuit including a storage capacitor C, a driving transistor DTFT, and a switching transistor T0.
  • the switching transistor T0 When the scan line scans a row of pixels, the switching transistor T0 is turned on, and the data write signal (here, the data write signal is a voltage) is written to the storage capacitor C.
  • the switching transistor T0 At the end of the line scan, the switching transistor T0 is turned off, and the voltage stored in the storage capacitor C drives the driving transistor DTFT to generate a current to drive the light emitting element OLED, ensuring that the light emitting element continues to emit light in one frame.
  • IOLED is the saturation current of the driving transistor DTFT
  • V GS is the gate-source voltage of the driving transistor DTFT
  • V th is the threshold voltage of the driving transistor DTFT
  • K is a parameter related to the illuminating element.
  • the threshold voltage of the driving transistor of each pixel Due to the process process and device aging, etc., the threshold voltage of the driving transistor of each pixel has unevenness, which causes the current flowing through the organic light emitting diode in each pixel to change, so that the display brightness is uneven, thereby affecting the whole The display of the image.
  • An object of the present invention is to provide a pixel circuit, a pixel circuit including the same
  • the display device and the driving method of the display device provide uniform display brightness.
  • a pixel circuit a light emitting member is provided;
  • a driving transistor comprising: a first pole for receiving the first level signal and a second pole for supplying a driving current to the light emitting member;
  • a storage module configured to store data input during a data writing phase and provide the data to a gate of the driving transistor during an illumination phase, wherein a first end of the memory module is coupled to a gate of the driving transistor And the second end of the memory module is connected to the second pole of the driving transistor.
  • the memory module is also configured to store a threshold voltage of the drive transistor.
  • the memory module is configured to connect the gate of the drive transistor and the second pole when the first level signal is low.
  • the first level signal is low before the data writing phase and is high during the data writing phase and the lighting phase.
  • the data write module comprises a data write transistor.
  • the gate of the data writing transistor is connected to the first gate line, and the first electrode of the data writing thin film transistor can be connected to the data line in a data writing phase, and the data is written into the second pole of the thin film transistor
  • the third ends of the storage modules are connected.
  • the first pole of the data write thin film transistor is connectable to a reference voltage line during a reset phase prior to the start of the data write phase.
  • the storage module includes a first storage capacitor disposed between the third end and the first end of the storage module, and a second storage disposed between the third end of the storage module and a ground level Capacitor and control transistor.
  • the first end of the first storage capacitor is connected to the output end of the data writing module, and the second end of the first storage capacitor is connected to the gate of the driving transistor.
  • the first end of the second storage capacitor is connected to the first end of the first storage capacitor, and the second end of the second storage capacitor is grounded.
  • a gate of the control transistor is connected to the second gate line, a first pole of the control transistor is connected to a first end of the first storage capacitor, a second pole of the control transistor is opposite to the driving transistor The second pole is connected.
  • a display device including a power source and N ⁇ M pixel units divided into N rows and M columns, wherein N and M are integers greater than 1.
  • a pixel circuit as described above is disposed in each of the pixel units.
  • the power source is used to provide a first level signal to the pixel circuit and the power
  • the source is configured to provide a low level signal prior to the data write phase and a high level signal during the data write phase and the illumination phase.
  • the display device comprises N sets of gate lines and M data lines, the N sets of gate lines are in one-to-one correspondence with the N rows of the pixel units, and the M pieces of the data lines are in one-to-one correspondence with the M columns of the pixel units.
  • Each set of gate lines includes a first gate line for providing a control signal to a data write transistor gate of the data write module to provide data from the data line to the memory module.
  • a gate of the data write transistor is coupled to the first gate line, a first pole of the data write transistor is connectable to the data line during a data write phase, and the data is written to a second pole of the transistor
  • the storage modules are connected.
  • the display device further includes a reference voltage line for supplying a reference voltage to the first pole of the data write transistor during a reset phase prior to the start of the data write phase.
  • the reference voltage line is formed integrally with the data line.
  • each set of the gate lines further includes a second gate line for controlling a control transistor connected between the first end and the second end of the memory module.
  • the storage module includes a first storage capacitor, a second storage capacitor, and a control thin film transistor, a first end of the first storage capacitor is connected to an output end of the data write module, and a second end of the first storage capacitor
  • the terminal is connected to the gate of the driving thin film transistor, the first end of the second storage capacitor is connected to the first end of the first storage capacitor, and the second end of the second storage capacitor is grounded, the control a gate of the thin film transistor is connected to the second gate line, a first pole of the control thin film transistor is connected to a first end of the first storage capacitor, and a second pole of the control thin film transistor and the driving film The second pole of the transistor is connected.
  • the driving method includes a plurality of display periods, each of the display periods including a reset and threshold voltage acquisition phase, a data writing phase, and an illumination phase, and the driving method includes:
  • a high level is supplied to the driving transistor by the power source.
  • the display device comprises N sets of gate lines and M data lines, the N sets of the gate lines are in one-to-one correspondence with the N rows of the pixel units, and the M pieces of the data lines and the M columns of the pixel lists Yuan corresponds to one, where N and M are integers greater than one.
  • Each set of gate lines includes a first gate line for providing a control signal to a data write transistor of the data write module to provide data from the data line to the memory module, the driving method comprising:
  • the first pole provides a data voltage
  • a level at which the data write transistor is turned off is provided to the gate of the data write transistor through the first gate line.
  • the driving method comprises a bit and threshold voltage acquisition phase:
  • each set of the gate lines further includes a second gate line for controlling a control transistor disposed between the first end and the second end of the memory module.
  • the memory module includes a first storage capacitor, a second storage capacitor, and a control transistor, and a first end of the first storage capacitor is connected to an output of the data write module, the first storage A second end of the capacitor is coupled to the gate of the drive transistor.
  • the first end of the second storage capacitor is connected to the first end of the first storage capacitor, and the second end of the second storage capacitor is grounded.
  • a gate of the control transistor is connected to the second gate line, a first pole of the control transistor is connected to a first end of the first storage capacitor, a second pole of the control transistor is opposite to the driving film The second pole of the transistor is connected, wherein
  • a level at which the control transistor is turned off is supplied to the second gate line.
  • the influence of the threshold voltage drift of the driving transistor on the current flowing through the illuminating member is eliminated, the brightness uniformity of the display panel including the pixel circuit can be improved, and the display panel is displayed The display defects such as afterimages are not generated, and the display effect of the display panel is optimized.
  • 1 is a circuit diagram of a conventional 2T1C pixel circuit
  • FIG. 2 is a block diagram of a pixel circuit in accordance with one embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a pixel circuit in accordance with one embodiment of the present invention.
  • FIG. 4 is a signal timing diagram of a driving pixel circuit in accordance with one embodiment of the present invention.
  • FIG. 5 is an equivalent circuit diagram of the pixel circuit shown in FIG. 3 in a reset and threshold acquisition phase
  • Figure 6 is an equivalent circuit diagram of the pixel circuit shown in Figure 3 at the data writing stage
  • Fig. 7 is an equivalent circuit diagram of the pixel circuit shown in Fig. 3 in the light emitting phase.
  • T1 driving thin film transistor
  • T2 controlling thin film transistor
  • T3 Data write thin film transistor C1: first storage capacitor
  • FIG. 2 is a block diagram of a pixel circuit in accordance with one embodiment of the present invention.
  • a pixel circuit including a power supply terminal 100, a driving thin film transistor T1, a light emitting member 400, a data writing module 300, and a memory module 200 is provided.
  • the gate of the driving thin film transistor T1 is connected to the first terminal N1 of the memory module 200, the first electrode of the driving thin film transistor T1 is connected to the power terminal 100, and the second electrode of the driving thin film transistor T1 is connected to the anode of the light emitting device 400.
  • the second pole of the driving thin film transistor T1 is also connected to the second end N2 of the memory module 200.
  • the data write module 300 is configured to write the data voltage Vdata to the memory module 200 during the data write phase.
  • the storage module 200 is for storing the data voltage Vdata of the data writing phase, and supplies the data voltage Vdata to the gate of the driving thin film transistor T1 at least in the light emitting phase.
  • the power terminal 100 can receive the low level voltage Vss before the data writing phase, and the memory module 200 can drive the gate of the thin film transistor T1 and the second pole of the driving thin film transistor T1 when the power terminal 100 is the low level voltage Vss Connected to cause the storage capacitor to discharge and store a threshold voltage of the driving thin film transistor.
  • the power supply terminal is at a high level after the data writing phase and the data writing phase to cause the light emitting member 400 to emit light.
  • the light emitting member 400 is typically an organic light emitting diode.
  • the last phase is the illumination phase of the pixel circuit, and the pixel circuit is continuously operated.
  • the memory module 200 maintains the previous work. The state at the end of the cycle.
  • the first end of the memory module 200 should be a high level that causes the driving thin film transistor T1 to be turned on.
  • the power supply terminal 100 provides a low level voltage Vss before the data write phase, and thus, the memory module 200 is driven.
  • the thin film transistor T1 is discharged to the power supply terminal 100.
  • the voltage stored in the memory module 200 is the voltage associated with Vth+Vss, that is, after the end of the discharge, the voltage of the first terminal N1 of the memory module 200 is the voltage associated with Vth+Vss.
  • Vth is the threshold voltage of the driving thin film transistor T1, that is, after the end of the discharging, the threshold voltage of the driving thin film transistor T1 is stored in the memory module 200.
  • the data voltage Vdata for causing the light-emitting member 400 in the pixel circuit to emit light is written into the memory module 200 through the data writing module 300, and the voltage of the power supply terminal 100 is high in the data writing phase.
  • the level voltage Vdd therefore, does not discharge the entire pixel circuit to the power supply terminal 100.
  • the voltage in the memory module 200 is a combination of the data voltage Vdata and the voltage Vth+Vss of the first terminal N1 of the memory module 200.
  • the driving current I 400 generated by the driving thin film transistor T1 satisfies the following formula:
  • K is a parameter related to the illuminating member itself
  • Vgs is the gate-source voltage of the driving thin film transistor
  • Vth is the threshold voltage of the driving thin film transistor.
  • the threshold voltage Vth of the driving thin film transistor T1 is stored in the memory module 200 in the first stage, the threshold voltage of the driving thin film transistor T1 is subtracted from the above formula, and thus the driving overcurrent of the light emitting device 400 becomes The threshold voltage of the driving thin film transistor T1 is independent, thereby eliminating the influence of the drift of the threshold voltage of the driving thin film transistor T1 on the pixel circuit, thereby improving the stability of the light emission of the display device.
  • the memory module 200 can store the threshold voltage of the driving thin film transistor T1 only by changing the input voltage of the power supply terminal 100, thereby eliminating the need to provide a dedicated threshold voltage compensation module in the pixel circuit, thereby The structure of the pixel circuit is simplified, the aperture ratio of a single pixel is improved, and the overall cost of manufacturing the display device is saved.
  • the specific structure of the data writing module 300 is not specifically limited as long as the pixel voltage Vdata that causes the light-emitting member 400 to emit light can be written by the data writing module 300.
  • the data writing module 300 may include a data writing thin film transistor T3. The data is written to the gate of the thin film transistor T3 for connection with the first gate line S1, and the first electrode of the data writing thin film transistor T3 can be connected to the data line Data in the data writing phase, and the data is written to the thin film transistor T3.
  • the two poles are connected to the storage module 200.
  • the first gate line S1 provides an enable signal for the gate of the data writing thin film transistor T3 at least in the data writing phase, so that the data writing thin film transistor T3 is turned on, and therefore, at least in the data writing phase, the data voltage Vdata passes through the data.
  • the write thin film transistor T3 is written in the memory module 200.
  • the data writing module of this preferred embodiment includes only one thin film transistor (i.e., data writing thin film transistor T3), and has a simple structure.
  • the first electrode of the data write thin film transistor T3 may be connected to the reference voltage line in a reset phase before the start of the data write phase. Therefore, the memory module 200 can be supplied with the reference voltage Vref for reset by the data writing thin film transistor T3.
  • the specific structure of the memory module 200 is also not particularly limited as long as the above-described threshold voltage Vth of the driving thin film transistor T1 is stored before the start of the data writing phase, and is in the data writing phase.
  • the data voltage Vdata can be stored.
  • the memory module 200 may include a first storage capacitor C1, a second storage capacitor C2, and a control thin film transistor T2.
  • the first end of the first storage capacitor C1 is connected to the output terminal N3 of the data writing module 200, and the first storage capacitor C1
  • the second end is connected to the gate of the driving thin film transistor T1.
  • the first end of the second storage capacitor C2 is connected to the first end of the first storage capacitor C1, and the second end of the second storage capacitor C2 is grounded.
  • the gate of the control thin film transistor T2 is connected to the second gate line S2, and the first electrode of the control thin film transistor T2 is connected to the first end of the first storage capacitor C1, and the second electrode of the thin film transistor T2 is controlled to drive the thin film transistor T1.
  • the second pole is connected.
  • the first storage capacitor C1 is used to store the threshold voltage Vth of the driving thin film transistor T1
  • the second storage capacitor C2 is used to store the data voltage Vdata.
  • the pixel circuit has a simple 3T2C structure, which can make the display device including the pixel circuit have a high aperture ratio. And lower costs.
  • a display device including a power source and N ⁇ M pixel units divided into N rows ⁇ M columns, wherein N and M are integers greater than 1.
  • a pixel circuit according to an embodiment of the present invention is disposed in each of the pixel units.
  • the power source is used to provide a first level signal to the pixel circuit and the power source is configured to provide a low level signal Vss prior to a data write phase and to provide a high level during a data write phase and an illumination phase Signal Vdd.
  • the memory module 200 of the pixel circuit can store the threshold voltage Vth of the driving thin film transistor T1 before the fast writing phase, thereby The driving current generated in the light emitting phase of the light emitting member is not affected by the threshold voltage Vth of the driving thin film transistor T1.
  • the display device When the display device performs display, it is usually necessary to perform progressive scan on a plurality of rows of pixel units, and then provide gray scale signals (ie, data voltages Vdata) to the columns of pixel units through the data lines.
  • the display device includes N sets of gate lines and M data lines, the N sets of the gate lines are in one-to-one correspondence with the N rows of the pixel units, and the M pieces of the data lines and the M columns of the pixel units are one by one. correspond.
  • each set of gate lines may include a first gate line S1, and therefore, the gate of the data writing thin film transistor T3 is connected to the first gate line S1.
  • the first electrode of the data writing thin film transistor T3 can be connected to the data line Data in the data writing phase, and the second electrode of the data writing thin film transistor T3 is connected to the third terminal N3 of the memory module 200.
  • an opening voltage is supplied to the gate of the data writing thin film transistor T3 through the first gate line S1, so that the data writing thin film transistor T3 is turned on, passing through the data line.
  • the data voltage Vdata provided by Data can be written in the storage module 200.
  • the data writing module 300 can also be used to write a reset voltage to the memory module 200.
  • the display device further includes a reference voltage line Ref, and the data is written into the thin film transistor T3.
  • a pole can be connected to the reference voltage line Ref during a reset phase prior to the start of the data writing phase. It is easily understood that, in the reset phase, the first gate line S1 still supplies an on-voltage to the gate of the data write thin film transistor T3.
  • the reference voltage line Ref is formed integrally with the data line Data.
  • the data voltage Vdata is supplied to the data line, and in the reset phase before the data writing phase, the reference voltage Vref is supplied to the data line Data, and the data line at this time is used as the reference voltage line Ref.
  • each set of gate lines further includes a second gate line S2 connected to the gate of the control thin film transistor T2.
  • each duty cycle of the pixel circuit includes three phases, namely, a reset and threshold voltage acquisition phase P1, a data writing phase P2, and an illumination phase P3.
  • the power supply supplies a low level voltage Vss to the power supply terminal 100, the first gate line S1 is connected to the high level, the second gate line S2 is connected to the high level, and the data line is used as the reference voltage line. , access reference voltage Vref.
  • 5 to 7 are equivalent circuit diagrams of the pixel circuit at different stages of operation, and the gray portion indicates the broken portion.
  • the driving thin film transistor T1, the data writing thin film transistor T3, and the control thin film transistor T2 are both turned on. Therefore, the voltage of the third terminal N3 of the memory module is Vref, and the second storage capacitor C2 will be reset.
  • the voltage of the first terminal N1 of the memory module is discharged to Vth+Vss due to the diode connection of the driving thin film transistor T1, and the threshold voltage Vth of the driving thin film transistor T1 is stored in the first storage capacitor C1. It is in the cut-off state and does not emit light.
  • the power supply supplies a high-level voltage Vdd to the power supply terminal 100, the first gate line S1 is connected to the high level, the second gate line S2 is connected to the low level, and the data line is used as the data line, and the access is performed.
  • Data voltage Vdata is a high-level voltage Vdd to the power supply terminal 100, the first gate line S1 is connected to the high level, the second gate line S2 is connected to the low level, and the data line is used as the data line, and the access is performed.
  • Data voltage Vdata Data voltage Vdata.
  • the control thin film transistor T2 is turned off, the voltage of the third terminal N3 of the memory module is turned into Vdata by the data writing thin film transistor T3, and the data voltage Vdata is stored in the second storage capacitor C2, and is stored at this time.
  • the voltage at the first terminal N1 of the module will also have a corresponding voltage rise, which becomes Vdata+Vth+Vss-Vref.
  • both the first gate line S1 and the second gate line S2 are connected to a low level, and both the control thin film transistor T2 and the data write thin film transistor T3 are in a closed state. Therefore, as shown in FIG. 7, at this time, the first electrode of the driving thin film transistor T1 is connected to the high-level voltage Vdd, and the second-pole voltage of the driving thin film transistor T1 is V 400 +Vss, wherein V 400 is the cross-section of the two ends of the light-emitting member 400. Therefore, the gate-source voltage Vgs of the driving thin film transistor T1 is Vdata+Vth-Vref- V400 . In this way, in the light-emitting phase P3, the driving current I 400 generated by the driving thin film transistor T1 can be expressed as the following equation:
  • the driving current of the light-emitting member 400 is independent of the threshold voltage of the driving thin film transistor T1. Therefore, in the process of display by the display device, the luminance of the light-emitting member 400 does not become uneven due to the drift of the threshold voltage of the driving thin film transistor T1.
  • the driving thin film transistor T1 alternately operates in a state of positive and negative bias. Specifically, in the reset and threshold voltage acquisition phase P1, the first extreme drain of the thin film transistor T1 is driven, and the second extreme source, in the light emitting phase P3, drives the first source and the second drain of the thin film transistor T1. That is to say, in the reset and threshold voltage collecting phase P1 and the light-emitting phase P3, the source and the drain of the driving thin film transistor T1 are exactly opposite, thereby slowing the drift speed of the threshold voltage of the driving thin film transistor T1. Moreover, since the driving current I 400 is independent of the power supply voltage, the display brightness of the light-emitting member 400 is no longer affected by the power line resistance voltage drop (IR Drop).
  • IR Drop power line resistance voltage drop
  • the display device of the present invention may be a television, a computer display, a mobile phone, a navigator or the like.
  • a driving method of a display device which is the above display device provided by the present invention, the driving method comprising a plurality of display periods, each of the display periods including a reset And a threshold voltage acquisition phase, a data writing phase, and an illumination phase, the driving method comprising:
  • a high level is supplied to the power supply terminal during the data writing phase and the light emitting phase.
  • the display device includes N sets of gate lines and M data lines, and the N sets of the gate lines are in one-to-one correspondence with the N rows of the pixel units, and the M lines of the data lines and M
  • the column of pixels corresponds to a one-to-one correspondence, wherein N and M are integers greater than one.
  • Each set of gate lines includes a first gate line
  • the data write module includes a data write thin film transistor
  • a gate of the data write thin film transistor is connected to the first gate line
  • the data write thin film transistor The first pole can be connected to the data line during a data writing phase
  • the second pole of the data write thin film transistor is connected to the memory module.
  • the driving method includes:
  • a level at which the data writing thin film transistor is turned on is provided to the gate of the data writing thin film transistor through the first gate line, and the data line is turned to the The first pole of the thin film transistor provides a data voltage;
  • a gate of the data writing thin film transistor is supplied through the first gate line to a level at which the data writing thin film transistor is turned off, and the data line is passed to the thin film transistor
  • the second pole provides a data voltage.
  • the driving method is performed before the data writing phase:
  • each set of the gate lines further includes a second gate line
  • the memory module includes a first storage capacitor, a second storage capacitor, and a control thin film transistor
  • the first of the first storage capacitor The end is connected to the output end of the data writing module
  • the second end of the first storage capacitor is connected to the gate of the driving thin film transistor
  • the first end of the second storage capacitor is connected to the first storage a first end of the capacitor is connected
  • a second end of the second storage capacitor is grounded
  • a gate of the control thin film transistor is connected to the second gate line
  • a first pole of the thin film transistor is controlled
  • a first end of the storage capacitor is connected
  • a second pole of the control thin film transistor is connected to the second pole of the driving thin film transistor.
  • the stage performed before the data writing phase is a reset and threshold voltage acquisition phase
  • the second gate line is provided to enable the control during the reset and threshold voltage acquisition phase The level at which the thin film transistor is turned on;
  • a level at which the control thin film transistor is turned off is supplied to the second gate line.

Abstract

一种像素电路，包括：发光件（400）；驱动晶体管（T1），所述驱动晶体管（T1）包括用于接收第一电平信号的第一极和用于向发光件（400）提供驱动电流的第二极；存储模块（200），用于存储在数据写入阶段输入的数据并在发光阶段将所述数据提供给所述驱动晶体管（T1）的栅极，其中存储模块（200）的第一端（N1）与驱动晶体管（T1）的栅极相连并且存储模块（200）的第二端（N2）与所述驱动晶体管（T1）的第二极相连。存储模块（200）还被配置为存储驱动晶体管（T1）的阈值电压。包括该像素电路的显示装置在显示时，发光件（400）的亮度不会随驱动晶体管（T1）的阈值漂移而变化。

Description

像素电路、显示装置及其驱动方法 技术领域
本发明涉及有机发光二极管显示领域，具体地，涉及一种像素电路、一种包括所述像素电路的显示装置和该显示装置的驱动方法。
背景技术
有机发光显示器是当今平板显示器研究领域的热点之一。与液晶显示器相比，有机发光二极管具有低能耗、生产成本低、自发光、宽视角及响应速度快等优点。目前，在手机、PDA、数码相机等显示领域，已经开始采用有机发光二极管显示面板取代传统的液晶显示面板。像素驱动电路设计是有源矩阵有机发光二极管显示面板(AMOLED)核心技术内容，具有重要的研究意义。
与液晶面板中利用稳定的电压控制亮度不同，有机发光二极管属于电流驱动，需要稳定的电流来控制发光。
图1中所示的是一种常用的2T1C像素电路，该像素电路包括存储电容C、驱动晶体管DTFT和开关晶体管T0。当扫描线扫描一行像素时，开关晶体管T0导通，数据写入信号(此处，数据写入信号为电压)写入存储电容C。该行扫描结束时，开关晶体管T0关闭，存储在存储电容C中的电压驱动所述驱动晶体管DTFT，使其产生电流驱动发光件OLED，保证发光件在一帧内持续发光。驱动晶体管DTFT的饱和电流为IOLED＝K(VGS-Vth)2。其中，IOLED为驱动晶体管DTFT的饱和电流，VGS为驱动晶体管DTFT的栅源电压，Vth为驱动晶体管DTFT的阈值电压，K是与发光件有关的参数。
由于工艺制程和器件老化等原因，各像素点的驱动晶体管的阈值电压存在不均匀性，这样就导致了流过每个像素点中有机发光二极管的电流发生变化使得显示亮度不均，从而影响整个图像的显示效果。
因此，如何提高显示面板的亮度均匀性成为本领域亟待解决的技术问题。
发明内容
本发明的目的在于提供一种像素电路、一种包括该像素电路的的 显示装置和该显示装置的驱动方法以提供均匀的显示亮度。
为了实现上述目的，作为本发明的一个方面，提供一种像素电路，发光件；
驱动晶体管，包括用于接收第一电平信号的第一极和用于向发光件提供驱动电流的第二极；
存储模块，用于存储在数据写入阶段输入的数据并在发光阶段将所述数据提供给所述驱动晶体管的栅极，其中所述存储模块的第一端与所述驱动晶体管的栅极相连并且所述存储模块的第二端与所述驱动晶体管的第二极相连。所述存储模块还被配置为存储驱动晶体管的阈值电压。
优选地，存储模块被配置当所述第一电平信号为低电平时将所述驱动晶体管的栅极和第二极连接。其中第一电平信号在数据写入阶段之前为低电平并且在数据写入阶段以及发光阶段为高电平。
优选地，数据写入模块包括数据写入晶体管。所述数据写入晶体管的栅极与第一栅线相连，所述数据写入薄膜晶体管的第一极能够在数据写入阶段与数据线相连，所述数据写入薄膜晶体管的第二极与所述存储模块的第三端相连。
优选地，所述数据写入薄膜晶体管的第一极能够在所述数据写入阶段开始之前的复位阶段与参考电压线相连。
优选地，所述存储模块包括置于所述存储模块的第三端和第一端之间的第一存储电容、置于所述存储模块的第三端和地电平之间的第二存储电容和控制晶体管。所述第一存储电容的第一端与所述数据写入模块的输出端相连，所述第一存储电容的第二端与所述驱动晶体管的栅极相连。所述第二存储电容的第一端与所述第一存储电容的第一端相连，所述第二存储电容的第二端接地。所述控制晶体管的栅极用于与第二栅线相连，所述控制晶体管的第一极与所述第一存储电容的第一端相连，所述控制晶体管的第二极与所述驱动晶体管的第二极相连。
作为本发明的另一个方面，提供一种显示装置，所述显示装置包括电源和被划分为排列为N行M列的N×M个像素单元，其中N和M是大于1的整数。每个所述像素单元内都设置有如前文所述的像素电路。所述电源被用于将第一电平信号提供给所述像素电路并且所述电 源被配置为在数据写入阶段之前提供低电平信号并且在数据写入阶段以及发光阶段提供高电平信号。
优选地，所述显示装置包括N组栅线和M条数据线，N组栅线与N行所述像素单元一一对应，M条所述数据线与M列所述像素单元一一对应。每组栅线都包括第一栅线，用于向数据写入模块的数据写入晶体管栅极提供控制信号，以将来自数据线的数据提供给所述存储模块。数据写入晶体管的栅极与所述第一栅线相连，所述数据写入晶体管的第一极能够在数据写入阶段与所述数据线相连，所述数据写入晶体管的第二极与所述存储模块相连。
优选地，所述显示装置还包括参考电压线，用于在所述数据写入阶段开始之前的复位阶段将参考电压提供给所述数据写入晶体管的第一极。
优选地，所述参考电压线与所述数据线形成为一体。
优选地，每组所述栅线还包括第二栅线，用于控制连接于所述存储模块的第一端和第二端之间的控制晶体管。所述存储模块包括第一存储电容、第二存储电容和控制薄膜晶体管，所述第一存储电容的第一端与所述数据写入模块的输出端相连，所述第一存储电容的第二端与所述驱动薄膜晶体管的栅极相连，所述第二存储电容的第一端与所述第一存储电容的第一端相连，所述第二存储电容的第二端接地，所述控制薄膜晶体管的栅极与所述第二栅线相连，所述控制薄膜晶体管的第一极与所述第一存储电容的第一端相连，所述控制薄膜晶体管的第二极与所述驱动薄膜晶体管的第二极相连。
作为本发明的再一个方面，提供一种驱动方法，用于驱动以上所述的显示装置。所述驱动方法包括多个显示周期，每个所述显示周期包括复位和阈值电压采集阶段、数据写入阶段和发光阶段，所述驱动方法包括：
在复位和阈值电压采集阶段，由所述电源向驱动晶体管提供低电平，以使得所述存储模块存储所述驱动晶体管的阈值电压；
在数据写入阶段以及所述发光阶段，由所述电源向驱动晶体管提供高电平。
优选地，所述显示装置包括N组栅线和M条数据线，N组所述栅线与N行所述像素单元一一对应，M条所述数据线与M列所述像素单 元一一对应，其中N和M是大于1的整数。每组栅线包括第一栅线，用于向数据写入模块的数据写入晶体管提供控制信号，以将来自所述数据线的数据提供给所述存储模块，所述驱动方法包括：
在所述数据写入阶段，通过所述第一栅线向所述数据写入晶体管的栅极提供使所述数据写入晶体管导通的电平，并通过所述数据线向所述晶体管的第一极提供数据电压；
在所述发光阶段，通过所述第一栅线向所述数据写入晶体管的栅极提供使所述数据写入晶体管关闭的电平。
优选地，所述驱动方法包括在位和阈值电压采集阶段：
通过所述第一栅线向所述数据写入晶体管的栅极提供使所述数据写入晶体管导通的电平，并通过所述数据线向所述数据写入晶体管的第一极提供参考电压。
优选地，每组所述栅线还包括第二栅线，用于控制置于所述存储模块的第一端和第二端之间的控制晶体管。根据一个实施例，所述存储模块包括第一存储电容、第二存储电容和控制晶体管，所述第一存储电容的第一端与所述数据写入模块的输出端相连，所述第一存储电容的第二端与所述驱动晶体管的栅极相连。所述第二存储电容的第一端与所述第一存储电容的第一端相连，所述第二存储电容的第二端接地。所述控制晶体管的栅极与所述第二栅线相连，所述控制晶体管的第一极与所述第一存储电容的第一端相连，所述控制晶体管的第二极与所述驱动薄膜晶体管的第二极相连，其中，
在复位及阈值电压采集阶段，向所述第二栅线提供使所述控制晶体管导通的电平；
在所述数据写入阶段，向所述第二栅线提供使所述控制晶体管关闭的电平；
在所述发光阶段，向所述第二栅线提供使所述控制晶体管关闭的电平。
在本发明所提供的像素电路中，消除了驱动晶体管的阈值电压漂移对流过发光件的电流的影响，可以提高包括所述像素电路的显示面板的亮度均匀性，并且使得所述显示面板在显示时不会产生残影等显示缺陷，进而优化显示面板的显示效果。
附图说明
附图是用来提供对本发明的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本发明，但并不构成对本发明的限制。在附图中：
图1是现有的2T1C像素电路的电路图；
图2是根据本发明一个实施例的像素电路的模块示意图；
图3是根据本发明一个实施例的像素电路的示意图；
图4是根据本发明一个实施例的驱动像素电路的信号时序图；
图5是图3中所示的像素电路在复位及阈值采集阶段的等效电路图；
图6是图3中所示的像素电路在数据写入阶段的等效电路图；
图7是图3中所示的像素电路在发光阶段的等效电路图。
附图标记说明
T1：驱动薄膜晶体管      T2：控制薄膜晶体管
T3：数据写入薄膜晶体管  C1：第一存储电容
C2：第二存储电容        100：电源端
200：存储模块           300：数据写入模块
400：发光件             S1：第一栅线
S2：第二栅线
具体实施方式
以下结合附图对本发明的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本发明，并不用于限制本发明。
图2是根据本发明一个实施例的像素电路的模块示意图。如图2所示，作为本发明的一个方面，提供一种像素电路，所述像素电路包括电源端100、驱动薄膜晶体管T1、发光件400、数据写入模块300和存储模块200。其中，驱动薄膜晶体管T1的栅极与存储模块200的第一端N1相连，驱动薄膜晶体管T1的第一极与电源端100相连，驱动薄膜晶体管T1的第二极与发光件400的阳极相连，且驱动薄膜晶体管T1的第二极还与存储模块200的第二端N2相连。数据写入模块300用于在数据写入阶段将数据电压Vdata写入存储模块200。该存储模块 200用于存储数据写入阶段的数据电压Vdata，并至少在发光阶段将数据电压Vdata提供给驱动薄膜晶体管T1的栅极。电源端100能够在数据写入阶段之前接收低电平电压Vss，存储模块200能够在电源端100为低电平电压Vss时将驱动薄膜晶体管T1的栅极和该驱动薄膜晶体管T1的第二极连接，以使得所述存储电容放电并存储驱动薄膜晶体管的阈值电压。所述电源端在数据写入阶段以及数据写入阶段以后为高电平，以使得发光件400发光。
本领域技术人员应当理解的是，发光件400通常为有机发光二极管。并且，在显示装置中的像素电路的一个工作周期中，最后一个阶段是像素电路的发光阶段，而像素电路是连续工作的，在一个工作周期开始的时候，存储模块200维持的是上一个工作周期结束时的状态。在上一个工作周期的最后一个阶段，为了使得像素电路在发光阶段发光，存储模块200的第一端应当是使得驱动薄膜晶体管T1导通的高电平。在像素电路的下一个工作周期开始时(即，上文中所述的数据写入阶段之前)，电源端100在数据写入阶段之前提供了低电平电压Vss，因此，存储模块200会通过驱动薄膜晶体管T1向电源端100放电。放电结束后，存储模块200中存储的是电压与Vth+Vss相关联的电压，即，在放电结束后，存储模块200的第一端N1的电压是Vth+Vss相关联的电压。其中，Vth为驱动薄膜晶体管T1的阈值电压，也就是说，在放电结束后，存储模块200中存储了驱动薄膜晶体管T1的阈值电压。
在数据写入阶段，通过数据写入模块300将用于使像素电路中的发光件400发光的数据电压Vdata写入存储模块200中，并且，在数据写入阶段，电源端100的电压为高电平电压Vdd，因此，整个像素电路并不会向电源端100放电。经过数据写入阶段后，存储模块200中的电压为数据电压Vdata和存储模块200的第一端N1的电压Vth+Vss的结合。
在发光阶段，驱动薄膜晶体管T1产生的驱动电流I400满足以下公式：
I400＝0.5K(Vgs-Vth)2
其中，K是与发光件自身有关的参数；
Vgs是驱动薄膜晶体管的栅源电压；
Vth是驱动薄膜晶体管的阈值电压。
由于在第一个阶段，存储模块200中存储了驱动薄膜晶体管T1的阈值电压Vth，在上述公式中又减去了驱动薄膜晶体管T1的阈值电压，因此，发光件400的驱动过电流变得与驱动薄膜晶体管T1的阈值电压无关，从而消除了驱动薄膜晶体管T1的阈值电压的漂移对像素电路造成的影响，进而提高了显示装置发光的稳定性。
在本发明所提供的像素电路中，仅通过改变电源端100的输入电压就可以使得存储模块200存储驱动薄膜晶体管T1的阈值电压，因此，无需在像素电路中设置专门的阈值电压补偿模块，从而简化了像素电路的结构，提高了单个像素的开口率，并节约了制造显示装置的整体成本。
在本发明中，对数据写入模块300的具体结构并不做具体的限定，只要能够通过该数据写入模块300写入使得发光件400发光的像素电压Vdata即可。作为本发明的一种优选实施方式，如图3所示，数据写入模块300可以包括数据写入薄膜晶体管T3。该数据写入薄膜晶体管T3的栅极用于与第一栅线S1相连，数据写入薄膜晶体管T3的第一极能够在数据写入阶段与数据线Data相连，数据写入薄膜晶体管T3的第二极与存储模块200相连。
第一栅线S1至少在数据写入阶段为数据写入薄膜晶体管T3的栅极提供使能信号，使得数据写入薄膜晶体管T3导通，因此，至少在数据写入阶段，数据电压Vdata通过数据写入薄膜晶体管T3被写入存储模块200中。这种优选实施方式的数据写入模块只包括一个薄膜晶体管(即，数据写入薄膜晶体管T3)，结构简单。
为了进一步简化所述像素电路的结构，数据写入薄膜晶体管T3的第一极可以在所述数据写入阶段开始之前的复位阶段与参考电压线相连。因此，通过数据写入薄膜晶体管T3可以为存储模块200提供复位用的参考电压Vref。
在本发明中，对存储模块200的具体结构也没有特殊的限定，只要能够满足上文中所述的，在数据写入阶段开始之前存储驱动薄膜晶体管T1的阈值电压Vth，并在数据写入阶段存储数据电压Vdata即可。作为一种优选的实施方式，如图3所示，存储模块200可以包括第一存储电容C1、第二存储电容C2和控制薄膜晶体管T2。第一存储电容C1的第一端与数据写入模块200的输出端N3相连，第一存储电容C1 的第二端与驱动薄膜晶体管T1的栅极相连。第二存储电容C2的第一端与第一存储电容C1的第一端相连，第二存储电容C2的第二端接地。控制薄膜晶体管T2的栅极用于与第二栅线S2相连，控制薄膜晶体管T2的第一极与第一存储电容C1的第一端相连，控制薄膜晶体管T2的第二极与驱动薄膜晶体管T1的第二极相连。
在具有上述结构的存储模块200中，第一存储电容C1用于存储驱动薄膜晶体管T1的阈值电压Vth，第二存储电容C2用于存储数据电压Vdata。
图3中所示的是本发明所提供的像素电路的优选实施方式，从图中可知，所述像素电路具有简单的3T2C结构，可以使得包括所述像素电路的显示装置具有较高的开口率和较低的成本。
作为本发明的另一个方面，提供一种显示装置，该显示装置包括电源和被划分为排列为N行×M列的N×M个像素单元，其中N和M为大于1的整数。每个所述像素单元内都设置根据本发明的实施例的像素电路。所述电源被用于将第一电平信号提供给所述像素电路并且所述电源被配置为在数据写入阶段之前提供低电平信号Vss并且在数据写入阶段以及发光阶段提供高电平信号Vdd。
如上文中所述，由于所述电源在数据写入阶段之前提供了低电平电压Vss，因此，在速决写入阶段之前，像素电路的存储模块200可以存储驱动薄膜晶体管T1的阈值电压Vth，从而使得发光件的发光阶段产生的驱动电流不受驱动薄膜晶体管T1的阈值电压Vth的影响。
在显示装置进行显示时，通常需要对多行像素单元进行逐行扫描，然后通过数据线对各列像素单元提供灰阶信号(即，数据电压Vdata)。相应地，所述显示装置包括N组栅线和M条数据线，N组所述栅线与N行所述像素单元一一对应，M条所述数据线与M列所述像素单元一一对应。在数据写入模块300包括数据写入薄膜晶体管T3的具体实施方式中，每一组栅线可以包括第一栅线S1，因此，数据写入薄膜晶体管T3的栅极与第一栅线S1相连，数据写入薄膜晶体管T3的第一极能够在数据写入阶段与数据线Data相连，数据写入薄膜晶体管T3的第二极与存储模块200的第三端N3相连。
在数据写入阶段，通过第一栅线S1向数据写入薄膜晶体管T3的栅极提供开启电压，使得数据写入薄膜晶体管T3导通，通过数据线 Data提供的数据电压Vdata可以写入存储模块200中。
为了简化像素电路的结构，也可以利用数据写入模块300向存储模块200写入复位电压，在这种实施方式中，所述显示装置还包括参考电压线Ref，数据写入薄膜晶体管T3的第一极能够在所述数据写入阶段开始之前的复位阶段与参考电压线Ref相连。容易理解的是，在复位阶段，第一栅线S1仍然向数据写入薄膜晶体管T3的栅极提供开启电压。
为了简化显示装置的结构，优选地，如图2中所示，参考电压线Ref与数据线Data形成为一体。在数据写入阶段以及发光阶段，向数据线提供数据电压Vdata，在数据写入阶段之前的复位阶段，向数据线Data提供参考电压Vref，此时的数据线用作参考电压线Ref。
在存储模块200包括第一存储电容C1、第二存储电容C2和控制薄膜晶体管T2的实施方式中，每组栅线还包括第二栅线S2，与控制薄膜晶体管T2的栅极相连。
下面结合图4至图7介绍本图3中所提供的具有3T2C结构的像素电路的工作原理。
如图4所示，所述像素电路的每个工作周期都包括三个阶段，即，复位及阈值电压采集阶段P1、数据写入阶段P2和发光阶段P3。
在复位及阈值电压采集阶段P1，电源向电源端100提供低电平电压Vss，第一栅线S1接入高电平，第二栅线S2接入高电平，数据线用作参考电压线，接入参考电压Vref。
图5至图7是像素电路在不同工作阶段时的等效电路图，灰色的部分表示断开的部分。
如图5中所示，驱动薄膜晶体管T1、数据写入薄膜晶体管T3以及控制薄膜晶体管T2均导通。基此，存储模块的第三端N3的电压为Vref，第二储存电容C2将会被复位。存储模块的第一端N1的电压因驱动薄膜晶体管T1形成了二极体连接而被放电到Vth+Vss，驱动薄膜晶体管T1的阈值电压Vth存储在第一存储电容C1中，此时发光件400处于截止状态，不发光。
在数据写入阶段P2，电源向电源端100提供高电平电压Vdd，第一栅线S1接入高电平，第二栅线S2接入低电平，数据线用作数据线，接入数据电压Vdata。
所以如图6所示，控制薄膜晶体管T2关闭，存储模块的第三端N3的电压因数据写入薄膜晶体管T3导通变为Vdata，数据电压Vdata存储在第二存储电容C2中，此时存储模块的第一端N1的电压也会有相应的电压抬升，变为Vdata+Vth+Vss-Vref。
在发光阶段P3时，第一栅线S1和第二栅线S2都接入低电平，控制薄膜晶体管T2和数据写入薄膜晶体管T3都处于关闭状态。所以如图7所示，此时，驱动薄膜晶体管T1的第一极连接高电平电压Vdd，驱动薄膜晶体管T1的第二极电压为V400+Vss，其中V400为发光件400两端的跨压，因此驱动薄膜晶体管T1的栅源电压Vgs为Vdata+Vth-Vref-V400。如此一来，在发光阶段P3，驱动薄膜晶体管T1所产生的驱动电流I400可以表示为如下方程式：
I400＝0.5K×(Vgs-Vth)2＝0.5K×(Vdata+Vth-Vref-V400-Vth)2
＝0.5K×(Vdata-Vref-Voled)2
由此可知，发光件400的驱动电流与驱动薄膜晶体管T1的阈值电压无关。因此，在显示装置进行显示的过程中，发光件400的亮度不会因驱动薄膜晶体管T1的阈值电压的漂移而变得不均匀。
并且，在整个显示过程中，驱动薄膜晶体管T1交替工作在正负偏置的状态。具体地，在复位及阈值电压采集阶段P1，驱动薄膜晶体管T1的第一极为漏极，第二极为源极，在发光阶段P3，驱动薄膜晶体管T1第一极为源极，第二极为漏极，也就是说在复位及阈值电压采集阶段P1和发光阶段P3，驱动薄膜晶体管T1的源极和漏极正好是相反的，从而减缓了驱动薄膜晶体管T1的阈值电压的漂移速度。并且，由于驱动电流I400与电源电压无关，因此发光件400的显示亮度不再受电源线电阻电压降(I-R Drop)的影响。
本发明的显示装置可以为电视、电脑显示屏、手机、导航仪等。
作为本发明的再一个方面，提供一种显示装置的驱动方法，所述显示装置为本发明所提供的上述显示装置，所述驱动方法包括多个显示周期，每个所述显示周期都包括复位和阈值电压采集阶段、数据写入阶段和发光阶段，所述驱动方法包括：
在复位和阈值电压采集阶段，利用所述电源向所述电源端提供低电平，以使得所述存储模块放电并存储所述驱动薄膜晶体管的阈值电 压；
在数据写入阶段以及所述发光阶段向所述电源端提供高电平。
作为本发明的一种优选实施方式，所述显示装置包括N组栅线和M条数据线，N组所述栅线与N行所述像素单元一一对应，M条所述数据线与M列所述像素单元一一对应，其中，N和M是大于1的整数。每组栅线都包括第一栅线，所述数据写入模块包括数据写入薄膜晶体管，所述数据写入薄膜晶体管的栅极与所述第一栅线相连，所述数据写入薄膜晶体管的第一极能够在数据写入阶段与所述数据线相连，所述数据写入薄膜晶体管的第二极与所述存储模块相连。
当所述显示装置具有上述结构时，所述驱动方法包括：
在所述数据写入阶段，通过所述第一栅线向所述数据写入薄膜晶体管的栅极提供使所述数据写入薄膜晶体管导通的电平，并通过所述数据线向所述薄膜晶体管的第一极提供数据电压；
在所述发光阶段，通过所述第一栅线向所述数据写入薄膜晶体管的栅极提供使所述数据写入薄膜晶体管关闭的电平，并通过所述数据线向所述薄膜晶体管的第二极提供数据电压。
优选地，所述驱动方法包括在所述数据写入阶段之前进行的：
通过所述第一栅线向所述数据写入薄膜晶体管的栅极提供使所述数据写入薄膜晶体管导通的电平，并通过所述数据线向所述薄膜晶体管的第一极提供参考电压。
所述显示装置可以具有以下结构：每组所述栅线还包括第二栅线，所述存储模块包括第一存储电容、第二存储电容和控制薄膜晶体管，所述第一存储电容的第一端与所述数据写入模块的输出端相连，所述第一存储电容的第二端与所述驱动薄膜晶体管的栅极相连，所述第二存储电容的第一端与所述第一存储电容的第一端相连，所述第二存储电容的第二端接地，所述控制薄膜晶体管的栅极与所述第二栅线相连，所述控制薄膜晶体管的第一极与所述第一存储电容的第一端相连，所述控制薄膜晶体管的第二极与所述驱动薄膜晶体管的第二极相连。
当所述显示装置具有上述结构时，在所述数据写入阶段之前进行的阶段为复位及阈值电压采集阶段，在所述复位及阈值电压采集阶段向所述第二栅线提供使所述控制薄膜晶体管导通的电平；
在所述数据写入阶段，向所述第二栅线提供使所述控制薄膜晶体 管关闭的电平；
在所述发光阶段，向所述第二栅线提供使所述控制薄膜晶体管关闭的电平。
上文中已经结合附图详细描述了本发明所提供的驱动方法，这里不再赘述。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (16)

  1. 一种像素电路，所述像素电路包括：
    发光件；
    驱动晶体管，包括用于接收第一电平信号的第一极和用于向发光件提供驱动电流的第二极；
    存储模块，用于存储在数据写入阶段输入的数据并在发光阶段将所述数据提供给所述驱动晶体管的栅极，其中所述存储模块的第一端与所述驱动晶体管的栅极相连并且所述存储模块的第二端与所述驱动晶体管的第二极相连；
    其特征在于，所述存储模块还被配置为存储驱动晶体管的阈值电压。
  2. 根据权利要求1所述的像素电路，其特征在于所述存储模块被配置当所述第一电平信号为低电平时将所述驱动晶体管的栅极和第二极连接。
  3. 根据权利要求2所述的像素电路，其特征在于所述第一电平信号在数据写入阶段之前为低电平并且在数据写入阶段以及发光阶段为高电平。
  4. 根据权利要求1至3中任一项所述的像素电路，还包括数据写入模块，用于在数据写入阶段将数据信号输入到所述存储模块。
  5. 根据权利要求4所述的像素电路，其特征在于，所述数据写入模块包括数据写入晶体管，其中所述数据写入晶体管的栅极与第一栅线相连，所述数据写入晶体管的第一极在数据写入阶段从数据线接收数据，所述数据写入晶体管的第二极与所述存储模块的第三端相连。
  6. 根据权利要求4所述的像素电路，其特征在于，所述数据写入晶体管的第一极在所述数据写入阶段开始之前的复位阶段与参考电压线相连。
  7. 根据权利要求5或6所述的像素电路，其特征在于，所述存储模块包括：
    第一存储电容，置于所述存储模块的第三端和第一端之间，
    第二存储电容，置于所述存储模块的第三端和地电平之间，以及
    控制晶体管，用于控制所述存储模块的第一端和第三端之间的电 路连接，其中该控制晶体管的栅极与第二栅线相连。
  8. 一种显示装置，所述显示装置包括电源和被划分为排列为N行×M列的N×M个像素单元，其中N和M为大于1的整数，每个所述像素单元内都设置有根据权利要求1所述的像素电路，其中，所述电源被用于将第一电平信号提供给所述像素电路并且所述电源被配置为在数据写入阶段之前提供低电平信号并且在数据写入阶段以及发光阶段提供高电平信号。
  9. 根据权利要求8所述的显示装置，其特征在于，所述显示装置包括N组栅线和M条数据线，所述N组栅线与N行所述像素单元一一对应，所述M条数据线与M列所述像素单元一一对应，
    其中每组栅线包括第一栅线，用于向数据写入模块的数据写入晶体管栅极提供控制信号，以将来自数据线的数据提供给所述存储模块。
  10. 根据权利要求9所述的显示装置，其特征在于，所述显示装置还包括参考电压线，用于在所述数据写入阶段开始之前的复位阶段将参考电压提供给所述数据写入晶体管的第一极。
  11. 根据权利要求10所述的显示装置，其特征在于，所述参考电压线与所述数据线形成为一体。
  12. 根据权利要求9至11中任意一项所述的显示装置，其特征在于，每组栅线还包括第二栅线，用于控制连接于所述存储模块的第一端和第二端之间的控制晶体管。
  13. 一种驱动方法，用于驱动权利要求8所述的显示装置，所述驱动方法包括多个显示周期，每个所述显示周期包括复位和阈值电压采集阶段、数据写入阶段和发光阶段，所述驱动方法包括：
    在复位和阈值电压采集阶段，由所述电源向驱动晶体管提供低电平，以使得所述存储模块存储所述驱动晶体管的阈值电压；
    在数据写入阶段以及所述发光阶段，由所述电源向驱动晶体管提供高电平。
  14. 根据权利要求13所述的驱动方法，其特征在于，所述显示装置包括N组栅线和M条数据线，N组所述栅线与N行所述像素单元一一对应，M条所述数据线与M列所述像素单元一一对应，其中N和M是大于1的整数，每组所述栅线都包括第一栅线，用于向数据写入模块的数据写入晶体管提供控制信号，以将来自所述数据线的数据提供 给所述存储模块，所述驱动方法包括：
    在所述数据写入阶段，通过所述第一栅线向所述数据写入晶体管的栅极提供使所述数据写入晶体管导通的电平，并通过所述数据线向所述数据写入晶体管的第一极提供数据电压；
    在所述发光阶段，通过所述第一栅线向所述数据写入晶体管的栅极提供使所述数据写入晶体管关闭的电平。
  15. 根据权利要求14所述的驱动方法，其特征在于，所述驱动方法包括，在复位和阈值电压采集阶段：
    通过所述第一栅线向所述数据写入晶体管的栅极提供使所述数据写入晶体管导通的电平，并通过所述数据线向所述数据写入晶体管的第一极提供参考电压。
  16. 根据权利要求13至15中任意一项所述的驱动方法，其特征在于，每组栅线还包括第二栅线，用于控制置于所述存储模块的第一端和第二端之间的控制晶体管，其中，所述驱动方法包括：
    在复位和阈值电压采集阶段，向所述第二栅线提供使所述控制晶体管导通的电平；
    在所述数据写入阶段，向所述第二栅线提供使所述控制晶体管关闭的电平；
    在所述发光阶段，向所述第二栅线提供使所述控制晶体管关闭的电平。
PCT/CN2015/086471 2015-04-03 2015-08-10 像素电路、显示装置及其驱动方法 WO2016155183A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/021,332 US20170047007A1 (en) 2015-04-03 2015-08-10 Pixel circuit, display device and drive method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510158292.6A CN104715725A (zh) 2015-04-03 2015-04-03 像素电路、显示装置及其驱动方法
CN201510158292.6 2015-04-03

Publications (1)

Publication Number Publication Date
WO2016155183A1 true WO2016155183A1 (zh) 2016-10-06

Family

ID=53414994

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/086471 WO2016155183A1 (zh) 2015-04-03 2015-08-10 像素电路、显示装置及其驱动方法

Country Status (3)

Country Link
US (1) US20170047007A1 (zh)
CN (1) CN104715725A (zh)
WO (1) WO2016155183A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110070825A (zh) * 2018-06-14 2019-07-30 友达光电股份有限公司 像素电路

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104715725A (zh) * 2015-04-03 2015-06-17 京东方科技集团股份有限公司 像素电路、显示装置及其驱动方法
CN105654906B (zh) * 2016-01-26 2018-08-03 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板以及显示装置
CN107358934B (zh) * 2017-09-20 2019-12-17 京东方科技集团股份有限公司 像素电路、存储电路、显示面板以及驱动方法
CN108735145B (zh) * 2018-05-25 2020-08-11 京东方科技集团股份有限公司 像素电路、像素驱动方法和显示装置
CN109346010A (zh) * 2018-12-26 2019-02-15 昆山国显光电有限公司 一种像素电路及其驱动方法、显示装置
CN109637454B (zh) * 2018-12-29 2020-10-13 深圳市华星光电半导体显示技术有限公司 发光二极管像素电路及显示面板
CN111128079B (zh) * 2020-01-02 2021-04-30 武汉天马微电子有限公司 像素电路及其驱动方法、显示面板和显示装置
CN111785210A (zh) * 2020-07-16 2020-10-16 京东方科技集团股份有限公司 像素电路及其驱动方法、显示基板、显示装置
CN111768742B (zh) * 2020-07-17 2021-06-01 武汉华星光电技术有限公司 像素驱动电路及显示面板
CN112309319A (zh) * 2020-11-05 2021-02-02 重庆惠科金渝光电科技有限公司 显示面板驱动电路及显示装置
CN112581908A (zh) * 2020-12-23 2021-03-30 上海天马有机发光显示技术有限公司 像素驱动电路、驱动方法、显示面板与显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1591104A (zh) * 2003-08-29 2005-03-09 精工爱普生株式会社 电子电路、电光学装置、电子装置以及这些的驱动方法
US20100134388A1 (en) * 2008-11-28 2010-06-03 Yuichi Maekawa Display device and pixel circuit
CN102708793A (zh) * 2012-02-27 2012-10-03 京东方科技集团股份有限公司 像素单元驱动电路、像素单元驱动方法以及像素单元
CN103021333A (zh) * 2012-12-11 2013-04-03 昆山工研院新型平板显示技术中心有限公司 有机发光显示器的像素电路及其驱动方法
CN203760050U (zh) * 2014-03-31 2014-08-06 京东方科技集团股份有限公司 一种像素电路和显示装置
CN104715725A (zh) * 2015-04-03 2015-06-17 京东方科技集团股份有限公司 像素电路、显示装置及其驱动方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2443206A1 (en) * 2003-09-23 2005-03-23 Ignis Innovation Inc. Amoled display backplanes - pixel driver circuits, array architecture, and external compensation
US8045697B1 (en) * 2004-06-02 2011-10-25 Nortel Networks Limited Method and apparatus for interfacing a customer with a call center
JP2008107785A (ja) * 2006-09-29 2008-05-08 Seiko Epson Corp 電気光学装置および電子機器
KR100897172B1 (ko) * 2007-10-25 2009-05-14 삼성모바일디스플레이주식회사 화소 및 그를 이용한 유기전계발광표시장치
TWI443629B (zh) * 2008-12-11 2014-07-01 Sony Corp 顯示裝置、其驅動方法及電子設備
JP2010237362A (ja) * 2009-03-31 2010-10-21 Sony Corp パネル及びその制御方法、表示装置、並びに電子機器
KR101082234B1 (ko) * 2010-05-13 2011-11-09 삼성모바일디스플레이주식회사 유기전계발광 표시장치 및 그의 구동방법
TWI433111B (zh) * 2010-12-22 2014-04-01 Univ Nat Taiwan Science Tech 有機發光二極體的畫素單元及具有其之顯示面板
KR101859474B1 (ko) * 2011-09-05 2018-05-23 엘지디스플레이 주식회사 유기 발광 다이오드 표시 장치의 화소 회로
KR20130046006A (ko) * 2011-10-27 2013-05-07 삼성디스플레이 주식회사 화소 회로, 이를 포함하는 유기 발광 표시 장치 및 유기 발광 표시 장치의 구동 방법
CN103137062A (zh) * 2011-11-24 2013-06-05 联胜（中国）科技有限公司 有机发光二极管像素电路及其驱动电路与应用
KR101964769B1 (ko) * 2012-10-26 2019-04-03 삼성디스플레이 주식회사 화소, 이를 포함하는 표시장치 및 그 구동 방법
KR101985501B1 (ko) * 2013-01-08 2019-06-04 삼성디스플레이 주식회사 화소 및 이를 포함하는 표시 장치, 및 그 구동 방법
KR20140111502A (ko) * 2013-03-11 2014-09-19 삼성디스플레이 주식회사 표시장치 및 그 구동 방법
KR101413585B1 (ko) * 2013-05-29 2014-07-04 숭실대학교산학협력단 전압 보상형 화소회로 및 그 구동방법
CN103700342B (zh) * 2013-12-12 2017-03-01 京东方科技集团股份有限公司 Oled像素电路及驱动方法、显示装置
CN103839520B (zh) * 2014-02-28 2017-01-18 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板和显示装置
CN104064139B (zh) * 2014-06-05 2016-06-29 上海天马有机发光显示技术有限公司 一种有机发光二极管像素补偿电路、显示面板和显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1591104A (zh) * 2003-08-29 2005-03-09 精工爱普生株式会社 电子电路、电光学装置、电子装置以及这些的驱动方法
US20100134388A1 (en) * 2008-11-28 2010-06-03 Yuichi Maekawa Display device and pixel circuit
CN102708793A (zh) * 2012-02-27 2012-10-03 京东方科技集团股份有限公司 像素单元驱动电路、像素单元驱动方法以及像素单元
CN103021333A (zh) * 2012-12-11 2013-04-03 昆山工研院新型平板显示技术中心有限公司 有机发光显示器的像素电路及其驱动方法
CN203760050U (zh) * 2014-03-31 2014-08-06 京东方科技集团股份有限公司 一种像素电路和显示装置
CN104715725A (zh) * 2015-04-03 2015-06-17 京东方科技集团股份有限公司 像素电路、显示装置及其驱动方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110070825A (zh) * 2018-06-14 2019-07-30 友达光电股份有限公司 像素电路

Also Published As

Publication number Publication date
US20170047007A1 (en) 2017-02-16
CN104715725A (zh) 2015-06-17

Similar Documents

Publication Publication Date Title
WO2016155183A1 (zh) 像素电路、显示装置及其驱动方法
US9390652B2 (en) Organic light emitting display device and driving method thereof
KR100931469B1 (ko) 화소 및 이를 이용한 유기전계발광 표시장치
WO2018145499A1 (zh) 像素电路、显示面板、显示装置及驱动方法
KR101760090B1 (ko) 화소 및 이를 이용한 유기전계발광 표시장치
US10366655B1 (en) Pixel driver circuit and driving method thereof
US9262966B2 (en) Pixel circuit, display panel and display apparatus
KR100907391B1 (ko) 화소 및 이를 이용한 유기전계발광 표시장치
CN109872692B (zh) 像素电路及其驱动方法、显示装置
WO2016173124A1 (zh) 像素电路、其驱动方法及相关装置
WO2016045283A1 (zh) 像素驱动电路、方法、显示面板和显示装置
JP5357399B2 (ja) 表示装置
WO2021103408A1 (zh) 一种像素内补偿电路及自发光显示装置
US20180108298A1 (en) Pixel driving circuits, pixel driving methods and display devices
US20170352316A1 (en) Pixel circuit and drive method therefor, and active matrix organic light-emitting display
CN104409047A (zh) 像素驱动电路、像素驱动方法和显示装置
WO2016086626A1 (zh) 一种像素驱动电路、像素驱动方法和显示装置
CN108376534B (zh) 像素电路及其驱动方法、显示面板
KR20100059318A (ko) 유기전계발광 표시장치 및 그의 구동방법
KR101142660B1 (ko) 화소 및 이를 이용한 유기전계발광 표시장치
KR20120009669A (ko) 화소 및 이를 이용한 유기전계발광 표시장치
WO2016086627A1 (zh) 一种像素驱动电路、像素驱动方法和显示装置
WO2016187991A1 (zh) 像素电路、驱动方法、有机电致发光显示面板及显示装置
US9424779B2 (en) Organic light emitting display device and driving method thereof
WO2016078282A1 (zh) 像素单元驱动电路和方法、像素单元和显示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 15021332

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15887145

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15887145

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 15887145

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 11/04/2018)

122 Ep: pct application non-entry in european phase

Ref document number: 15887145

Country of ref document: EP

Kind code of ref document: A1