WO2018090620A1 - 像素电路、显示面板、显示设备及驱动方法 - Google Patents

像素电路、显示面板、显示设备及驱动方法 Download PDF

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Publication number
WO2018090620A1
WO2018090620A1 PCT/CN2017/089173 CN2017089173W WO2018090620A1 WO 2018090620 A1 WO2018090620 A1 WO 2018090620A1 CN 2017089173 W CN2017089173 W CN 2017089173W WO 2018090620 A1 WO2018090620 A1 WO 2018090620A1
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Prior art keywords
transistor
control signal
voltage
node
compensation
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PCT/CN2017/089173
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English (en)
French (fr)
Inventor
皇甫鲁江
郑灿
李云飞
刘利宾
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京东方科技集团股份有限公司
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Priority to US15/751,267 priority Critical patent/US11170715B2/en
Publication of WO2018090620A1 publication Critical patent/WO2018090620A1/zh

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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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Definitions

  • Embodiments of the present disclosure relate to a pixel circuit, a display panel, a display device, and a driving method.
  • organic light-emitting diode (OLED) display panels have the characteristics of self-luminous, high contrast, low power consumption, wide viewing angle, fast response, flexible panel, wide temperature range, and simple manufacturing. Prospects.
  • the organic light emitting diode (OLED) display panel can be applied to a device having a display function such as a mobile phone, a display, a notebook computer, a digital camera, an instrument meter, and the like.
  • At least one embodiment of the present disclosure provides a pixel circuit including: a driving transistor, a first transistor, a first capacitor, an organic light emitting diode, and a switching error compensation circuit
  • the driving transistor includes a first power supply line connected to receive the first power voltage a first pole, a gate connected to the first node, and a second pole connected to the second node
  • the first transistor includes a first pole connected to the second node, connected to the first control signal line to receive the first a gate of the control signal and a second pole connected to the first node
  • the first capacitor includes a first end connected to the first node and a second end connected to the third node
  • the organic light emitting diode is configured to Illuminating under operation of the drive transistor during operation
  • a switch error compensation circuit coupled to the first node and/or the second node and configured to compensate for switching errors of the first transistor.
  • the switching error compensation circuit includes a first compensation transistor, and a first pole and/or a second pole of the first compensation transistor are connected to the first node.
  • the gate of the first compensation transistor is connected to the light emission control signal line to receive the light emission control signal.
  • the first compensation transistor and the first transistor are made by the same process.
  • the switching error compensation circuit includes a compensation capacitor, a first end of the compensation capacitor is connected to the first node, and a second end of the compensation capacitor is The second node is connected.
  • the switching error compensation circuit includes a second compensation transistor, a first pole of the second compensation transistor is connected to the second node, and a second pole of the second compensation transistor is connected to a discharge voltage line to receive the discharge voltage, the second compensation The gate of the transistor is coupled to the compensation control signal line to receive the compensation control signal.
  • a pixel circuit provided by an example of the present disclosure further includes: a data writing circuit configured to receive the first control signal and the data signal and write the same to the third node according to the first control signal Data signal.
  • the data write circuit includes a second transistor, and a first electrode of the second transistor is connected to a data signal line to receive the data signal, the second transistor The second pole is connected to the third node, and the gate of the second transistor is connected to the first control signal line to receive the first control signal.
  • a pixel circuit provided by an example of the present disclosure further includes: a first reference voltage writing circuit configured to receive the light emission control signal and the first reference voltage and write the light to the third node according to the light emission control signal The first reference voltage is described.
  • the first reference voltage writing circuit includes a third transistor, and a first pole of the third transistor is connected to a first reference voltage line to receive the first reference a voltage, a second pole of the third transistor is coupled to the third node, and a gate of the third transistor is coupled to the illumination control signal line to receive the illumination control signal.
  • a pixel circuit provided by one example of the present disclosure further includes an illumination control circuit configured to receive an illumination control signal and control the illumination of the organic light emitting diode according to the illumination control signal.
  • the light emission control circuit includes a fourth transistor, a first pole of the fourth transistor is connected to the second node, and a second pole of the fourth transistor is a fourth node is connected, a gate of the fourth transistor is connected to the light emission control signal line to receive the light emission control signal, and the organic light emitting diode comprises a first pole connected to the fourth node and a second power line Connected to receive a second pole of the second supply voltage.
  • a pixel circuit provided by an example of the present disclosure further includes: a second reference voltage writing circuit configured to receive the second control signal and the second reference voltage and write to the third node according to the second control signal Entering the second reference voltage.
  • the second reference voltage writing circuit includes a fifth transistor, and a first pole of the fifth transistor is connected to a second reference voltage line to receive the second reference a voltage, a second pole of the fifth transistor is coupled to the third node, and a gate of the fifth transistor is coupled to the second control signal line to receive the second control signal.
  • a pixel circuit provided by one example of the present disclosure further includes: a discharge circuit configured to receive the second control signal and the discharge voltage and write the discharge voltage to the first node according to the second control signal.
  • the discharge circuit includes a sixth transistor.
  • a first pole of the sixth transistor is connected to the first node, a second pole of the sixth transistor is connected to a discharge voltage line to receive the discharge voltage, and a gate and a second control of the sixth transistor A signal line is connected to receive the second control signal.
  • a pixel circuit provided by an example of the present disclosure further includes a second capacitor, the first end of the second capacitor being connected to the first power line to receive the first power voltage, and the second capacitor The two ends are connected to the first node.
  • At least one embodiment of the present disclosure further provides a display panel including the pixel circuit provided by any embodiment of the present disclosure.
  • At least one embodiment of the present disclosure further provides a display device, including the display panel provided by any embodiment of the present disclosure.
  • At least one embodiment of the present disclosure further provides a driving method of a pixel circuit according to any embodiment of the present disclosure, including a reset phase, a data writing phase, a switching error compensation phase, and an illumination phase, wherein in the reset phase, The first node performs a reset; during the data writing phase, a data signal is written; in the switching error compensation phase, a switching error of the first transistor is compensated; and in the illuminating phase, the organic light is driven The diode emits light.
  • the pixel circuit includes: a driving transistor including a first electrode connected to the first power line to receive the first power voltage, a gate connected to the first node, and a second pole connected to the second node; the first transistor includes a first pole connected to the second node, a gate connected to the first control signal line to receive the first control signal, and a first node connected a second capacitor; a first capacitor comprising a first end coupled to the first node and a second end coupled to the third node; an organic light emitting diode configured to be driven by the drive transistor during operation And a switching error compensation circuit, the switching error compensation circuit includes a first compensation transistor, a first pole and a second pole of the first compensation transistor are connected to the first node, and a gate of the first compensation transistor The pole is connected to the illumination control signal line to receive the illumination control signal, in the data writing phase, the first control signal is an on voltage, and the illumination control signal is off In the switching error compensation phase, the first
  • the pixel circuit includes: a driving transistor including a first electrode connected to the first power supply line to receive the first power supply voltage, a gate connected to the first node, and a second pole connected to the second node; the first transistor includes a first pole connected to the second node, a gate connected to the first control signal line to receive the first control signal, and a first node connected a second capacitor; a first capacitor comprising a first end coupled to the first node and a second end coupled to the third node; an organic light emitting diode configured to be driven by the drive transistor during operation And a switching error compensation circuit, the switching error compensation circuit includes a compensation capacitor, a first end of the compensation capacitor is connected to the first node, and a second end of the compensation capacitor is connected to the second node, In the data writing phase, the first control signal is an on voltage, the illumination control signal is a shutdown voltage; in the switching error compensation phase, the first control signal Off voltage, the emission control signal is
  • the pixel circuit includes: a driving transistor including a first electrode connected to the first power supply line to receive the first power supply voltage, a gate connected to the first node, and a second pole connected to the second node; the first transistor includes a first pole connected to the second node, a gate connected to the first control signal line to receive the first control signal, and a first node connected a second capacitor; a first capacitor comprising a first end coupled to the first node and a second end coupled to the third node; an organic light emitting diode configured to be driven by the drive transistor during operation And a switching error compensation circuit, the switching error compensation circuit includes a second compensation transistor, a first pole of the second compensation transistor is connected to the second node, and a second pole of the second compensation transistor is discharged a voltage line connected to receive a discharge voltage, a gate of the second compensation transistor being coupled to the compensation control signal line to receive a compensation control signal, in the data writing phase,
  • the first control signal including a first electrode connected to the first power supply line to receive
  • the compensation control signal is changed from the turn-off voltage to the turn-on voltage.
  • the pixel circuit, the display panel, the display device, and the driving method provided by the embodiments of the present disclosure may be In order to reduce or eliminate the switching error in the threshold compensation process, the display panel uniformity is improved.
  • FIG. 1 is a schematic diagram of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 2 is a second schematic diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 3 is a third schematic diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 4 is a fourth schematic diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 5 is a fifth schematic diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 6 is a sixth schematic diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 7 is a seventh schematic diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of a display panel according to an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • FIG. 11 is a driving timing diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 12 is a second timing diagram of driving of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 13 is a third timing diagram of driving of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 14 is a schematic diagram showing a state before the threshold voltage charging end short-circuiting switch transistor is turned off;
  • Fig. 15 is a view showing a state in which the threshold voltage sampling end-of-charge switching transistor is turned off.
  • the threshold voltages of the driving transistors in the respective pixel units may differ from each other due to a manufacturing process, and the threshold voltage of the driving transistor is affected by, for example, a temperature change. It also produces drift. The difference in threshold voltages of the respective driving transistors may also cause the display panel to be unevenly displayed. Therefore, it is necessary to compensate the threshold voltage of the driving transistor.
  • the conventional threshold voltage compensation circuit generally includes a shorting switch transistor, the source of the shorting switching transistor is connected to the drain of the driving transistor, and the drain of the shorting switching transistor is connected to the gate of the driving transistor.
  • Drive timing during the compensation process, the shorting drive transistor can short the drive transistor to a diode connection to compensate for the threshold voltage of the drive transistor.
  • this threshold voltage compensation method is not ideal. An important reason is that during the operation of the threshold voltage compensation circuit, when the short-circuiting switch transistor is turned off, the capacitor maintains a potential error, which is called a switching error. Switching induced error).
  • the switching error occurs because there is an equivalent capacitance (including the electrode overlap parasitic capacitance and the channel capacitance) between the gate and the drain of the shorting switching transistor.
  • the storage capacitor When the storage capacitor is charged, the storage capacitor is connected to the gate of the driving transistor.
  • the potential at one end is the threshold voltage of the driving transistor.
  • the charge stored in the equivalent capacitance of the switching transistor is short-circuited due to the bias voltage and the capacitance is injected into the storage capacitor, causing the storage capacitor to remain.
  • the threshold voltage signal produces an error.
  • the threshold voltage unevenness caused by the switching error is still one of the main reasons for restricting the production yield of the organic light-emitting diode display panel, and the switching error needs to be compensated.
  • An equivalent capacitance CTgd0 exists between the gate and the drain of the short-circuiting switching transistor T', including the electrode overlap parasitic capacitance Col and the channel capacitance Cchn.
  • the second and third are the errors generated during the turn-off of the short-circuiting switch transistor T', the second term is the correlation error of the threshold voltage Vth of the driving transistor DT', and the third term is the correlation of the signal Vref-Vdt.
  • Vref is the reference voltage
  • Vdt is the voltage of the data signal
  • VgH is the high level voltage
  • VgL is the low level voltage.
  • ⁇ n is the channel mobility of the driving transistor DT′
  • Cox is the channel capacitance per unit area of the driving transistor DT′
  • W and L are the channel width and the channel length of the driving transistor DT′, respectively
  • V DTgs is the driving transistor DT 'The gate-source voltage (ie, the difference between the gate voltage and the source voltage of the drive transistor DT').
  • Cgs and Cgs0 are the capacitances between the gate and the source of the driving transistor DT' in the on state and the threshold state, respectively, and the difference between the threshold voltage Vth and the related error is not prominent.
  • Cgd and Cgd0 are the capacitances between the gate and the drain of the driving transistor DT' in the on and threshold states, respectively, and their characteristics are similar to those between the gate and source.
  • Cgd0 is short-circuited by the short-circuiting switch transistor T' in the threshold state, no charge is stored, and after the short-circuiting switch transistor T' is turned off, Cgd may absorb more charge, thereby having an influence on the threshold voltage Vth-related error.
  • the threshold voltage Vth correlation coefficient of the error is mainly determined by the channel capacitance Cchn of the short-circuiting switching transistor T' and the gate-to-drain capacitance Cgd of the driving transistor DT', and the physical process is short during the turn-off process.
  • the conductive channel of the switching transistor T' disappears, and the corresponding equivalent capacitance is also close to 0.
  • the charge is originally injected into the storage capacitor C1', and some of the driven transistor DT' is a capacitor such as the gate and drain capacitance Cgd. absorb.
  • the pixel circuit, the display panel, the display device, and the driving method provided by the embodiments of the present disclosure may be In order to reduce or eliminate the switching error in the threshold compensation process, the display panel uniformity is improved.
  • At least one embodiment of the present disclosure provides a pixel circuit including: a driving transistor, a first transistor, a first capacitor, an organic light emitting diode, and a switching error compensation circuit.
  • the driving transistor includes a first electrode connected to the first power line to receive the first power voltage, a gate connected to the first node, and a second pole connected to the second node;
  • the first transistor includes a second node connected to the second node a pole connected to the first control signal line to receive the first control signal and a second pole connected to the first node;
  • the first capacitor includes a first end connected to the first node and connected to the third node a second end;
  • the organic light emitting diode is configured to emit light under operation of the driving transistor during operation;
  • the switching error compensation circuit is coupled to the first node and/or the second node and configured to compensate for a switching error of the first transistor.
  • the embodiment provides a pixel circuit 100.
  • the pixel circuit 100 includes a driving transistor DT, a first transistor T1, a first capacitor C1, an organic light emitting diode OLED, and a switching error compensation circuit 110.
  • the driving transistor DT includes a first electrode connected to the first power supply line to receive the first power supply voltage Vdd, a gate connected to the first node N1, and a second electrode connected to the second node N2.
  • the first transistor T1 includes a first pole connected to the second node N2, a gate connected to the first control signal line to receive the first control signal Sn, and a second pole connected to the first node N1.
  • the first capacitor C1 includes a first end connected to the first node N1 and a second end connected to the third node N3.
  • the organic light emitting diode OLED is configured to emit light under driving of the driving transistor DT during operation.
  • the switching error compensation circuit 110 is coupled to the first node N1 and configured to compensate for the switching error of the first transistor T1.
  • the transistors used in the embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other switching devices having the same characteristics.
  • the source and drain of the transistor used here may be structurally symmetrical, so that the source and the drain may be structurally indistinguishable.
  • the transistors in order to distinguish the two poles of the transistor except the gate, one of the first poles and the other second pole are directly described, so the source and the total of all or part of the transistors in the embodiment of the present disclosure
  • the drains are interchangeable as needed.
  • the transistors can be divided into N-type and P-type transistors according to the characteristics of the transistors. Embodiments of the present disclosure are described by taking a P-type transistor as an example.
  • the pixel circuit 100 provided by the embodiment of the present disclosure further includes data writing power.
  • the circuit 120, the data writing circuit 120 is configured to receive the first control signal Sn and the data signal Vdt and write the data signal Vdt to the third node N3 according to the first control signal Sn.
  • the pixel circuit 100 provided by the embodiment of the present disclosure further includes a first reference voltage writing circuit 130 configured to receive the light emission control signal EM and the first reference voltage Vref1 . And writing the first reference voltage Vref1 to the third node N3 according to the light emission control signal EM.
  • the pixel circuit 100 provided by the embodiment of the present disclosure further includes an illumination control circuit 140 configured to receive the illumination control signal EM and control the illumination of the organic light emitting diode OLED according to the illumination control signal EM.
  • the embodiments of the present disclosure include, but are not limited to, the case where the pixel circuit 100 includes the data writing circuit 120, the first reference voltage writing circuit 130, and the lighting control circuit 140, and may be other situations, for example, The data writing circuit 120 and the first reference voltage writing circuit 130 are not included, and the data signal line is directly connected to the third node N3, and the writing of the data signal and the first reference voltage is realized by setting the timing and voltage value of the data signal Vdt.
  • the pixel circuit 100 includes the data writing circuit 120, the first reference voltage writing circuit 130, and the lighting control circuit 140, and may be other situations, for example, The data writing circuit 120 and the first reference voltage writing circuit 130 are not included, and the data signal line is directly connected to the third node N3, and the writing of the data signal and the first reference voltage is realized by setting the timing and voltage value of the data signal Vdt.
  • the switch error compensation circuit 110 includes a first compensation transistor TC1, and the first and second poles of the first compensation transistor TC1 are both The first node N1 is connected, and the gate of the first compensation transistor TC1 is connected to the light emission control signal line to receive the light emission control signal EM.
  • the embodiment of the present disclosure includes but is not limited to the case where the first pole and the second pole of the first compensation transistor TC1 are connected to the first node N1, and may also be the first pole of the first compensation transistor TC1.
  • the first node N1 is connected, the second pole is suspended, or the second pole of the first compensation transistor TC1 is connected to the first node N1, and the first pole is suspended.
  • the first compensation transistor TC1 and the first transistor T1 are made by the same process.
  • the first compensation transistor TC1 also has an equivalent capacitance, the charge released by the equivalent capacitance between the gate and the drain of the first transistor T1 may be partially or partially compensated while the first transistor T1 is turned off.
  • the equivalent capacitance of the transistor TC1 is absorbed, thereby achieving the purpose of keeping the threshold voltage in the first capacitor C1 accurate and stable.
  • the first compensation transistor TC1 and the first transistor T1 are made by the same process, the characteristics of the first compensation transistor TC1 and the first transistor T1 are the same or similar, the equivalent capacitance of the first compensation transistor TC1 and the first transistor T1 The equivalent capacitance is the same or close, and the equivalent capacitance of the first compensation transistor TC1 can accurately absorb the equivalent capacitance of the first transistor T1. The charge is obtained to obtain a better compensation effect.
  • the equivalent capacitance of the first compensation transistor TC1 includes Ctcgs and Ctcgd, Ctcgs is the equivalent capacitance between the gate and the source of the first compensation transistor TC1, and Ctcgd is between the gate and the drain of the first compensation transistor TC1.
  • Equivalent capacitance whether the first pole and the second pole of the first compensation transistor TC1 are simultaneously connected to the first node N1, since there is no other bypass, the Ctcgd and Ctcgs of the first compensation transistor are all involved in the absorption or discharge of the charge
  • the equivalent capacitance of the first transistor T1 includes only the equivalent capacitance C1gd between the gate and the drain of the first transistor T1.
  • the equivalent capacitance C1gs between the gate and the source and the equivalent capacitance C1gd between the gate and the drain are constant, but the first transistor T1 is turned off according to the circuit bias.
  • the condition is to distribute the charge between C1gd and C1gs, resulting in a change in the equivalent capacitance of C1gd and C1gs.
  • C1gd of the first transistor T1 will be greater than C1gs.
  • the data writing circuit 120 includes a second transistor T2, and the first electrode of the second transistor T2 is connected to the data signal line to receive data.
  • the signal Vdt, the second pole of the second transistor T2 is connected to the third node N3, and the gate of the second transistor T2 is connected to the first control signal line to receive the first control signal Sn.
  • the first reference voltage writing circuit 130 includes a third transistor T3, the first pole of the third transistor T3 and the first reference voltage.
  • the line is connected to receive the first reference voltage Vref1
  • the second pole of the third transistor T3 is connected to the third node N3
  • the gate of the third transistor T3 is connected to the light emission control signal line to receive the light emission control signal EM.
  • the illumination control circuit 140 includes a fourth transistor T4, and the first pole of the fourth transistor T4 is connected to the second node N2, and the fourth The second pole of the transistor T4 is connected to the fourth node N4, and the gate of the fourth transistor T4 is connected to the light emission control signal line to receive the light emission control signal EM, and the organic light emitting diode OLED includes a first pole connected to the fourth node N4 and The second power line is connected to receive the second pole of the second power voltage Vss.
  • the first power supply voltage Vdd is a high level voltage (for example, 8 V)
  • the second power supply voltage Vss is a low level voltage (for example, 0 V).
  • the first of the organic light emitting diodes OLED is extremely anode, and the second is extremely cathode.
  • FIG. 2 is only one implementation of the pixel circuit shown in FIG. 1. Ways, embodiments of the present disclosure include, but are not limited to, the embodiment shown in FIG. 2.
  • the pixel circuit 100 provided by the embodiment of the present disclosure further includes a second reference voltage writing circuit 150, and the second reference voltage writing circuit 150 is configured.
  • the second reference voltage Vref2 is written to the third node N3 according to the second control signal Sn-1 and the second reference voltage Vref2 and according to the second control signal Sn-1.
  • the second reference voltage writing circuit 150 includes a fifth transistor T5, and the first electrode of the fifth transistor T5 is connected to the second reference voltage line.
  • the second pole of the fifth transistor T5 is connected to the third node N3, and the gate of the fifth transistor T5 is connected to the second control signal line to receive the second control signal Sn-1.
  • the second control signal Sn-1 may be one line scan time ahead of the first control signal Sn, that is, the second control signal Sn-1 of the pixel circuit of the row may be controlled by the first control of the adjacent previous row of pixel circuits.
  • the signal Sn is implemented, which simplifies the design of the circuit and facilitates the wiring of the circuit.
  • the first reference voltage Vref1 and the second reference voltage Vref2 are stable reference voltages, which may be the same voltage or different voltages.
  • adding the second reference voltage writing circuit 150 based on the first reference voltage writing circuit 130 can improve the display quality and prevent the residual signal of the adjacent previous frame from affecting the signal compensation of the current frame.
  • the pixel circuit 100 provided by the embodiment of the present disclosure further includes a discharge circuit 160 configured to receive the second control signal Sn-1 and the discharge voltage Vini and to first according to the second control signal Sn-1.
  • the node N1 writes the discharge voltage Vini.
  • the discharge circuit 160 includes a sixth transistor T6, the first pole of the sixth transistor T6 is connected to the first node N1, and the sixth transistor T6 is The diode is connected to the discharge voltage line to receive the discharge voltage Vini, and the gate of the sixth transistor T6 is connected to the second control signal line to receive the second control signal Sn-1.
  • the discharge voltage Vini is a low level voltage (for example, 0 V).
  • the first reference voltage Vref1, the second reference voltage Vref2, and the discharge voltage Vini may be the same voltage. This arrangement can simplify circuit wiring and improve the resolution of the display panel.
  • the pixel circuit 100 provided by the embodiment of the present disclosure further includes a second capacitor C2, and the first end of the second capacitor C2 is connected to the first power line to receive the first power source.
  • the voltage Vdd, the second end of the second capacitor C2 is connected to the first node N1.
  • setting the second capacitor C2 can improve the stability of the pixel circuit 100.
  • the embodiment provides a pixel circuit 100.
  • the pixel circuit 100 includes a driving transistor DT, a first transistor T1, a first capacitor C1, an organic light emitting diode OLED, and a switching error compensation circuit 110.
  • the driving transistor DT includes a first electrode connected to the first power supply line to receive the first power supply voltage Vdd, a gate connected to the first node N1, and a second electrode connected to the second node N2.
  • the first transistor T1 includes a first pole connected to the second node N2, a gate connected to the first control signal line to receive the first control signal Sn, and a second pole connected to the first node N1.
  • the first capacitor C1 includes a first end connected to the first node N1 and a second end connected to the third node N3.
  • the organic light emitting diode OLED is configured to emit light under driving of the driving transistor DT during operation.
  • the switching error compensation circuit 110 is coupled to the first node N1 and the second node N2 and configured to compensate for the switching error of the first transistor T1.
  • the pixel circuit 100 provided by the embodiment of the present disclosure further includes a data writing circuit 120 configured to receive the first control signal Sn and the data signal Vdt and according to the first control signal Sn.
  • the data signal Vdt is written to the third node N3.
  • the pixel circuit 100 provided by the embodiment of the present disclosure further includes a first reference voltage writing circuit 130 configured to receive the lighting control signal EM and the first reference voltage Vref1. And writing the first reference voltage Vref1 to the third node N3 according to the light emission control signal EM.
  • the pixel circuit 100 provided by the embodiment of the present disclosure further includes an illumination control circuit 140 configured to receive the illumination control signal EM and control the illumination of the organic light emitting diode OLED according to the illumination control signal EM.
  • the embodiments of the present disclosure include, but are not limited to, the case where the pixel circuit 100 includes the data writing circuit 120, the first reference voltage writing circuit 130, and the lighting control circuit 140, and may be other situations.
  • the switch error compensation circuit 110 includes a compensation capacitor CC, and the first end of the compensation capacitor CC is connected to the first node N1, and the compensation capacitor CC The second end is connected to the second node N2.
  • the compensation capacitor CC due to the addition of the compensation capacitor CC, while the first transistor T1 is turned off, the charge released by the equivalent capacitance between the gate and the drain of the first transistor T1 can be absorbed by the compensation capacitor CC in whole or in part, thereby achieving the retention.
  • the threshold voltage in a capacitor C1 is accurate and stable.
  • the capacitance value of the compensation capacitor CC can be obtained, for example, by a test method.
  • the write circuit 120 includes a second transistor T2, the first electrode of which is connected to the data signal line to receive the data signal Vdt, the second electrode of the second transistor T2 is connected to the third node N3, and the gate of the second transistor T2 The pole is connected to the first control signal line to receive the first control signal Sn.
  • the first reference voltage writing circuit 130 includes a third transistor T3, and the first electrode of the third transistor T3 and the first reference voltage The line is connected to receive the first reference voltage Vref1, the second pole of the third transistor T3 is connected to the third node N3, and the gate of the third transistor T3 is connected to the light emission control signal line to receive the light emission control signal EM.
  • the illumination control circuit 140 includes a fourth transistor T4, and the first pole of the fourth transistor T4 is connected to the second node N2, and the fourth The second pole of the transistor T4 is connected to the fourth node N4, and the gate of the fourth transistor T4 is connected to the light emission control signal line to receive the light emission control signal EM, and the organic light emitting diode OLED includes a first pole connected to the fourth node N4 and The second power line is connected to receive the second pole of the second power voltage Vss.
  • the pixel circuit shown in FIG. 6 is only one embodiment of the pixel circuit shown in FIG. 5, and embodiments of the present disclosure include, but are not limited to, the embodiment shown in FIG. 6.
  • the pixel circuit may further include a second reference voltage writing circuit, a discharging circuit, a second capacitor, and the like (not shown), and the implementation manner thereof is similar to that of the first embodiment, and details are not described herein again. .
  • the embodiment provides a pixel circuit 100.
  • the pixel circuit 100 includes a driving transistor DT, a first transistor T1, a first capacitor C1, an organic light emitting diode OLED, and a switching error compensation circuit 110.
  • the driving transistor DT includes a first electrode connected to the first power supply line to receive the first power supply voltage Vdd, a gate connected to the first node N1, and a second electrode connected to the second node N2.
  • the first transistor T1 includes a first pole connected to the second node N2, a gate connected to the first control signal line to receive the first control signal Sn, and a second pole connected to the first node N1.
  • the first capacitor C1 includes a first end connected to the first node N1 and a second end connected to the third node N3.
  • the organic light emitting diode OLED is configured to emit light under driving of the driving transistor DT during operation.
  • the switch error compensation circuit 110 is connected to the second node N2 and configured to compensate for the opening of the first transistor T1. Off error.
  • the pixel circuit 100 provided by the embodiment of the present disclosure further includes a data writing circuit 120 configured to receive the first control signal Sn and the data signal Vdt and according to the first control signal Sn The data signal Vdt is written to the third node N3.
  • the pixel circuit 100 provided by the embodiment of the present disclosure further includes a first reference voltage writing circuit 130 configured to receive the lighting control signal EM and the first reference voltage Vref1 . And writing the first reference voltage Vref1 to the third node N3 according to the light emission control signal EM.
  • the pixel circuit 100 provided by the embodiment of the present disclosure further includes an illumination control circuit 140 configured to receive the illumination control signal EM and control the illumination of the organic light emitting diode OLED according to the illumination control signal EM.
  • the embodiments of the present disclosure include, but are not limited to, the case where the pixel circuit 100 includes the data writing circuit 120, the first reference voltage writing circuit 130, and the lighting control circuit 140, and may be other situations.
  • the switch error compensation circuit 110 includes a second compensation transistor TC2, and the first pole of the second compensation transistor TC2 is connected to the second node N2.
  • the second pole of the second compensation transistor TC2 is connected to the discharge voltage line to receive the discharge voltage Vini, and the gate of the second compensation transistor TC2 is connected to the compensation control signal line to receive the compensation control signal NSn.
  • the second compensation transistor TC2 is turned on by the timing control, and the potential of the first electrode (eg, the source) of the first transistor T1 is pulled down to the discharge voltage Vini (for example, 0V). ), the first transistor T1 channel bias state is instantaneously turned over (source and drain are interchanged). Thus, most of the channel charge will be driven to the source of the normal operation of the first transistor T1 during the channel disappearance, avoiding affecting the threshold voltage held in the first capacitor C1.
  • the data writing circuit 120 includes a second transistor T2, and the first electrode of the second transistor T2 is connected to the data signal line to receive data.
  • the signal Vdt, the second pole of the second transistor T2 is connected to the third node N3, and the gate of the second transistor T2 is connected to the first control signal line to receive the first control signal Sn.
  • the first reference voltage writing circuit 130 includes a third transistor T3, the first pole of the third transistor T3 and the first reference voltage.
  • the line is connected to receive the first reference voltage Vref1, and the second and third nodes of the third transistor T3 N3 is connected, and the gate of the third transistor T3 is connected to the light emission control signal line to receive the light emission control signal EM.
  • the illumination control circuit 140 includes a fourth transistor T4, and the first pole of the fourth transistor T4 is connected to the second node N2, and the fourth The second pole of the transistor T4 is connected to the fourth node N4, and the gate of the fourth transistor T4 is connected to the light emission control signal line to receive the light emission control signal EM, and the organic light emitting diode OLED includes a first pole connected to the fourth node N4 and The second power line is connected to receive the second pole of the second power voltage Vss.
  • the pixel circuit shown in FIG. 8 is only one embodiment of the pixel circuit shown in FIG. 7. Embodiments of the present disclosure include, but are not limited to, the embodiment shown in FIG.
  • the pixel circuit may further include a second reference voltage writing circuit, a discharging circuit, a second capacitor, and the like (not shown), and the implementation manner thereof is similar to that of the first embodiment, and details are not described herein again. .
  • the implementation of the switching error compensation circuit 110 in the first embodiment, the second embodiment, and the third embodiment is different, but the compensation of the switching error of the first transistor T1 can be realized.
  • embodiments of the switch error compensation circuit 110 of these embodiments can be used in combination without conflict.
  • the present embodiment provides a display panel 10, as shown in FIG. 9, the display panel 10 includes the pixel circuit 100 provided by any embodiment of the present disclosure.
  • the display panel 10 provided in this embodiment further includes a data driver 11, a scan driver 12, and a controller 13.
  • the data driver 11 is configured to provide a data signal Vdt to the pixel circuit 100;
  • the scan driver 12 is configured to provide the pixel circuit 100 with an illumination control signal EM, a first control signal Sn, a second control signal Sn-1, and a compensation control signal NSn;
  • the controller 13 is configured to provide control instructions to the data driver 11 and the scan driver 12 to cause the data driver 11 and the scan driver 12 to cooperate.
  • the present embodiment provides a display device 1 .
  • the display device 1 includes the display panel 10 provided by any embodiment of the present disclosure.
  • the display device 1 provided by the embodiment of the present disclosure may include any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the embodiment provides a driving method of the pixel circuit 100 according to any embodiment of the present disclosure.
  • the driving method includes a reset phase t1, a data writing phase t2, a switching error compensation phase t3, and an illumination phase t4.
  • the reset phase t1 the first node N1 is reset; in the data writing phase t2, the data signal Vdt is written; in the switching error compensation phase t3, the switching error of the first transistor T1 is compensated; in the lighting phase t4, the organic light is driven
  • the diode OLED emits light.
  • the pixel circuit 100 includes a driving transistor DT, a first transistor T1, a first capacitor C1, and an organic light emitting diode OLED.
  • the driving transistor DT includes a first electrode connected to the first power supply line to receive the first power supply voltage Vdd, a gate connected to the first node N1, and a second electrode connected to the second node N2.
  • the first transistor T1 includes a first pole connected to the second node N2, a gate connected to the first control signal line to receive the first control signal Sn, and a second pole connected to the first node N1.
  • the first capacitor C1 includes a first end connected to the first node N1 and a second end connected to the third node N3.
  • the organic light emitting diode OLED is configured to emit light under driving of the driving transistor DT during operation.
  • the switching error compensation circuit 110 includes a first compensation transistor TC1.
  • the first and second poles of the first compensation transistor TC1 are connected to the first node N1, and the gate of the first compensation transistor TC1 is connected to the illumination control signal line to receive the illumination control. Signal EM.
  • the data writing circuit 120 includes a second transistor T2, the first electrode of which is connected to the data signal line to receive the data signal Vdt, the second electrode of the second transistor T2 is connected to the third node N3, and the second transistor T2 The gate is coupled to the first control signal line to receive the first control signal Sn.
  • the first reference voltage writing circuit 130 includes a third transistor T3, the first pole of the third transistor T3 is connected to the first reference voltage line to receive the first reference voltage Vref1, and the second pole and the third node N3 of the third transistor T3 Connected, the gate of the third transistor T3 is connected to the light emission control signal line to receive the light emission control signal EM.
  • the illumination control circuit 140 includes a fourth transistor T4, the first pole of the fourth transistor T4 is connected to the second node N2, the second pole of the fourth transistor T4 is connected to the fourth node N4, and the gate and illumination control of the fourth transistor T4
  • the signal line is connected to receive the light emission control signal EM
  • the organic light emitting diode OLED includes a first pole connected to the fourth node N4 and a second pole connected to the second power line to receive the second power voltage Vss.
  • the driving timing of the pixel circuit 100 is as shown in FIG.
  • the first control signal Sn is an on voltage, and the illumination control signal EM is an on voltage
  • the first control signal Sn is an on voltage
  • the illumination control signal EM To turn off the voltage
  • the first control signal Sn is The voltage is turned off, and the light emission control signal EM is a turn-off voltage
  • the first control signal Sn is a turn-off voltage
  • the light emission control signal EM is an turn-on voltage
  • the turn-on voltage in the embodiment of the present disclosure refers to a voltage that can turn on the first pole and the second pole of the corresponding transistor
  • the turn-off voltage refers to disconnecting the first pole and the second pole of the corresponding transistor.
  • Voltage When the transistor is a P-type transistor, the turn-on voltage is a low voltage (for example, 0V), the turn-off voltage is a high voltage (for example, 5V); when the transistor is an N-type transistor, the turn-on voltage is a high voltage (for example, 5V), and is turned off.
  • the voltage is a low voltage (eg, 0V).
  • the driving timing diagrams shown in FIGS. 11 to 13 are all described by taking a P-type transistor as an example, that is, the turn-on voltage is a low voltage (for example, 0 V), and the turn-off voltage is a high voltage (for example, 5 V).
  • the operation of the pixel circuit 100 will be described below by taking the pixel circuit 100 shown in FIG. 2 and the driving timing shown in FIG. 11 as an example.
  • the first control signal Sn is a low level voltage
  • the light emission control signal EM is a low level voltage
  • the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are both turned on (ie, the source and the drain are turned on), and the third transistor T3 writes the first reference voltage Vref1 into the third node, and the third The voltage of the node N3 is the first reference voltage Vref1, and the second power voltage Vss is written to the first node N1 through the fourth transistor T4 and the first transistor T1, and the voltage of the first node N1 is the second power voltage Vss, that is, the pixel circuit 100 was reset.
  • the first control signal Sn is a low level voltage
  • the light emission control signal EM is a high level voltage.
  • the first transistor T1 and the second transistor T2 are turned on, the third transistor T3 and the fourth transistor T4 are turned off (ie, the source and the drain are not turned on), and the second transistor T2 writes the data signal Vdt to the third node N3,
  • the voltage of the three nodes is Vdt
  • the voltage of the first node N1 is Vdd+Vth
  • Vth is the threshold voltage of the driving transistor DT
  • the voltage difference across the first capacitor C1 is Vdd+Vth-Vdt.
  • the first control signal Sn is a high level voltage
  • the light emission control signal EM is a high level voltage.
  • the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are turned off.
  • the voltage difference across the first capacitor C1 is maintained at Vdd + Vth - Vdt. Since the first compensation transistor TC1 also has an equivalent capacitance, the charge released by the equivalent capacitance between the gate and the drain of the first transistor T1 may be wholly or partially replaced by the first compensation transistor TC1 while the first transistor T1 is turned off.
  • the equivalent capacitance is absorbed, thereby achieving the purpose of maintaining the threshold voltage maintained in the first capacitor C1 accurately and stably.
  • the equivalent capacitance of the first compensation transistor TC1 and the first transistor T1 is the same or close to the first compensation transistor TC1
  • the equivalent capacitance can accurately absorb the charge released by the equivalent capacitance of the first transistor T1.
  • the first control signal Sn is a high-level voltage
  • the light-emission control signal EM is a low-level voltage.
  • the first transistor T1 and the second transistor T2 are turned off, and the third transistor T3 and the fourth transistor T4 are turned on.
  • the third transistor T3 writes the first reference voltage Vref1 to the third node again, and the voltage of the third node N3 is the first reference voltage Vref1.
  • the voltage of the first node N1 changes due to the bootstrap effect of the first capacitor C1. Is Vref1+Vdd+Vth-Vdt.
  • the illuminating current Ioled flows into the organic light emitting diode OLED through the driving transistor DT and the fourth transistor T4, and the organic light emitting diode OLED emits light.
  • the illuminating current Ioled satisfies the following saturation current formula:
  • ⁇ n is the channel mobility of the driving transistor
  • Cox is the channel capacitance per unit area of the driving transistor
  • W and L are the channel width and channel length of the driving transistor, respectively
  • Vgs is the gate-source voltage of the driving transistor (ie, driving The difference between the gate voltage and the source voltage of the transistor).
  • the pixel circuit shown in FIG. 2 can compensate the threshold voltage of the driving transistor DT.
  • the pixel circuit 100 includes a driving transistor DT, a first transistor T1, a first capacitor C1, and an organic LED OLED, switching error compensation circuit 110, data writing circuit 120, first reference voltage writing circuit 130, lighting control circuit 140, second reference voltage writing circuit 150 and discharging circuit 160, pixel circuit shown in FIG. 100 also includes a second capacitor C2.
  • the driving transistor DT includes a first electrode connected to the first power supply line to receive the first power supply voltage Vdd, a gate connected to the first node N1, and a second electrode connected to the second node N2.
  • the first transistor T1 includes a first pole connected to the second node N2, a gate connected to the first control signal line to receive the first control signal Sn, and a second pole connected to the first node N1.
  • the first capacitor C1 includes a first end connected to the first node N1 and a second end connected to the third node N3.
  • the organic light emitting diode OLED is configured to emit light under driving of the driving transistor DT during operation.
  • the switching error compensation circuit 110 includes a first compensation transistor TC1.
  • the first and second poles of the first compensation transistor TC1 are connected to the first node N1, and the gate of the first compensation transistor TC1 is connected to the illumination control signal line to receive the illumination control. Signal EM.
  • the data writing circuit 120 includes a second transistor T2, the first electrode of which is connected to the data signal line to receive the data signal Vdt, the second electrode of the second transistor T2 is connected to the third node N3, and the second transistor T2 The gate is coupled to the first control signal line to receive the first control signal Sn.
  • First reference voltage write The input circuit 130 includes a third transistor T3, the first electrode of the third transistor T3 is connected to the first reference voltage line to receive the first reference voltage Vref1, and the second electrode of the third transistor T3 is connected to the third node N3, the third transistor The gate of T3 is connected to the light emission control signal line to receive the light emission control signal EM.
  • the illumination control circuit 140 includes a fourth transistor T4, the first pole of the fourth transistor T4 is connected to the second node N2, the second pole of the fourth transistor T4 is connected to the fourth node N4, and the gate and illumination control of the fourth transistor T4
  • the signal line is connected to receive the light emission control signal EM
  • the organic light emitting diode OLED includes a first pole connected to the fourth node N4 and a second pole connected to the second power line to receive the second power voltage Vss.
  • the second reference voltage writing circuit 150 includes a fifth transistor T5, the first pole of the fifth transistor T5 is connected to the second reference voltage line to receive the second reference voltage Vref2, and the second pole and the third node N3 of the fifth transistor T5 Connected, the gate of the fifth transistor T5 is connected to the second control signal line to receive the second control signal Sn-1.
  • the discharge circuit 160 includes a sixth transistor T6, the first pole of the sixth transistor T6 is connected to the first node N1, and the second pole of the sixth transistor T6 is connected to the discharge voltage line to receive the discharge voltage Vini, the gate of the sixth transistor T6. Connected to the second control signal line to receive the second control signal Sn-1.
  • the first end of the second capacitor C2 in the pixel circuit shown in FIG. 4 is connected to the first power line to receive the first power voltage Vdd, and the second end of the second capacitor C2 is connected to the first node N1.
  • the driving timing of the pixel circuit 100 is as shown in FIG.
  • the first control signal Sn is the off voltage
  • the second control signal Sn-1 is the turn-on voltage
  • the illumination control signal EM is the off voltage
  • the first The control signal Sn is the turn-on voltage
  • the second control signal Sn-1 is the turn-off voltage
  • the light-emission control signal EM is the turn-off voltage
  • the first control signal Sn is the turn-off voltage
  • the second control signal Sn-1 is The voltage is turned off, and the light emission control signal EM is a turn-off voltage
  • the first control signal Sn is a turn-off voltage
  • the second control signal Sn-1 is a turn-off voltage
  • the light emission control signal EM is an turn-on voltage.
  • the driving method of the pixel circuit 100 as shown in FIG. 3 or FIG. 4 may further include a reset stabilization phase t1' between the reset phase t1 and the data writing phase t2.
  • the first control signal Sn is the off voltage
  • the second control signal Sn-1 is the off voltage
  • the illumination control signal EM is the off voltage.
  • the reset stabilization phase t1' can provide a stable phase after circuit reset, improving the stability of the circuit.
  • the pixel circuit 100 includes a driving transistor DT, a first transistor T1, a first capacitor C1, and an organic light emitting diode OLED. , switching error compensation circuit 110, data writing circuit 120, A reference voltage writing circuit 130 and an illumination control circuit 140.
  • the driving transistor DT includes a first electrode connected to the first power supply line to receive the first power supply voltage Vdd, a gate connected to the first node N1, and a second electrode connected to the second node N2.
  • the first transistor T1 includes a first pole connected to the second node N2, a gate connected to the first control signal line to receive the first control signal Sn, and a second pole connected to the first node N1.
  • the first capacitor C1 includes a first end connected to the first node N1 and a second end connected to the third node N3.
  • the organic light emitting diode OLED is configured to emit light under driving of the driving transistor DT during operation.
  • the switch error compensation circuit 110 includes a compensation capacitor CC. The first end of the compensation capacitor CC is connected to the first node N1, and the second end of the compensation capacitor CC is connected to the second node N2.
  • the data writing circuit 120 includes a second transistor T2, the first electrode of which is connected to the data signal line to receive the data signal Vdt, the second electrode of the second transistor T2 is connected to the third node N3, and the second transistor T2 The gate is coupled to the first control signal line to receive the first control signal Sn.
  • the first reference voltage writing circuit 130 includes a third transistor T3, the first pole of the third transistor T3 is connected to the first reference voltage line to receive the first reference voltage Vref1, and the second pole and the third node N3 of the third transistor T3 Connected, the gate of the third transistor T3 is connected to the light emission control signal line to receive the light emission control signal EM.
  • the illumination control circuit 140 includes a fourth transistor T4, the first pole of the fourth transistor T4 is connected to the second node N2, the second pole of the fourth transistor T4 is connected to the fourth node N4, and the gate and illumination control of the fourth transistor T4
  • the signal line is connected to receive the light emission control signal EM
  • the organic light emitting diode OLED includes a first pole connected to the fourth node N4 and a second pole connected to the second power line to receive the second power voltage Vss.
  • the driving timing of the pixel circuit 100 is as shown in FIG.
  • the first control signal Sn is an on voltage, and the illumination control signal EM is an on voltage
  • the first control signal Sn is an on voltage
  • the illumination control signal EM To turn off the voltage
  • the switching error compensation phase t3 the first control signal Sn is the off voltage, and the illumination control signal EM is the off voltage
  • the illumination phase t4 the first control signal Sn is the off voltage, and the illumination control signal EM is the on voltage.
  • the pixel circuit 100 includes a driving transistor DT, a first transistor T1, a first capacitor C1, and an organic light emitting diode OLED.
  • the driving transistor DT includes a first electrode connected to the first power supply line to receive the first power supply voltage Vdd, a gate connected to the first node N1, and a second electrode connected to the second node N2.
  • the first transistor T1 includes a first pole connected to the second node N2, a gate connected to the first control signal line to receive the first control signal Sn, and the first node N1 The second pole of the connection.
  • the first capacitor C1 includes a first end connected to the first node N1 and a second end connected to the third node N3.
  • the organic light emitting diode OLED is configured to emit light under driving of the driving transistor DT during operation.
  • the switch error compensation circuit 110 includes a second compensation transistor TC2.
  • the first pole of the second compensation transistor TC2 is connected to the second node N2, and the second pole of the second compensation transistor TC2 is connected to the discharge voltage line to receive the discharge voltage Vini.
  • the gate of the compensation transistor TC2 is connected to the compensation control signal line to receive the compensation control signal NSn.
  • the data writing circuit 120 includes a second transistor T2, the first electrode of which is connected to the data signal line to receive the data signal Vdt, the second electrode of the second transistor T2 is connected to the third node N3, and the second transistor T2 The gate is coupled to the first control signal line to receive the first control signal Sn.
  • the first reference voltage writing circuit 130 includes a third transistor T3, the first pole of the third transistor T3 is connected to the first reference voltage line to receive the first reference voltage Vref1, and the second pole and the third node N3 of the third transistor T3 Connected, the gate of the third transistor T3 is connected to the light emission control signal line to receive the light emission control signal EM.
  • the illumination control circuit 140 includes a fourth transistor T4, the first pole of the fourth transistor T4 is connected to the second node N2, the second pole of the fourth transistor T4 is connected to the fourth node N4, and the gate and illumination control of the fourth transistor T4
  • the signal line is connected to receive the light emission control signal EM
  • the organic light emitting diode OLED includes a first pole connected to the fourth node N4 and a second pole connected to the second power line to receive the second power voltage Vss.
  • the driving timing of the pixel circuit 100 is as shown in FIG.
  • the first control signal Sn is the turn-on voltage
  • the compensation control signal NSn is the turn-off voltage
  • the light-emission control signal EM is the turn-on voltage
  • the first control signal Sn To turn on the voltage
  • the compensation control signal NSn is the off voltage
  • the illumination control signal EM is the off voltage
  • the first control signal Sn is the off voltage
  • the compensation control signal NSn is the on voltage
  • the illumination control signal EM is off.
  • Voltage in the lighting phase t4
  • the first control signal Sn is the off voltage
  • the compensation control signal NSn is the off voltage
  • the illumination control signal EM is the on voltage.
  • the driving method of the pixel circuit 100 shown in FIG. 8 may further include a compensation stabilization phase t3' between the switching error compensation phase t3 and the illumination phase t4.
  • the first control signal Sn is the off voltage
  • the compensation control signal NSn is the off voltage
  • the illumination control signal EM is the off voltage.
  • the compensation stabilization phase t3' can provide a stable phase for circuit switching error compensation and improve the stability of the circuit.
  • the compensation control signal NSn when the first control signal Sn is changed from the turn-on voltage to the turn-off voltage, the compensation control signal NSn is turned off.
  • the synchronous change is the turn-on voltage, that is, at the time when the data writing phase t2 and the compensation phase t3 meet, when the first control signal Sn changes from the turn-on voltage to the turn-off voltage, the compensation control signal NSn changes from the turn-off voltage to the turn-on voltage. .
  • the pixel circuit, the display panel, the display device, and the driving method provided by the embodiments of the present disclosure can reduce or eliminate switching errors in the threshold compensation process and improve display uniformity of the display panel.

Abstract

一种像素电路（100）、显示面板（10）、显示设备（1）及驱动方法。像素电路（100）包括：驱动晶体管（DT）、第一晶体管（T1）、第一电容（C1）、有机发光二极管（OLED）和开关误差补偿电路（110）。驱动晶体管（DT）包括与第一电源线连接以接收第一电源电压（Vdd）的第一极、与第一节点（N1）连接的栅极以及与第二节点（N2）连接的第二极；第一晶体管（T1）包括与第二节点（N2）连接的第一极、与第一控制信号线连接以接收第一控制信号（Sn）的栅极以及与第一节点（N1）连接的第二极；第一电容（C1）包括与第一节点（N1）连接的第一端以及与第三节点（N3）连接的第二端；有机发光二极管（OLED）被配置为在工作时在驱动晶体管（DT）的驱动下发光；开关误差补偿电路（110）与第一节点（N1）和/或第二节点（N2）连接，被配置为补偿第一晶体管（T1）的开关误差。像素电路（100）可以减小或消除阈值补偿过程中的开关误差，提高显示面板显示的均匀性。

Description

像素电路、显示面板、显示设备及驱动方法 技术领域
本公开的实施例涉及一种像素电路、显示面板、显示设备及驱动方法。
背景技术
在显示领域，有机发光二极管(OLED)显示面板具有自发光、对比度高、能耗低、视角广、响应速度快、可用于挠曲性面板、使用温度范围广、制造简单等特点，具有广阔的发展前景。
由于上述特点，有机发光二极管(OLED)显示面板可以适用于手机、显示器、笔记本电脑、数码相机、仪器仪表等具有显示功能的装置。
发明内容
本公开至少一实施例提供一种像素电路，包括：驱动晶体管、第一晶体管、第一电容、有机发光二极管和开关误差补偿电路，驱动晶体管包括与第一电源线连接以接收第一电源电压的第一极、与第一节点连接的栅极以及与第二节点连接的第二极；第一晶体管包括与所述第二节点连接的第一极、与第一控制信号线连接以接收第一控制信号的栅极以及与所述第一节点连接的第二极；第一电容包括与所述第一节点连接的第一端以及与第三节点连接的第二端；有机发光二极管被配置为在工作时在所述驱动晶体管的驱动下发光；开关误差补偿电路与所述第一节点和/或所述第二节点连接，且被配置为补偿所述第一晶体管的开关误差。
例如，在本公开一个示例提供的像素电路中，所述开关误差补偿电路包括第一补偿晶体管，所述第一补偿晶体管的第一极和/或第二极与所述第一节点连接，所述第一补偿晶体管的栅极与发光控制信号线连接以接收发光控制信号。
例如，在本公开一个示例提供的像素电路中，所述第一补偿晶体管与所述第一晶体管由同一工艺制成。
例如，在本公开一个示例提供的像素电路中，所述开关误差补偿电路包括补偿电容，所述补偿电容的第一端与所述第一节点连接，所述补偿电容的第二端与所述第二节点连接。
例如，在本公开一个示例提供的像素电路中，所述开关误差补偿电路包括 第二补偿晶体管，所述第二补偿晶体管的第一极与所述第二节点连接，所述第二补偿晶体管的第二极与放电电压线连接以接收所述放电电压，所述第二补偿晶体管的栅极与补偿控制信号线连接以接收补偿控制信号。
例如，本公开一个示例提供的像素电路，还包括：数据写入电路，被配置为接收所述第一控制信号和数据信号并根据所述第一控制信号向所述第三节点写入所述数据信号。
例如，在本公开一个示例提供的像素电路中，所述数据写入电路包括第二晶体管，所述第二晶体管的第一极与数据信号线连接以接收所述数据信号，所述第二晶体管的第二极与所述第三节点连接，所述第二晶体管的栅极与所述第一控制信号线连接以接收所述第一控制信号。
例如，本公开一个示例提供的像素电路，还包括：第一参考电压写入电路，被配置为接收发光控制信号和第一参考电压并根据所述发光控制信号向所述第三节点写入所述第一参考电压。
例如，在本公开一个示例提供的像素电路中，所述第一参考电压写入电路包括第三晶体管，所述第三晶体管的第一极与第一参考电压线连接以接收所述第一参考电压，所述第三晶体管的第二极与所述第三节点连接，所述第三晶体管的栅极与发光控制信号线连接以接收所述发光控制信号。
例如，本公开一个示例提供的像素电路，还包括：发光控制电路，被配置为接收发光控制信号并根据所述发光控制信号控制所述有机发光二极管发光。
例如，在本公开一个示例提供的像素电路中，所述发光控制电路包括第四晶体管，所述第四晶体管的第一极与所述第二节点连接，所述第四晶体管的第二极与第四节点连接，所述第四晶体管的栅极与发光控制信号线连接以接收所述发光控制信号，所述有机发光二极管包括与所述第四节点连接的第一极以及与第二电源线连接以接收第二电源电压的第二极。
例如，本公开一个示例提供的像素电路，还包括：第二参考电压写入电路，被配置为接收第二控制信号和第二参考电压并根据所述第二控制信号向所述第三节点写入所述第二参考电压。
例如，在本公开一个示例提供的像素电路中，所述第二参考电压写入电路包括第五晶体管，所述第五晶体管的第一极与第二参考电压线连接以接收所述第二参考电压，所述第五晶体管的第二极与所述第三节点连接，所述第五晶体管的栅极与第二控制信号线连接以接收所述第二控制信号。
例如，本公开一个示例提供的像素电路，还包括：放电电路，被配置为接收第二控制信号和放电电压并根据所述第二控制信号向所述第一节点写入所述放电电压。
例如，在本公开一个示例提供的像素电路中，所述放电电路包括第六晶体管。所述第六晶体管的第一极与所述第一节点连接，所述第六晶体管的第二极与放电电压线连接以接收所述放电电压，所述第六晶体管的栅极与第二控制信号线连接以接收所述第二控制信号。
例如，本公开一个示例提供的像素电路，还包括第二电容，所述第二电容的第一端与所述第一电源线连接以接收所述第一电源电压，所述第二电容的第二端与所述第一节点连接。
本公开至少一实施例还提供一种显示面板，包括本公开任一实施例提供的像素电路。
本公开至少一实施例还提供一种显示设备，包括本公开任一实施例提供的显示面板。
本公开至少一实施例还提供一种本公开任一实施例提供的像素电路的驱动方法，包括复位阶段、数据写入阶段、开关误差补偿阶段和发光阶段，其中，在所述复位阶段，对所述第一节点进行复位；在所述数据写入阶段，写入数据信号；在所述开关误差补偿阶段，补偿所述第一晶体管的开关误差；在所述发光阶段，驱动所述有机发光二极管发光。
例如，在本公开实施例提供的驱动方法中，所述像素电路包括：驱动晶体管，包括与第一电源线连接以接收第一电源电压的第一极、与第一节点连接的栅极以及与第二节点连接的第二极；第一晶体管，包括与所述第二节点连接的第一极、与第一控制信号线连接以接收第一控制信号的栅极以及与所述第一节点连接的第二极；第一电容，包括与所述第一节点连接的第一端以及与第三节点连接的第二端；有机发光二极管，被配置为在工作时在所述驱动晶体管的驱动下发光；以及开关误差补偿电路，所述开关误差补偿电路包括第一补偿晶体管，所述第一补偿晶体管的第一极、第二极与所述第一节点连接，所述第一补偿晶体管的栅极与发光控制信号线连接以接收发光控制信号，在所述数据写入阶段，所述第一控制信号为开启电压，所述发光控制信号为关闭电压；在所述开关误差补偿阶段，所述第一控制信号为关闭电压，所述发光控制信号为关闭电压；在所述发光阶段，所述第一控制信号为关闭电压，所述发光控制信号为 开启电压。
例如，在本公开一个示例提供的驱动方法中，所述像素电路包括：驱动晶体管，包括与第一电源线连接以接收第一电源电压的第一极、与第一节点连接的栅极以及与第二节点连接的第二极；第一晶体管，包括与所述第二节点连接的第一极、与第一控制信号线连接以接收第一控制信号的栅极以及与所述第一节点连接的第二极；第一电容，包括与所述第一节点连接的第一端以及与第三节点连接的第二端；有机发光二极管，被配置为在工作时在所述驱动晶体管的驱动下发光；以及开关误差补偿电路，所述开关误差补偿电路包括补偿电容，所述补偿电容的第一端与所述第一节点连接，所述补偿电容的第二端与所述第二节点连接，在所述数据写入阶段，所述第一控制信号为开启电压，所述发光控制信号为关闭电压；在所述开关误差补偿阶段，所述第一控制信号为关闭电压，所述发光控制信号为关闭电压；在所述发光阶段，所述第一控制信号为关闭电压，所述发光控制信号为开启电压。
例如，在本公开一个示例提供的驱动方法中，所述像素电路包括：驱动晶体管，包括与第一电源线连接以接收第一电源电压的第一极、与第一节点连接的栅极以及与第二节点连接的第二极；第一晶体管，包括与所述第二节点连接的第一极、与第一控制信号线连接以接收第一控制信号的栅极以及与所述第一节点连接的第二极；第一电容，包括与所述第一节点连接的第一端以及与第三节点连接的第二端；有机发光二极管，被配置为在工作时在所述驱动晶体管的驱动下发光；以及开关误差补偿电路，所述开关误差补偿电路包括第二补偿晶体管，所述第二补偿晶体管的第一极与所述第二节点连接，所述第二补偿晶体管的第二极与放电电压线连接以接收放电电压，所述第二补偿晶体管的栅极与补偿控制信号线连接以接收补偿控制信号，在所述数据写入阶段，所述第一控制信号为开启电压，所述发光控制信号为关闭电压，所述补偿控制信号为关闭电压；在所述开关误差补偿阶段，所述第一控制信号为关闭电压，所述发光控制信号为关闭电压，所述补偿控制信号为开启电压；在所述发光阶段，所述第一控制信号为关闭电压，所述发光控制信号为开启电压，所述补偿控制信号为关闭电压。
例如，在本公开一个示例提供的驱动方法中，当所述第一控制信号由开启电压变化为关闭电压时，所述补偿控制信号由关闭电压同步变化为开启电压。
例如，本公开实施例提供的像素电路、显示面板、显示设备及驱动方法可 以减小或消除阈值补偿过程中的开关误差，提高显示面板显示的均匀性。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，并非对本公开的限制。
图1是本公开实施例提供的一种像素电路的示意图之一；
图2是本公开实施例提供的一种像素电路的示意图之二；
图3是本公开实施例提供的一种像素电路的示意图之三；
图4是本公开实施例提供的一种像素电路的示意图之四；
图5是本公开实施例提供的一种像素电路的示意图之五；
图6是本公开实施例提供的一种像素电路的示意图之六；
图7是本公开实施例提供的一种像素电路的示意图之七；
图8是本公开实施例提供的一种像素电路的示意图之八；
图9是本公开实施例提供的一种显示面板的示意图；
图10是本公开实施例提供的一种显示设备的示意图；
图11是本公开实施例提供的一种像素电路的驱动时序图之一；
图12是本公开实施例提供的一种像素电路的驱动时序图之二；
图13是本公开实施例提供的一种像素电路的驱动时序图之三；
图14是阈值电压充电结束短接开关晶体管关断前的状态示意图；以及
图15是阈值电压取样充电结束短接开关晶体管关断时的状态示意图。
具体实施方式
下面将结合附图，对本公开实施例中的技术方案进行清楚、完整地描述参考在附图中示出并在以下描述中详述的非限制性示例实施例，更加全面地说明本公开的示例实施例和它们的多种特征及有利细节。应注意的是，图中示出的特征不是必须按照比例绘制。本公开省略了已知材料、组件和工艺技术的描述，从而不使本公开的示例实施例模糊。所给出的示例仅旨在有利于理解本公开示例实施例的实施，以及进一步使本领域技术人员能够实施示例实施例。因而，这些示例不应被理解为对本公开的实施例的范围的限制。
除非另外特别定义，本公开使用的技术术语或者科学术语应当为本公开所 属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。此外，在本公开各个实施例中，相同或类似的参考标号表示相同或类似的构件。
在有机发光二极管(Organic Light-Emitting Diode,OLED)显示面板中，各个像素单元中的驱动晶体管的阈值电压由于制备工艺可能彼此之间存在差异，而且由于例如温度变化的影响，驱动晶体管的阈值电压也会产生漂移的现象。各个驱动晶体管的阈值电压的不同也可能会导致显示面板显示不均匀。因此，需要对驱动晶体管的阈值电压进行补偿。
传统的阈值电压补偿电路通常包括短接开关晶体管，短接开关晶体管的源极与驱动晶体管的漏极连接，短接开关晶体管的漏极与驱动晶体管的栅极连接，这种设置方式配合相应的驱动时序，在补偿过程中，短接驱动晶体管可将驱动晶体管短接为二极管连接，以实现驱动晶体管阈值电压的补偿。然而，这种阈值电压补偿方式的效果并不理想，一个重要原因是在阈值电压补偿电路工作过程中，短接开关晶体管关断时会造成电容保持电位误差，这一误差被称为开关误差(switching induced error)。
开关误差产生的原因为短接开关晶体管的栅极和漏极之间存在等效电容(包括电极重叠寄生电容和沟道电容)，在存储电容充电完成时，存储电容与驱动晶体管栅极相连的一端的电位是驱动晶体管的阈值电压，在短接开关晶体管关断的过程中，因偏压和容量变化短接开关晶体管的等效电容中存储的电荷被注入存储电容，造成存储电容上保持的阈值电压信号产生误差。
因此，由开关误差引起的阈值电压不均匀依然是制约有机发光二级管显示面板生产良率的主要原因之一，需要对开关误差进行补偿。
例如，结合图14和图15对开关误差产生的原因进行说明。图14是阈值电压充电结束短接开关晶体管关断前的状态示意图；图15是阈值电压取样充电结束短接开关晶体管关断时的状态示意图。短接开关晶体管T'的栅极和漏极之间存在等效电容CTgd0，包括电极重叠寄生电容Col和沟道电容Cchn。在存储电容充电完成时，存储电容与驱动晶体管DT’栅极相连的一端的电位是驱动晶体管DT'的阈值电压Vth。在短接开关晶体管T'关断过程中，因偏压和容量变化，短接开关晶体管T'的电容CTgd0中存储的电荷被注入存储电容C1'，造成存储电容上保持的Vth信号误差。在不考虑其他晶体管相关电容的情况下， 解相关电荷守恒方程，得短接开关晶体管T'关断后驱动晶体管DT’的栅极电位为：
Figure PCTCN2017089173-appb-000001
上式中第2、3两项均为短接开关晶体管T'关断过程中产生的误差，第2项为驱动晶体管DT'的阈值电压Vth的相关误差，第3项为信号Vref-Vdt相关误差，其中Vref为参考电压，Vdt为数据信号的电压，VgH为高电平电压，VgL为低电平电压。基于相同工作过程，驱动晶体管DT'的电流如下：
Figure PCTCN2017089173-appb-000002
其中，
Figure PCTCN2017089173-appb-000003
μn为驱动晶体管DT’的沟道迁移率，Cox为驱动晶体管DT'单位面积的沟道电容，W和L分别为驱动晶体管DT'的沟道宽度和沟道长度，VDTgs为驱动晶体管DT’的栅源电压(即，驱动晶体管DT’的栅极电压与源极电压之差)。
因驱动晶体管DT'的阈值电压Vth相关项的存在，阈值电压Vth不均匀仍然会影响显示均匀性。上式阈值电压Vth相关项中，Cgs和Cgs0分别是驱动晶体管DT’在开启和阈值状态下栅极和源极间的电容，通常差异不大对阈值电压Vth相关误差影响不突出。Cgd和Cgd0分别是驱动晶体管DT’在开启和阈值状态下栅极和漏极之间电容，其特性与栅极和源极间电容类似。但是，由于阈值状态下Cgd0被短接开关晶体管T’短路没有存储电荷，短接开关晶体管T'关断后，Cgd可能吸收较多的电荷，从而可以对阈值电压Vth相关误差产生一定影响。
可以看出，误差的阈值电压Vth相关项系数主要由短接开关晶体管T'的沟道电容Cchn和驱动晶体管DT'的栅极和漏极间电容Cgd决定，物理过程是关断过程中，短接开关晶体管T’的导电沟道消失，相应的等效电容也接近于0，原先存在其中的电荷注入存储电容C1'，也有部分被驱动晶体管DT'是栅极和漏极间电容Cgd等电容吸收。
例如，本公开实施例提供的像素电路、显示面板、显示设备及驱动方法可 以减小或消除阈值补偿过程中的开关误差，提高显示面板显示的均匀性。
本公开至少一实施例提供一种像素电路，其包括：驱动晶体管、第一晶体管、第一电容、有机发光二极管和开关误差补偿电路。驱动晶体管包括与第一电源线连接以接收第一电源电压的第一极、与第一节点连接的栅极以及与第二节点连接的第二极；第一晶体管包括与第二节点连接的第一极、与第一控制信号线连接以接收第一控制信号的栅极以及与第一节点连接的第二极；第一电容包括与第一节点连接的第一端以及与第三节点连接的第二端；有机发光二极管被配置为在工作时在驱动晶体管的驱动下发光；开关误差补偿电路与第一节点和/或第二节点连接，被配置为补偿第一晶体管的开关误差。
实施例一
例如，本实施例提供一种像素电路100，如图1所示，像素电路100包括驱动晶体管DT、第一晶体管T1、第一电容C1、有机发光二极管OLED以及开关误差补偿电路110。驱动晶体管DT包括与第一电源线连接以接收第一电源电压Vdd的第一极、与第一节点N1连接的栅极以及与第二节点N2连接的第二极。第一晶体管T1包括与第二节点N2连接的第一极、与第一控制信号线连接以接收第一控制信号Sn的栅极以及与第一节点N1连接的第二极。第一电容C1包括与第一节点N1连接的第一端以及与第三节点N3连接的第二端。有机发光二极管OLED被配置为在工作时在驱动晶体管DT的驱动下发光。开关误差补偿电路110与第一节点N1连接，被配置为补偿第一晶体管T1的开关误差。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极，所以本公开实施例中全部或部分晶体管的源极和漏极根据需要是可以互换的。此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管，本公开的实施例均以P型晶体管为例进行说明。基于本公开对P型晶体管实现方式的描述和教导，本领域普通技术人员在没有做出创造性劳动前提下能够容易想到本公开实施例采用N型晶体管的实现方式，因此，这些实现方式也是在本公开的保护范围内的。
例如，如图1所示，本公开实施例提供的像素电路100还包括数据写入电 路120，数据写入电路120被配置为接收第一控制信号Sn和数据信号Vdt并根据第一控制信号Sn向第三节点N3写入数据信号Vdt。
例如，如图1所示，本公开实施例提供的像素电路100还包括第一参考电压写入电路130，第一参考电压写入电路130被配置为接收发光控制信号EM和第一参考电压Vref1并根据发光控制信号EM向第三节点N3写入第一参考电压Vref1。
例如，如图1所示，本公开实施例提供的像素电路100还包括发光控制电路140，发光控制电路140被配置为接收发光控制信号EM并根据发光控制信号EM控制有机发光二极管OLED发光。
需要说明的是，本公开的实施例包括但不局限于像素电路100包括数据写入电路120、第一参考电压写入电路130和发光控制电路140的情形，也可以是其他的情形，例如，不包括数据写入电路120和第一参考电压写入电路130，而使数据信号线直接连接第三节点N3，同时通过设置数据信号Vdt的时序和电压值实现数据信号和第一参考电压的写入。
例如，如图1和图2所示，在本公开实施例提供的像素电路100中，开关误差补偿电路110包括第一补偿晶体管TC1，第一补偿晶体管TC1的第一极、第二极均与第一节点N1连接，第一补偿晶体管TC1的栅极与发光控制信号线连接以接收发光控制信号EM。
需要说明的是，本公开的实施例包括但不局限于第一补偿晶体管TC1的第一极、第二极与第一节点N1连接的情形，也可以是第一补偿晶体管TC1的第一极与第一节点N1连接，第二极悬空，或者第一补偿晶体管TC1的第二极与第一节点N1连接，第一极悬空。
例如，在本公开实施例提供的像素电路100中，第一补偿晶体管TC1与第一晶体管T1由相同的工艺制成。
例如，由于第一补偿晶体管TC1也具有等效的电容，在第一晶体管T1关断的同时，第一晶体管T1栅极和漏极间的等效电容释放的电荷可以全部或部分被第一补偿晶体管TC1的等效电容吸收，从而达到保持第一电容C1中阈值电压准确和稳定的目的。由于第一补偿晶体管TC1与第一晶体管T1由相同的工艺制成，使得第一补偿晶体管TC1与第一晶体管T1的特性相同或相似，第一补偿晶体管TC1的等效电容与第一晶体管T1的等效电容相同或接近，第一补偿晶体管TC1的等效电容能够准确地吸收第一晶体管T1的等效电容释放的 电荷，从而获得较佳的补偿效果。
例如，第一补偿晶体管TC1的等效电容包括Ctcgs和Ctcgd，Ctcgs为第一补偿晶体管TC1栅极和源极之间的等效电容，Ctcgd为第一补偿晶体管TC1栅极和漏极之间的等效电容(无论第一补偿晶体管TC1的第一极、第二极是否同时与第一节点N1连接，由于没有其他旁路，第一补偿晶体管的Ctcgd和Ctcgs都会共同参与电荷的吸收或排出)，而第一晶体管T1的等效电容仅仅包括第一晶体管T1的栅极和漏极之间的等效电容C1gd。第一晶体管T1导通时栅极和源极之间的等效电容C1gs与栅极和漏极之间的等效电容C1gd中总电荷量一定，但第一晶体管T1关断时会根据电路偏置条件在C1gd和C1gs间分配电荷，造成C1gd和C1gs等效电容变动。例如，第一晶体管T1的C1gd会大于C1gs。
例如，对于如图2所示的像素电路，只需要提供第一控制信号Sn和发光控制信号EM，便于电路的布线，可提升显示面板的分辨率。
例如，如图1和图2所示，在本公开实施例提供的像素电路100中，数据写入电路120包括第二晶体管T2，第二晶体管T2的第一极与数据信号线连接以接收数据信号Vdt，第二晶体管T2的第二极与第三节点N3连接，第二晶体管T2的栅极与第一控制信号线连接以接收第一控制信号Sn。
例如，如图1和图2所示，在本公开实施例提供的像素电路100中，第一参考电压写入电路130包括第三晶体管T3，第三晶体管T3的第一极与第一参考电压线连接以接收第一参考电压Vref1，第三晶体管T3的第二极与第三节点N3连接，第三晶体管T3的栅极与发光控制信号线连接以接收发光控制信号EM。
例如，如图1和图2所示，在本公开实施例提供的像素电路100中，发光控制电路140包括第四晶体管T4，第四晶体管T4的第一极与第二节点N2连接，第四晶体管T4的第二极与第四节点N4连接，第四晶体管T4的栅极与发光控制信号线连接以接收发光控制信号EM，有机发光二极管OLED包括与第四节点N4连接的第一极以及与第二电源线连接以接收第二电源电压Vss的第二极。
例如，第一电源电压Vdd为高电平电压(例如8V)，第二电源电压Vss为低电平电压(例如，0V)。
例如，有机发光二极管OLED的第一极为阳极，第二极为阴极。
需要说明的是，图2所示的像素电路仅仅为图1所示像素电路的一种实施 方式，本公开的实施例包括但不局限于图2所示的实施方式。
例如，在图2所示的像素电路的基础上，如图3所示，本公开实施例提供的像素电路100还包括第二参考电压写入电路150，第二参考电压写入电路150被配置为接收第二控制信号Sn-1和第二参考电压Vref2并根据第二控制信号Sn-1向第三节点N3写入第二参考电压Vref2。
例如，如图3所示，在本公开实施例提供的像素电路100中，第二参考电压写入电路150包括第五晶体管T5，第五晶体管T5的第一极与第二参考电压线连接以接收第二参考电压Vref2，第五晶体管T5的第二极与第三节点N3连接，第五晶体管T5的栅极与第二控制信号线连接以接收第二控制信号Sn-1。
例如，第二控制信号Sn-1可以比第一控制信号Sn提前一行扫描时间，也就是说，本行像素电路的第二控制信号Sn-1可以由相邻的上一行像素电路的第一控制信号Sn来实现，这样可以简化电路的设计，方便电路的布线。
例如，第一参考电压Vref1和第二参考电压Vref2是稳定的基准电压，它们可以是相同的电压或者是不同的电压。
例如，在第一参考电压写入电路130的基础上增加第二参考电压写入电路150可以改善显示品质，防止相邻的上一帧的残存信号影响本帧的信号补偿。
例如，如图3所示，本公开实施例提供的像素电路100还包括放电电路160，被配置为接收第二控制信号Sn-1和放电电压Vini并根据第二控制信号Sn-1向第一节点N1写入放电电压Vini。
例如，如图3所示，在本公开实施例提供的像素电路100中，放电电路160包括第六晶体管T6，第六晶体管T6的第一极与第一节点N1连接，第六晶体管T6的第二极与放电电压线连接以接收放电电压Vini，第六晶体管T6的栅极与第二控制信号线连接以接收第二控制信号Sn-1。
例如，放电电压Vini为低电平电压(例如，0V)。
例如，第一参考电压Vref1、第二参考电压Vref2和放电电压Vini可以是相同的电压，这种设置方式可以简化电路布线，提高显示面板的分辨率。
例如，在图3的基础上，如图4所示，本公开实施例提供的像素电路100还包括第二电容C2，第二电容C2的第一端与第一电源线连接以接收第一电源电压Vdd，第二电容C2的第二端与第一节点N1连接。
例如，设置第二电容C2可以提高像素电路100的稳定性。
实施例二
例如，本实施例提供一种像素电路100，如图5所示，像素电路100包括驱动晶体管DT、第一晶体管T1、第一电容C1、有机发光二极管OLED以及开关误差补偿电路110。驱动晶体管DT包括与第一电源线连接以接收第一电源电压Vdd的第一极、与第一节点N1连接的栅极以及与第二节点N2连接的第二极。第一晶体管T1包括与第二节点N2连接的第一极、与第一控制信号线连接以接收第一控制信号Sn的栅极以及与第一节点N1连接的第二极。第一电容C1包括与第一节点N1连接的第一端以及与第三节点N3连接的第二端。有机发光二极管OLED被配置为在工作时在驱动晶体管DT的驱动下发光。开关误差补偿电路110与第一节点N1和第二节点N2连接，被配置为补偿第一晶体管T1的开关误差。
例如，如图5所示，本公开实施例提供的像素电路100还包括数据写入电路120，数据写入电路120被配置为接收第一控制信号Sn和数据信号Vdt并根据第一控制信号Sn向第三节点N3写入数据信号Vdt。
例如，如图5所示，本公开实施例提供的像素电路100还包括第一参考电压写入电路130，第一参考电压写入电路130被配置为接收发光控制信号EM和第一参考电压Vref1并根据发光控制信号EM向第三节点N3写入第一参考电压Vref1。
例如，如图5所示，本公开实施例提供的像素电路100还包括发光控制电路140，发光控制电路140被配置为接收发光控制信号EM并根据发光控制信号EM控制有机发光二极管OLED发光。
需要说明的是，本公开的实施例包括但不局限于像素电路100包括数据写入电路120、第一参考电压写入电路130和发光控制电路140的情形，也可以是其他的情形。
例如，如图5和图6所示，在本公开实施例提供的像素电路100中，开关误差补偿电路110包括补偿电容CC，补偿电容CC的第一端与第一节点N1连接，补偿电容CC的第二端与第二节点N2连接。
例如，由于加入了补偿电容CC，在第一晶体管T1关断的同时，第一晶体管T1栅极和漏极间的等效电容释放的电荷可以全部或部分被补偿电容CC吸收，从而达到保持第一电容C1中阈值电压准确和稳定的目的。补偿电容CC的电容值例如可以通过试验的方法获得。
例如，如图5和图6所示，在本公开实施例提供的像素电路100中，数据 写入电路120包括第二晶体管T2，第二晶体管T2的第一极与数据信号线连接以接收数据信号Vdt，第二晶体管T2的第二极与第三节点N3连接，第二晶体管T2的栅极与第一控制信号线连接以接收第一控制信号Sn。
例如，如图5和图6所示，在本公开实施例提供的像素电路100中，第一参考电压写入电路130包括第三晶体管T3，第三晶体管T3的第一极与第一参考电压线连接以接收第一参考电压Vref1，第三晶体管T3的第二极与第三节点N3连接，第三晶体管T3的栅极与发光控制信号线连接以接收发光控制信号EM。
例如，如图5和图6所示，在本公开实施例提供的像素电路100中，发光控制电路140包括第四晶体管T4，第四晶体管T4的第一极与第二节点N2连接，第四晶体管T4的第二极与第四节点N4连接，第四晶体管T4的栅极与发光控制信号线连接以接收发光控制信号EM，有机发光二极管OLED包括与第四节点N4连接的第一极以及与第二电源线连接以接收第二电源电压Vss的第二极。
需要说明的是，图6所示的像素电路仅仅为图5所示像素电路的一种实施方式，本公开的实施例包括但不局限于图6所示的实施方式。
例如，对于如图6所示的像素电路，只需要提供第一控制信号Sn和发光控制信号EM，便于电路的布线，可提升显示面板的分辨率。
例如，在本实施例中，像素电路还可以包括第二参考电压写入电路、放电电路和第二电容等(图中未示出)，其实施方式与实施例一类似，在此不再赘述。
实施例三
例如，本实施例提供一种像素电路100，如图7所示，像素电路100包括驱动晶体管DT、第一晶体管T1、第一电容C1、有机发光二极管OLED以及开关误差补偿电路110。驱动晶体管DT包括与第一电源线连接以接收第一电源电压Vdd的第一极、与第一节点N1连接的栅极以及与第二节点N2连接的第二极。第一晶体管T1包括与第二节点N2连接的第一极、与第一控制信号线连接以接收第一控制信号Sn的栅极以及与第一节点N1连接的第二极。第一电容C1包括与第一节点N1连接的第一端以及与第三节点N3连接的第二端。有机发光二极管OLED被配置为在工作时在驱动晶体管DT的驱动下发光。开关误差补偿电路110与第二节点N2连接，被配置为补偿第一晶体管T1的开 关误差。
例如，如图7所示，本公开实施例提供的像素电路100还包括数据写入电路120，数据写入电路120被配置为接收第一控制信号Sn和数据信号Vdt并根据第一控制信号Sn向第三节点N3写入数据信号Vdt。
例如，如图7所示，本公开实施例提供的像素电路100还包括第一参考电压写入电路130，第一参考电压写入电路130被配置为接收发光控制信号EM和第一参考电压Vref1并根据发光控制信号EM向第三节点N3写入第一参考电压Vref1。
例如，如图7所示，本公开实施例提供的像素电路100还包括发光控制电路140，发光控制电路140被配置为接收发光控制信号EM并根据发光控制信号EM控制有机发光二极管OLED发光。
需要说明的是，本公开的实施例包括但不局限于像素电路100包括数据写入电路120、第一参考电压写入电路130和发光控制电路140的情形，也可以是其他的情形。
例如，如图7和图8所示，在本公开实施例提供的像素电路100中，开关误差补偿电路110包括第二补偿晶体管TC2，第二补偿晶体管TC2的第一极与第二节点N2连接，第二补偿晶体管TC2的第二极与放电电压线连接以接收放电电压Vini，第二补偿晶体管TC2的栅极与补偿控制信号线连接以接收补偿控制信号NSn。
例如，在第一晶体管T1关断的同时，由时序控制第二补偿晶体管TC2导通，第一晶体管T1的第一极(例如，源极)的电位被拉低为放电电压Vini(例如，0V)，使第一晶体管T1沟道偏压状态瞬间翻转(源极和漏极互换)。这样，大部分的沟道电荷在沟道消失过程中，会被赶到第一晶体管T1正常工作状态的源极，避免影响第一电容C1中保持的阈值电压。
例如，如图7和图8所示，在本公开实施例提供的像素电路100中，数据写入电路120包括第二晶体管T2，第二晶体管T2的第一极与数据信号线连接以接收数据信号Vdt，第二晶体管T2的第二极与第三节点N3连接，第二晶体管T2的栅极与第一控制信号线连接以接收第一控制信号Sn。
例如，如图7和图8所示，在本公开实施例提供的像素电路100中，第一参考电压写入电路130包括第三晶体管T3，第三晶体管T3的第一极与第一参考电压线连接以接收第一参考电压Vref1，第三晶体管T3的第二极与第三节点 N3连接，第三晶体管T3的栅极与发光控制信号线连接以接收发光控制信号EM。
例如，如图7和图8所示，在本公开实施例提供的像素电路100中，发光控制电路140包括第四晶体管T4，第四晶体管T4的第一极与第二节点N2连接，第四晶体管T4的第二极与第四节点N4连接，第四晶体管T4的栅极与发光控制信号线连接以接收发光控制信号EM，有机发光二极管OLED包括与第四节点N4连接的第一极以及与第二电源线连接以接收第二电源电压Vss的第二极。
需要说明的是，图8所示的像素电路仅仅为图7所示像素电路的一种实施方式，本公开的实施例包括但不局限于图8所示的实施方式。
例如，在本实施例中，像素电路还可以包括第二参考电压写入电路、放电电路和第二电容等(图中未示出)，其实施方式与实施例一类似，在此不再赘述。
需要说明的是，实施例一、实施例二、实施例三中的开关误差补偿电路110的实现方式不同，但均能实现对第一晶体管T1开关误差的补偿。因此，在不冲突的情况下，这些实施例中开关误差补偿电路110的实施方式可以结合使用。
实施例四
本实施例提供一种显示面板10，如图9所示，显示面板10包括本公开任一实施例提供的像素电路100。
例如，如图9所示，本实施例提供的显示面板10还包括：数据驱动器11、扫描驱动器12和控制器13。数据驱动器11被配置为向像素电路100提供数据信号Vdt；扫描驱动器12被配置为向像素电路100提供发光控制信号EM、第一控制信号Sn、第二控制信号Sn-1和补偿控制信号NSn；控制器13被配置为向数据驱动器11和扫描驱动器12提供控制指令以使数据驱动器11和扫描驱动器12协同工作。
实施例五
本实施例提供一种显示设备1，如图10所示，显示设备1包括本公开任一实施例提供的显示面板10。
例如，本公开实施例提供的显示设备1可以包括手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
实施例六
本实施例提供一种本公开任一实施例提供的像素电路100的驱动方法。该驱动方法包括复位阶段t1、数据写入阶段t2、开关误差补偿阶段t3和发光阶段t4。在复位阶段t1，对第一节点N1进行复位；在数据写入阶段t2，写入数据信号Vdt；在开关误差补偿阶段t3，补偿第一晶体管T1的开关误差；在发光阶段t4，驱动有机发光二极管OLED发光。
例如，在一个示例中，在本公开实施例提供的驱动方法中，对于图2所示的像素电路，即像素电路100包括驱动晶体管DT、第一晶体管T1、第一电容C1、有机发光二极管OLED、开关误差补偿电路110、数据写入电路120、第一参考电压写入电路130和发光控制电路140。驱动晶体管DT包括与第一电源线连接以接收第一电源电压Vdd的第一极、与第一节点N1连接的栅极以及与第二节点N2连接的第二极。第一晶体管T1包括与第二节点N2连接的第一极、与第一控制信号线连接以接收第一控制信号Sn的栅极以及与第一节点N1连接的第二极。第一电容C1包括与第一节点N1连接的第一端以及与第三节点N3连接的第二端。有机发光二极管OLED被配置为在工作时在驱动晶体管DT的驱动下发光。开关误差补偿电路110包括第一补偿晶体管TC1，第一补偿晶体管TC1的第一极、第二极与第一节点N1连接，第一补偿晶体管TC1的栅极与发光控制信号线连接以接收发光控制信号EM。数据写入电路120包括第二晶体管T2，第二晶体管T2的第一极与数据信号线连接以接收数据信号Vdt，第二晶体管T2的第二极与第三节点N3连接，第二晶体管T2的栅极与第一控制信号线连接以接收第一控制信号Sn。第一参考电压写入电路130包括第三晶体管T3，第三晶体管T3的第一极与第一参考电压线连接以接收第一参考电压Vref1，第三晶体管T3的第二极与第三节点N3连接，第三晶体管T3的栅极与发光控制信号线连接以接收发光控制信号EM。发光控制电路140包括第四晶体管T4，第四晶体管T4的第一极与第二节点N2连接，第四晶体管T4的第二极与第四节点N4连接，第四晶体管T4的栅极与发光控制信号线连接以接收发光控制信号EM，有机发光二极管OLED包括与第四节点N4连接的第一极以及与第二电源线连接以接收第二电源电压Vss的第二极。该像素电路100的驱动时序如图11所示。
例如，如图11所示，在复位阶段t1，第一控制信号Sn为开启电压，发光控制信号EM为开启电压；在数据写入阶段t2，第一控制信号Sn为开启电压，发光控制信号EM为关闭电压；在开关误差补偿阶段t3，第一控制信号Sn为 关闭电压，发光控制信号EM为关闭电压；在发光阶段t4，第一控制信号Sn为关闭电压，发光控制信号EM为开启电压。
需要说明的是，本公开实施例中的开启电压是指能使相应晶体管第一极和第二级导通的电压，关闭电压是指能使相应晶体管的第一极和第二级断开的电压。当晶体管为P型晶体管时，开启电压为低电压(例如，0V)，关闭电压为高电压(例如，5V)；当晶体管为N型晶体管时，开启电压为高电压(例如，5V)，关闭电压为低电压(例如，0V)。图11至图13所示的驱动时序图均以P型晶体管为例进行说明，即开启电压为低电压(例如，0V)，关闭电压为高电压(例如，5V)。
例如，下面以图2所示的像素电路100和图11所示的驱动时序为例介绍像素电路100的工作过程。
例如，在复位阶段t1，第一控制信号Sn为低电平电压，发光控制信号EM为低电平电压。第一晶体管T1、第二晶体管T2、第三晶体管T3和第四晶体管T4均开启(即源极和漏极导通)，第三晶体管T3将第一参考电压Vref1写入第三节点，第三节点N3的电压为第一参考电压Vref1，第二电源电压Vss通过第四晶体管T4和第一晶体管T1写入第一节点N1，第一节点N1的电压为第二电源电压Vss，即对像素电路100进行了复位。
在数据写入阶段t2，第一控制信号Sn为低电平电压，发光控制信号EM为高电平电压。第一晶体管T1和第二晶体管T2开启，第三晶体管T3和第四晶体管T4关断(即源极和漏极未导通)，第二晶体管T2将数据信号Vdt写入第三节点N3，第三节点的电压为Vdt，第一节点N1的电压为Vdd+Vth，Vth为驱动晶体管DT的阈值电压，第一电容C1两端的电压差为Vdd+Vth-Vdt。
在开关误差补偿阶段t3，第一控制信号Sn为高电平电压，发光控制信号EM为高电平电压。第一晶体管T1、第二晶体管T2、第三晶体管T3和第四晶体管T4关断。第一电容C1两端的电压差保持在Vdd+Vth-Vdt。由于第一补偿晶体管TC1也具有等效的电容，在第一晶体管T1关断的同时，第一晶体管T1栅极和漏极间的等效电容释放的电荷可以全部或部分被第一补偿晶体管TC1的等效电容吸收，从而达到保持第一电容C1中保持的阈值电压准确和稳定的目的。由于第一补偿晶体管TC1与第一晶体管T1由相同的工艺制成，使得第一补偿晶体管TC1与第一晶体管T1的特性相同或相似，第一补偿晶体管TC1的等效电容与第一晶体管T1的等效电容相同或接近，第一补偿晶体管TC1的 等效电容可以准确地吸收第一晶体管T1的等效电容释放的电荷。
在发光阶段t4，第一控制信号Sn为高电平电压，发光控制信号EM为低电平电压。第一晶体管T1和第二晶体管T2关断，第三晶体管T3和第四晶体管T4开启。第三晶体管T3将第一参考电压Vref1再次写入第三节点，第三节点N3的电压为第一参考电压Vref1，此时，由于第一电容C1的自举效应，第一节点N1的电压变化为Vref1+Vdd+Vth-Vdt。发光电流Ioled通过驱动晶体管DT和第四晶体管T4流入有机发光二极管OLED，有机发光二极管OLED发光。发光电流Ioled满足如下饱和电流公式：
K(Vgs-Vth)2＝K(Vref1+Vdd+Vth-Vdt-Vdd-Vth)2＝K(Vref1-Vdt)2
其中，
Figure PCTCN2017089173-appb-000004
μn为驱动晶体管的沟道迁移率，Cox为驱动晶体管单位面积的沟道电容，W和L分别为驱动晶体管的沟道宽度和沟道长度，Vgs为驱动晶体管的栅源电压(即，驱动晶体管的栅极电压与源极电压之差)。
由上式中可以看到流经OLED的电流与驱动晶体管DT的阈值电压无关。因此，图2所示的像素电路可以补偿驱动晶体管DT的阈值电压。
例如，在一个示例中，在本公开实施例提供的驱动方法中，对于图3或图4所示的像素电路，即像素电路100包括驱动晶体管DT、第一晶体管T1、第一电容C1、有机发光二极管OLED、开关误差补偿电路110、数据写入电路120、第一参考电压写入电路130、发光控制电路140、第二参考电压写入电路150和放电电路160，图4所示的像素电路100还包括第二电容C2。驱动晶体管DT包括与第一电源线连接以接收第一电源电压Vdd的第一极、与第一节点N1连接的栅极以及与第二节点N2连接的第二极。第一晶体管T1包括与第二节点N2连接的第一极、与第一控制信号线连接以接收第一控制信号Sn的栅极以及与第一节点N1连接的第二极。第一电容C1包括与第一节点N1连接的第一端以及与第三节点N3连接的第二端。有机发光二极管OLED被配置为在工作时在驱动晶体管DT的驱动下发光。开关误差补偿电路110包括第一补偿晶体管TC1，第一补偿晶体管TC1的第一极、第二极与第一节点N1连接，第一补偿晶体管TC1的栅极与发光控制信号线连接以接收发光控制信号EM。数据写入电路120包括第二晶体管T2，第二晶体管T2的第一极与数据信号线连接以接收数据信号Vdt，第二晶体管T2的第二极与第三节点N3连接，第二晶体管T2的栅极与第一控制信号线连接以接收第一控制信号Sn。第一参考电压写 入电路130包括第三晶体管T3，第三晶体管T3的第一极与第一参考电压线连接以接收第一参考电压Vref1，第三晶体管T3的第二极与第三节点N3连接，第三晶体管T3的栅极与发光控制信号线连接以接收发光控制信号EM。发光控制电路140包括第四晶体管T4，第四晶体管T4的第一极与第二节点N2连接，第四晶体管T4的第二极与第四节点N4连接，第四晶体管T4的栅极与发光控制信号线连接以接收发光控制信号EM，有机发光二极管OLED包括与第四节点N4连接的第一极以及与第二电源线连接以接收第二电源电压Vss的第二极。第二参考电压写入电路150包括第五晶体管T5，第五晶体管T5的第一极与第二参考电压线连接以接收第二参考电压Vref2，第五晶体管T5的第二极与第三节点N3连接，第五晶体管T5的栅极与第二控制信号线连接以接收第二控制信号Sn-1。放电电路160包括第六晶体管T6，第六晶体管T6的第一极与第一节点N1连接，第六晶体管T6的第二极与放电电压线连接以接收放电电压Vini，第六晶体管T6的栅极与第二控制信号线连接以接收第二控制信号Sn-1。图4所示的像素电路中的第二电容C2的第一端与第一电源线连接以接收第一电源电压Vdd，第二电容C2的第二端与第一节点N1连接。该像素电路100的驱动时序如图12所示。
例如，如图12所示，在复位阶段t1，第一控制信号Sn为关闭电压，第二控制信号Sn-1为开启电压，发光控制信号EM为关闭电压；在数据写入阶段t2，第一控制信号Sn为开启电压，第二控制信号Sn-1为关闭电压，发光控制信号EM为关闭电压；在开关误差补偿阶段t3，第一控制信号Sn为关闭电压，第二控制信号Sn-1为关闭电压，发光控制信号EM为关闭电压；在发光阶段t4，第一控制信号Sn为关闭电压，第二控制信号Sn-1为关闭电压，发光控制信号EM为开启电压。
例如，如图12所示，如图3或图4所示的像素电路100的驱动方法还可以包括复位稳定阶段t1'，复位稳定阶段t1'在复位阶段t1和数据写入阶段t2之间。在复位稳定阶段t1'，第一控制信号Sn为关闭电压，第二控制信号Sn-1为关闭电压，发光控制信号EM为关闭电压。例如，复位稳定阶段t1'可以为电路复位后提供一个稳定的阶段，提高电路的稳定性。
例如，在一个示例中，在本公开实施例提供的驱动方法中，对于图6所示的像素电路，即像素电路100包括驱动晶体管DT、第一晶体管T1、第一电容C1、有机发光二极管OLED、开关误差补偿电路110、数据写入电路120、第 一参考电压写入电路130和发光控制电路140。驱动晶体管DT包括与第一电源线连接以接收第一电源电压Vdd的第一极、与第一节点N1连接的栅极以及与第二节点N2连接的第二极。第一晶体管T1包括与第二节点N2连接的第一极、与第一控制信号线连接以接收第一控制信号Sn的栅极以及与第一节点N1连接的第二极。第一电容C1包括与第一节点N1连接的第一端以及与第三节点N3连接的第二端。有机发光二极管OLED被配置为在工作时在驱动晶体管DT的驱动下发光。开关误差补偿电路110包括补偿电容CC，补偿电容CC的第一端与第一节点N1连接，补偿电容CC的第二端与第二节点N2连接。数据写入电路120包括第二晶体管T2，第二晶体管T2的第一极与数据信号线连接以接收数据信号Vdt，第二晶体管T2的第二极与第三节点N3连接，第二晶体管T2的栅极与第一控制信号线连接以接收第一控制信号Sn。第一参考电压写入电路130包括第三晶体管T3，第三晶体管T3的第一极与第一参考电压线连接以接收第一参考电压Vref1，第三晶体管T3的第二极与第三节点N3连接，第三晶体管T3的栅极与发光控制信号线连接以接收发光控制信号EM。发光控制电路140包括第四晶体管T4，第四晶体管T4的第一极与第二节点N2连接，第四晶体管T4的第二极与第四节点N4连接，第四晶体管T4的栅极与发光控制信号线连接以接收发光控制信号EM，有机发光二极管OLED包括与第四节点N4连接的第一极以及与第二电源线连接以接收第二电源电压Vss的第二极。该像素电路100的驱动时序如图11所示。
例如，如图11所示，在复位阶段t1，第一控制信号Sn为开启电压，发光控制信号EM为开启电压；在数据写入阶段t2，第一控制信号Sn为开启电压，发光控制信号EM为关闭电压；在开关误差补偿阶段t3，第一控制信号Sn为关闭电压，发光控制信号EM为关闭电压；在发光阶段t4，第一控制信号Sn为关闭电压，发光控制信号EM为开启电压。
例如，在一个示例中，在本公开实施例提供的驱动方法中，对于图8所示的像素电路，即像素电路100包括驱动晶体管DT、第一晶体管T1、第一电容C1、有机发光二极管OLED、开关误差补偿电路110、数据写入电路120、第一参考电压写入电路130和发光控制电路140。驱动晶体管DT包括与第一电源线连接以接收第一电源电压Vdd的第一极、与第一节点N1连接的栅极以及与第二节点N2连接的第二极。第一晶体管T1包括与第二节点N2连接的第一极、与第一控制信号线连接以接收第一控制信号Sn的栅极以及与第一节点N1 连接的第二极。第一电容C1包括与第一节点N1连接的第一端以及与第三节点N3连接的第二端。有机发光二极管OLED被配置为在工作时在驱动晶体管DT的驱动下发光。开关误差补偿电路110包括第二补偿晶体管TC2，第二补偿晶体管TC2的第一极与第二节点N2连接，第二补偿晶体管TC2的第二极与放电电压线连接以接收放电电压Vini，第二补偿晶体管TC2的栅极与补偿控制信号线连接以接收补偿控制信号NSn。数据写入电路120包括第二晶体管T2，第二晶体管T2的第一极与数据信号线连接以接收数据信号Vdt，第二晶体管T2的第二极与第三节点N3连接，第二晶体管T2的栅极与第一控制信号线连接以接收第一控制信号Sn。第一参考电压写入电路130包括第三晶体管T3，第三晶体管T3的第一极与第一参考电压线连接以接收第一参考电压Vref1，第三晶体管T3的第二极与第三节点N3连接，第三晶体管T3的栅极与发光控制信号线连接以接收发光控制信号EM。发光控制电路140包括第四晶体管T4，第四晶体管T4的第一极与第二节点N2连接，第四晶体管T4的第二极与第四节点N4连接，第四晶体管T4的栅极与发光控制信号线连接以接收发光控制信号EM，有机发光二极管OLED包括与第四节点N4连接的第一极以及与第二电源线连接以接收第二电源电压Vss的第二极。该像素电路100的驱动时序如图13所示。
例如，如图13所示，在复位阶段t1，第一控制信号Sn为开启电压，补偿控制信号NSn为关闭电压，发光控制信号EM为开启电压；在数据写入阶段t2，第一控制信号Sn为开启电压，补偿控制信号NSn为关闭电压，发光控制信号EM为关闭电压；在开关误差补偿阶段t3，第一控制信号Sn为关闭电压，补偿控制信号NSn为开启电压，发光控制信号EM为关闭电压；在发光阶段t4，第一控制信号Sn为关闭电压，补偿控制信号NSn为关闭电压，发光控制信号EM为开启电压。
例如，如图13所示，图8所示的像素电路100的驱动方法还可以包括补偿稳定阶段t3'，补偿稳定阶段t3'在开关误差补偿阶段t3和发光阶段t4之间。在补偿稳定阶段t3'，第一控制信号Sn为关闭电压，补偿控制信号NSn为关闭电压，发光控制信号EM为关闭电压。例如，补偿稳定阶段t3'可以为电路开关误差补偿后提供一个稳定的阶段，提高电路的稳定性。
例如，如图13所示，在如图8所示的像素电路100的驱动方法中，当第一控制信号Sn由开启电压变化为关闭电压时，补偿控制信号NSn由关闭电压 同步变化为开启电压，也就是说，在数据写入阶段t2和补偿阶段t3交界的时刻，第一控制信号Sn由开启电压变化为关闭电压时，补偿控制信号NSn由关闭电压同步变化为开启电压。
本公开实施例提供的像素电路、显示面板、显示设备及驱动方法可以减小或消除阈值补偿过程中的开关误差，提高显示面板显示的均匀性。
虽然上文中已经用一般性说明及具体实施方式，对本公开作了详尽的描述，但在本公开实施例基础上，可以对之作一些修改或改进，这对本领域技术人员而言是显而易见的。因此，在不偏离本公开精神的基础上所做的这些修改或改进，均属于本公开要求保护的范围。
本申请要求于2016年11月18日递交的中国专利申请第201611014202.7号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (23)

  1. 一种像素电路，包括：
    驱动晶体管，包括与第一电源线连接以接收第一电源电压的第一极、与第一节点连接的栅极以及与第二节点连接的第二极；
    第一晶体管，包括与所述第二节点连接的第一极、与第一控制信号线连接以接收第一控制信号的栅极以及与所述第一节点连接的第二极；
    第一电容，包括与所述第一节点连接的第一端以及与第三节点连接的第二端；
    有机发光二极管，被配置为在工作时在所述驱动晶体管的驱动下发光；以及
    开关误差补偿电路，与所述第一节点和/或所述第二节点连接，被配置为补偿所述第一晶体管的开关误差。
  2. 根据权利要求1所述的像素电路，其中，所述开关误差补偿电路包括第一补偿晶体管，所述第一补偿晶体管的第一极和/或第二极与所述第一节点连接，所述第一补偿晶体管的栅极与发光控制信号线连接以接收发光控制信号。
  3. 根据权利要求2所述的像素电路，其中，所述第一补偿晶体管与所述第一晶体管由同一工艺制成。
  4. 根据权利要求1-3任一项所述的像素电路，其中，所述开关误差补偿电路包括补偿电容，所述补偿电容的第一端与所述第一节点连接，所述补偿电容的第二端与所述第二节点连接。
  5. 根据权利要求1-3任一项所述的像素电路，其中，所述开关误差补偿电路包括第二补偿晶体管，所述第二补偿晶体管的第一极与所述第二节点连接，所述第二补偿晶体管的第二极与放电电压线连接以接收所述放电电压，所述第二补偿晶体管的栅极与补偿控制信号线连接以接收补偿控制信号。
  6. 根据权利要求1-5任一项所述的像素电路，还包括：
    数据写入电路，被配置为接收所述第一控制信号和数据信号并根据所述第一控制信号向所述第三节点写入所述数据信号。
  7. 根据权利要求6所述的像素电路，其中，所述数据写入电路包括第二晶体管，所述第二晶体管的第一极与数据信号线连接以接收所述数据信号，所述第二晶体管的第二极与所述第三节点连接，所述第二晶体管的栅极与所述第 一控制信号线连接以接收所述第一控制信号。
  8. 根据权利要求1-7任一项所述的像素电路，还包括：
    第一参考电压写入电路，被配置为接收发光控制信号和第一参考电压并根据所述发光控制信号向所述第三节点写入所述第一参考电压。
  9. 根据权利要求8所述的像素电路，其中，所述第一参考电压写入电路包括第三晶体管，所述第三晶体管的第一极与第一参考电压线连接以接收所述第一参考电压，所述第三晶体管的第二极与所述第三节点连接，所述第三晶体管的栅极与发光控制信号线连接以接收所述发光控制信号。
  10. 根据权利要求1-9任一项所述的像素电路，还包括：
    发光控制电路，被配置为接收发光控制信号并根据所述发光控制信号控制所述有机发光二极管发光。
  11. 根据权利要求10所述的像素电路，其中，所述发光控制电路包括第四晶体管，所述第四晶体管的第一极与所述第二节点连接，所述第四晶体管的第二极与第四节点连接，所述第四晶体管的栅极与发光控制信号线连接以接收所述发光控制信号，所述有机发光二极管包括与所述第四节点连接的第一极以及与第二电源线连接以接收第二电源电压的第二极。
  12. 根据权利要求1-11任一项所述的像素电路，还包括：
    第二参考电压写入电路，被配置为接收第二控制信号和第二参考电压并根据所述第二控制信号向所述第三节点写入所述第二参考电压。
  13. 根据权利要求12所述的像素电路，其中，所述第二参考电压写入电路包括第五晶体管，所述第五晶体管的第一极与第二参考电压线连接以接收所述第二参考电压，所述第五晶体管的第二极与所述第三节点连接，所述第五晶体管的栅极与第二控制信号线连接以接收所述第二控制信号。
  14. 根据权利要求1-13任一项所述的像素电路，还包括：
    放电电路，被配置为接收第二控制信号和放电电压并根据所述第二控制信号向所述第一节点写入所述放电电压。
  15. 根据权利要求14所述的像素电路，其中，所述放电电路包括第六晶体管，所述第六晶体管的第一极与所述第一节点连接，所述第六晶体管的第二极与放电电压线连接以接收所述放电电压，所述第六晶体管的栅极与第二控制信号线连接以接收所述第二控制信号。
  16. 根据权利要求1-15任一项所述的像素电路，还包括第二电容，
    其中，所述第二电容的第一端与所述第一电源线连接以接收所述第一电源电压，所述第二电容的第二端与所述第一节点连接。
  17. 一种显示面板，包括如权利要求1-16任一项所述的像素电路。
  18. 一种显示设备，包括如权利要求17所述的显示面板。
  19. 一种如权利要求1-16任一项所述的像素电路的驱动方法，包括复位阶段、数据写入阶段、开关误差补偿阶段和发光阶段，其中，
    在所述复位阶段，对所述第一节点进行复位；
    在所述数据写入阶段，写入数据信号；
    在所述开关误差补偿阶段，补偿所述第一晶体管的开关误差；
    在所述发光阶段，驱动所述有机发光二极管发光。
  20. 根据权利要求19所述的驱动方法，其中，
    所述开关误差补偿电路包括第一补偿晶体管，所述第一补偿晶体管的第一极、第二极与所述第一节点连接，所述第一补偿晶体管的栅极与发光控制信号线连接以接收发光控制信号，
    其中，在所述数据写入阶段，所述第一控制信号为开启电压，所述发光控制信号为关闭电压；
    在所述开关误差补偿阶段，所述第一控制信号为关闭电压，所述发光控制信号为关闭电压；
    在所述发光阶段，所述第一控制信号为关闭电压，所述发光控制信号为开启电压。
  21. 根据权利要求19所述的驱动方法，其中，
    所述开关误差补偿电路包括补偿电容，所述补偿电容的第一端与所述第一节点连接，所述补偿电容的第二端与所述第二节点连接，
    其中，在所述数据写入阶段，所述第一控制信号为开启电压，所述发光控制信号为关闭电压；
    在所述开关误差补偿阶段，所述第一控制信号为关闭电压，所述发光控制信号为关闭电压；
    在所述发光阶段，所述第一控制信号为关闭电压，所述发光控制信号为开启电压。
  22. 根据权利要求19所述的驱动方法，其中，
    所述开关误差补偿电路包括第二补偿晶体管，所述第二补偿晶体管的第一 极与所述第二节点连接，所述第二补偿晶体管的第二极与放电电压线连接以接收放电电压，所述第二补偿晶体管的栅极与补偿控制信号线连接以接收补偿控制信号，
    其中，在所述数据写入阶段，所述第一控制信号为开启电压，所述发光控制信号为关闭电压，所述补偿控制信号为关闭电压；
    在所述开关误差补偿阶段，所述第一控制信号为关闭电压，所述发光控制信号为关闭电压，所述补偿控制信号为开启电压；
    在所述发光阶段，所述第一控制信号为关闭电压，所述发光控制信号为开启电压，所述补偿控制信号为关闭电压。
  23. 根据权利要求22所述的驱动方法，其中，当所述第一控制信号由开启电压变化为关闭电压时，所述补偿控制信号由关闭电压同步变化为开启电压。
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