WO2022082751A1 - 像素电路、显示面板及显示装置 - Google Patents

像素电路、显示面板及显示装置 Download PDF

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Publication number
WO2022082751A1
WO2022082751A1 PCT/CN2020/123332 CN2020123332W WO2022082751A1 WO 2022082751 A1 WO2022082751 A1 WO 2022082751A1 CN 2020123332 W CN2020123332 W CN 2020123332W WO 2022082751 A1 WO2022082751 A1 WO 2022082751A1
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Prior art keywords
transistor
compensation
electrically connected
base substrate
electrode
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PCT/CN2020/123332
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English (en)
French (fr)
Inventor
王丽
殷新社
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/433,068 priority Critical patent/US11776449B2/en
Priority to PCT/CN2020/123332 priority patent/WO2022082751A1/zh
Priority to CN202080002451.2A priority patent/CN114830216B/zh
Publication of WO2022082751A1 publication Critical patent/WO2022082751A1/zh
Priority to US18/452,795 priority patent/US20230401990A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/067—Special waveforms for scanning, where no circuit details of the gate driver are given
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/066—Adjustment of display parameters for control of contrast

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a pixel circuit, a display panel and a display device.
  • OLED Organic Light Emitting Diode
  • QLED Quantum Dot Light Emitting Diode
  • Micro LED Micro Light Emitting Diode
  • other electroluminescent diodes have self-illumination, low energy consumption, etc.
  • the advantages are one of the hot spots in the field of application research of display devices today.
  • a pixel circuit is used to drive an electroluminescent diode to emit light.
  • the data voltage may exceed the output range of the driver IC (Integrated Circuit), resulting in the problem that the dark state is not black enough, affecting the display device. contrast.
  • driver IC Integrated Circuit
  • the gate of the data writing transistor is electrically connected to the first scan line, the first pole of the data writing transistor is electrically connected to the data line, and the second pole of the data writing transistor is electrically connected to the drive
  • the first electrode of the transistor is electrically connected; wherein, the material of the active layer of the data writing transistor is a low temperature polysilicon material;
  • the gate of the threshold compensation transistor is electrically connected to the second scan line
  • the first pole of the threshold compensation transistor is electrically connected to the gate of the driving transistor
  • the second pole of the threshold compensation transistor is electrically connected to The second electrode of the driving transistor is electrically connected
  • the material of the active layer of the threshold compensation transistor is a metal oxide semiconductor material
  • the compensation circuit is electrically connected to the gate of the driving transistor
  • the light-emitting control circuit is respectively electrically connected to the first power supply terminal, the first electrode and the second electrode of the driving transistor and the first electrode of the light-emitting device, and is configured to, under the control of the signal of the light-emitting control line, connect the The first power supply terminal is connected with the first electrode of the driving transistor, and the second electrode of the driving transistor is connected with the first electrode of the light-emitting device, so as to drive the light-emitting device to emit light.
  • the compensation circuit is configured to compensate the voltage of the gate of the drive transistor according to parasitic capacitance.
  • the compensation circuit includes: a first compensation capacitor
  • the first electrode of the first compensation capacitor is electrically connected to the gate of the driving transistor, and the second electrode of the first compensation capacitor is electrically connected to the first scan line.
  • the parasitic capacitance includes a channel capacitance between a gate and a first electrode of the threshold compensation transistor.
  • the capacitance value of the channel capacitance between the gate and the first electrode of the threshold compensation transistor is a first channel capacitance value
  • the capacitance value of the first compensation capacitance is the same as that of the first channel capacitance. The difference between the capacitance values satisfies 0 ⁇ c1.
  • the compensation circuit includes: a first compensation control transistor
  • the gate of the first compensation control transistor is electrically connected to the first scan line, and both the first electrode and the second electrode of the first compensation control transistor are electrically connected to the gate of the driving transistor.
  • the parasitic capacitance includes a channel capacitance between the gate and the first electrode of the threshold compensation transistor, and the threshold compensation transistor has a capacitance value of the channel capacitance between the gate and the first electrode. is the first channel capacitance value;
  • the capacitance value of the channel capacitance between the gate and the first electrode of the first compensation control transistor is the second channel capacitance value
  • the channel capacitance between the gate and the second electrode of the first compensation control transistor is The capacitance value of the capacitor is the third channel capacitance value
  • the sum of the second channel capacitance value and the third channel capacitance value is the total channel capacitance value
  • the difference between the total channel capacitance value and the first channel capacitance value satisfies 0 ⁇ c2.
  • the compensation circuit includes: a second compensation control transistor
  • the gate of the second compensation control transistor is electrically connected to the first scan line
  • the first electrode of the first compensation control transistor is electrically connected to the gate of the driving transistor
  • the first electrode of the first compensation control transistor is electrically connected to the gate of the driving transistor.
  • the second pole is floating.
  • the parasitic capacitance includes a channel capacitance between the gate and the first electrode of the threshold compensation transistor, and the threshold compensation transistor has a capacitance value of the channel capacitance between the gate and the first electrode. is the first channel capacitance value;
  • the capacitance value of the channel capacitance between the gate and the first electrode of the second compensation control transistor is a fourth channel capacitance value
  • the difference between the fourth channel capacitance value and the first channel capacitance value satisfies 0 ⁇ c3.
  • the compensation circuit includes: a second compensation capacitor
  • the first electrode of the second compensation capacitor is electrically connected to the gate of the driving transistor, and the second electrode of the second compensation capacitor is electrically connected to the first electrode of the light emitting device.
  • the pixel circuit further includes: a first reset transistor
  • the gate of the first reset transistor is electrically connected to the first reset line
  • the first pole of the first reset transistor is electrically connected to the initialization signal line
  • the second pole of the first reset transistor is electrically connected to the drive transistor.
  • the grid is electrically connected.
  • the material of the active layer of the first reset transistor is a metal oxide semiconductor material.
  • the pixel circuit further includes: a second reset transistor
  • the gate of the second reset transistor is electrically connected to the second reset line
  • the first pole of the second reset transistor is electrically connected to the initialization signal line
  • the second pole of the second reset transistor is electrically connected to the light emitting device.
  • the first electrodes are electrically connected.
  • the driving circuit includes: a first light emission control transistor, a second light emission control transistor, and a storage capacitor;
  • the gate of the first light-emitting control transistor is electrically connected to the light-emitting control line
  • the first electrode of the first light-emitting control transistor is electrically connected to the first power supply terminal
  • the second light-emitting control transistor is electrically connected to the first power supply terminal.
  • the pole is electrically connected to the first pole of the driving transistor
  • the gate of the second light-emitting control transistor is electrically connected to the light-emitting control line
  • the first electrode of the second light-emitting control transistor is electrically connected to the second electrode of the driving transistor
  • the second light-emitting control transistor is electrically connected to the second electrode of the driving transistor.
  • the second electrode is electrically connected to the first electrode of the light emitting device
  • the first pole of the storage capacitor is electrically connected to the first power supply terminal, and the second pole of the storage capacitor is electrically connected to the gate of the driving transistor.
  • a base substrate including a plurality of sub-pixels, the sub-pixels include a pixel circuit, and the pixel circuit includes a first compensation capacitor and a driving transistor;
  • a first conductive layer located on the base substrate, and the first conductive layer includes a first scan line and a gate of a driving transistor; wherein one row of sub-pixels corresponds to one of the first scan lines;
  • a first interlayer dielectric layer located on the side of the first conductive layer away from the base substrate;
  • the second conductive layer is located on the side of the first interlayer dielectric layer away from the base substrate, and the second conductive layer includes a compensation conductive portion; wherein, the sub-pixel includes the compensation conductive portion, and the same In the sub-pixel, the compensation conductive portion is electrically connected to the gate of the driving transistor;
  • the difference between the orthographic projection of the first scan line on the base substrate and the orthographic projection of the compensation conductive portion on the base substrate There is a first overlap area between the two, the first compensation capacitor is located in the first overlap area, and the first compensation capacitor is formed by the overlap portion between the first scan line and the compensation conductive portion .
  • the orthographic projection of the first scan line on the base substrate covers the compensation conductive portion on the base substrate. Orthographic projection.
  • the pixel circuit further includes a threshold compensation transistor; the display panel further includes:
  • a second interlayer dielectric layer located on the side of the second conductive layer away from the base substrate;
  • an oxide semiconductor layer located on the side of the second interlayer dielectric layer away from the base substrate, and the oxide semiconductor layer includes an active layer of the threshold compensation transistor;
  • a second gate insulating layer located on the side of the oxide semiconductor layer away from the base substrate;
  • a third conductive layer is located on the side of the second gate insulating layer away from the base substrate, and the third conductive layer includes a second scan line; wherein one row of sub-pixels corresponds to one of the second scan lines;
  • the orthographic projection of the active layer of the threshold compensation transistor on the base substrate and the second scan line on the base substrate has a second overlapping area; a first part of the capacitance of the channel capacitance of the threshold compensation transistor is located in the second overlapping area, and the first part of the capacitance is determined by the second scan line and the threshold compensation transistor.
  • the second conductive layer further includes an auxiliary scan line; wherein, one row of sub-pixels corresponds to one of the auxiliary scan lines;
  • the active layer of the auxiliary scan line and the threshold compensation transistor has a third overlapping area on the orthographic projection of the base substrate;
  • the second part of the capacitance of the channel capacitance of the threshold compensation transistor is located in the third overlapping region, and the second part of the capacitance is determined by the intersection between the auxiliary scan line and the active layer of the threshold compensation transistor. Stacked parts are formed.
  • the orthographic projection of the second scan line on the base substrate is the same as that of the auxiliary scan line on the base substrate.
  • the orthographic projections overlap.
  • the display panel further includes:
  • a third interlayer dielectric layer located on the side of the third conductive layer away from the base substrate;
  • the fourth conductive layer is located on the side of the third interlayer dielectric layer away from the base substrate, and the fourth conductive layer includes a first connection part; wherein, the first end of the first connection part passes through the first connection part.
  • a via hole is electrically connected to the compensation conductive portion, and the second end of the first connection portion is electrically connected to the gate of the driving transistor through a second via hole; the first via hole penetrates through the third layer an interlayer dielectric layer, the second gate insulating layer, and the second interlayer dielectric layer, and the second via hole penetrates the third interlayer dielectric layer, the second gate insulating layer, and the second layer an interlayer dielectric layer and the first interlayer dielectric layer.
  • the third end of the first connection portion is electrically connected to the conductive region of the active layer of the threshold compensation transistor through a third via hole; the third via hole penetrates the second gate insulation layer and the third interlayer dielectric layer.
  • the orthographic projection of the first scan line on the base substrate covers the third via hole at Orthographic projection of the base substrate.
  • first end and the third end of the first connection part extend in substantially the same direction, and the first end, the second end and the third end of the first connection part substantially form a "T" shape type.
  • the second scan line has a fourth overlap between the orthographic projection of the base substrate and the orthographic projection of the first connection portion on the base substrate region, the fourth overlapping region has an auxiliary capacitor, and the auxiliary capacitor is formed by the overlapping portion between the second scan line and the first connection portion;
  • the capacitance value of the auxiliary capacitor is approximately ⁇ c1.
  • the display panel further includes:
  • an interlayer insulating layer located on the side of the fourth conductive layer away from the base substrate;
  • a fifth conductive layer located on the side of the interlayer insulating layer away from the base substrate, and the fifth conductive layer includes a data line and a power supply line; wherein one column of sub-pixels corresponds to one of the data lines and one of the power cable;
  • the orthographic projection of the power supply line on the base substrate overlaps with the orthographic projection of the active layer of the threshold compensation transistor on the base substrate area.
  • the power supply line for the power supply line, the first via hole, the second via hole, the third via hole, and the third overlapping region corresponding to the same sub-pixel, the power supply
  • the orthographic projection of the line on the base substrate and the first via hole, the second via hole and the third via hole respectively have overlapping areas, and the power line is on the front side of the base substrate. The projection does not overlap the fourth overlapping area.
  • the pixel circuit further includes a first reset transistor, and the oxide semiconductor layer further includes an active layer of the first reset transistor;
  • the third conductive layer further includes a first reset line; wherein, one row of sub-pixels corresponds to one of the first reset lines;
  • the orthographic projection of the first reset line on the base substrate is where the active layer of the first reset transistor is located.
  • the orthographic projection of the base substrate has an overlapping area.
  • the orthographic projection of the power supply line on the base substrate and the active layer of the first reset transistor on the substrate have overlapping regions.
  • the orthographic projection of the first scan line on the base substrate is located at The second scan line and the first reset line are between orthographic projections of the base substrate.
  • the pixel circuit further includes a data writing transistor; the display panel further includes:
  • a silicon semiconductor layer located between the first conductive layer and the base substrate, and the silicon semiconductor layer includes an active layer of the data writing transistor;
  • a first gate insulating layer located between the first conductive layer and the silicon semiconductor layer
  • the orthographic projection of the first scan line on the base substrate is where the active layer of the data writing transistor is located.
  • the orthographic projection of the base substrate has an overlapping area.
  • the compensation conductive portion is orthographically projected on the base substrate between the orthographic projection of the active layer of the data writing transistor on the base substrate and the orthographic projection of the active layer of the threshold compensation transistor corresponding to the third via hole on the base substrate.
  • the display device provided by the embodiment of the present disclosure includes the above-mentioned display panel.
  • FIG. 1 is a schematic structural diagram of some pixel circuits in an embodiment of the disclosure
  • FIG. 2 is a schematic structural diagram of other pixel circuits in an embodiment of the disclosure.
  • FIG. 3 is a signal timing diagram of some pixel circuits in an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of further pixel circuits in an embodiment of the disclosure.
  • FIG. 5 is a schematic structural diagram of further pixel circuits in an embodiment of the disclosure.
  • FIG. 6 is a schematic structural diagram of further pixel circuits in an embodiment of the disclosure.
  • FIG. 7a is a schematic structural diagram of further pixel circuits in an embodiment of the disclosure.
  • FIG. 7b is a signal timing diagram of further pixel circuits in an embodiment of the disclosure.
  • FIG. 8a is a schematic structural diagram of further pixel circuits in an embodiment of the disclosure.
  • FIG. 8b is a signal timing diagram of further pixel circuits in an embodiment of the disclosure.
  • FIG. 9 is a schematic structural diagram of some display panels in an embodiment of the disclosure.
  • FIG. 10 is a schematic diagram of a layout structure of pixel circuits in some display panels according to an embodiment of the disclosure.
  • 11a is a schematic diagram of a layout structure of a silicon semiconductor layer in some display panels according to an embodiment of the disclosure.
  • 11b is a schematic diagram of a layout structure of a first conductive layer in some display panels according to an embodiment of the disclosure.
  • 11c is a schematic diagram of a layout structure of a second conductive layer in some display panels according to an embodiment of the disclosure.
  • FIG. 11d is a schematic diagram of the layout structure of oxide semiconductor layers in some display panels according to an embodiment of the disclosure.
  • 11e is a schematic diagram of a layout structure of a third conductive layer in some display panels according to an embodiment of the disclosure.
  • 11f is a schematic diagram of a layout structure of a fourth conductive layer in some display panels according to an embodiment of the disclosure.
  • 11g is a schematic diagram of a layout structure of a fifth conductive layer in some display panels according to an embodiment of the disclosure.
  • FIG. 12 is a cross-sectional structural view along the AA' direction of the schematic layout structure of the pixel circuit in the display panel shown in FIG. 10;
  • FIG. 13 is a cross-sectional structural view along the BB' direction of the schematic layout structure of the pixel circuit in the display panel shown in FIG. 10 .
  • An embodiment of the present disclosure provides a pixel circuit, as shown in FIG. 1 , which may include:
  • the data writing transistor M3, the gate of the data writing transistor M3 is electrically connected to the first scan line G1, the first pole of the data writing transistor M3 is electrically connected to the data line DA, and the second pole of the data writing transistor M3 is electrically connected to the drive
  • the first pole of the transistor M0 is electrically connected; wherein, the material of the active layer of the data writing transistor M3 is a low temperature polysilicon material;
  • Threshold compensation transistor M2 the gate of the threshold compensation transistor M2 is electrically connected to the second scan line G2, the first pole of the threshold compensation transistor M2 is electrically connected to the gate of the driving transistor M0, and the second pole of the threshold compensation transistor M2 is electrically connected to the driving transistor The second electrode of M0 is electrically connected; wherein, the material of the active layer of the threshold compensation transistor M2 is a metal oxide semiconductor material;
  • the compensation circuit 10 is electrically connected to the gate of the driving transistor M0, and is configured to compensate the channel capacitance between the gate of the transistor M2 and the first electrode according to the threshold value, and the voltage of the gate of the driving transistor M0 is adjusted. compensate;
  • the light-emitting control circuit 20 is respectively electrically connected to the first power supply terminal VDD, the first electrode and the second electrode of the driving transistor M0 and the first electrode of the light-emitting device L, and is configured to be controlled by the signal of the light-emitting control line EM,
  • the first power supply terminal VDD is turned on with the first electrode of the driving transistor M0
  • the second electrode of the driving transistor M0 is turned on with the first electrode of the light emitting device L to drive the light emitting device L to emit light.
  • the above-mentioned pixel circuit provided by the embodiment of the present disclosure is provided with a compensation circuit electrically connected to the gate of the driving transistor, and the compensation circuit can compensate the channel capacitance between the gate and the first electrode of the transistor M2 according to the threshold value, so as to compensate the driving transistor M2.
  • the gate voltage is compensated. In this way, when the level of the signal of the second scan line G2 is switched, the gate voltage of the driving transistor M0 can be pulled down by the compensation circuit due to the channel capacitance between the gate of the threshold compensation transistor M2 and the first electrode.
  • the voltage ⁇ Vn1 is compensated, so that the stability of the gate voltage of the driving transistor can be improved.
  • the first pole of the light emitting device L is electrically connected to the light emitting control circuit 20
  • the second pole of the light emitting device L is electrically connected to the second power supply terminal VSS.
  • the first pole of the light emitting device L electrically connected to the light emitting control circuit 20 is its positive pole
  • the second pole electrically connected to the second power supply terminal VSS is its negative pole.
  • the light-emitting device L may be an electroluminescent diode, such as OLED, QLED, Micro LED, Mini LED.
  • the light emitting device L realizes light emission under the action of the current when the driving transistor M0 is in a saturated state.
  • the light-emitting device L has a turn-on voltage, and emits light when the voltage difference between the two ends of the light-emitting device L is greater than or equal to the turn-on voltage.
  • the voltage Vdd of the first power supply terminal VDDVDD is generally positive
  • the voltage Vss of the second power supply terminal VSS is generally grounded or negative.
  • the voltage Vinit of the initialization signal line VINIT and the voltage Vss of the second power supply terminal VSS need to satisfy the formula: Vinit-Vss ⁇ VL; wherein, VL is the turn-on voltage of the light-emitting device L.
  • the driving transistor M0 may be a P-type transistor; wherein, the gate of the driving transistor M0 may be its gate, and the first pole of the driving transistor M0 may be The source electrode and the second electrode of the driving transistor M0 can be its drain electrode.
  • the driving transistor M0 may also be an N-type transistor; wherein, the gate of the driving transistor M0 may be its gate, the first pole of the driving transistor M0 may be its drain, and the second pole of the driving transistor M0 may be its source pole.
  • the type of the driving transistor M0 can be specifically designed and determined according to the requirements of the practical application, which is not limited herein.
  • the compensation circuit 10 may include: a first compensation capacitor CF1 ; wherein the first electrode of the first compensation capacitor CF1 is electrically connected to the gate of the driving transistor M0 , the second pole of the first compensation capacitor CF1 is electrically connected to the first scan line G1.
  • the capacitance value of the channel capacitance between the gate and the first pole of the threshold compensation transistor M2 is the first channel capacitance value CgsT2, the capacitance value Cf1 of the first compensation capacitor CF1 and the first channel capacitance value CgsT2 The difference between them satisfies 0 ⁇ c1.
  • ⁇ c1 may be 0.1, or ⁇ c1 may be 0.01, or ⁇ c1 may be 0.05, which is not limited herein.
  • the capacitance value of the first compensation capacitor CF1 and the capacitance value of the first channel are not exactly the same, and there may be some deviations.
  • the same relationship between the capacitance value of the compensation capacitor CF1 and the capacitance value of the first channel only needs to roughly satisfy the above-mentioned conditions, and all belong to the protection scope of the present disclosure. For example, when the difference between the capacitance value of the first compensation capacitor CF1 and the first channel capacitance value satisfies 0 ⁇ c1, it can be considered that the difference is allowed within the allowable error range.
  • the pixel circuit may further include: a first reset transistor M1; the gate of the first reset transistor M1 is electrically connected to the first reset line S1, and the first reset transistor M1 is electrically connected to the first reset line S1.
  • the first electrode of the transistor M1 is electrically connected to the initialization signal line VINIT, and the second electrode of the first reset transistor M1 is electrically connected to the gate of the driving transistor M0.
  • the pixel circuit further includes: a second reset transistor M4; wherein the gate of the second reset transistor M4 is electrically connected to the second reset line S2, and the second reset transistor M4 is electrically connected to the second reset line S2.
  • the first electrode of the reset transistor M4 is electrically connected to the initialization signal line VINIT, and the second electrode of the second reset transistor M4 is electrically connected to the first electrode of the light emitting device L.
  • the second reset line S2 and the first scan line G1 may be the same signal terminal.
  • the gate of the data writing transistor M3 and the gate of the second reset transistor M4 are both electrically connected to the first scan line G1.
  • the driving circuit may include: a first light-emitting control transistor M5, a second light-emitting control transistor M6 and a storage capacitor C1; wherein, the first light-emitting control transistor M5 The gate is electrically connected to the emission control line EM, the first electrode of the first emission control transistor M5 is electrically connected to the first power supply terminal VDD, and the second electrode of the first emission control transistor M5 is electrically connected to the first electrode of the driving transistor M0.
  • the gate of the second light-emitting control transistor M6 is electrically connected to the light-emitting control line EM
  • the first electrode of the second light-emitting control transistor M6 is electrically connected to the second electrode of the driving transistor M0
  • the second electrode of the second light-emitting control transistor M6 is connected to the light-emitting control line EM.
  • the first electrode of the device L is electrically connected.
  • the first pole of the storage capacitor C1 is electrically connected to the first power supply terminal VDD, and the second pole of the storage capacitor C1 is electrically connected to the gate of the driving transistor M0.
  • the data writing transistor M3 , the second reset transistor M4 , the first light emission control transistor M5 , the second light emission control transistor M6 and the driving transistor M0 may all be configured as P-type transistors.
  • the data writing transistor M3, the second reset transistor M4, the first light-emitting control transistor M5, the second light-emitting control transistor M6, and the driving transistor M0 can also be configured as N-type transistors.
  • the specific types of the data writing transistor M3, the second reset transistor M4, the first light-emitting control transistor M5, the second light-emitting control transistor M6 and the driving transistor M0 can be determined according to the requirements of the actual application. This is not limited.
  • both the first reset transistor M1 and the threshold compensation transistor M2 may be set as N-type transistors.
  • both the first reset transistor M1 and the threshold compensation transistor M2 may be configured as P-type transistors.
  • the specific types of the first reset transistor M1 and the threshold compensation transistor M2 can be determined by design according to the requirements of the practical application, which are not limited herein.
  • the P-type transistor is turned on under the action of a low-level signal, and turned off under the action of a high-level signal;
  • the N-type transistor is turned on under the action of a high-level signal, and is turned off under the action of a low-level signal Cut off under the action of the signal.
  • the gate of the transistor may be used as its gate, the first electrode may be used as its source, the second electrode may be used as its drain, or the first electrode of the transistor may be used as its drain. pole, the second pole is used as its source, and no specific distinction is made here.
  • a low temperature polysilicon (Low Temperature Poly-Silicon, LTPS) material is used as the active layer of the transistor, which has high mobility and can be made thinner and smaller, with lower power consumption, etc.
  • the material of the active layer of the driving transistor M0 may include low temperature polysilicon material
  • the material of the active layer of the data writing transistor M3 may include low temperature polysilicon material
  • the material of the second reset transistor M4 may include low temperature polysilicon material
  • the material of the transistor M5 may include low temperature polysilicon material
  • the material of the second light emission control transistor M6 may include low temperature polysilicon material.
  • the data writing transistor M3, the second reset transistor M4, the first light-emitting control transistor M5, the second light-emitting control transistor M6 and the driving transistor M0 are all set as LTPS transistors, so that the data writing transistor M3, the second reset transistor M4 , the first light-emitting control transistor M5 , the second light-emitting control transistor M6 and the driving transistor M0 have high mobility and can be made thinner and smaller, with lower power consumption and the like.
  • the leakage current of a transistor using a metal oxide semiconductor material as the active layer is relatively small. Therefore, in order to reduce the leakage current, during specific implementation, in the embodiment of the present disclosure, the material of the active layer of the first reset transistor M1 may include Metal-oxide-semiconductor material, the material of the active layer of the threshold compensation transistor M2 may include metal-oxide-semiconductor material. That is, both the first reset transistor M1 and the threshold compensation transistor M2 are set as oxide transistors, so that the leakage current of the first reset transistor M1 and the threshold compensation transistor M2 can be reduced.
  • the metal oxide semiconductor material may be IGZO (Indium GaLium Zinc Oxide, indium gallium zinc oxide).
  • the metal oxide semiconductor material may also be other metal oxide semiconductor materials, which are not limited herein.
  • the leakage current of the first reset transistor M1 and the threshold compensation transistor M2 can be reduced when they are turned off, so that when the light-emitting device L emits light, it is beneficial to reduce the interference of the leakage current on the gate voltage of the driving transistor M0, thereby enabling the driving transistor M0
  • the stability of the driving current for driving the light emitting device L to emit light is improved.
  • the pixel circuit provided by the embodiment of the present disclosure, two transistor fabrication processes, LTPS type transistor and oxide type transistor, are combined to prepare a pixel circuit of low temperature polysilicon combined with oxide, so that the drain of the gate of the driving transistor M0 is The current is smaller and the power consumption is lower. Therefore, when the pixel circuit is applied to an electroluminescence display panel display device, the stability of the gate voltage of the driving transistor M0 can be improved, especially when the display device displays with a reduced refresh frequency, the display uniformity can be guaranteed.
  • 1 means high level and 0 means low level. It should be noted that 1 and 0 are logic levels, which are only to better explain the specific working process of the embodiments of the present disclosure, rather than specific voltage values.
  • the signals of the first scan line G1 and the second scan line G2 are respectively composed of a high-level signal and a low-level signal.
  • the voltage of the high-level signal is generally the high voltage VGH
  • the voltage of the low-level signal is generally the low voltage VGL.
  • the specific values of the high voltage VGH and the low voltage VGL can be designed and determined according to actual application requirements, which are not limited here.
  • the absolute values of the high and low levels may be equal, for example, the high level is +5V and the low level is -5V. Alternatively, a high level is +6V and a low level is -6V. Alternatively, a high level is +7V and a low level is -7V. Alternatively, the absolute values of the high and low levels may also be unequal, for example, the high level is a value greater than 0, and the low level is 0V. Of course, in practical applications, the design can be determined according to the requirements of practical applications, which is not limited here.
  • the voltage of the second pole of the first compensation capacitor CF1 is the high voltage VGH of the high level signal of the first scan line G1, and the first pole is the voltage Vinit of the initialization signal line VINIT.
  • the turned-on data writing transistor M3 inputs the data voltage Vda of the data line DA to the first electrode of the driving transistor M0.
  • the turned-on threshold compensation transistor M2 turns on the gate and the second electrode of the driving transistor M0, so that the driving transistor M0 forms a diode electrical connection structure, so that the data voltage Vda charges the gate of the driving transistor M0 and drives the driving transistor M0.
  • the gate voltage of transistor M0 is successfully Vda+Vth.
  • the turned-on second reset transistor M4 supplies the signal of the initialization signal line VINIT to the first electrode of the light emitting device L to initialize the first electrode of the light emitting device L.
  • the voltage of the gate of the driving transistor M0 can vary by the voltage ⁇ Vn11 on the basis of Vda+Vth.
  • CgsT2 represents the capacitance value of the first channel
  • Cc1 represents the capacitance value of the storage capacitor C1
  • Cf1 represents the capacitance value of the first compensation capacitor CF1
  • Co represents other related capacitance values (generally fixed values).
  • the voltage of the gate of the driving transistor M0 can vary by the voltage ⁇ Vn12 on the basis of Vda+Vth. in,
  • both the first light emission control transistor M5 and the second light emission control transistor M6 are turned on.
  • the turned-on first light-emitting control transistor M5 supplies the voltage of the first power supply terminal VDD to the first electrode of the driving transistor M0.
  • the driving transistor M0 generates the operating current Ids under the action of the gate voltage and the first electrode voltage.
  • Ids K(Vdd-Vda) 2 .
  • K is a structural parameter.
  • the turned-on second light emitting control transistor M6 conducts the second electrode of the driving transistor M0 with the first electrode of the light emitting device L, so that the working current Ids drives the light emitting device L to emit light. Therefore, the operating current generated by the pixel circuit provided by the embodiment of the present disclosure has nothing to do with the threshold voltage Vth of the driving transistor M0.
  • Embodiments of the present disclosure further provide some display panels, the schematic diagram of which is shown in FIG. 4 , which is modified from the implementation in the above-mentioned embodiments. Only the differences between this embodiment and the above-mentioned embodiments will be described below, and the similarities will not be repeated here.
  • the compensation circuit 10 may include: a first compensation control transistor; wherein the gate of the first compensation control transistor is electrically connected to the first scan line G1, and the first compensation control transistor is electrically connected to the first scan line G1. Both the first electrode and the second electrode of a compensation control transistor are electrically connected to the gate of the driving transistor M0.
  • the first compensation control transistor may be a P-type transistor.
  • the material of the active layer of the first compensation control transistor may be a low temperature polysilicon material or a metal oxide semiconductor material, which is not limited herein.
  • the capacitance value of the channel capacitance between the gate and the first electrode of the first compensation control transistor is the second channel capacitance value CgsMF1
  • the gate of the first compensation control transistor is The capacitance value of the channel capacitance between the second pole and the second pole is the third channel capacitance value CgdMF1; the sum of the second channel capacitance value CgsMF1 and the third channel capacitance value CgdMF1 is the total channel capacitance value CmMF1.
  • the difference between the total channel capacitance value CmMF1 and the first channel capacitance value CgsT2 satisfies 0 ⁇ c2.
  • ⁇ c2 may be 0.1, or ⁇ c2 may be 0.01, or ⁇ c2 may be 0.05, which is not limited herein.
  • the above-mentioned first channel capacitance value and the total channel capacitance value may not be exactly the same, and there may be some deviations. Therefore, the above-mentioned first channel capacitance value The same relationship between the value and the total channel capacitance value only needs to roughly satisfy the above-mentioned conditions, and all belong to the protection scope of the present disclosure. For example, when the difference between the first channel capacitance value and the total channel capacitance value satisfies 0 ⁇ c2, it can be regarded as the same allowed within the allowable error range.
  • 1 means high level and 0 means low level. It should be noted that 1 and 0 are logic levels, which are only to better explain the specific working process of the embodiments of the present disclosure, rather than specific voltage values.
  • the signals of the first scan line G1 and the second scan line G2 are respectively composed of a high-level signal and a low-level signal.
  • the voltage of the high-level signal is generally the high voltage VGH
  • the voltage of the low-level signal is generally the low voltage VGL.
  • the specific values of the high voltage VGH and the low voltage VGL can be designed and determined according to actual application requirements, which are not limited here.
  • the turned-on data writing transistor M3 inputs the data voltage Vda of the data line DA to the first electrode of the driving transistor M0.
  • the turned-on threshold compensation transistor M2 turns on the gate and the second electrode of the driving transistor M0, so that the driving transistor M0 forms a diode electrical connection structure, so that the data voltage Vda charges the gate of the driving transistor M0 and drives the driving transistor M0.
  • the gate voltage of transistor M0 is successfully Vda+Vth.
  • the voltage of the gate of the driving transistor M0 can vary by the voltage ⁇ Vn21 on the basis of Vda+Vth.
  • CgsT2 represents the capacitance value of the first channel
  • Cc1 represents the capacitance value of the storage capacitor C1
  • CgsMF1 represents the capacitance value of the second channel
  • CgdMF1 represents the capacitance value of the third channel
  • Co represents other related capacitance values (usually fixed values) .
  • the gate voltage of the driving transistor M0 can vary by the voltage ⁇ Vn22 on the basis of Vda+Vth. in,
  • both the first light emission control transistor M5 and the second light emission control transistor M6 are turned on.
  • the turned-on first light-emitting control transistor M5 supplies the voltage of the first power supply terminal VDD to the first electrode of the driving transistor M0.
  • the driving transistor M0 generates the operating current Ids under the action of the gate voltage and the first electrode voltage.
  • Ids K(Vdd-Vda) 2 .
  • K is a structural parameter.
  • the turned-on second light emitting control transistor M6 conducts the second electrode of the driving transistor M0 with the first electrode of the light emitting device L, so that the working current Ids drives the light emitting device L to emit light. Therefore, the operating current generated by the pixel circuit provided by the embodiment of the present disclosure has nothing to do with the threshold voltage Vth of the driving transistor M0.
  • Embodiments of the present disclosure further provide some display panels, the schematic diagram of which is shown in FIG. 5 , which is modified from the implementations in the above-mentioned embodiments. Only the differences between this embodiment and the above-mentioned embodiments will be described below, and the similarities will not be repeated here.
  • the compensation circuit 10 may also include: a second compensation control transistor; wherein the gate of the second compensation control transistor is electrically connected to the first scan line G1, The first electrode of the first compensation control transistor is electrically connected to the gate of the driving transistor M0, and the second electrode of the first compensation control transistor is floating.
  • the second compensation control transistor may be a P-type transistor.
  • the material of the active layer of the second compensation control transistor may be a low temperature polysilicon material or a metal oxide semiconductor material, which is not limited herein.
  • the capacitance value of the channel capacitance between the gate and the first electrode of the second compensation control transistor is a fourth channel capacitance value CgsMF2; wherein, the fourth channel capacitance value is The difference between CgsMF2 and the first channel capacitance value CgsT2 satisfies 0 ⁇ c3.
  • ⁇ c3 may be 0.1, or ⁇ c3 may be 0.01, or ⁇ c3 may be 0.05, which is not limited herein. It should be noted that, in the actual process, due to the limitation of process conditions or other factors, the capacitance value of the first channel and the capacitance value of the fourth channel may not be exactly the same, and there may be some deviations.
  • the same relationship between the capacitance value and the capacitance value of the fourth channel only needs to roughly satisfy the above conditions, and all belong to the protection scope of the present disclosure.
  • the difference between the first channel capacitance value and the fourth channel capacitance value satisfies 0 ⁇ c3
  • it can be regarded as the same allowed within the allowable error range.
  • 1 means high level and 0 means low level. It should be noted that 1 and 0 are logic levels, which are only to better explain the specific working process of the embodiments of the present disclosure, rather than specific voltage values.
  • the signals of the first scan line G1 and the second scan line G2 are respectively composed of a high-level signal and a low-level signal.
  • the voltage of the high-level signal is generally the high voltage VGH
  • the voltage of the low-level signal is generally the low voltage VGL.
  • the specific values of the high voltage VGH and the low voltage VGL can be designed and determined according to actual application requirements, which are not limited here.
  • the turned-on data writing transistor M3 inputs the data voltage Vda of the data line DA to the first electrode of the driving transistor M0.
  • the turned-on threshold compensation transistor M2 turns on the gate and the second electrode of the driving transistor M0, so that the driving transistor M0 forms a diode electrical connection structure, so that the data voltage Vda charges the gate of the driving transistor M0 and drives the driving transistor M0.
  • the gate voltage of transistor M0 is successfully Vda+Vth.
  • the gate voltage of the driving transistor M0 can be changed by the voltage ⁇ Vn31 on the basis of Vda+Vth.
  • CgsT2 represents the capacitance value of the first channel
  • Cc1 represents the capacitance value of the storage capacitor C1
  • CgsMF2 represents the capacitance value of the fourth channel
  • Co represents other related capacitance values (generally fixed values).
  • the voltage of the gate of the driving transistor M0 can vary by the voltage ⁇ Vn32 on the basis of Vda+Vth. in,
  • both the first light emission control transistor M5 and the second light emission control transistor M6 are turned on.
  • the turned-on first light-emitting control transistor M5 supplies the voltage of the first power supply terminal VDD to the first electrode of the driving transistor M0.
  • the driving transistor M0 generates the operating current Ids under the action of the gate voltage and the first electrode voltage.
  • Ids K(Vdd-Vda) 2 .
  • K is a structural parameter.
  • the turned-on second light emitting control transistor M6 conducts the second electrode of the driving transistor M0 with the first electrode of the light emitting device L, so that the working current Ids drives the light emitting device L to emit light. Therefore, the operating current generated by the pixel circuit provided by the embodiment of the present disclosure has nothing to do with the threshold voltage Vth of the driving transistor M0.
  • Embodiments of the present disclosure further provide some display panels, the schematic diagram of which is shown in FIG. 6 , which is modified from the implementations in the above-mentioned embodiments. Only the differences between this embodiment and the above-mentioned embodiments will be described below, and the similarities will not be repeated here.
  • the compensation circuit 10 may also include: a second compensation capacitor CF2; wherein the first electrode of the second compensation capacitor CF2 is electrically connected to the gate of the driving transistor M0 connected, the second electrode of the second compensation capacitor CF2 is electrically connected to the first electrode of the light emitting device L.
  • the capacitance value Cf2 of the second compensation capacitor CF2 is related to the first channel capacitance value CgsT2.
  • 1 means high level and 0 means low level. It should be noted that 1 and 0 are logic levels, which are only to better explain the specific working process of the embodiments of the present disclosure, rather than specific voltage values.
  • the voltage of the first electrode of the second compensation capacitor CF2 is the voltage Vinit of the initialization signal line VINIT, and the voltage of the second electrode is the voltage of the first electrode of the light emitting device L.
  • the turned-on data writing transistor M3 inputs the data voltage Vda of the data line DA to the first electrode of the driving transistor M0.
  • the turned-on threshold compensation transistor M2 turns on the gate and the second electrode of the driving transistor M0, so that the driving transistor M0 forms a diode electrical connection structure, so that the data voltage Vda charges the gate of the driving transistor M0 and drives the driving transistor M0.
  • the gate voltage of transistor M0 is successfully Vda+Vth.
  • the turned-on second reset transistor M4 supplies the signal of the initialization signal line VINIT to the first electrode of the light emitting device L to initialize the first electrode of the light emitting device L.
  • the voltage of the gate of the driving transistor M0 can vary by the voltage ⁇ Vn41 on the basis of Vda+Vth.
  • CgsT2 represents the capacitance value of the first channel
  • Cc1 represents the capacitance value of the storage capacitor C1
  • Cf2 represents the capacitance value of the second compensation capacitor CF2
  • Co represents other related capacitance values (generally fixed values).
  • the voltage of the first electrode of the light emitting device L changes from Vinit to Vss+VL
  • the voltage of the gate of the driving transistor M0 can be changed by the voltage ⁇ Vn42 on the basis of Vda+Vth.
  • both the first light emission control transistor M5 and the second light emission control transistor M6 are turned on.
  • the turned-on first light-emitting control transistor M5 supplies the voltage of the first power supply terminal VDD to the first electrode of the driving transistor M0.
  • the driving transistor M0 generates the operating current Ids under the action of the gate voltage and the first electrode voltage.
  • Ids K(Vdd-Vda) 2 .
  • K is a structural parameter.
  • the turned-on second light emitting control transistor M6 conducts the second electrode of the driving transistor M0 with the first electrode of the light emitting device L, so that the working current Ids drives the light emitting device L to emit light. Therefore, the operating current generated by the pixel circuit provided by the embodiment of the present disclosure has nothing to do with the threshold voltage Vth of the driving transistor M0.
  • Embodiments of the present disclosure further provide some display panels, the schematic structural diagram of which is shown in FIG. 7a, which is modified from the implementation in the above-mentioned embodiments. Only the differences between this embodiment and the above-mentioned embodiments will be described below, and the similarities will not be repeated here.
  • the pixel circuit may further include: a stabilization transistor M7; wherein, the gate of the stabilization transistor M7 is electrically connected to the stabilization control signal terminal VS, and the first gate of the stabilization transistor M7 is electrically connected.
  • One pole is electrically connected to the gate of the driving transistor M0
  • the second pole of the stabilization transistor M7 is electrically connected to the second pole of the first reset transistor M1 and the first pole of the threshold compensation transistor M2, respectively. That is, the second electrode of the first reset transistor M1 and the first electrode of the threshold compensation transistor M2 are electrically connected to the gate of the driving transistor M0 through the stabilization transistor M7.
  • the first reset transistor M1 and the threshold compensation transistor M2 may be P-type transistors, and the materials of the active layers of the first reset transistor M1 and the threshold compensation transistor M2 are low temperature polysilicon materials.
  • the stabilization transistor M7 may be an N-type transistor, and the material of the active layer of the stabilization transistor M7 may be a metal oxide semiconductor material.
  • 1 means high level and 0 means low level. It should be noted that 1 and 0 are logic levels, which are only to better explain the specific working process of the embodiments of the present disclosure, rather than specific voltage values.
  • the voltage of the second pole of the first compensation capacitor CF1 is the high voltage VGH of the high level signal of the first scan line G1, and the first pole is the voltage Vinit of the initialization signal line VINIT.
  • the turned-on data writing transistor M3 inputs the data voltage Vda of the data line DA to the first electrode of the driving transistor M0.
  • the turned-on threshold compensation transistor M2 and the stabilization transistor M7 turn on the gate and the second electrode of the driving transistor M0, so that the driving transistor M0 forms a diode electrical connection structure, so that the data voltage Vda charges the gate of the driving transistor M0 , and the gate voltage of the driving transistor M0 is successfully Vda+Vth.
  • the turned-on second reset transistor M4 supplies the signal of the initialization signal line VINIT to the first electrode of the light emitting device L to initialize the first electrode of the light emitting device L.
  • the voltage of the gate of the driving transistor M0 can vary by the voltage ⁇ Vn11 on the basis of Vda+Vth.
  • CgsT2 represents the capacitance value of the first channel
  • Cc1 represents the capacitance value of the storage capacitor C1
  • Cf1 represents the capacitance value of the first compensation capacitor CF1
  • Co represents other related capacitance values (generally fixed values).
  • the voltage of the gate of the driving transistor M0 can vary by the voltage ⁇ Vn12 on the basis of Vda+Vth. in,
  • both the first light emission control transistor M5 and the second light emission control transistor M6 are turned on.
  • the turned-on first light-emitting control transistor M5 supplies the voltage of the first power supply terminal VDD to the first electrode of the driving transistor M0.
  • the driving transistor M0 generates the operating current Ids under the action of the gate voltage and the first electrode voltage.
  • Ids K(Vdd-Vda) 2 .
  • K is a structural parameter.
  • the turned-on second light emitting control transistor M6 conducts the second electrode of the driving transistor M0 with the first electrode of the light emitting device L, so that the working current Ids drives the light emitting device L to emit light. Therefore, the operating current generated by the pixel circuit provided by the embodiment of the present disclosure has nothing to do with the threshold voltage Vth of the driving transistor M0.
  • Embodiments of the present disclosure further provide some display panels, the schematic diagram of which is shown in FIG. 8 a , which is modified from the implementations in the above-mentioned embodiments. Only the differences between this embodiment and the above-mentioned embodiments will be described below, and the similarities will not be repeated here.
  • the pixel circuit may include: a first reset transistor M1, a threshold compensation transistor M2, a data writing transistor M3, a second reset transistor M4, and a second light-emitting control transistor M1.
  • Transistor M6 first reference transistor M8, second reference transistor M9, storage capacitor C1 and first compensation capacitor CF1.
  • the electrical connection relationship between the compensation capacitors CF1 is shown in FIG. 8 a , which is not repeated here.
  • 1 means high level and 0 means low level. It should be noted that 1 and 0 are logic levels, which are only to better explain the specific working process of the embodiments of the present disclosure, rather than specific voltage values.
  • both the data writing transistor M3 and the second reset transistor M4 are turned on.
  • the turned-on data writing transistor M3 inputs the data voltage Vda of the data line DA to the storage capacitor C1.
  • the turned-on threshold compensation transistor M2 turns on the gate and the second electrode of the driving transistor M0, so that the driving transistor M0 forms a diode electrical connection structure, so that the first power supply terminal VDD charges the gate of the driving transistor M0, and
  • the gate voltage of the drive transistor M0 is successfully made to be Vdd+Vth.
  • Vdd is the voltage of the first power supply terminal VDD.
  • the voltage of the gate of the driving transistor M0 can vary by the voltage ⁇ Vn11 on the basis of Vdd+Vth.
  • CgsT2 represents the capacitance value of the first channel
  • Cc1 represents the capacitance value of the storage capacitor C1
  • Cf1 represents the capacitance value of the first compensation capacitor CF1
  • Co represents other related capacitance values (generally fixed values).
  • the voltage of the gate of the driving transistor M0 can vary by the voltage ⁇ Vn12 on the basis of Vdd+Vth. in,
  • both the first reference transistor M8 and the second light emission control transistor M6 are turned on.
  • the turned-on first reference transistor M8 supplies the voltage of the reference signal terminal VREF to the storage capacitor C1, so that the voltage of the driving transistor M0 becomes Vdd+Vth+Vda. Therefore, the driving transistor M0 generates the operating current Ids under the action of the gate voltage and the first electrode voltage.
  • Ids K(Vda) 2 .
  • K is a structural parameter.
  • the turned-on second light emitting control transistor M6 conducts the second electrode of the driving transistor M0 with the first electrode of the light emitting device L, so that the working current Ids drives the light emitting device L to emit light. Therefore, the operating current generated by the pixel circuit provided by the embodiment of the present disclosure is independent of the threshold voltage Vth of the driving transistor M0 and the voltage of the first power supply terminal VDD.
  • An embodiment of the present disclosure further provides a display panel, as shown in FIG. 9 , which may include: a plurality of pixel units PX arranged in an array in the display area of the base substrate 1000 .
  • Each pixel unit PX includes a plurality of sub-pixels spx.
  • the pixel unit may include red sub-pixels, green sub-pixels and blue sub-pixels, so that red, green and blue colors can be mixed to realize color display.
  • the pixel unit may also include red sub-pixels, green sub-pixels, blue sub-pixels and white sub-pixels, so that red, green, blue and white can be mixed to realize color display.
  • the light-emitting colors of the sub-pixels spx in the pixel unit can be designed and determined according to the actual application environment, which is not limited herein.
  • the sub-pixel spx may include the above-mentioned pixel circuit. It should be noted that, for the structure and working process of the pixel circuit, reference may be made to the above-mentioned embodiments, and details are not repeated here. The following description will take the structure of the pixel circuit shown in FIG. 2 as an example.
  • FIG. 10 is a schematic diagram of a layout (Layout) structure of a pixel circuit in a display panel provided on a base substrate 1000 according to some embodiments of the present disclosure.
  • 11a to 11g are schematic diagrams of various layers of a pixel circuit provided by some embodiments of the present disclosure.
  • FIG. 12 is a schematic cross-sectional structural schematic diagram along the AA' direction of a schematic diagram of a layout (Layout) structure of the pixel circuit in the display panel shown in FIG. 10 on the base substrate 1000 .
  • FIG. 13 is a schematic cross-sectional structural schematic diagram of the pixel circuit in the display panel shown in FIG. 10 on the base substrate 1000 along the BB' direction.
  • the examples shown in FIGS. 10 to 11g take the pixel circuit in one sub-pixel spx as an example.
  • the silicon semiconductor layer 600 of the pixel circuit is shown.
  • the silicon semiconductor layer 600 is located on the base substrate 1000 .
  • the silicon semiconductor layer 600 may be formed by patterning a low temperature polysilicon (Low Temperature Poly-Silicon, LTPS) material.
  • the silicon semiconductor layer 600 can be used to fabricate the above-mentioned active layers of the driving transistor M0 , the data writing transistor M3 , the second reset transistor M4 , the first light-emitting control transistor M5 and the second light-emitting control transistor M6 .
  • the active layers of the driving transistor M0, the data writing transistor M3, the second reset transistor M4, the first light emission control transistor M5, and the second light emission control transistor M6 may include a first region, a second region, and a the first channel region between the second regions.
  • FIG. 11a illustrates the first channel region M0-A of the driving transistor M0, the first channel region M3-A of the data writing transistor M3, the first channel region M4-A of the second reset transistor M4, The first channel region M5-A of the first light-emitting control transistor M5, and the first channel region M6-A of the second light-emitting control transistor M6.
  • first region and second region may be regions in the silicon semiconductor layer 600 doped with n-type impurities or p-type impurities to form conductive regions.
  • first region and the second region can be used as the source region and the drain region of the active layer for electrical connection.
  • a first gate insulating layer 810 is formed on the side of the above-mentioned silicon semiconductor layer 600 away from the base substrate 1000 to protect the above-mentioned silicon semiconductor layer 600 .
  • the thickness of the first gate insulating layer 810 may be
  • the thickness of the first gate insulating layer 810 may be
  • the thickness of the first gate insulating layer 810 may be It is not limited here.
  • the first conductive layer 100 of the pixel circuit is shown.
  • the first conductive layer 100 is disposed on the side of the first gate insulating layer 810 away from the base substrate 1000 so as to be insulated from the silicon semiconductor layer 600 .
  • the first conductive layer 100 may include: a plurality of first scan lines G1, a plurality of light-emitting control lines EM, a plurality of second reset lines S2, and gates M0-G of the driving transistor M0, and a data writing transistor M3, which are spaced apart from each other.
  • the gate M3-G of the second reset transistor M4 the gate M5-G of the first light emission control transistor M5, and the gate M6-G of the second light emission control transistor M6.
  • the thickness of the first conductive layer 100 may be
  • the thickness of the first conductive layer 100 may be The thickness of the first conductive layer 100 may be The thickness of the first conductive layer 100 may be It is not limited here.
  • a row of sub-pixels corresponds to a first scan line G1 , an emission control line EM and a second reset line S2 .
  • the first scan line G1 , the light emission control line EM and the second reset line S2 may extend substantially along the F1 direction and be arranged along the F2 direction.
  • the F1 direction may be the row direction of the sub-pixels, and the F2 direction may be the column direction of the sub-pixels.
  • the F1 direction may be the column direction of the sub-pixels, and the F2 direction may be the row direction of the sub-pixels.
  • the gate M3 -G of the data writing transistor M3 may be the portion where the first scan line G1 overlaps with the silicon semiconductor layer 600 .
  • the gate M4-G of the second reset transistor M4 may be a portion where the second reset line S2 overlaps with the silicon semiconductor layer 600 .
  • the gate M5-G of the first light emission control transistor M5 may be a first portion where the light emission control line EM overlaps with the silicon semiconductor layer 600 .
  • the gate M6-G of the second light emission control transistor M6 may be a second portion of the light emission control line EM overlapping the silicon semiconductor layer 600 .
  • the orthographic projection of the first scan line G1 on the base substrate 1000 is the same as that of the data writing transistor M3.
  • the orthographic projection of the active layer on the base substrate 1000 has an overlapping area.
  • the compensation conductive part BD is on the positive side of the base substrate 1000 .
  • the projection is located between the orthographic projection of the active layer of the data writing transistor M3 on the base substrate 1000 and the orthographic projection of the third via hole GK3 corresponding to the active layer of the threshold compensation transistor M2 on the base substrate 1000 .
  • the orthographic projection of the gate M0-G of the driving transistor M0 on the base substrate 1000 is located at the orthographic projection of the first scan line G1 on the base substrate 1000 and the light emission control line EM is located at Between the orthographic projections of the base substrate 1000 .
  • the orthographic projection of the second reset line S2 on the base substrate 1000 is located on the side of the orthographic projection of the light emitting control line EM on the base substrate 1000 away from the gate M0-G of the driving transistor M0.
  • a first interlayer dielectric layer 820 is formed on the side of the above-mentioned first conductive layer 100 away from the base substrate 1000 for insulating the first conductive layer 100 from the second conductive layer 200 .
  • the thickness of the first interlayer dielectric layer 820 may be
  • the thickness of the first interlayer dielectric layer 820 may be
  • the thickness of the first interlayer dielectric layer 820 may be It is not limited here.
  • the second conductive layer 200 of the pixel circuit is shown.
  • the second conductive layer 200 is disposed on the side of the first interlayer dielectric layer 820 away from the base substrate 1000 .
  • the second conductive layer 200 may include a plurality of compensation conductive parts BD, a plurality of auxiliary scan lines FG, a plurality of auxiliary reset lines FS, and a storage conductive part CC1a that are spaced apart from each other.
  • the orthographic projection of the storage conductive portion CC1a on the base substrate 1000 at least partially overlaps with the orthographic projection of the gate electrode M0-G of the driving transistor M0 on the base substrate 1000 to form the storage capacitor C1.
  • the storage conductive portion CC1a serves as the first pole of the storage capacitor C1, and the gate M0-G of the driving transistor M0 serves as the second pole of the storage capacitor C1.
  • the distance between the first pole and the second pole of the storage capacitor C1 may be
  • the distance between the first pole and the second pole of the storage capacitor C1 can be
  • the distance between the first pole and the second pole of the storage capacitor C1 can be
  • the distance between the first pole and the second pole of the storage capacitor C1 can be
  • the distance between the first pole and the second pole of the storage capacitor C1 can be The distance between the first pole and the second pole of the storage capacitor C1 can be It is not limited here.
  • the thickness of the second conductive layer 200 may be
  • the thickness of the second conductive layer 200 may be The thickness of the second conductive layer 200 may be The thickness of the second conductive layer 200 may be It is not limited here.
  • one row of sub-pixels corresponds to one auxiliary scan line FG and one auxiliary reset line FS.
  • the auxiliary scan line FG and the auxiliary reset line FS may extend along the F1 direction and be arranged along the F2 direction.
  • each sub-pixel may include a compensation conductive portion BD.
  • the compensation conductive portion BD is electrically connected to the gate M0-G of the driving transistor M0.
  • the first scan line G1 has the first scan line G1 between the orthographic projection of the base substrate 1000 and the orthographic projection of the compensation conductive portion BD on the base substrate 1000 .
  • the first compensation capacitor CF1 is located in the first overlap region SQ1, and the first compensation capacitor CF1 is formed by the overlap portion between the first scan line G1 and the compensation conductive portion BD.
  • the first scan line G1 located in the first overlapping region SQ1 serves as the second pole of the first compensation capacitor CF1
  • the compensation conductive portion BD located in the first overlapping region SQ1 serves as the first pole of the first compensation capacitor CF1 .
  • the distance between the first pole of the first compensation capacitor CF1 and the second pole of the first compensation capacitor CF1 may be
  • the distance between the first pole of the first compensation capacitor CF1 and the second pole of the first compensation capacitor CF1 may be
  • the distance between the first pole of the first compensation capacitor CF1 and the second pole of the first compensation capacitor CF1 may be
  • the distance between the first pole of the first compensation capacitor CF1 and the second pole of the first compensation capacitor CF1 may be
  • the distance between the first pole of the first compensation capacitor CF1 and the second pole of the first compensation capacitor CF1 may be
  • the distance between the first pole of the first compensation capacitor CF1 and the second pole of the first compensation capacitor CF1 may be It is not limited here.
  • the orthographic projection of the first scan line G1 on the base substrate 1000 covers the compensation conductive part BD on the backing.
  • Orthographic projection of the base substrate 1000 for the first scan line G1 and the compensation conductive part BD corresponding to the same sub-pixel, covers the compensation conductive part BD on the backing.
  • a second interlayer dielectric layer 830 is formed on the side of the above-mentioned second conductive layer 200 away from the base substrate 1000 for insulating the oxide semiconductor layer 700 from the second conductive layer 200 .
  • the oxide semiconductor layer 700 of the pixel circuit is shown.
  • the oxide semiconductor layer 700 is located on the side of the second interlayer dielectric layer 830 away from the base substrate 1000 .
  • the oxide semiconductor layer 700 includes the active layer of the first reset transistor M1 and the active layer of the threshold compensation transistor M2.
  • the thickness of the second interlayer dielectric layer 830 may be
  • the thickness of the second interlayer dielectric layer 830 may be The thickness of the second interlayer dielectric layer 830 may be The thickness of the second interlayer dielectric layer 830 may be It is not limited here.
  • a buffer layer 870 is formed on the side of the second interlayer dielectric layer 830 facing away from the base substrate 1000 , and the buffer layer 870 faces away from the base substrate.
  • the oxide semiconductor layer 700 is formed on the 1000 side.
  • the material of the buffer layer 870 may be silicon oxide
  • the material of the second interlayer dielectric layer 830 may be silicon nitride. Since the oxide semiconductor layer 700 is in direct contact with the silicon nitride, the characteristics of the material in the oxide semiconductor layer 700 may be affected.
  • the buffer layer 870 between the second interlayer dielectric layer 830 and the oxide semiconductor layer 700 , the direct contact between the oxide semiconductor layer 700 and the silicon nitride can be avoided, and the contact between the silicon nitride and the oxide semiconductor layer 700 can be avoided. affected by the properties of the material.
  • the material of the second interlayer dielectric layer 830 and the material of the buffer layer 870 can also be set to be silicon oxide.
  • the thickness of the buffer layer 870 may be
  • the thickness of the buffer layer 870 may be
  • the thickness of the buffer layer 870 may be
  • the thickness of the buffer layer 870 may be It is not limited here.
  • the thickness of the oxide semiconductor layer 700 may be
  • the thickness of the oxide semiconductor layer 700 may be
  • the thickness of the oxide semiconductor layer 700 may be
  • the thickness of the oxide semiconductor layer 700 may be It is not limited here.
  • the active layer of the first reset transistor M1 and the active layer of the threshold compensation transistor M2 may include a third region, a fourth region, and a second channel region between the third and fourth regions.
  • FIG. 11d illustrates the second channel region M1-A of the active layer of the first reset transistor M1, the second channel region M2-A of the active layer of the threshold compensation transistor M2.
  • the above-mentioned third region and fourth region may be regions in the oxide semiconductor layer 700 doped with n-type impurities or p-type impurities to form conductive regions.
  • the third region and the fourth region can be used as the source region and the drain region of the active layer for electrical connection.
  • the active layer of the first reset transistor M1 and the active layer of the threshold compensation transistor M2 may have an integrated structure.
  • the fourth region M1-D of the active layer of the first reset transistor M1 and the fourth region of the active layer of the threshold compensation transistor M2 are shared.
  • a second gate insulating layer 840 is formed on the side of the oxide semiconductor layer 700 away from the base substrate 1000 .
  • a third conductive layer 300 is formed on the side of the second gate insulating layer 840 facing away from the base substrate 1000 .
  • the third conductive layer 300 of the pixel circuit is shown.
  • the third conductive layer 300 may include: a plurality of second scan lines G2 and a plurality of first reset lines S1 that are spaced apart from each other. Wherein, one row of sub-pixels corresponds to one second scan line G2 and one first reset line S1.
  • the thickness of the second gate insulating layer 840 may be
  • the thickness of the second gate insulating layer 840 may be The thickness of the second gate insulating layer 840 may be It is not limited here.
  • the thickness of the third conductive layer 300 may be
  • the thickness of the third conductive layer 300 may be The thickness of the third conductive layer 300 may be The thickness of the third conductive layer 300 may be It is not limited here.
  • the orthographic projection of the active layer of the threshold compensation transistor M2 on the base substrate 1000 and the second scan line The orthographic projection of G2 on the base substrate 1000 has a second overlapping region SQ2; and the first part of the capacitance of the channel capacitance of the threshold compensation transistor M2 is located in the second overlapping region SQ2, and the first part of the capacitance is determined by the second scan line G2
  • An overlapped portion with the active layer of the threshold compensation transistor M2 is formed.
  • the orthographic projection of the fourth region of the active layer of the threshold compensation transistor M2 on the base substrate 1000 and the orthographic projection of the second scan line G2 on the base substrate 1000 have a second overlapping region SQ2; the trench of the threshold compensation transistor M2
  • the first part of the capacitance of the channel capacitance is located in the second overlapping region SQ2, and the first part of the capacitance of the channel capacitance of the threshold compensation transistor M2 is determined by the overlap between the second scan line G2 and the fourth region of the active layer of the threshold compensation transistor M2 partially formed.
  • the orthographic projection of the active layer of the auxiliary scan line FG and the threshold compensation transistor M2 on the base substrate 1000 There is a third overlapping region SQ3; the second part of the capacitance of the channel capacitance of the threshold compensation transistor M2 is located in the third overlapping region SQ3, and the second part of the capacitance is formed between the auxiliary scan line FG and the active layer of the threshold compensation transistor M2 the overlapping part is formed.
  • the auxiliary scan line FG and the fourth region of the active layer of the threshold compensation transistor M2 have a third overlapping region SQ3 in the orthographic projection of the base substrate 1000; the channel capacitance of the threshold compensation transistor M2 also includes a third overlapping region SQ3.
  • the third overlapping area SQ3 and the second overlapping area SQ2 may overlap.
  • the orthographic projection of the second scan line G2 on the base substrate 1000 and the threshold compensation transistor M2 have The orthographic projection of the source layer on the base substrate 1000 has an overlapping region.
  • the orthographic projection of the auxiliary scan line FG on the base substrate 1000 overlaps with the orthographic projection of the active layer of the threshold compensation transistor M2 on the base substrate 1000 area.
  • the orthographic projection of the second scan line G2 on the base substrate 1000 and the channel region of the active layer of the threshold compensation transistor M2 are on the base substrate.
  • the orthographic projection of 1000 has overlapping areas.
  • the orthographic projection of the auxiliary scan line FG on the base substrate 1000 and the channel region of the active layer of the threshold compensation transistor M2 on the positive side of the base substrate 1000 Projections have overlapping areas. In this way, the threshold compensation transistor M2 can form a double gate structure. Therefore, the on-state current of the threshold compensation transistor M2 can be increased, thereby improving the driving capability of the threshold compensation transistor M2 and improving the transistor characteristics of the threshold compensation transistor M2.
  • the orthographic projection of the second scan line G2 on the base substrate 1000 and the channel region of the active layer of the threshold compensation transistor M2 on the orthographic projection of the base substrate 1000 have an overlapping region.
  • the orthographic projection of the auxiliary scan line FG on the base substrate 1000 and the channel region of the active layer of the threshold compensation transistor M2 on the orthographic projection of the base substrate 1000 have an overlapping region. In this way, light can be shielded by the second scan line G2 and the auxiliary scan line FG, thereby preventing ambient light from being incident on the channel region of the active layer of the threshold compensation transistor M2 through the upper and lower sides of the display panel.
  • the orthographic projection of the second scan line G2 on the base substrate 1000 is lined with the auxiliary scan line FG.
  • the orthographic projections of the base substrate 1000 overlap.
  • the second scan line G2 and the auxiliary scan line FG corresponding to the same sub-pixel are electrically connected together in the peripheral region of the base substrate 1000 .
  • the orthographic projection of the first reset line S1 on the base substrate 1000 is the same as that of the first reset transistor M1.
  • the active layer of 1000 has an overlapping area in the orthographic projection of the base substrate 1000 .
  • the orthographic projection of the auxiliary reset line FS on the base substrate 1000 and the orthographic projection of the active layer of the first reset transistor M1 on the base substrate 1000 have overlapping area.
  • the orthographic projection of the first reset line S1 on the base substrate 1000 is lined with the channel region of the active layer of the first reset transistor M1.
  • the orthographic projection of the base substrate 1000 has an overlapping area.
  • the orthographic projection of the auxiliary reset line FS on the base substrate 1000 and the channel region of the active layer of the first reset transistor M1 on the base substrate 1000 The orthographic projections have overlapping regions. In this way, the first reset transistor M1 can form a double gate structure. Therefore, the on-state current of the first reset transistor M1 can be increased, thereby improving the driving capability of the first reset transistor M1 and improving the transistor characteristics of the first reset transistor M1.
  • the orthographic projection of the first reset line S1 on the base substrate 1000 and the orthographic projection of the active layer of the first reset transistor M1 on the base substrate 1000 have an overlapping region.
  • the orthographic projection of the auxiliary reset line FS on the base substrate 1000 and the channel region of the active layer of the first reset transistor M1 on the orthographic projection of the base substrate 1000 have an overlapping area. In this way, light can also be shielded by the first reset line S1 and the auxiliary reset line FS, thereby preventing ambient light from being incident on the channel region of the active layer of the first reset transistor M1 through the upper and lower sides of the display panel.
  • the orthographic projection of the first reset line S1 on the base substrate 1000 is lined with the auxiliary reset line FS.
  • the orthographic projections of the base substrate 1000 overlap.
  • the first reset line S1 and the auxiliary reset line FS corresponding to the same sub-pixel are electrically connected together in the peripheral region of the base substrate 1000 .
  • the orthographic projection of the first scan line G1 on the base substrate 1000 It is located between the orthographic projections of the second scan line G2 and the first reset line S1 on the base substrate 1000 .
  • a third interlayer dielectric layer 850 is formed on the side of the above-mentioned third conductive layer away from the base substrate 1000
  • a fourth conductive layer 400 is formed on the side of the third interlayer dielectric layer 850 away from the base substrate 1000 .
  • the fourth conductive layer 400 may include a plurality of first connection parts LB1 , a plurality of second connection parts LB2 , a plurality of third connection parts LB3 , a plurality of fourth connection parts LB4 , and a plurality of fifth connection parts LB5 arranged at intervals from each other.
  • One sub-pixel may include one first connection part LB1 , one second connection part LB2 , one third connection part LB3 , one fourth connection part LB4 , one fifth connection part LB5 , and one initialization signal line VINIT.
  • the thickness of the third interlayer dielectric layer 850 may be
  • the thickness of the third interlayer dielectric layer 850 may be The thickness of the third interlayer dielectric layer 850 may be The thickness of the third interlayer dielectric layer 850 may be It is not limited here.
  • the thickness of the fourth conductive layer 400 may be
  • the thickness of the fourth conductive layer 400 may be The thickness of the fourth conductive layer 400 may be The thickness of the fourth conductive layer 400 may be It is not limited here.
  • the first end of the first connection part LB1 is electrically connected to the compensation conductive part BD through the first via hole GK1
  • the second end of the first connection part LB1 is electrically connected to the compensation conductive part BD
  • the terminal is electrically connected to the gate of the driving transistor through the second via GK2
  • the third terminal of the first connection part LB1 is electrically connected to the conductive area of the active layer of the threshold compensation transistor M2 through the third via GK3.
  • the first via hole GK1 penetrates through the third interlayer dielectric layer 850 , the second gate insulating layer 840 and the second interlayer dielectric layer 830 .
  • the second via hole GK2 penetrates through the third interlayer dielectric layer 850 , the second gate insulating layer 840 , the second interlayer dielectric layer 830 and the first interlayer dielectric layer 820 .
  • the third via hole GK3 penetrates through the second gate insulating layer 840 and the third interlayer dielectric layer 850 .
  • the orthographic projection of the first scan line G1 on the base substrate 1000 is covered.
  • the first end and the third end of the first connecting part LB1 extend substantially in the same direction F1 , and the first end, The second end and the third end generally form a "T" shape. It should be noted that, in the actual preparation process, due to process errors, the first end, the second end and the third end of the first connection portion LB1 may be roughly formed in a "T" shape.
  • the orthographic projection of the second scan line G2 on the base substrate 1000 and the orthographic projection of the first connection portion LB1 on the base substrate 1000 there is a fourth overlapping area SQ4 between the projections, and the fourth overlapping area SQ4 has an auxiliary capacitor, and the auxiliary capacitor is formed by the overlapping portion between the second scan line G2 and the first connection portion LB1 .
  • the capacitance value of the auxiliary capacitor is approximately ⁇ c1.
  • the capacitance value of the auxiliary capacitor may not be equal to ⁇ c1, and there may be some deviations. Therefore, as long as the capacitance value of the auxiliary capacitor roughly meets the above conditions, it belongs to the present invention. protected range.
  • the initialization signal line VINIT is electrically connected to the conductive layer of the active layer of the first reset transistor M1 through the fourth via hole GK4 .
  • the fourth via hole GK4 penetrates through the second gate insulating layer 840 and the third interlayer dielectric layer 850 .
  • the first end of the fourth connection part LB4 is electrically connected to the semiconductor layer (eg, the third region) of the active layer of the threshold compensation transistor M2 through the fifth via hole GK5, and the The second ends of the four connection parts LB4 are electrically connected to the semiconductor layer (eg, the second region) of the active layer of the driving transistor M0 through the sixth via hole GK6 .
  • the fifth via hole GK5 penetrates through the second gate insulating layer 840 and the third interlayer dielectric layer 850 .
  • the sixth via hole GK6 penetrates through the third interlayer dielectric layer 850 , the second gate insulating layer 840 , the second interlayer dielectric layer 830 , the first interlayer dielectric layer 820 and the first gate insulating layer 810 .
  • an interlayer insulating layer 860 is formed on the side of the fourth conductive layer 400 facing away from the base substrate 1000 , and the interlayer insulating layer 860 faces away from the base substrate 1000 .
  • a fifth conductive layer 500 is formed on one side. As shown in FIG. 10 , FIG. 11 f , FIG. 12 and FIG. 13 , the fifth conductive layer 500 of the pixel circuit is shown.
  • the fifth conductive layer 500 may include a plurality of data lines DA, a plurality of power lines VD, and a plurality of anode transfer parts YZ, which are spaced apart from each other.
  • One sub-pixel includes one anode transfer portion YZ, and one column of sub-pixels corresponds to one data line DA and one power supply line VD.
  • the thickness of the interlayer insulating layer 860 may be
  • the thickness of the interlayer insulating layer 860 may be The thickness of the interlayer insulating layer 860 may be The thickness of the interlayer insulating layer 860 may be It is not limited here.
  • the thickness of the fifth conductive layer 500 may be
  • the thickness of the fifth conductive layer 500 may be
  • the thickness of the fifth conductive layer 500 may be
  • the data line DA is electrically connected to the second connection part LB2 through the seventh via hole GK7
  • the second connection part LB2 passes through the eighth via hole GK8 It is electrically connected to the conductive region (eg, the first region) of the active layer of the data writing transistor M3.
  • the seventh via GK7 penetrates the interlayer insulating layer 860
  • the eighth via GK8 penetrates the third interlayer dielectric layer 850 , the second gate insulating layer 840 , the second interlayer dielectric layer 830 , and the first interlayer dielectric layer 820 and the first gate insulating layer 810 .
  • the orthographic projection of the data line DA on the base substrate 1000 covers the orthographic projection of the electrically connected second connection portion LB2 on the base substrate 1000 .
  • the power line VD is electrically connected to the first end of the third connection part LB3 through the ninth via hole GK9 , and the second end of the third connection part LB3 passes through the tenth through hole GK9 .
  • the via hole GK10 is electrically connected to the conductive region (eg, the first region) of the active layer of the first light emission control transistor M5.
  • the third end of the third connection portion LB3 is electrically connected to the storage conductive portion CC1a through the eleventh via hole GK11. That is, the power line VD is electrically connected to the first power terminal to transmit voltage to the first power terminal.
  • the ninth via hole GK9 penetrates through the interlayer insulating layer 860 .
  • the tenth via hole GK10 penetrates through the third interlayer dielectric layer 850 , the second gate insulating layer 840 , the second interlayer dielectric layer 830 , the first interlayer dielectric layer 820 and the first gate insulating layer 810 .
  • the tenth via hole GK10 penetrates through the interlayer insulating layer 860 , the third interlayer dielectric layer 850 , the second gate insulating layer 840 , and the second interlayer dielectric layer 830 .
  • the first end and the second end of the third connection part LB3 extend substantially along the direction F1 , and the first end and the second end of the third connection part LB3 and The third end roughly forms an inverted "T" shape. It should be noted that, in the actual preparation process, due to process errors, the first end, the second end and the third end of the third connection portion LB3 may be roughly formed in an inverted "T" shape.
  • the orthographic projection of the power supply line VD on the base substrate 1000 and the active power of the threshold compensation transistor M2 The layers have overlapping regions in the orthographic projection of the base substrate 1000 . Further, for the power supply line VD and the threshold compensation transistor M2 corresponding to the same sub-pixel, the orthographic projection of the power supply line VD on the base substrate 1000 covers the orthographic projection of the active layer of the threshold compensation transistor M2 on the base substrate 1000 .
  • the orthographic projection of the power supply line VD on the base substrate 1000 is the same as that of the first reset transistor M1 .
  • the orthographic projection of the active layer on the base substrate 1000 has an overlapping area.
  • the orthographic projection of the power supply line VD on the base substrate 1000 covers the orthographic projection of the active layer of the first reset transistor M1 on the base substrate 1000 .
  • the orthographic projection of the power supply line VD on the base substrate 1000 covers the active layer of the threshold compensation transistor M2 and the first reset transistor M1. Orthographic projection on the base substrate 1000 .
  • the orthographic projection of the power supply line VD on the base substrate 1000 and the first via hole GK1 , the second via hole GK2 and the third via hole GK3 respectively have overlapping areas
  • the orthographic projection of the power supply line VD on the base substrate 1000 and the first via hole GK1 , the second via hole GK2 and the third via hole GK3 The four overlapping regions SQ4 do not overlap.
  • the anode transfer part YZ is electrically connected to the fifth connection part LB5 through the twelfth via hole GK12, the anode transfer part YZ is electrically connected to the anode of the light-emitting device through the fourteenth via hole GK14, and the anode transfer part YZ passes through the thirteenth via hole GK14.
  • the via hole GK13 is electrically connected to the conductive region (eg, the second region) of the active layer of the second light-emitting control transistor M6.
  • the twelfth via hole GK12 penetrates the interlayer insulating layer 860
  • the thirteenth via hole GK13 penetrates the third interlayer dielectric layer 850 , the second gate insulating layer 840 , the second interlayer dielectric layer 830 , and the first interlayer dielectric layer 850 .
  • the fourteenth via hole GK14 penetrates the flat layer between the fifth conductive layer 500 and the layer where the anode is located.
  • the thickness of the flat layer may be
  • the thickness of the flat layer can be The thickness of the flat layer can be The thickness of the flat layer can be It is not limited here.
  • the parasitic capacitance may include a coupling capacitance formed by overlapping between a channel capacitance and other metal layers, or the parasitic capacitance may also include a channel capacitance.
  • the size of the compensation capacitor set in this application can consider the size of the parasitic capacitor.
  • an embodiment of the present disclosure further provides a display device including the above-mentioned pixel circuit provided by an embodiment of the present disclosure.
  • the principle of solving the problem of the display device is similar to that of the aforementioned pixel circuit. Therefore, the implementation of the display device can refer to the implementation of the aforementioned pixel circuit, and repeated details are not repeated here.
  • the display device may be any product or component with display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • a mobile phone such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be repeated here, nor should it be regarded as a limitation of the present disclosure.

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  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种像素电路、显示面板及显示装置，数据写入晶体管（M3）的栅极与第一扫描线（G1）电连接，数据写入晶体管（M3）的第一极与数据线（DA）电连接，数据写入晶体管（M3）的第二极与驱动晶体管（M0）的第一极电连接；阈值补偿晶体管（M2）的栅极与第二扫描线（G2）电连接，阈值补偿晶体管（M2）的第一极与驱动晶体管（M0）的栅极电连接，阈值补偿晶体管（M2）的第二极与驱动晶体管（M0）的第二极电连接；补偿电路（10）与驱动晶体管（M0）的栅极电连接；发光控制电路（20）分别与第一电源端（VDD）、驱动晶体管（M0）的第一极、第二极以及发光器件（L）的第一电极电连接，且被配置为在发光控制线（EM）的信号的控制下，将第一电源端（VDD）与驱动晶体管（M0）的第一极导通，以及将驱动晶体管（M0）的第二极与发光器件（L）的第一电极导通，驱动发光器件（L）发光。

Description

像素电路、显示面板及显示装置 技术领域
本公开涉及显示技术领域，特别涉及像素电路、显示面板及显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)、量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)、微型发光二极管(Micro Light Emitting Diode，Micro LED)等电致发光二极管具有自发光、低能耗等优点，是当今显示装置应用研究领域的热点之一。一般采用像素电路来驱动电致发光二极管发光。在实际应用中，当显示装置要显示灰阶范围内的任一灰阶时，可能使数据电压超出驱动IC(Integrated Circuit，集成电路)的输出范围，导致暗态不够黑的问题，影响显示装置的对比度。
发明内容
本公开实施例提供的像素电路，包括：
数据写入晶体管，所述数据写入晶体管的栅极与第一扫描线电连接，所述数据写入晶体管的第一极与数据线电连接，所述数据写入晶体管的第二极与驱动晶体管的第一极电连接；其中，所述数据写入晶体管的有源层的材料为低温多晶硅材料；
阈值补偿晶体管，所述阈值补偿晶体管的栅极与第二扫描线电连接，所述阈值补偿晶体管的第一极与所述驱动晶体管的栅极电连接，所述阈值补偿晶体管的第二极与所述驱动晶体管的第二极电连接；其中，所述阈值补偿晶体管的有源层的材料为金属氧化物半导体材料；
补偿电路，所述补偿电路与所述驱动晶体管的栅极电连接；
发光控制电路，分别与第一电源端、所述驱动晶体管的第一极、第二极以及发光器件的第一电极电连接，且被配置为在发光控制线的信号的控制下， 将所述第一电源端与所述驱动晶体管的第一极导通，以及将所述驱动晶体管的第二极与所述发光器件的第一电极导通，驱动所述发光器件发光。
在一些示例中，所述补偿电路被配置为根据寄生电容对所述驱动晶体管的栅极的电压进行补偿。
在一些示例中，所述补偿电路包括：第一补偿电容；
所述第一补偿电容的第一极与所述驱动晶体管的栅极电连接，所述第一补偿电容的第二极与所述第一扫描线电连接。
在一些示例中，所述寄生电容包括所述阈值补偿晶体管的栅极和第一极之间的沟道电容。
在一些示例中，所述阈值补偿晶体管的栅极和第一极之间的沟道电容的电容值为第一沟道电容值，所述第一补偿电容的电容值与所述第一沟道电容值之间的差值满足0±Δc1。
在一些示例中，所述补偿电路包括：第一补偿控制晶体管；
所述第一补偿控制晶体管的栅极与所述第一扫描线电连接，所述第一补偿控制晶体管的第一极和第二极均与所述驱动晶体管的栅极电连接。
在一些示例中，所述寄生电容包括所述阈值补偿晶体管的栅极和第一极之间的沟道电容，所述阈值补偿晶体管的栅极和第一极之间的沟道电容的电容值为第一沟道电容值；
所述第一补偿控制晶体管的栅极与第一极之间的沟道电容的电容值为第二沟道电容值，所述第一补偿控制晶体管的栅极与第二极之间的沟道电容的电容值为第三沟道电容值；所述第二沟道电容值与所述第三沟道电容值之和为总沟道电容值；
所述总沟道电容值与所述第一沟道电容值之间的差值满足0±Δc2。
在一些示例中，所述补偿电路包括：第二补偿控制晶体管；
所述第二补偿控制晶体管的栅极与所述第一扫描线电连接，所述第一补偿控制晶体管的第一极与所述驱动晶体管的栅极电连接，所述第一补偿控制晶体管的第二极浮接。
在一些示例中，所述寄生电容包括所述阈值补偿晶体管的栅极和第一极之间的沟道电容，所述阈值补偿晶体管的栅极和第一极之间的沟道电容的电容值为第一沟道电容值；
所述第二补偿控制晶体管的栅极与第一极之间的沟道电容的电容值为第四沟道电容值；
所述第四沟道电容值与所述第一沟道电容值之间的差值满足0±Δc3。
在一些示例中，所述补偿电路包括：第二补偿电容；
所述第二补偿电容的第一极与所述驱动晶体管的栅极电连接，所述第二补偿电容的第二极与所述发光器件的第一电极电连接。
在一些示例中，所述像素电路还包括：第一复位晶体管；
所述第一复位晶体管的栅极与第一复位线电连接，所述第一复位晶体管的第一极与初始化信号线电连接，所述第一复位晶体管的第二极与所述驱动晶体管的栅极电连接。
在一些示例中，所述第一复位晶体管的有源层的材料为金属氧化物半导体材料。
在一些示例中，所述像素电路还包括：第二复位晶体管；
所述第二复位晶体管的栅极与第二复位线电连接，所述第二复位晶体管的第一极与初始化信号线电连接，所述第二复位晶体管的第二极与所述发光器件的第一电极电连接。
在一些示例中，所述驱动电路包括：第一发光控制晶体管，第二发光控制晶体管以及存储电容；
所述第一发光控制晶体管的栅极与所述发光控制线电连接，所述第一发光控制晶体管的第一极与所述第一电源端电连接，所述第一发光控制晶体管的第二极与所述驱动晶体管的第一极电连接；
所述第二发光控制晶体管的栅极与所述发光控制线电连接，所述第二发光控制晶体管的第一极与所述驱动晶体管的第二极电连接，所述第二发光控制晶体管的第二极与所述发光器件的第一电极电连接；
所述存储电容的第一极与所述第一电源端电连接，所述存储电容的第二极与所述驱动晶体管的栅极电连接。
本公开实施例提供的显示面板，包括：
衬底基板，包括多个子像素，所述子像素包括像素电路，所述像素电路包括第一补偿电容和驱动晶体管；
第一导电层，位于所述衬底基板上，且所述第一导电层包括第一扫描线和驱动晶体管的栅极；其中，一行子像素对应一条所述第一扫描线；
第一层间介质层，位于所述第一导电层背离所述衬底基板一侧；
第二导电层，位于所述第一层间介质层背离所述衬底基板一侧，且所述第二导电层包括补偿导电部；其中，所述子像素包括所述补偿导电部，且同一所述子像素中，所述补偿导电部与所述驱动晶体管的栅极电连接；
其中，针对同一所述子像素对应的第一扫描线和补偿导电部，所述第一扫描线在所述衬底基板的正投影与所述补偿导电部在所述衬底基板的正投影之间具有第一交叠区域，所述第一补偿电容位于所述第一交叠区域，且所述第一补偿电容由所述第一扫描线和所述补偿导电部之间的交叠部分形成。
在一些示例中，针对同一所述子像素对应的第一扫描线和补偿导电部，所述第一扫描线在所述衬底基板的正投影覆盖所述补偿导电部在所述衬底基板的正投影。
在一些示例中，所述像素电路还包括阈值补偿晶体管；所述显示面板还包括：
第二层间介质层，位于所述第二导电层背离所述衬底基板一侧；
氧化物半导体层，位于所述第二层间介质层背离所述衬底基板一侧，且所述氧化物半导体层包括所述阈值补偿晶体管的有源层；
第二栅绝缘层，位于所述氧化物半导体层背离所述衬底基板一侧；
第三导电层，位于所述第二栅绝缘层背离所述衬底基板一侧，且所述第三导电层包括第二扫描线；其中，一行子像素对应一条所述第二扫描线；
针对同一所述子像素对应的第二扫描线以及和阈值补偿晶体管，所述阈 值补偿晶体管的有源层在所述衬底基板的正投影和所述第二扫描线在所述衬底基板的正投影具有第二交叠区域；所述阈值补偿晶体管的沟道电容的第一部分电容位于所述第二交叠区域，且所述第一部分电容由所述第二扫描线和所述阈值补偿晶体管的有源层之间的交叠部分形成。
在一些示例中，所述第二导电层还包括辅助扫描线；其中，一行子像素对应一条所述辅助扫描线；
针对同一所述子像素对应的辅助扫描线和阈值补偿晶体管，所述辅助扫描线和所述阈值补偿晶体管的有源层在所述衬底基板的正投影具有第三交叠区域；
所述阈值补偿晶体管的沟道电容的第二部分电容位于所述第三交叠区域，且所述第二部分电容由所述辅助扫描线和所述阈值补偿晶体管的有源层之间的交叠部分形成。
在一些示例中，针对同一所述子像素对应的第二扫描线和辅助扫描线，所述第二扫描线在所述衬底基板的正投影与所述辅助扫描线在所述衬底基板的正投影重叠。
在一些示例中，所述显示面板还包括：
第三层间介质层，位于所述第三导电层背离所述衬底基板一侧；
第四导电层，位于所述第三层间介质层背离所述衬底基板一侧，且所述第四导电层包括第一连接部；其中，所述第一连接部的第一端通过第一过孔与所述补偿导电部电连接，所述第一连接部的第二端通过第二过孔与所述驱动晶体管的栅极电连接；所述第一过孔贯穿所述第三层间介质层、所述第二栅绝缘层与所述第二层间介质层，所述第二过孔贯穿所述第三层间介质层、所述第二栅绝缘层、所述第二层间介质层以及所述第一层间介质层。
在一些示例中，所述第一连接部的第三端通过第三过孔与所述阈值补偿晶体管的有源层的导体化区电连接；所述第三过孔贯穿所述第二栅绝缘层和所述第三层间介质层。
在一些示例中，针对同一所述子像素对应的所述第一扫描线和所述第三 过孔，所述第一扫描线在所述衬底基板的正投影覆盖所述第三过孔在所述衬底基板的正投影。
在一些示例中，所述第一连接部的第一端和第三端大致沿同一方向延伸，且所述第一连接部的第一端、第二端以及第三端大致形成“T”字型。
在一些示例中，针对同一所述子像素，所述第二扫描线在所述衬底基板的正投影与所述第一连接部在所述衬底基板的正投影之间具有第四交叠区域，所述第四交叠区域具有辅助电容，所述辅助电容由所述第二扫描线和所述第一连接部之间的交叠部分形成；
所述辅助电容的电容值大致为Δc1。
在一些示例中，所述显示面板还包括：
层间绝缘层，位于所述第四导电层背离所述衬底基板一侧；
第五导电层，位于所述层间绝缘层背离所述衬底基板一侧，且所述第五导电层包括数据线和电源线；其中，一列子像素对应一条所述数据线和一条所述电源线；
针对同一所述子像素对应的电源线和阈值补偿晶体管，所述电源线在所述衬底基板的正投影与所述阈值补偿晶体管的有源层在所述衬底基板的正投影具有交叠区域。
在一些示例中，针对同一所述子像素对应的所述电源线、所述第一过孔、所述第二过孔、所述第三过孔以及所述第三交叠区域，所述电源线在所述衬底基板的正投影分别与所述第一过孔、所述第二过孔以及所述第三过孔具有交叠区域，且所述电源线在所述衬底基板的正投影与所述第四交叠区域不交叠。
在一些示例中，所述像素电路还包括第一复位晶体管，所述氧化物半导体层还包括所述第一复位晶体管的有源层；
所述第三导电层还包括第一复位线；其中，一行子像素对应一条所述第一复位线；
针对同一所述子像素对应的所述第一复位晶体管和所述第一复位线，所 述第一复位线在所述衬底基板的正投影与所述第一复位晶体管的有源层在所述衬底基板的正投影具有交叠区域。
在一些示例中，针对同一所述子像素对应的电源线和第一复位晶体管，所述电源线在所述衬底基板的正投影与所述第一复位晶体管的有源层在所述衬底基板的正投影具有交叠区域。
在一些示例中，针对同一所述子像素对应的所述第一扫描线、所述第二扫描线以及所述第一复位线，所述第一扫描线在所述衬底基板的正投影位于所述第二扫描线和所述第一复位线在所述衬底基板的正投影之间。
在一些示例中，所述像素电路还包括数据写入晶体管；所述显示面板还包括：
硅半导体层，位于所述第一导电层与所述衬底基板之间，且所述硅半导体层包括所述数据写入晶体管的有源层；
第一栅绝缘层，位于所述第一导电层与所述硅半导体层之间；
针对同一所述子像素对应的所述第一扫描线和所述数据写入晶体管，所述第一扫描线在所述衬底基板的正投影与所述数据写入晶体管的有源层在所述衬底基板的正投影具有交叠区域。
在一些示例中，针对同一所述子像素对应的所述数据写入晶体管、所述阈值补偿晶体管的有源层以及所述补偿导电部，所述补偿导电部在所述衬底基板的正投影位于所述数据写入晶体管的有源层在所述衬底基板的正投影和所述阈值补偿晶体管的有源层对应的第三过孔在所述衬底基板的正投影之间。
本公开实施例提供的显示装置，包括上述显示面板。
附图说明
图1为本公开实施例中的一些像素电路的结构示意图；
图2为本公开实施例中的另一些像素电路的结构示意图；
图3为本公开实施例中的一些像素电路的信号时序图；
图4为本公开实施例中的又一些像素电路的结构示意图；
图5为本公开实施例中的又一些像素电路的结构示意图；
图6为本公开实施例中的又一些像素电路的结构示意图；
图7a为本公开实施例中的又一些像素电路的结构示意图；
图7b为本公开实施例中的又一些像素电路的信号时序图；
图8a为本公开实施例中的又一些像素电路的结构示意图；
图8b为本公开实施例中的又一些像素电路的信号时序图；
图9为本公开实施例中的一些显示面板的结构示意图；
图10为本公开实施例中的一些显示面板中的像素电路的布局结构示意图；
图11a为本公开实施例中的一些显示面板中的硅半导体层的布局结构示意图；
图11b为本公开实施例中的一些显示面板中的第一导电层的布局结构示意图；
图11c为本公开实施例中的一些显示面板中的第二导电层的布局结构示意图；
图11d为本公开实施例中的一些显示面板中的氧化物半导体层的布局结构示意图；
图11e为本公开实施例中的一些显示面板中的第三导电层的布局结构示意图；
图11f为本公开实施例中的一些显示面板中的第四导电层的布局结构示意图；
图11g为本公开实施例中的一些显示面板中的第五导电层的布局结构示意图；
图12为图10所示的显示面板中的像素电路的布局结构示意图沿AA’方向上的剖视结构图；
图13为图10所示的显示面板中的像素电路的布局结构示意图沿BB’方向上的剖视结构图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
本公开实施例提供一种像素电路，如图1所示，可以包括：
数据写入晶体管M3，数据写入晶体管M3的栅极与第一扫描线G1电连接，数据写入晶体管M3的第一极与数据线DA电连接，数据写入晶体管M3的第二极与驱动晶体管M0的第一极电连接；其中，数据写入晶体管M3的有源层的材料为低温多晶硅材料；
阈值补偿晶体管M2，阈值补偿晶体管M2的栅极与第二扫描线G2电连接，阈值补偿晶体管M2的第一极与驱动晶体管M0的栅极电连接，阈值补偿晶体管M2的第二极与驱动晶体管M0的第二极电连接；其中，阈值补偿晶体管M2的有源层的材料为金属氧化物半导体材料；
补偿电路10，补偿电路10与驱动晶体管M0的栅极电连接，且被配置为 根据阈值补偿晶体管M2的栅极和第一极之间的沟道电容，对驱动晶体管M0的栅极的电压进行补偿；
发光控制电路20，分别与第一电源端VDD、驱动晶体管M0的第一极、第二极以及发光器件L的第一电极电连接，且被配置为在发光控制线EM的信号的控制下，将第一电源端VDD与驱动晶体管M0的第一极导通，以及将驱动晶体管M0的第二极与发光器件L的第一电极导通，驱动发光器件L发光。
本公开实施例提供的上述像素电路，通过设置与驱动晶体管的栅极电连接的补偿电路，并且补偿电路可以根据阈值补偿晶体管M2的栅极和第一极之间的沟道电容，对驱动晶体管的栅极的电压进行补偿。这样在第二扫描线G2的信号的电平进行切换时，可以通过补偿电路对驱动晶体管M0的栅极电压因阈值补偿晶体管M2的栅极和第一极之间的沟道电容而拉低的电压ΔVn1进行补偿，从而可以提高驱动晶体管的栅极电压的稳定性。
在具体实施时，在本公开实施例中，发光器件L的第一极与发光控制电路20电连接，发光器件L的第二极与第二电源端VSS电连接。示例性地，发光器件L与发光控制电路20电连接的第一极为其正极，与第二电源端VSS电连接的第二极为其负极。例如，发光器件L可以为电致发光二极管，例如OLED、QLED、Micro LED、Mini LED。并且，发光器件L在驱动晶体管M0处于饱和状态时的电流的作用下实现发光。另外，一般发光器件L具有开启电压，在发光器件L两端的电压差大于或等于开启电压时进行发光。
在具体实施时，在本公开实施例中，第一电源端VDDVDD的电压Vdd一般为正值，第二电源端VSS的电压Vss一般接地或为负值。并且初始化信号线VINIT的电压Vinit与第二电源端VSS的电压Vss需要满足公式：Vinit-Vss<VL；其中，VL为发光器件L的开启电压。
在具体实施时，在本公开实施例中，如图1所示，驱动晶体管M0可以为P型晶体管；其中，驱动晶体管M0的栅极可以为其栅极，驱动晶体管M0的第一极可以为其源极，驱动晶体管M0的第二极可以为其漏极。或者，驱动晶 体管M0也可以为N型晶体管；其中，驱动晶体管M0的栅极可以为其栅极，驱动晶体管M0的第一极可以为其漏极，驱动晶体管M0的第二极可以为其源极。在实际应用中，驱动晶体管M0的类型具体可以根据实际应用的需求进行设计确定，在此不作限定。
在具体实施时，在本公开实施例中，如图2所示，补偿电路10可以包括：第一补偿电容CF1；其中，第一补偿电容CF1的第一极与驱动晶体管M0的栅极电连接，第一补偿电容CF1的第二极与第一扫描线G1电连接。示例性地，阈值补偿晶体管M2的栅极和第一极之间的沟道电容的电容值为第一沟道电容值CgsT2，第一补偿电容CF1的电容值Cf1与第一沟道电容值CgsT2之间的差值满足0±Δc1。例如，Δc1可以为0.1，或者Δc1也可以为0.01，或者Δc1也可以为0.05，在此不作限定。需要说明的是，在实际工艺中，由于工艺条件的限制或其他因素，上述第一补偿电容CF1的电容值与第一沟道电容值并不能完全相同，可能会有一些偏差，因此上述第一补偿电容CF1的电容值与第一沟道电容值之间的相同关系只要大致满足上述条件即可，均属于本公开的保护范围。例如，在第一补偿电容CF1的电容值与第一沟道电容值之间的差值满足0±Δc1时，可以认为是在误差允许范围之内所允许的相同。
在具体实施时，在本公开实施例中，如图2所示，像素电路还可以包括：第一复位晶体管M1；第一复位晶体管M1的栅极与第一复位线S1电连接，第一复位晶体管M1的第一极与初始化信号线VINIT电连接，第一复位晶体管M1的第二极与驱动晶体管M0的栅极电连接。
在具体实施时，在本公开实施例中，如图1所示，像素电路还包括：第二复位晶体管M4；其中，第二复位晶体管M4的栅极与第二复位线S2电连接，第二复位晶体管M4的第一极与初始化信号线VINIT电连接，第二复位晶体管M4的第二极与发光器件L的第一电极电连接。示例性地，第二复位线S2可以与第一扫描线G1为同一信号端。例如，如图2所示，数据写入晶体管M3的栅极和第二复位晶体管M4的栅极均与第一扫描线G1电连接。
在具体实施时，在本公开实施例中，如图2所示，驱动电路可以包括： 第一发光控制晶体管M5，第二发光控制晶体管M6以及存储电容C1；其中，第一发光控制晶体管M5的栅极与发光控制线EM电连接，第一发光控制晶体管M5的第一极与第一电源端VDD电连接，第一发光控制晶体管M5的第二极与驱动晶体管M0的第一极电连接。第二发光控制晶体管M6的栅极与发光控制线EM电连接，第二发光控制晶体管M6的第一极与驱动晶体管M0的第二极电连接，第二发光控制晶体管M6的第二极与发光器件L的第一电极电连接。存储电容C1的第一极与第一电源端VDD电连接，存储电容C1的第二极与驱动晶体管M0的栅极电连接。
示例性地，如图2所示，可以使数据写入晶体管M3、第二复位晶体管M4、第一发光控制晶体管M5、第二发光控制晶体管M6以及驱动晶体管M0均设置为P型晶体管。当然，也可以使数据写入晶体管M3、第二复位晶体管M4、第一发光控制晶体管M5、第二发光控制晶体管M6以及驱动晶体管M0均设置为N型晶体管。当然，在实际应用中，可以根据实际应用的需求进行设计确定数据写入晶体管M3、第二复位晶体管M4、第一发光控制晶体管M5、第二发光控制晶体管M6以及驱动晶体管M0的具体类型，在此不作限定。
示例性地，如图2所示，可以使第一复位晶体管M1和阈值补偿晶体管M2均设置为N型晶体管。当然，也可以使第一复位晶体管M1和阈值补偿晶体管M2均设置为P型晶体管。当然，在实际应用中，可以根据实际应用的需求进行设计确定第一复位晶体管M1和阈值补偿晶体管M2的具体类型，在此不作限定。
示例性地，在本公开实施例中，P型晶体管在低电平信号作用下导通，在高电平信号作用下截止；N型晶体管在高电平信号作用下导通，在低电平信号作用下截止。
示例性地，在本公开实施例中，上述晶体管的栅极可以作为其栅极，第一极可以作为其源极，第二极作为其漏极，或者上述晶体管的第一极可以作为其漏极，第二极作为其源极，在此不作具体区分。
一般采用低温多晶硅(Low Temperature Poly-Silicon，LTPS)材料作为有源层的晶体管的迁移率高且可以做得更薄更小、功耗更低等，在具体实施时，在本公开实施例中，驱动晶体管M0的有源层的材料可以包括低温多晶硅材料，数据写入晶体管M3的有源层的材料可以包括低温多晶硅材料，第二复位晶体管M4的材料可以包括低温多晶硅材料，第一发光控制晶体管M5的材料可以包括低温多晶硅材料，第二发光控制晶体管M6的材料可以包括低温多晶硅材料。即将数据写入晶体管M3、第二复位晶体管M4、第一发光控制晶体管M5、第二发光控制晶体管M6以及驱动晶体管M0均设置为LTPS型晶体管，这样可以使数据写入晶体管M3、第二复位晶体管M4、第一发光控制晶体管M5、第二发光控制晶体管M6以及驱动晶体管M0迁移率较高且可以做得更薄更小、功耗更低等。
一般采用金属氧化物半导体材料作为有源层的晶体管的漏电流较小，因此为了降低漏电流，在具体实施时，在本公开实施例中，第一复位晶体管M1的有源层的材料可以包括金属氧化物半导体材料，阈值补偿晶体管M2的有源层的材料可以包括金属氧化物半导体材料。即将第一复位晶体管M1和阈值补偿晶体管M2均设置为氧化物型晶体管，这样可以使第一复位晶体管M1和阈值补偿晶体管M2漏电流较小。示例性地，金属氧化物半导体材料可以为IGZO(Indium GaLium Zinc Oxide，铟镓锌氧化物)，当然，金属氧化物半导体材料也可以为其他金属氧化物半导体材料，在此不作限定。这样可以减少第一复位晶体管M1和阈值补偿晶体管M2在截止时的漏电流，从而在发光器件L发光时，有利于减少漏电流对驱动晶体管M0的栅极电压的干扰，进而可以使驱动晶体管M0驱动发光器件L发光的驱动电流的稳定性提高。
本公开实施例提供的像素电路，通过将LTPS型晶体管与氧化物型晶体管这两种制备晶体管的工艺进行结合，以制备低温多晶硅结合氧化物的像素电路，以使驱动晶体管M0的栅极的漏电流较小，以及使功耗较低。从而将该像素电路应用于电致发光显示面板显示装置中时，可以提高驱动晶体管M0的栅极电压的稳定性，尤其是在显示装置降低刷新频率进行显示时，可以保证显 示的均一性。
下面以图2所示的结构为例，结合图3所示的信号时序图，对本公开实施例提供的像素电路的工作过程作以描述。下述描述中以1表示高电平，0表示低电平。需要说明的是，1和0是逻辑电平，其仅是为了更好的解释本公开实施例的具体工作过程，而不是具体的电压值。
需要说明的是，第一扫描线G1和第二扫描线G2的信号分别是由高电平信号和低电平信号组成的。其高电平信号的电压一般为高电压VGH，低电平信号的电压一般为低电压VGL。当然，高电压VGH和低电压VGL的具体数值可以根据实际应用的需求进行设计确定，在此不作限定。
示例性地，高低电平的绝对值可以是相等的，例如，高电平为+5V，低电平为-5V。或者，高电平为+6V，低电平为-6V。或者，高电平为+7V，低电平为-7V。或者，高低电平的绝对值也可以是不相等的，例如高电平为大于0的数值，低电平为0V。当然，在实际应用中，可以根据实际应用的需求进行设计确定，在此不作限定。
在复位阶段T1，S1＝1，G2＝0，G1＝1，EM＝1。
由于S1＝1，因此第一复位晶体管M1导通，以将初始化信号线VINIT的信号提供给驱动晶体管M0的栅极，以对驱动晶体管M0的栅极进行初始化。由于G2＝0，因此阈值补偿晶体管M2截止。由于G1＝1，因此数据写入晶体管M3和第二复位晶体管M4均截止。由于EM＝1，因此第一发光控制晶体管M5和第二发光控制晶体管M6均截止。第一补偿电容CF1的第二极的电压为第一扫描线G1的高电平信号的高电压VGH，第一极为初始化信号线VINIT的电压Vinit。
在数据写入阶段T2，S1＝0，G2＝1，G1＝0，EM＝1。
由于G1＝0，因此数据写入晶体管M3和第二复位晶体管M4均导通。由于G2＝1，因此阈值补偿晶体管M2导通。导通的数据写入晶体管M3将数据线DA的数据电压Vda输入驱动晶体管M0的第一极。导通的阈值补偿晶体管M2将驱动晶体管M0的栅极和第二极导通，以使驱动晶体管M0形成二极 管电连接结构，以使数据电压Vda对驱动晶体管M0的栅极进行充电，并使驱动晶体管M0的栅极电压成功为Vda+Vth。导通的第二复位晶体管M4将初始化信号线VINIT的信号提供给发光器件L的第一电极，以对发光器件L的第一电极进行初始化。第一补偿电容CF1的第二极的电压为第一扫描线G1的低电平信号的低电压VGL，第一极为Vda+Vth。由于S1＝0，因此第一复位晶体管M1截止。由于EM＝1，因此第一发光控制晶体管M5和第二发光控制晶体管M6均截止。
在发光阶段T3，S1＝0，G2＝0，G1＝1，EM＝0。
由于第二扫描线G2由高电平信号的高电压VGH切换为低电平信号的低电压VGL，这样使得驱动晶体管M0的栅极的电压在Vda+Vth的基础上可以变化电压ΔVn11。其中，
Figure PCTCN2020123332-appb-000001
其中，CgsT2代表第一沟道电容值，Cc1代表存储电容C1的电容值，Cf1代表第一补偿电容CF1的电容值，Co代表其他相关电容值(一般为定值)。
由于第一扫描线G1由低电平信号的低电压VGL切换为高电平信号的高电压VGH，这样使得驱动晶体管M0的栅极的电压在Vda+Vth的基础上可以变化电压ΔVn12。其中，
Figure PCTCN2020123332-appb-000002
则驱动晶体管M0的栅极的电压的改变量为：ΔVn10＝ΔVn11+ΔVn12。由于第一补偿电容CF1的电容值Cf1与第一沟道电容值CgsT2之间的差值满足0±Δc1，即可认为第一补偿电容CF1的电容值Cf1与第一沟道电容值CgsT2是相等的。因此，ΔVn11与ΔVn12可以相互抵消，则使得ΔVn10可以为0。这样使得在进行发光阶段T2后，驱动晶体管M0的栅极的电压可以稳定在Vda+Vth。
由于EM＝0，因此第一发光控制晶体管M5和第二发光控制晶体管M6均导通。导通的第一发光控制晶体管M5将第一电源端VDD的电压提供给驱动晶体管M0的第一极。驱动晶体管M0在其栅极电压和第一极电压的作用下， 产生工作电流Ids。其中，Ids＝K(Vdd-Vda) 2。K为结构参数。导通的第二发光控制晶体管M6将驱动晶体管M0的第二极与发光器件L的第一电极导通，以使工作电流Ids驱动发光器件L发光。因此，本公开实施例提供的像素电路产生的工作电流与驱动晶体管M0的阈值电压Vth无关。
本公开实施例又提供了一些显示面板，其结构示意图如图4所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在具体实施时，在本公开实施例中，如图4所示，补偿电路10可以包括：第一补偿控制晶体管；其中，第一补偿控制晶体管的栅极与第一扫描线G1电连接，第一补偿控制晶体管的第一极和第二极均与驱动晶体管M0的栅极电连接。示例性地，第一补偿控制晶体管可以为P型晶体管。进一步地，第一补偿控制晶体管的有源层的材料可以为低温多晶硅材料或金属氧化物半导体材料，在此不作限定。
在具体实施时，在本公开实施例中，第一补偿控制晶体管的栅极与第一极之间的沟道电容的电容值为第二沟道电容值CgsMF1，第一补偿控制晶体管的栅极与第二极之间的沟道电容的电容值为第三沟道电容值CgdMF1；第二沟道电容值CgsMF1与第三沟道电容值CgdMF1之和为总沟道电容值CmMF1。其中，总沟道电容值CmMF1与第一沟道电容值CgsT2之间的差值满足0±Δc2。例如，Δc2可以为0.1，或者Δc2也可以为0.01，或者Δc2也可以为0.05，在此不作限定。需要说明的是，在实际工艺中，由于工艺条件的限制或其他因素，上述第一沟道电容值与总沟道电容值并不能完全相同，可能会有一些偏差，因此上述第一沟道电容值与总沟道电容值之间的相同关系只要大致满足上述条件即可，均属于本公开的保护范围。例如，在第一沟道电容值与总沟道电容值之间的差值满足0±Δc2时，可以认为是在误差允许范围之内所允许的相同。
下面以图4所示的结构为例，结合图3所示的信号时序图，对本公开实施例提供的像素电路的工作过程作以描述。下述描述中以1表示高电平，0表 示低电平。需要说明的是，1和0是逻辑电平，其仅是为了更好的解释本公开实施例的具体工作过程，而不是具体的电压值。
需要说明的是，第一扫描线G1和第二扫描线G2的信号分别是由高电平信号和低电平信号组成的。其高电平信号的电压一般为高电压VGH，低电平信号的电压一般为低电压VGL。当然，高电压VGH和低电压VGL的具体数值可以根据实际应用的需求进行设计确定，在此不作限定。
在复位阶段T1，S1＝1，G2＝0，G1＝1，EM＝1。
由于S1＝1，因此第一复位晶体管M1导通，以将初始化信号线VINIT的信号提供给驱动晶体管M0的栅极，以对驱动晶体管M0的栅极进行初始化。由于G2＝0，因此阈值补偿晶体管M2截止。由于G1＝1，因此数据写入晶体管M3、第一补偿控制晶体管以及第二复位晶体管M4均截止。由于EM＝1，因此第一发光控制晶体管M5和第二发光控制晶体管M6均截止。
在数据写入阶段T2，S1＝0，G2＝1，G1＝0，EM＝1。
由于G1＝0，因此数据写入晶体管M3、第二复位晶体管M4以及第一补偿控制晶体管均导通。由于G2＝1，因此阈值补偿晶体管M2导通。导通的数据写入晶体管M3将数据线DA的数据电压Vda输入驱动晶体管M0的第一极。导通的阈值补偿晶体管M2将驱动晶体管M0的栅极和第二极导通，以使驱动晶体管M0形成二极管电连接结构，以使数据电压Vda对驱动晶体管M0的栅极进行充电，并使驱动晶体管M0的栅极电压成功为Vda+Vth。导通的第二复位晶体管M4将初始化信号线VINIT的信号提供给发光器件L的第一电极，以对发光器件L的第一电极进行初始化。由于S1＝0，因此第一复位晶体管M1截止。由于EM＝1，因此第一发光控制晶体管M5和第二发光控制晶体管M6均截止。此阶段中，第一补偿控制晶体管对驱动晶体管M0的栅极电压无影响。
在发光阶段T3，S1＝0，G2＝0，G1＝1，EM＝0。
由于第二扫描线G2由高电平信号的高电压VGH切换为低电平信号的低电压VGL，这样使得驱动晶体管M0的栅极的电压在Vda+Vth的基础上可以 变化电压ΔVn21。其中，
Figure PCTCN2020123332-appb-000003
其中，CgsT2代表第一沟道电容值，Cc1代表存储电容C1的电容值，CgsMF1代表第二沟道电容值，CgdMF1代表第三沟道电容值，Co代表其他相关电容值(一般为定值)。
由于第一扫描线G1由低电平信号的低电压VGL切换为高电平信号的高电压VGH，这样使得驱动晶体管M0的栅极的电压在Vda+Vth的基础上可以变化电压ΔVn22。其中，
Figure PCTCN2020123332-appb-000004
则驱动晶体管M0的栅极的电压的改变量为：ΔVn20＝ΔVn21+ΔVn22。由于第二沟道电容值CgsMF1与第三沟道电容值CgdMF1之和为总沟道电容值CmMF1与第一沟道电容值CgsT2之间的差值满足0±Δc2，即可认为总沟道电容值CmMF1与第一沟道电容值CgsT2是相等的。因此，ΔVn21与ΔVn22可以相互抵消，则使得ΔVn20可以为0。这样使得在进行发光阶段T2后，驱动晶体管M0的栅极的电压可以稳定在Vda+Vth。
由于EM＝0，因此第一发光控制晶体管M5和第二发光控制晶体管M6均导通。导通的第一发光控制晶体管M5将第一电源端VDD的电压提供给驱动晶体管M0的第一极。驱动晶体管M0在其栅极电压和第一极电压的作用下，产生工作电流Ids。其中，Ids＝K(Vdd-Vda) 2。K为结构参数。导通的第二发光控制晶体管M6将驱动晶体管M0的第二极与发光器件L的第一电极导通，以使工作电流Ids驱动发光器件L发光。因此，本公开实施例提供的像素电路产生的工作电流与驱动晶体管M0的阈值电压Vth无关。
本公开实施例又提供了一些显示面板，其结构示意图如图5所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在具体实施时，在本公开实施例中，如图5所示，补偿电路10也可以包括：第二补偿控制晶体管；其中，第二补偿控制晶体管的栅极与第一扫描线 G1电连接，第一补偿控制晶体管的第一极与驱动晶体管M0的栅极电连接，第一补偿控制晶体管的第二极浮接。示例性地，第二补偿控制晶体管可以为P型晶体管。进一步地，第二补偿控制晶体管的有源层的材料可以为低温多晶硅材料或金属氧化物半导体材料，在此不作限定。
在具体实施时，在本公开实施例中，第二补偿控制晶体管的栅极与第一极之间的沟道电容的电容值为第四沟道电容值CgsMF2；其中，第四沟道电容值CgsMF2与第一沟道电容值CgsT2之间的差值满足0±Δc3。例如，Δc3可以为0.1，或者Δc3也可以为0.01，或者Δc3也可以为0.05，在此不作限定。需要说明的是，在实际工艺中，由于工艺条件的限制或其他因素，上述第一沟道电容值与第四沟道电容值并不能完全相同，可能会有一些偏差，因此上述第一沟道电容值与第四沟道电容值之间的相同关系只要大致满足上述条件即可，均属于本公开的保护范围。例如，在第一沟道电容值与第四沟道电容值之间的差值满足0±Δc3时，可以认为是在误差允许范围之内所允许的相同。
下面以图5所示的结构为例，结合图3所示的信号时序图，对本公开实施例提供的像素电路的工作过程作以描述。下述描述中以1表示高电平，0表示低电平。需要说明的是，1和0是逻辑电平，其仅是为了更好的解释本公开实施例的具体工作过程，而不是具体的电压值。
需要说明的是，第一扫描线G1和第二扫描线G2的信号分别是由高电平信号和低电平信号组成的。其高电平信号的电压一般为高电压VGH，低电平信号的电压一般为低电压VGL。当然，高电压VGH和低电压VGL的具体数值可以根据实际应用的需求进行设计确定，在此不作限定。
在复位阶段T1，S1＝1，G2＝0，G1＝1，EM＝1。
由于S1＝1，因此第一复位晶体管M1导通，以将初始化信号线VINIT的信号提供给驱动晶体管M0的栅极，以对驱动晶体管M0的栅极进行初始化。由于G2＝0，因此阈值补偿晶体管M2截止。由于G1＝1，因此数据写入晶体管M3、第一补偿控制晶体管以及第二复位晶体管M4均截止。由于EM＝1， 因此第一发光控制晶体管M5和第二发光控制晶体管M6均截止。
在数据写入阶段T2，S1＝0，G2＝1，G1＝0，EM＝1。
由于G1＝0，因此数据写入晶体管M3、第二复位晶体管M4以及第一补偿控制晶体管均导通。由于G2＝1，因此阈值补偿晶体管M2导通。导通的数据写入晶体管M3将数据线DA的数据电压Vda输入驱动晶体管M0的第一极。导通的阈值补偿晶体管M2将驱动晶体管M0的栅极和第二极导通，以使驱动晶体管M0形成二极管电连接结构，以使数据电压Vda对驱动晶体管M0的栅极进行充电，并使驱动晶体管M0的栅极电压成功为Vda+Vth。导通的第二复位晶体管M4将初始化信号线VINIT的信号提供给发光器件L的第一电极，以对发光器件L的第一电极进行初始化。由于S1＝0，因此第一复位晶体管M1截止。由于EM＝1，因此第一发光控制晶体管M5和第二发光控制晶体管M6均截止。此阶段中，第一补偿控制晶体管对驱动晶体管M0的栅极电压无影响。
在发光阶段T3，S1＝0，G2＝0，G1＝1，EM＝0。
由于第二扫描线G2由高电平信号的高电压VGH切换为低电平信号的低电压VGL，这样使得驱动晶体管M0的栅极的电压在Vda+Vth的基础上可以变化电压ΔVn31。其中，
Figure PCTCN2020123332-appb-000005
其中，CgsT2代表第一沟道电容值，Cc1代表存储电容C1的电容值，CgsMF2代表第四沟道电容值，Co代表其他相关电容值(一般为定值)。
由于第一扫描线G1由低电平信号的低电压VGL切换为高电平信号的高电压VGH，这样使得驱动晶体管M0的栅极的电压在Vda+Vth的基础上可以变化电压ΔVn32。其中，
Figure PCTCN2020123332-appb-000006
则驱动晶体管M0的栅极的电压的改变量为：ΔVn30＝ΔVn31+ΔVn32。由于第四沟道电容值CgsMF2与第一沟道电容值CgsT2之间的差值满足0±Δc3，即可认为第四沟道电容值CgsMF2与第一沟道电容值CgsT2是相等的。 因此，ΔVn31与ΔVn32可以相互抵消，则使得ΔVn30可以为0。这样使得在进行发光阶段T2后，驱动晶体管M0的栅极的电压可以稳定在Vda+Vth。
由于EM＝0，因此第一发光控制晶体管M5和第二发光控制晶体管M6均导通。导通的第一发光控制晶体管M5将第一电源端VDD的电压提供给驱动晶体管M0的第一极。驱动晶体管M0在其栅极电压和第一极电压的作用下，产生工作电流Ids。其中，Ids＝K(Vdd-Vda) 2。K为结构参数。导通的第二发光控制晶体管M6将驱动晶体管M0的第二极与发光器件L的第一电极导通，以使工作电流Ids驱动发光器件L发光。因此，本公开实施例提供的像素电路产生的工作电流与驱动晶体管M0的阈值电压Vth无关。
本公开实施例又提供了一些显示面板，其结构示意图如图6所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在具体实施时，在本公开实施例中，如图6所示，补偿电路10也可以包括：第二补偿电容CF2；其中，第二补偿电容CF2的第一极与驱动晶体管M0的栅极电连接，第二补偿电容CF2的第二极与发光器件L的第一电极电连接。示例性地，第二补偿电容CF2的电容值Cf2与第一沟道电容值CgsT2相关。
下面以图4所示的结构为例，结合图3所示的信号时序图，对本公开实施例提供的像素电路的工作过程作以描述。下述描述中以1表示高电平，0表示低电平。需要说明的是，1和0是逻辑电平，其仅是为了更好的解释本公开实施例的具体工作过程，而不是具体的电压值。
在复位阶段T1，S1＝1，G2＝0，G1＝1，EM＝1。
由于S1＝1，因此第一复位晶体管M1导通，以将初始化信号线VINIT的信号提供给驱动晶体管M0的栅极，以对驱动晶体管M0的栅极进行初始化。由于G2＝0，因此阈值补偿晶体管M2截止。由于G1＝1，因此数据写入晶体管M3和第二复位晶体管M4均截止。由于EM＝1，因此第一发光控制晶体管M5和第二发光控制晶体管M6均截止。第二补偿电容CF2的第一极的电压为初始化信号线VINIT的电压Vinit，第二极的电压为发光器件L的第一电极的 电压。
在数据写入阶段T2，S1＝0，G2＝1，G1＝0，EM＝1。
由于G1＝0，因此数据写入晶体管M3和第二复位晶体管M4均导通。由于G2＝0，因此阈值补偿晶体管M2导通。导通的数据写入晶体管M3将数据线DA的数据电压Vda输入驱动晶体管M0的第一极。导通的阈值补偿晶体管M2将驱动晶体管M0的栅极和第二极导通，以使驱动晶体管M0形成二极管电连接结构，以使数据电压Vda对驱动晶体管M0的栅极进行充电，并使驱动晶体管M0的栅极电压成功为Vda+Vth。导通的第二复位晶体管M4将初始化信号线VINIT的信号提供给发光器件L的第一电极，以对发光器件L的第一电极进行初始化。第二补偿电容CF2的第一极的电压为Vda+Vth，第二极的电压为初始化信号线VINIT的电压Vinit。由于S1＝0，因此第一复位晶体管M1截止。由于EM＝1，因此第一发光控制晶体管M5和第二发光控制晶体管M6均截止。
在发光阶段T3，S1＝0，G2＝0，G1＝1，EM＝0。
由于第二扫描线G2由高电平信号的高电压VGH切换为低电平信号的低电压VGL，这样使得驱动晶体管M0的栅极的电压在Vda+Vth的基础上可以变化电压ΔVn41。其中，
Figure PCTCN2020123332-appb-000007
其中，CgsT2代表第一沟道电容值，Cc1代表存储电容C1的电容值，Cf2代表第二补偿电容CF2的电容值，Co代表其他相关电容值(一般为定值)。
由于发光器件L的第一电极的电压由Vinit变为Vss+VL，这样使得驱动晶体管M0的栅极的电压在Vda+Vth的基础上可以变化电压ΔVn42。其中，
Figure PCTCN2020123332-appb-000008
则驱动晶体管M0的栅极的电压的改变量为：ΔVn40＝ΔVn41+ΔVn42。可以通过使CgsT2*(VGL-VGH)+Cf2*(VL+Vss-Vinit)通过使大致为0，则可以使ΔVn41与ΔVn42可以相互抵消，则使得ΔVn40可以为0。这样使得在进行发光阶段T2后，驱动晶体管M0的栅极的电压可以稳定在Vda+Vth。
由于EM＝0，因此第一发光控制晶体管M5和第二发光控制晶体管M6均导通。导通的第一发光控制晶体管M5将第一电源端VDD的电压提供给驱动晶体管M0的第一极。驱动晶体管M0在其栅极电压和第一极电压的作用下，产生工作电流Ids。其中，Ids＝K(Vdd-Vda) 2。K为结构参数。导通的第二发光控制晶体管M6将驱动晶体管M0的第二极与发光器件L的第一电极导通，以使工作电流Ids驱动发光器件L发光。因此，本公开实施例提供的像素电路产生的工作电流与驱动晶体管M0的阈值电压Vth无关。
本公开实施例又提供了一些显示面板，其结构示意图如图7a所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在具体实施时，在本公开实施例中，如图7a所示，像素电路还可以包括：稳定晶体管M7；其中，稳定晶体管M7的栅极与稳定控制信号端VS电连接，稳定晶体管M7的第一极与驱动晶体管M0的栅极电连接，稳定晶体管M7的第二极分别与第一复位晶体管M1的第二极以及阈值补偿晶体管M2的第一极电连接。也就是说，第一复位晶体管M1的第二极与阈值补偿晶体管M2的第一极通过稳定晶体管M7与驱动晶体管M0的栅极电连接。
示例性地，第一复位晶体管M1和阈值补偿晶体管M2可以为P型晶体管，并且，第一复位晶体管M1和阈值补偿晶体管M2的有源层的材料为低温多晶硅材料。
示例性地，稳定晶体管M7可以为N型晶体管，并且，稳定晶体管M7的有源层的材料可以为金属氧化物半导体材料。
下面以图7a所示的结构为例，结合图7b所示的信号时序图，对本公开实施例提供的像素电路的工作过程作以描述。下述描述中以1表示高电平，0表示低电平。需要说明的是，1和0是逻辑电平，其仅是为了更好的解释本公开实施例的具体工作过程，而不是具体的电压值。
在复位阶段T1，S1＝0，G2＝1，G1＝1，EM＝1，VS＝1。
由于S1＝0，因此第一复位晶体管M1导通，以将初始化信号线VINIT的 信号提供给稳定晶体管M7的第二极。由于VS＝1，因此稳定晶体管M7导通，以将初始化信号线VINIT的信号提供给驱动晶体管M0的栅极，以对驱动晶体管M0的栅极进行初始化。由于G2＝1，因此阈值补偿晶体管M2截止。由于G1＝1，因此数据写入晶体管M3和第二复位晶体管M4均截止。由于EM＝1，因此第一发光控制晶体管M5和第二发光控制晶体管M6均截止。第一补偿电容CF1的第二极的电压为第一扫描线G1的高电平信号的高电压VGH，第一极为初始化信号线VINIT的电压Vinit。
在数据写入阶段T2，S1＝1，G2＝0，G1＝0，EM＝1，VS＝1。
由于G1＝0，因此数据写入晶体管M3和第二复位晶体管M4均导通。由于G2＝0，因此阈值补偿晶体管M2导通。由于VS＝1，因此稳定晶体管M7导通。导通的数据写入晶体管M3将数据线DA的数据电压Vda输入驱动晶体管M0的第一极。导通的阈值补偿晶体管M2和稳定晶体管M7将驱动晶体管M0的栅极和第二极导通，以使驱动晶体管M0形成二极管电连接结构，以使数据电压Vda对驱动晶体管M0的栅极进行充电，并使驱动晶体管M0的栅极电压成功为Vda+Vth。导通的第二复位晶体管M4将初始化信号线VINIT的信号提供给发光器件L的第一电极，以对发光器件L的第一电极进行初始化。第一补偿电容CF1的第二极的电压为第一扫描线G1的低电平信号的低电压VGL，第一极为Vda+Vth。由于S1＝1，因此第一复位晶体管M1截止。由于EM＝1，因此第一发光控制晶体管M5和第二发光控制晶体管M6均截止。
在发光阶段T3，S1＝0，G2＝0，G1＝1，EM＝0，VS＝0。
由于第二扫描线G2由高电平信号的高电压VGH切换为低电平信号的低电压VGL，这样使得驱动晶体管M0的栅极的电压在Vda+Vth的基础上可以变化电压ΔVn11。其中，
Figure PCTCN2020123332-appb-000009
其中，CgsT2代表第一沟道电容值，Cc1代表存储电容C1的电容值，Cf1代表第一补偿电容CF1的电容值，Co代表其他相关电容值(一般为定值)。
由于第一扫描线G1由低电平信号的低电压VGL切换为高电平信号的高 电压VGH，这样使得驱动晶体管M0的栅极的电压在Vda+Vth的基础上可以变化电压ΔVn12。其中，
Figure PCTCN2020123332-appb-000010
则驱动晶体管M0的栅极的电压的改变量为：ΔVn10＝ΔVn11+ΔVn12。由于第一补偿电容CF1的电容值Cf1与第一沟道电容值CgsT2之间的差值满足0±Δc1，即可认为第一补偿电容CF1的电容值Cf1与第一沟道电容值CgsT2是相等的。因此，ΔVn11与ΔVn12可以相互抵消，则使得ΔVn10可以为0。这样使得在进行发光阶段T2后，驱动晶体管M0的栅极的电压可以稳定在Vda+Vth。
由于EM＝0，因此第一发光控制晶体管M5和第二发光控制晶体管M6均导通。导通的第一发光控制晶体管M5将第一电源端VDD的电压提供给驱动晶体管M0的第一极。驱动晶体管M0在其栅极电压和第一极电压的作用下，产生工作电流Ids。其中，Ids＝K(Vdd-Vda) 2。K为结构参数。导通的第二发光控制晶体管M6将驱动晶体管M0的第二极与发光器件L的第一电极导通，以使工作电流Ids驱动发光器件L发光。因此，本公开实施例提供的像素电路产生的工作电流与驱动晶体管M0的阈值电压Vth无关。
本公开实施例又提供了一些显示面板，其结构示意图如图8a所示，其针对上述实施例中的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
在具体实施时，在本公开实施例中，如图8a所示，像素电路可以包括：第一复位晶体管M1、阈值补偿晶体管M2、数据写入晶体管M3、第二复位晶体管M4、第二发光控制晶体管M6、第一参考晶体管M8、第二参考晶体管M9、存储电容C1以及第一补偿电容CF1。其中，第一复位晶体管M1、阈值补偿晶体管M2、数据写入晶体管M3、第二复位晶体管M4、第二发光控制晶体管M6、第一参考晶体管M8、第二参考晶体管M9、存储电容C1以及第一补偿电容CF1之间的电连接关系如图8a所示，在此不作赘述。
下面以图8a所示的结构为例，结合图8b所示的信号时序图，对本公开 实施例提供的像素电路的工作过程作以描述。下述描述中以1表示高电平，0表示低电平。需要说明的是，1和0是逻辑电平，其仅是为了更好的解释本公开实施例的具体工作过程，而不是具体的电压值。
在复位阶段T1，S1＝1，G2＝0，G1＝1，EM＝1，CS＝0。
由于S1＝1，因此第一复位晶体管M1导通，以将初始化信号线VINIT的信号提供给驱动晶体管M0的栅极，以对驱动晶体管M0的栅极进行初始化。由于CS＝0，因此第二参考晶体管M9导通，以将参考信号端VREF的信号提供给存储电容C1。由于G2＝0，因此阈值补偿晶体管M2截止。由于G1＝1，因此数据写入晶体管M3和第二复位晶体管M4均截止。由于EM＝1，因此第一参考晶体管M8和第二发光控制晶体管M6均截止。第一补偿电容CF1的第二极的电压为第一扫描线G1的高电平信号的高电压VGH，第一极为初始化信号线VINIT的电压Vinit。
在数据写入阶段T2，S1＝0，G2＝1，G1＝0，EM＝1，CS＝1。
由于G1＝0，因此数据写入晶体管M3和第二复位晶体管M4均导通。导通的数据写入晶体管M3将数据线DA的数据电压Vda输入存储电容C1。导通的第二复位晶体管M4将初始化信号线VINIT的信号提供给发光器件L的第一电极，以对发光器件L的第一电极进行初始化。由于G2＝1，因此阈值补偿晶体管M2导通。导通的阈值补偿晶体管M2将驱动晶体管M0的栅极和第二极导通，以使驱动晶体管M0形成二极管电连接结构，以使第一电源端VDD对驱动晶体管M0的栅极进行充电，并使驱动晶体管M0的栅极电压成功为Vdd+Vth。第一补偿电容CF1的第二极的电压为第一扫描线G1的低电平信号的低电压VGL，第一极为Vdd+Vth。由于S1＝0，因此第一复位晶体管M1截止。由于EM＝1，因此第一参考晶体管M8和第二发光控制晶体管M6均截止。其中，Vdd为第一电源端VDD的电压。
在发光阶段T3，S1＝0，G2＝0，G1＝1，EM＝0。
由于第二扫描线G2由高电平信号的高电压VGH切换为低电平信号的低电压VGL，这样使得驱动晶体管M0的栅极的电压在Vdd+Vth的基础上可以 变化电压ΔVn11。其中，
Figure PCTCN2020123332-appb-000011
其中，CgsT2代表第一沟道电容值，Cc1代表存储电容C1的电容值，Cf1代表第一补偿电容CF1的电容值，Co代表其他相关电容值(一般为定值)。
由于第一扫描线G1由低电平信号的低电压VGL切换为高电平信号的高电压VGH，这样使得驱动晶体管M0的栅极的电压在Vdd+Vth的基础上可以变化电压ΔVn12。其中，
Figure PCTCN2020123332-appb-000012
则驱动晶体管M0的栅极的电压的改变量为：ΔVn10＝ΔVn11+ΔVn12。由于第一补偿电容CF1的电容值Cf1与第一沟道电容值CgsT2之间的差值满足0±Δc1，即可认为第一补偿电容CF1的电容值Cf1与第一沟道电容值CgsT2是相等的。因此，ΔVn11与ΔVn12可以相互抵消，则使得ΔVn10可以为0。这样使得在进行发光阶段T2后，驱动晶体管M0的栅极的电压可以稳定在Vdd+Vth。
由于EM＝0，因此第一参考晶体管M8和第二发光控制晶体管M6均导通。导通的第一参考晶体管M8将参考信号端VREF的电压提供给存储电容C1，使驱动晶体管M0的电压变为Vdd+Vth+Vda。因此，驱动晶体管M0在其栅极电压和第一极电压的作用下，产生工作电流Ids。其中，Ids＝K(Vda) 2。K为结构参数。导通的第二发光控制晶体管M6将驱动晶体管M0的第二极与发光器件L的第一电极导通，以使工作电流Ids驱动发光器件L发光。因此，本公开实施例提供的像素电路产生的工作电流与驱动晶体管M0的阈值电压Vth和第一电源端VDD的电压无关。
本公开实施例还提供了显示面板，如图9所示，可以包括：位于衬底基板1000的显示区中阵列排布的多个像素单元PX。每个像素单元PX包括多个子像素spx。示例性地，像素单元可以包括红色子像素，绿色子像素以及蓝色子像素，这样可以通过红绿蓝进行混色，以实现彩色显示。或者，像素单元也可以包括红色子像素，绿色子像素、蓝色子像素以及白色子像素，这样可 以通过红绿蓝白进行混色，以实现彩色显示。当然，在实际应用中，像素单元中的子像素spx的发光颜色可以根据实际应用环境来设计确定，在此不作限定。
在具体实施时，在本公开实施例中，子像素spx可以包括上述像素电路。需要说明的是，像素电路的结构和工作过程可以参见上述实施例，具体在此不作赘述。下面以图2所示的像素电路的结构为例进行说明。
图10为本公开一些实施例提供的显示面板中的像素电路在衬底基板1000上的布局(Layout)结构示意图。图11a至图11g为本公开一些实施例提供的像素电路的各层的示意图。图12为图10所示的显示面板中的像素电路在衬底基板1000上的布局(Layout)结构示意图沿AA’方向上的剖视结构示意图。图13为图10所示的显示面板中的像素电路在衬底基板1000上的布局(Layout)结构示意图沿BB’方向上的剖视结构示意图。其中，图10至图11g所示的示例以一个子像素spx中的像素电路为例。
示例性地，如图10、图11a、图12以及图13所示，示出了该像素电路的硅半导体层600。其中，硅半导体层600位于衬底基板1000上。示例性地，硅半导体层600可采用低温多晶硅(Low Temperature Poly-Silicon，LTPS)材料图案化形成。硅半导体层600可用于制作上述的驱动晶体管M0、数据写入晶体管M3、第二复位晶体管M4、第一发光控制晶体管M5以及第二发光控制晶体管M6的有源层。并且，驱动晶体管M0、数据写入晶体管M3、第二复位晶体管M4、第一发光控制晶体管M5以及第二发光控制晶体管M6的有源层可包括第一区、第二区以及位于第一区和第二区之间的第一沟道区。例如，图11a示意出了驱动晶体管M0的第一沟道区M0-A，数据写入晶体管M3的第一沟道区M3-A，第二复位晶体管M4的第一沟道区M4-A，第一发光控制晶体管M5的第一沟道区M5-A，第二发光控制晶体管M6的第一沟道区M6-A。需要说明的是，上述的第一区和第二区可为硅半导体层600中掺杂有n型杂质或p型杂质的区域，以形成的导体化区。从而可以使第一区和第二区作为有源层的源极区和漏极区，以进行电连接。
示例性地，在上述的硅半导体层600背离衬底基板1000一侧形成有第一栅绝缘层810，用于保护上述的硅半导体层600。示例性地，第一栅绝缘层810的厚度可以为
Figure PCTCN2020123332-appb-000013
例如，第一栅绝缘层810的厚度可以为
Figure PCTCN2020123332-appb-000014
第一栅绝缘层810的厚度可以为
Figure PCTCN2020123332-appb-000015
第一栅绝缘层810的厚度可以为
Figure PCTCN2020123332-appb-000016
在此不作限定。
如图10、图11b、图12以及图13所示，示出了该像素电路的第一导电层100。第一导电层100设置在第一栅绝缘层810背离衬底基板1000一侧，从而与硅半导体层600绝缘。第一导电层100可以包括：相互间隔设置的多条第一扫描线G1、多条发光控制线EM、多条第二复位线S2以及驱动晶体管M0的栅极M0-G、数据写入晶体管M3的栅极M3-G、第二复位晶体管M4的栅极M4-G、第一发光控制晶体管M5的栅极M5-G以及第二发光控制晶体管M6的栅极M6-G。
示例性地，第一导电层100的厚度可以为
Figure PCTCN2020123332-appb-000017
例如，第一导电层100的厚度可以为
Figure PCTCN2020123332-appb-000018
第一导电层100的厚度可以为
Figure PCTCN2020123332-appb-000019
第一导电层100的厚度可以为
Figure PCTCN2020123332-appb-000020
在此不作限定。
示例性地，如图10、图11b所示，一行子像素对应一条第一扫描线G1、一条发光控制线EM以及一条第二复位线S2。示例性地，第一扫描线G1、发光控制线EM以及第二复位线S2可以大致沿F1方向延伸，沿F2方向排列。其中，F1方向可以为子像素的行方向，F2方向可以为子像素的列方向。或者，F1方向可以为子像素的列方向，F2方向可以为子像素的行方向。
示例性地，如图10、图11b所示，数据写入晶体管M3的栅极M3-G可以为第一扫描线G1与硅半导体层600交叠的部分。第二复位晶体管M4的栅极M4-G可以为第二复位线S2与硅半导体层600交叠的部分。第一发光控制晶体管M5的栅极M5-G可以为发光控制线EM与硅半导体层600交叠的第一部分。第二发光控制晶体管M6的栅极M6-G可以为发光控制线EM与硅半导体层600交叠的第二部分。
示例性地，如图10、图11b所示，针对同一子像素对应的第一扫描线G1 和数据写入晶体管，第一扫描线G1在衬底基板1000的正投影与数据写入晶体管M3的有源层在衬底基板1000的正投影具有交叠区域。
示例性地，如图10、图11b所示，针对同一子像素对应的数据写入晶体管M3、阈值补偿晶体管M2的有源层以及补偿导电部BD，补偿导电部BD在衬底基板1000的正投影位于数据写入晶体管M3的有源层在衬底基板1000的正投影和阈值补偿晶体管M2的有源层对应的第三过孔GK3在衬底基板1000的正投影之间。
示例性地，如图10、图11b所示，驱动晶体管M0的栅极M0-G在衬底基板1000的正投影位于第一扫描线G1在衬底基板1000的正投影和发光控制线EM在衬底基板1000的正投影之间。第二复位线S2在衬底基板1000的正投影位于发光控制线EM在衬底基板1000的正投影背离驱动晶体管M0的栅极M0-G一侧。
示例性地，在上述的第一导电层100背离衬底基板1000一侧形成有第一层间介质层820，用于使第一导电层100与第二导电层200绝缘设置。示例性地，第一层间介质层820的厚度可以为
Figure PCTCN2020123332-appb-000021
例如，第一层间介质层820的厚度可以为
Figure PCTCN2020123332-appb-000022
第一层间介质层820的厚度可以为
Figure PCTCN2020123332-appb-000023
第一层间介质层820的厚度可以为
Figure PCTCN2020123332-appb-000024
在此不作限定。
如图10、图11c、图12以及图13所示，示出了该像素电路的第二导电层200。第二导电层200设置在第一层间介质层820背离衬底基板1000一侧。第二导电层200可以包括相互间隔设置的多个补偿导电部BD、多条辅助扫描线FG，多条辅助复位线FS以及存储导电部CC1a。示例性地，存储导电部CC1a在衬底基板1000的正投影与驱动晶体管M0的栅极M0-G在衬底基板1000的正投影至少部分交叠以形成存储电容C1。其中，存储导电部CC1a作为存储电容C1的第一极，驱动晶体管M0的栅极M0-G作为存储电容C1的第二极。示例性地，存储电容C1的第一极和第二极之间的距离可以为
Figure PCTCN2020123332-appb-000025
例如，存储电容C1的第一极和第二极之间的距离可以为
Figure PCTCN2020123332-appb-000026
存储电容C1的第一极和第二极之间的距离可以为
Figure PCTCN2020123332-appb-000027
存储电容C1的第 一极和第二极之间的距离可以为
Figure PCTCN2020123332-appb-000028
存储电容C1的第一极和第二极之间的距离可以为
Figure PCTCN2020123332-appb-000029
存储电容C1的第一极和第二极之间的距离可以为
Figure PCTCN2020123332-appb-000030
在此不作限定。
示例性地，第二导电层200的厚度可以为
Figure PCTCN2020123332-appb-000031
例如，第二导电层200的厚度可以为
Figure PCTCN2020123332-appb-000032
第二导电层200的厚度可以为
Figure PCTCN2020123332-appb-000033
第二导电层200的厚度可以为
Figure PCTCN2020123332-appb-000034
在此不作限定。
示例性地，如图10、图11c所示，一行子像素对应一条辅助扫描线FG和一条辅助复位线FS。示例性地，辅助扫描线FG和辅助复位线FS可以沿F1方向延伸，沿F2方向排列。
示例性地，如图10、图11c、图12以及图13所示，各子像素可以包括补偿导电部BD。且同一子像素中，补偿导电部BD与驱动晶体管M0的栅极M0-G电连接。其中，针对同一子像素对应的第一扫描线G1和补偿导电部BD，第一扫描线G1在衬底基板1000的正投影与补偿导电部BD在衬底基板1000的正投影之间具有第一交叠区域SQ1，第一补偿电容CF1位于第一交叠区域SQ1，且第一补偿电容CF1由第一扫描线G1和补偿导电部BD之间的交叠部分形成。其中，位于第一交叠区域SQ1中的第一扫描线G1作为第一补偿电容CF1的第二极，位于第一交叠区域SQ1中的补偿导电部BD作为第一补偿电容CF1的第一极。示例性地，第一补偿电容CF1的第一极和第一补偿电容CF1的第二极之间的距离可以为
Figure PCTCN2020123332-appb-000035
例如，第一补偿电容CF1的第一极和第一补偿电容CF1的第二极之间的距离可以为
Figure PCTCN2020123332-appb-000036
第一补偿电容CF1的第一极和第一补偿电容CF1的第二极之间的距离可以为
Figure PCTCN2020123332-appb-000037
第一补偿电容CF1的第一极和第一补偿电容CF1的第二极之间的距离可以为
Figure PCTCN2020123332-appb-000038
第一补偿电容CF1的第一极和第一补偿电容CF1的第二极之间的距离可以为
Figure PCTCN2020123332-appb-000039
第一补偿电容CF1的第一极和第一补偿电容CF1的第二极之间的距离可以为
Figure PCTCN2020123332-appb-000040
在此不作限定。
示例性地，如图10、图11c所示，针对同一子像素对应的第一扫描线G1和补偿导电部BD，第一扫描线G1在衬底基板1000的正投影覆盖补偿导电部 BD在衬底基板1000的正投影。
示例性地，在上述的第二导电层200背离衬底基板1000一侧形成有第二层间介质层830，用于使氧化物半导体层700与第二导电层200绝缘设置。如图10、图11d、图12以及图13所示，示出了该像素电路的氧化物半导体层700。氧化物半导体层700位于第二层间介质层830背离衬底基板1000一侧。且氧化物半导体层700包括第一复位晶体管M1的有源层和阈值补偿晶体管M2的有源层。
示例性地，第二层间介质层830的厚度可以为
Figure PCTCN2020123332-appb-000041
例如，第二层间介质层830的厚度可以为
Figure PCTCN2020123332-appb-000042
第二层间介质层830的厚度可以为
Figure PCTCN2020123332-appb-000043
第二层间介质层830的厚度可以为
Figure PCTCN2020123332-appb-000044
在此不作限定。
示例性地，如图10、图11d、图12以及图13所示，在上述的第二层间介质层830背离衬底基板1000一侧形成有缓冲层870，在缓冲层870背离衬底基板1000一侧形成有氧化物半导体层700。示例性地，缓冲层870的材料可以是氧化硅，第二层间介质层830的材料可以是氮化硅。由于氧化物半导体层700与氮化硅直接接触会影响氧化物半导体层700中材料的特征。本公开实施例通过在第二层间介质层830与氧化物半导体层700之间设置缓冲层870，可以避免氧化物半导体层700与氮化硅直接接触，避免氮化硅对氧化物半导体层700的材料的特性造成影响。当然，也可以使第二层间介质层830的材料和缓冲层870的材料均设置为氧化硅。
示例性地，缓冲层870的厚度可以为
Figure PCTCN2020123332-appb-000045
例如，缓冲层870的厚度可以为
Figure PCTCN2020123332-appb-000046
缓冲层870的厚度可以为
Figure PCTCN2020123332-appb-000047
缓冲层870的厚度可以为
Figure PCTCN2020123332-appb-000048
在此不作限定。
示例性地，氧化物半导体层700的厚度可以为
Figure PCTCN2020123332-appb-000049
例如，氧化物半导体层700的厚度可以为
Figure PCTCN2020123332-appb-000050
氧化物半导体层700的厚度可以为
Figure PCTCN2020123332-appb-000051
氧化物半导体层700的厚度可以为
Figure PCTCN2020123332-appb-000052
在此不作限定。
并且，第一复位晶体管M1的有源层和阈值补偿晶体管M2的有源层可包括第三区、第四区以及位于第三区和第四区之间的第二沟道区。例如，图11d 示意出了第一复位晶体管M1的有源层的第二沟道区M1-A，阈值补偿晶体管M2的有源层的第二沟道区M2-A。需要说明的是，上述的第三区和第四区可为氧化物半导体层700中掺杂有n型杂质或p型杂质的区域，以形成的导体化区。从而可以使第三区和第四区作为有源层的源极区和漏极区，以进行电连接。
并且，如图10、图11d、图12以及图13所示，第一复位晶体管M1的有源层和阈值补偿晶体管M2的有源层可以为一体结构。示例性地，第一复位晶体管M1的有源层的第四区M1-D和阈值补偿晶体管M2的有源层的第四区共用。
示例性地，在氧化物半导体层700背离衬底基板1000一侧形成有第二栅绝缘层840。在述第二栅绝缘层840背离衬底基板1000一侧形成有第三导电层300。如图10、图11e、图12以及图13所示，示出了该像素电路的第三导电层300。第三导电层300可以包括：相互间隔设置的多条第二扫描线G2和多条第一复位线S1。其中，一行子像素对应一条第二扫描线G2和一条第一复位线S1。
示例性地，第二栅绝缘层840的厚度可以为
Figure PCTCN2020123332-appb-000053
例如，第二栅绝缘层840的厚度可以为
Figure PCTCN2020123332-appb-000054
第二栅绝缘层840的厚度可以为
Figure PCTCN2020123332-appb-000055
第二栅绝缘层840的厚度可以为
Figure PCTCN2020123332-appb-000056
在此不作限定。
示例性地，第三导电层300的厚度可以为
Figure PCTCN2020123332-appb-000057
例如，第三导电层300的厚度可以为
Figure PCTCN2020123332-appb-000058
第三导电层300的厚度可以为
Figure PCTCN2020123332-appb-000059
第三导电层300的厚度可以为
Figure PCTCN2020123332-appb-000060
在此不作限定。
其中，如图10、图11e所示，针对同一子像素对应的第二扫描线G2以及和阈值补偿晶体管M2，阈值补偿晶体管M2的有源层在衬底基板1000的正投影和第二扫描线G2在衬底基板1000的正投影具有第二交叠区域SQ2；且阈值补偿晶体管M2的沟道电容的第一部分电容位于所述第二交叠区域SQ2，且第一部分电容由第二扫描线G2和阈值补偿晶体管M2的有源层之间的交叠部分形成。例如，阈值补偿晶体管M2的有源层的第四区在衬底基板1000的 正投影和第二扫描线G2在衬底基板1000的正投影具有第二交叠区域SQ2；阈值补偿晶体管M2的沟道电容的第一部分电容位于第二交叠区域SQ2，阈值补偿晶体管M2的沟道电容的第一部分电容由第二扫描线G2和阈值补偿晶体管M2的有源层的第四区之间的交叠部分形成。
示例性地，如图10、图11e所示，针对同一子像素对应的辅助扫描线FG和阈值补偿晶体管M2，辅助扫描线FG和阈值补偿晶体管M2的有源层在衬底基板1000的正投影具有第三交叠区域SQ3；阈值补偿晶体管M2的沟道电容的第二部分电容位于第三交叠区域SQ3，且第二部分电容由辅助扫描线FG和阈值补偿晶体管M2的有源层之间的交叠部分形成。例如，辅助扫描线FG和阈值补偿晶体管M2的有源层的第四区在衬底基板1000的正投影具有第三交叠区域SQ3；阈值补偿晶体管M2的沟道电容还包括位于第三交叠区域SQ3中的辅助扫描线FG和阈值补偿晶体管M2的有源层的第四区。示例性地，第三交叠区域SQ3和第二交叠区域SQ2可以重合。
示例性地，如图10、图11e所示，针对同一子像素对应的阈值补偿晶体管M2和第二扫描线G2，第二扫描线G2在衬底基板1000的正投影与阈值补偿晶体管M2的有源层在衬底基板1000的正投影具有交叠区域。并且，针对同一子像素对应的阈值补偿晶体管M2和辅助扫描线FG，辅助扫描线FG在衬底基板1000的正投影与阈值补偿晶体管M2的有源层在衬底基板1000的正投影具有交叠区域。进一步地，针对同一子像素对应的阈值补偿晶体管M2和第二扫描线G2，第二扫描线G2在衬底基板1000的正投影与阈值补偿晶体管M2的有源层的沟道区在衬底基板1000的正投影具有交叠区域。并且，针对同一子像素对应的阈值补偿晶体管M2和辅助扫描线FG，辅助扫描线FG在衬底基板1000的正投影与阈值补偿晶体管M2的有源层的沟道区在衬底基板1000的正投影具有交叠区域。这样可以使阈值补偿晶体管M2形成双栅结构。从而可以提高阈值补偿晶体管M2的开态电流，进而提高阈值补偿晶体管M2的驱动能力，改善阈值补偿晶体管M2的晶体管特性。
并且，第二扫描线G2在衬底基板1000的正投影与阈值补偿晶体管M2 的有源层的沟道区在衬底基板1000的正投影具有交叠区域。以及，辅助扫描线FG在衬底基板1000的正投影与阈值补偿晶体管M2的有源层的沟道区在衬底基板1000的正投影具有交叠区域。这样还可以通过第二扫描线G2和辅助扫描线FG进行遮光，从而可以避免外界环境光通过显示面板的上下两侧入射到阈值补偿晶体管M2的有源层的沟道区上。
示例性地，如图10、图11e所示，针对同一子像素对应的第二扫描线G2和辅助扫描线FG，第二扫描线G2在衬底基板1000的正投影与辅助扫描线FG在衬底基板1000的正投影重叠。进一步地，针对同一子像素对应的第二扫描线G2和辅助扫描线FG，第二扫描线G2与辅助扫描线FG在衬底基板1000的外围区域电连接在一起。
示例性地，如图10、图11e所示，针对同一子像素对应的第一复位晶体管M1和第一复位线S1，第一复位线S1在衬底基板1000的正投影与第一复位晶体管M1的有源层在衬底基板1000的正投影具有交叠区域。并且，针对同一子像素对应的第一复位晶体管M1和辅助复位线FS，辅助复位线FS在衬底基板1000的正投影与第一复位晶体管M1的有源层在衬底基板1000的正投影具有交叠区域。进一步地，针对同一子像素对应的第一复位晶体管M1和第一复位线S1，第一复位线S1在衬底基板1000的正投影与第一复位晶体管M1的有源层的沟道区在衬底基板1000的正投影具有交叠区域。并且，针对同一子像素对应的第一复位晶体管M1和辅助复位线FS，辅助复位线FS在衬底基板1000的正投影与第一复位晶体管M1的有源层的沟道区在衬底基板1000的正投影具有交叠区域。这样可以使第一复位晶体管M1形成双栅结构。从而可以提高第一复位晶体管M1的开态电流，进而提高第一复位晶体管M1的驱动能力，改善第一复位晶体管M1的晶体管特性。
并且，第一复位线S1在衬底基板1000的正投影与第一复位晶体管M1的有源层的沟道区在衬底基板1000的正投影具有交叠区域。以及辅助复位线FS在衬底基板1000的正投影与第一复位晶体管M1的有源层的沟道区在衬底基板1000的正投影具有交叠区域。这样还可以通过第一复位线S1和辅助复 位线FS进行遮光，从而可以避免外界环境光通过显示面板的上下两侧入射到第一复位晶体管M1的有源层的沟道区上。
示例性地，如图10、图11e所示，针对同一子像素对应的第一复位线S1和辅助复位线FS，第一复位线S1在衬底基板1000的正投影与辅助复位线FS在衬底基板1000的正投影重叠。进一步地，针对同一子像素对应的第一复位线S1和辅助复位线FS，第一复位线S1和辅助复位线FS在衬底基板1000的外围区域电连接在一起。
示例性地，如图10、图11e所示，针对同一子像素对应的第一扫描线G1、第二扫描线G2以及第一复位线S1，第一扫描线G1在衬底基板1000的正投影位于第二扫描线G2和第一复位线S1在衬底基板1000的正投影之间。
示例性地，在上述的第三导电层背离衬底基板1000一侧形成有第三层间介质层850，在第三层间介质层850背离衬底基板1000一侧形成有第四导电层400。如图10、图11f、图12以及图13所示，示出了该像素电路的第四导电层400。第四导电层400可以包括相互间隔设置的多个第一连接部LB1、多个第二连接部LB2、多个第三连接部LB3、多个第四连接部LB4、多个第五连接部LB5、多个初始化信号线VINIT。其中，一个子像素可以包括一个第一连接部LB1、一个第二连接部LB2、一个第三连接部LB3、一个第四连接部LB4、一个第五连接部LB5、一个初始化信号线VINIT。
示例性地，第三层间介质层850的厚度可以为
Figure PCTCN2020123332-appb-000061
例如，第三层间介质层850的厚度可以为
Figure PCTCN2020123332-appb-000062
第三层间介质层850的厚度可以为
Figure PCTCN2020123332-appb-000063
第三层间介质层850的厚度可以为
Figure PCTCN2020123332-appb-000064
在此不作限定。
示例性地，第四导电层400的厚度可以为
Figure PCTCN2020123332-appb-000065
例如，第四导电层400的厚度可以为
Figure PCTCN2020123332-appb-000066
第四导电层400的厚度可以为
Figure PCTCN2020123332-appb-000067
第四导电层400的厚度可以为
Figure PCTCN2020123332-appb-000068
在此不作限定。
示例性地，如图10、图11f、图12以及图13所示，第一连接部LB1的第一端通过第一过孔GK1与补偿导电部BD电连接，第一连接部LB1的第二端通过第二过孔GK2与驱动晶体管的栅极电连接；第一连接部LB1的第三端 通过第三过孔GK3与阈值补偿晶体管M2的有源层的导体化区电连接。并且，第一过孔GK1贯穿第三层间介质层850、第二栅绝缘层840与第二层间介质层830。第二过孔GK2贯穿第三层间介质层850、第二栅绝缘层840、第二层间介质层830以及第一层间介质层820。第三过孔GK3贯穿第二栅绝缘层840和第三层间介质层850。
示例性地，如图10、图11f、图12以及图13所示，针对同一子像素对应的第一扫描线G1和第三过孔GK3，第一扫描线G1在衬底基板1000的正投影覆盖第三过孔GK3在衬底基板1000的正投影。
示例性地，如图10、图11f、图12以及图13所示，第一连接部LB1的第一端和第三端大致沿同一方向F1延伸，且第一连接部LB1的第一端、第二端以及第三端大致形成“T”字型。需要说明的是，在实际制备过程中，由于工艺误差，第一连接部LB1的第一端、第二端以及第三端大致形成“T”字型即可。
示例性地，如图10、图11f、图12以及图13所示，针对同一子像素，第二扫描线G2在衬底基板1000的正投影与第一连接部LB1在衬底基板1000的正投影之间具有第四交叠区域SQ4，第四交叠区域SQ4具有辅助电容，辅助电容由第二扫描线G2和第一连接部LB1之间的交叠部分形成。并且，辅助电容的电容值大致为Δc1。需要说明的是，由于工艺条件的限制或其他因素，辅助电容的电容值可能不能完成等于Δc1，可能会有一些偏差，因此辅助电容的电容值只要大致满足上述条件即可，均属于本发明的保护范围。
示例性地，如图10、图11f所示，初始化信号线VINIT通过第四过孔GK4与第一复位晶体管M1的有源层的导体化层电连接。其中，第四过孔GK4贯穿第二栅绝缘层840和第三层间介质层850。
示例性地，如图10、图11f所示，第四连接部LB4的第一端通过第五过孔GK5与阈值补偿晶体管M2的有源层的半导体层(例如第三区)电连接，第四连接部LB4的第二端通过第六过孔GK6与驱动晶体管M0的有源层的半导体层(例如第二区)电连接。其中，第五过孔GK5贯穿第二栅绝缘层840 和第三层间介质层850。第六过孔GK6贯穿第三层间介质层850、第二栅绝缘层840、第二层间介质层830、第一层间介质层820以及第一栅绝缘层810。
示例性地，如图10、图11g、图12以及图13所示，第四导电层400背离衬底基板1000一侧形成有层间绝缘层860，在层间绝缘层860背离衬底基板1000一侧形成有第五导电层500。如图10、图11f、图12以及图13所示，示出了该像素电路的第五导电层500。第五导电层500可以包括相互间隔设置的多条数据线DA、多条电源线VD以及多个阳极转接部YZ。其中，一个子像素包括一个阳极转接部YZ，一列子像素对应一条数据线DA和一条电源线VD。
示例性地，层间绝缘层860的厚度可以为
Figure PCTCN2020123332-appb-000069
例如，层间绝缘层860的厚度可以为
Figure PCTCN2020123332-appb-000070
层间绝缘层860的厚度可以为
Figure PCTCN2020123332-appb-000071
层间绝缘层860的厚度可以为
Figure PCTCN2020123332-appb-000072
在此不作限定。
示例性地，第五导电层500的厚度可以为
Figure PCTCN2020123332-appb-000073
例如，第五导电层500的厚度可以为
Figure PCTCN2020123332-appb-000074
第五导电层500的厚度可以为
Figure PCTCN2020123332-appb-000075
第五导电层500的厚度可以为
Figure PCTCN2020123332-appb-000076
在此不作限定。
示例性地，如图10、图11f、图11g所示，针对一个子像素，数据线DA通过第七过孔GK7与第二连接部LB2电连接，第二连接部LB2通过第八过孔GK8与数据写入晶体管M3的有源层的导体化区(例如第一区)电连接。其中，第七过孔GK7贯穿层间绝缘层860，第八过孔GK8贯穿第三层间介质层850、第二栅绝缘层840、第二层间介质层830、第一层间介质层820以及第一栅绝缘层810。示例性地，数据线DA在衬底基板1000的正投影覆盖电连接的第二连接部LB2在衬底基板1000的正投影。
示例性地，如图10、图11f、图11g所示，电源线VD通过第九过孔GK9与第三连接部LB3的第一端电连接，第三连接部LB3的第二端通过第十过孔GK10与第一发光控制晶体管M5的有源层的导体化区(例如第一区)电连接。第三连接部LB3的第三端通过第十一过孔GK11与存储导电部CC1a电连接。即电源线VD与第一电源端电连接，以向第一电源端传输电压。其中，第九 过孔GK9贯穿层间绝缘层860。第十过孔GK10贯穿第三层间介质层850、第二栅绝缘层840、第二层间介质层830、第一层间介质层820以及第一栅绝缘层810。第十过孔GK10贯穿层间绝缘层860、第三层间介质层850、第二栅绝缘层840、第二层间介质层830。
示例性地，如图10、图11f、图11g所示，第三连接部LB3的第一端和第二端大致沿方向F1延伸，且第三连接部LB3的第一端、第二端以及第三端大致形成倒“T”字型。需要说明的是，在实际制备过程中，由于工艺误差，第三连接部LB3的第一端、第二端以及第三端大致形成倒“T”字型即可。
示例性地，如图10、图11d、图11g所示，针对同一子像素对应的电源线VD和阈值补偿晶体管M2，电源线VD在衬底基板1000的正投影与阈值补偿晶体管M2的有源层在衬底基板1000的正投影具有交叠区域。进一步地，针对同一子像素对应的电源线VD和阈值补偿晶体管M2，电源线VD在衬底基板1000的正投影覆盖阈值补偿晶体管M2的有源层在衬底基板1000的正投影。
示例性地，如图10、图11d、图11g所示，针对同一子像素对应的电源线VD和第一复位晶体管M1，电源线VD在衬底基板1000的正投影与第一复位晶体管M1的有源层在衬底基板1000的正投影具有交叠区域。进一步地，针对同一子像素对应的电源线VD和第一复位晶体管M1，电源线VD在衬底基板1000的正投影覆盖第一复位晶体管M1的有源层在衬底基板1000的正投影。
进一步地，针对同一子像素对应的电源线VD、阈值补偿晶体管M2和第一复位晶体管M1，电源线VD在衬底基板1000的正投影覆盖阈值补偿晶体管M2和第一复位晶体管M1的有源层在衬底基板1000的正投影。
示例性地，如图10、图11d、图11g所示，针对同一子像素对应的电源线VD、第一过孔GK1、第二过孔GK2、第三过孔GK3以及第三交叠区域SQ3，电源线VD在衬底基板1000的正投影分别与第一过孔GK1、第二过孔GK2以及第三过孔GK3具有交叠区域，且电源线VD在衬底基板1000的正投影与 第四交叠区域SQ4不交叠。
阳极转接部YZ通过第十二过孔GK12与第五连接部LB5电连接，阳极转接部YZ通过第十四过孔GK14与发光器件的阳极电连接，阳极转接部YZ通过第十三过孔GK13与第二发光控制晶体管M6的有源层的导体化区(例如第二区)电连接。其中，第十二过孔GK12贯穿层间绝缘层860，第十三过孔GK13贯穿第三层间介质层850、第二栅绝缘层840、第二层间介质层830、第一层间介质层820以及第一栅绝缘层810。第十四过孔GK14贯穿第五导电层500与阳极所在层之间的平坦层。
示例性地，平坦层的厚度可以为
Figure PCTCN2020123332-appb-000077
例如，平坦层的厚度可以为
Figure PCTCN2020123332-appb-000078
平坦层的厚度可以为
Figure PCTCN2020123332-appb-000079
平坦层的厚度可以为
Figure PCTCN2020123332-appb-000080
在此不作限定。
示例性地，寄生电容是可以包括沟道电容和其他金属层之间交叠形成的耦合电容，或者，寄生电容也可以包括沟道电容。本申请中设置的补偿电容的大小可以考虑的寄生电容的大小。
基于同一公开构思，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述像素电路。该显示装置解决问题的原理与前述像素电路相似，因此该显示装置的实施可以参见前述像素电路的实施，重复之处在此不再赘述。
在具体实施时，在本公开实施例中，显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变 型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (32)

  1. 一种像素电路，其中，包括：
    数据写入晶体管，所述数据写入晶体管的栅极与第一扫描线电连接，所述数据写入晶体管的第一极与数据线电连接，所述数据写入晶体管的第二极与驱动晶体管的第一极电连接；其中，所述数据写入晶体管的有源层的材料为低温多晶硅材料；
    阈值补偿晶体管，所述阈值补偿晶体管的栅极与第二扫描线电连接，所述阈值补偿晶体管的第一极与所述驱动晶体管的栅极电连接，所述阈值补偿晶体管的第二极与所述驱动晶体管的第二极电连接；其中，所述阈值补偿晶体管的有源层的材料为金属氧化物半导体材料；
    补偿电路，所述补偿电路与所述驱动晶体管的栅极电连接；
    发光控制电路，分别与第一电源端、所述驱动晶体管的第一极、第二极以及发光器件的第一电极电连接，且被配置为在发光控制线的信号的控制下，将所述第一电源端与所述驱动晶体管的第一极导通，以及将所述驱动晶体管的第二极与所述发光器件的第一电极导通，驱动所述发光器件发光。
  2. 如权利要求1所述的像素电路，其中，所述补偿电路被配置为根据寄生电容对所述驱动晶体管的栅极的电压进行补偿。
  3. 如权利要求2所述的像素电路，其中，所述补偿电路包括：第一补偿电容；
    所述第一补偿电容的第一极与所述驱动晶体管的栅极电连接，所述第一补偿电容的第二极与所述第一扫描线电连接。
  4. 如权利要求3所述的像素电路，其中，所述寄生电容包括所述阈值补偿晶体管的栅极和第一极之间的沟道电容。
  5. 如权利要求4所述的像素电路，其中，所述阈值补偿晶体管的栅极和第一极之间的沟道电容的电容值为第一沟道电容值，所述第一补偿电容的电容值与所述第一沟道电容值之间的差值满足0±Δc1。
  6. 如权利要求2所述的像素电路，其中，所述补偿电路包括：第一补偿控制晶体管；
    所述第一补偿控制晶体管的栅极与所述第一扫描线电连接，所述第一补偿控制晶体管的第一极和第二极均与所述驱动晶体管的栅极电连接。
  7. 如权利要求6所述的像素电路，其中，所述寄生电容包括所述阈值补偿晶体管的栅极和第一极之间的沟道电容，所述阈值补偿晶体管的栅极和第一极之间的沟道电容的电容值为第一沟道电容值；
    所述第一补偿控制晶体管的栅极与第一极之间的沟道电容的电容值为第二沟道电容值，所述第一补偿控制晶体管的栅极与第二极之间的沟道电容的电容值为第三沟道电容值；所述第二沟道电容值与所述第三沟道电容值之和为总沟道电容值；
    所述总沟道电容值与所述第一沟道电容值之间的差值满足0±Δc2。
  8. 如权利要求2所述的像素电路，其中，所述补偿电路包括：第二补偿控制晶体管；
    所述第二补偿控制晶体管的栅极与所述第一扫描线电连接，所述第一补偿控制晶体管的第一极与所述驱动晶体管的栅极电连接，所述第一补偿控制晶体管的第二极浮接。
  9. 如权利要求8所述的像素电路，其中，所述寄生电容包括所述阈值补偿晶体管的栅极和第一极之间的沟道电容，所述阈值补偿晶体管的栅极和第一极之间的沟道电容的电容值为第一沟道电容值；
    所述第二补偿控制晶体管的栅极与第一极之间的沟道电容的电容值为第四沟道电容值；
    所述第四沟道电容值与所述第一沟道电容值之间的差值满足0±Δc3。
  10. 如权利要求2所述的像素电路，其中，所述补偿电路包括：第二补偿电容；
    所述第二补偿电容的第一极与所述驱动晶体管的栅极电连接，所述第二补偿电容的第二极与所述发光器件的第一电极电连接。
  11. 如权利要求1-10任一项所述的像素电路，其中，所述像素电路还包括：第一复位晶体管；
    所述第一复位晶体管的栅极与第一复位线电连接，所述第一复位晶体管的第一极与初始化信号线电连接，所述第一复位晶体管的第二极与所述驱动晶体管的栅极电连接。
  12. 如权利要求11所述的像素电路，其中，所述第一复位晶体管的有源层的材料为金属氧化物半导体材料。
  13. 如权利要求1-12任一项所述的像素电路，其中，所述像素电路还包括：第二复位晶体管；
    所述第二复位晶体管的栅极与第二复位线电连接，所述第二复位晶体管的第一极与初始化信号线电连接，所述第二复位晶体管的第二极与所述发光器件的第一电极电连接。
  14. 如权利要求1-13任一项所述的像素电路，其中，所述驱动电路包括：第一发光控制晶体管，第二发光控制晶体管以及存储电容；
    所述第一发光控制晶体管的栅极与所述发光控制线电连接，所述第一发光控制晶体管的第一极与所述第一电源端电连接，所述第一发光控制晶体管的第二极与所述驱动晶体管的第一极电连接；
    所述第二发光控制晶体管的栅极与所述发光控制线电连接，所述第二发光控制晶体管的第一极与所述驱动晶体管的第二极电连接，所述第二发光控制晶体管的第二极与所述发光器件的第一电极电连接；
    所述存储电容的第一极与所述第一电源端电连接，所述存储电容的第二极与所述驱动晶体管的栅极电连接。
  15. 一种显示面板，其中，包括：
    衬底基板，包括多个子像素，所述子像素包括像素电路，所述像素电路包括第一补偿电容和驱动晶体管；
    第一导电层，位于所述衬底基板上，且所述第一导电层包括第一扫描线和驱动晶体管的栅极；其中，一行子像素对应一条所述第一扫描线；
    第一层间介质层，位于所述第一导电层背离所述衬底基板一侧；
    第二导电层，位于所述第一层间介质层背离所述衬底基板一侧，且所述第二导电层包括补偿导电部；其中，所述子像素包括所述补偿导电部，且同一所述子像素中，所述补偿导电部与所述驱动晶体管的栅极电连接；
    其中，针对同一所述子像素对应的第一扫描线和补偿导电部，所述第一扫描线在所述衬底基板的正投影与所述补偿导电部在所述衬底基板的正投影之间具有第一交叠区域，所述第一补偿电容位于所述第一交叠区域，且所述第一补偿电容由所述第一扫描线和所述补偿导电部之间的交叠部分形成。
  16. 如权利要求15所述的显示面板，其中，针对同一所述子像素对应的第一扫描线和补偿导电部，所述第一扫描线在所述衬底基板的正投影覆盖所述补偿导电部在所述衬底基板的正投影。
  17. 如权利要求15或16所述的显示面板，其中，所述像素电路还包括阈值补偿晶体管；所述显示面板还包括：
    第二层间介质层，位于所述第二导电层背离所述衬底基板一侧；
    氧化物半导体层，位于所述第二层间介质层背离所述衬底基板一侧，且所述氧化物半导体层包括所述阈值补偿晶体管的有源层；
    第二栅绝缘层，位于所述氧化物半导体层背离所述衬底基板一侧；
    第三导电层，位于所述第二栅绝缘层背离所述衬底基板一侧，且所述第三导电层包括第二扫描线；其中，一行子像素对应一条所述第二扫描线；
    针对同一所述子像素对应的第二扫描线以及和阈值补偿晶体管，所述阈值补偿晶体管的有源层在所述衬底基板的正投影和所述第二扫描线在所述衬底基板的正投影具有第二交叠区域；所述阈值补偿晶体管的沟道电容的第一部分电容位于所述第二交叠区域，且所述第一部分电容由所述第二扫描线和所述阈值补偿晶体管的有源层之间的交叠部分形成。
  18. 如权利要求17所述的显示面板，其中，所述第二导电层还包括辅助扫描线；其中，一行子像素对应一条所述辅助扫描线；
    针对同一所述子像素对应的辅助扫描线和阈值补偿晶体管，所述辅助扫 描线和所述阈值补偿晶体管的有源层在所述衬底基板的正投影具有第三交叠区域；
    所述阈值补偿晶体管的沟道电容的第二部分电容位于所述第三交叠区域，且所述第二部分电容由所述辅助扫描线和所述阈值补偿晶体管的有源层之间的交叠部分形成。
  19. 如权利要求18所述的显示面板，其中，针对同一所述子像素对应的第二扫描线和辅助扫描线，所述第二扫描线在所述衬底基板的正投影与所述辅助扫描线在所述衬底基板的正投影重叠。
  20. 如权利要求17-19任一项所述的显示面板，其中，所述显示面板还包括：
    第三层间介质层，位于所述第三导电层背离所述衬底基板一侧；
    第四导电层，位于所述第三层间介质层背离所述衬底基板一侧，且所述第四导电层包括第一连接部；其中，所述第一连接部的第一端通过第一过孔与所述补偿导电部电连接，所述第一连接部的第二端通过第二过孔与所述驱动晶体管的栅极电连接；所述第一过孔贯穿所述第三层间介质层、所述第二栅绝缘层与所述第二层间介质层，所述第二过孔贯穿所述第三层间介质层、所述第二栅绝缘层、所述第二层间介质层以及所述第一层间介质层。
  21. 如权利要求20所述的显示面板，其中，所述第一连接部的第三端通过第三过孔与所述阈值补偿晶体管的有源层的导体化区电连接；所述第三过孔贯穿所述第二栅绝缘层和所述第三层间介质层。
  22. 如权利要求21所述的显示面板，其中，针对同一所述子像素对应的所述第一扫描线和所述第三过孔，所述第一扫描线在所述衬底基板的正投影覆盖所述第三过孔在所述衬底基板的正投影。
  23. 如权利要求22所述的显示面板，其中，所述第一连接部的第一端和第三端大致沿同一方向延伸，且所述第一连接部的第一端、第二端以及第三端大致形成“T”字型。
  24. 如权利要求20-23任一项所述的显示面板，其中，针对同一所述子像 素，所述第二扫描线在所述衬底基板的正投影与所述第一连接部在所述衬底基板的正投影之间具有第四交叠区域，所述第四交叠区域具有辅助电容，所述辅助电容由所述第二扫描线和所述第一连接部之间的交叠部分形成；
    所述辅助电容的电容值大致为Δc1。
  25. 如权利要求20-24任一项所述的显示面板，其中，所述显示面板还包括：
    层间绝缘层，位于所述第四导电层背离所述衬底基板一侧；
    第五导电层，位于所述层间绝缘层背离所述衬底基板一侧，且所述第五导电层包括数据线和电源线；其中，一列子像素对应一条所述数据线和一条所述电源线；
    针对同一所述子像素对应的电源线和阈值补偿晶体管，所述电源线在所述衬底基板的正投影与所述阈值补偿晶体管的有源层在所述衬底基板的正投影具有交叠区域。
  26. 如权利要求25所述的显示面板，其中，针对同一所述子像素对应的所述电源线、所述第一过孔、所述第二过孔、所述第三过孔以及所述第三交叠区域，所述电源线在所述衬底基板的正投影分别与所述第一过孔、所述第二过孔以及所述第三过孔具有交叠区域，且所述电源线在所述衬底基板的正投影与所述第四交叠区域不交叠。
  27. 如权利要求25或26所述的显示面板，其中，所述像素电路还包括第一复位晶体管，所述氧化物半导体层还包括所述第一复位晶体管的有源层；
    所述第三导电层还包括第一复位线；其中，一行子像素对应一条所述第一复位线；
    针对同一所述子像素对应的所述第一复位晶体管和所述第一复位线，所述第一复位线在所述衬底基板的正投影与所述第一复位晶体管的有源层在所述衬底基板的正投影具有交叠区域。
  28. 如权利要求27所述的显示面板，其中，针对同一所述子像素对应的电源线和第一复位晶体管，所述电源线在所述衬底基板的正投影与所述第一 复位晶体管的有源层在所述衬底基板的正投影具有交叠区域。
  29. 如权利要求28所述的显示面板，其中，针对同一所述子像素对应的所述第一扫描线、所述第二扫描线以及所述第一复位线，所述第一扫描线在所述衬底基板的正投影位于所述第二扫描线和所述第一复位线在所述衬底基板的正投影之间。
  30. 如权利要求29所述的显示面板，其中，所述像素电路还包括数据写入晶体管；所述显示面板还包括：
    硅半导体层，位于所述第一导电层与所述衬底基板之间，且所述硅半导体层包括所述数据写入晶体管的有源层；
    第一栅绝缘层，位于所述第一导电层与所述硅半导体层之间；
    针对同一所述子像素对应的所述第一扫描线和所述数据写入晶体管，所述第一扫描线在所述衬底基板的正投影与所述数据写入晶体管的有源层在所述衬底基板的正投影具有交叠区域。
  31. 如权利要求30所述的显示面板，其中，针对同一所述子像素对应的所述数据写入晶体管、所述阈值补偿晶体管的有源层以及所述补偿导电部，所述补偿导电部在所述衬底基板的正投影位于所述数据写入晶体管的有源层在所述衬底基板的正投影和所述阈值补偿晶体管的有源层对应的第三过孔在所述衬底基板的正投影之间。
  32. 一种显示装置，其中，包括如权利要求15-31任一项所述的显示面板。
PCT/CN2020/123332 2020-10-23 2020-10-23 像素电路、显示面板及显示装置 WO2022082751A1 (zh)

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