WO2018166172A1 - 像素驱动电路及其驱动方法、显示装置 - Google Patents

像素驱动电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2018166172A1
WO2018166172A1 PCT/CN2017/103708 CN2017103708W WO2018166172A1 WO 2018166172 A1 WO2018166172 A1 WO 2018166172A1 CN 2017103708 W CN2017103708 W CN 2017103708W WO 2018166172 A1 WO2018166172 A1 WO 2018166172A1
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Prior art keywords
transistor
control signal
voltage
capacitor
control
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PCT/CN2017/103708
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English (en)
French (fr)
Inventor
董甜
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京东方科技集团股份有限公司
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Priority to US15/769,018 priority Critical patent/US10546535B2/en
Publication of WO2018166172A1 publication Critical patent/WO2018166172A1/zh

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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present disclosure relates to the field of organic light emitting display technologies, and in particular, to a pixel driving circuit, a driving method thereof, and a display device.
  • OLED Organic Light-Emitting Diode
  • OLED has many advantages such as self-luminous, fast response, high contrast, wide viewing angle, etc.
  • OLED has been widely used in display devices.
  • the size of the ordinary OLED display is not very large, the power supply in the power supply circuit and the power supply lead of each pixel are not very long, that is, the resistance of the power supply wire is small, and therefore, the OLED display is in operation.
  • the power drop of the power supply wire is small, the voltage of each pixel is basically the same, and each pixel emits light of the same brightness, so there is no problem of uneven brightness of the OLED display; but with the OLED display
  • the size gradually increases, which makes the power supply in the power supply circuit and the power supply wire of each pixel point increase in length, that is, the resistance value of the power supply wire increases, resulting in the resistance drop of the power supply wire during the operation of the OLED display (IR drop)
  • the increase is such that the voltages of the pixels in different regions of the OLED display are inconsistent, and the pixels of different regions emit light of different brightness, thereby causing uneven brightness of the screen during the operation of the OLED display.
  • the present disclosure provides a pixel driving circuit, a driving method thereof, and a display device for improving uniformity of screen brightness of an OLED display.
  • a pixel driving circuit including: a capacitor, a reset unit, a data writing unit, a compensation unit, an emission control unit, a driving transistor, and a light emitting device;
  • the reset unit is connected to the first power voltage terminal, the first control signal terminal, the second control signal terminal, the first end of the capacitor, the first pole of the driving transistor, and the control terminal of the driving transistor, and And configured to write a first power voltage of the first power voltage terminal to the first end of the capacitor under the control of the first control signal of the first control signal end and the second control signal of the second control signal end to clear the upper end a voltage of the first end of the capacitor in a driving cycle;
  • the data writing unit is connected to the second control signal end, the data signal end, and the second end of the capacitor, and configured to be at the second control signal end Controlling, by the second control signal, a data signal of the data signal end is written to the second end of the capacitor;
  • the compensation unit is connected to the second control signal end, the third control signal
  • the pixel driving circuit provided by the present disclosure has the following beneficial effects: by compensating the threshold voltage of the driving transistor and the resistance voltage drop of the power supply line, the magnitude of the current flowing through the driving transistor is affected by the reference voltage signal and
  • the control of the data signal is independent of the threshold voltage Vth of the driving transistor, and is independent of the power supply signal and the negative pole of the power supply, eliminating the threshold voltage of the driving transistor, the power supply signal, and the influence of the negative pole of the power supply on the current flowing through the light emitting element, thereby avoiding the power supply wire being too long.
  • the problem of the voltage drop caused by the resistor makes the normal output of the data signal ensure the brightness of the display screen is uniform.
  • a driving method of the above pixel driving circuit including a plurality of driving periods, each of the driving periods including: in a first stage, the reset unit is to be first a supply voltage is written to the first end of the capacitor to clear the voltage at the first end of the capacitor in the third phase of the last drive cycle, the data write unit writing a data signal to the second end of the capacitor,
  • the compensation unit supplies a reference voltage to the first node; in the second phase, the reset unit stops writing the first power supply voltage to the first end of the capacitor, such that the first end of the trip voltage is discharged; a stage, the illumination control unit provides illumination to the illumination device Flow causing it to illuminate and lowering the voltage of the first node, the compensation unit writing the reduced voltage of the first node to the second end of the capacitor such that the voltage of the first end of the capacitor is according to its second The amount of change in the voltage at the terminal jumps.
  • a display device including the above pixel driving circuit is provided.
  • the driving method of the pixel driving circuit and the beneficial effects of the display device provided by the present disclosure are the same as those of the pixel driving circuit provided by the above technical solution, and are not described herein.
  • FIG. 1 illustrates a block diagram of a pixel driving circuit in accordance with an embodiment of the present disclosure
  • FIG. 2 shows a schematic structural diagram of a pixel driving circuit according to an embodiment of the present disclosure
  • FIG. 3 illustrates another structural schematic diagram of a pixel driving circuit according to an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram showing driving signals of the pixel driving circuit of FIG. 2;
  • FIG. 5 is a schematic diagram showing driving signals of the pixel driving circuit of FIG.
  • the transistors employed in all embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other device having the same characteristics.
  • the connection modes of the drain and the source of each transistor are interchangeable. Therefore, the drain and source of each transistor in the embodiment of the present disclosure are practically indistinguishable.
  • one of the drain and the source of the transistor is referred to as the first pole of the transistor, and the other is referred to as the second pole of the transistor.
  • FIG. 1 shows a block diagram of a pixel driving circuit in accordance with an embodiment of the present disclosure.
  • the pixel driving circuit includes a capacitor C, a reset unit 1, a data writing unit 2, a compensation unit 3, an emission control unit 4, a driving transistor DTFT, and a light emitting device 5.
  • the reset unit 1 is connected to the first power voltage terminal VDD, the first control signal terminal Sn1, the second control signal terminal Sn2, the first end of the capacitor C, the first pole of the driving transistor DTFT, and the driving The control terminal of the transistor DTFT.
  • the reset unit 1 is configured to write the first power voltage of the first power voltage terminal VDD under the control of the first control signal of the first control signal terminal Sn1 and the second control signal of the second control signal terminal Sn2 The first end of the capacitor C.
  • the data writing unit 2 is connected to the second control signal terminal Sn2, the data signal terminal 7 and the second terminal of the capacitor C.
  • the data writing unit 2 is configured to write the data signal of the data signal terminal 7 to the second end of the capacitor C under the control of the second control signal of the second control signal terminal Sn2.
  • the compensation unit 3 is connected to the second control signal terminal Sn2, the third control signal terminal Sn3, the reference voltage signal terminal 6, the second end of the capacitor C, and the first node S, wherein the first node S is A connection point of the second electrode of the driving transistor DTFT, the compensation unit 3, and the light emission control unit 4.
  • the compensation unit 3 is configured to provide a reference voltage of the reference voltage signal terminal 6 to the first node S under the control of the second control signal of the second control signal terminal Sn2, and at the third control signal terminal Sn3 Under the control of the three control signals, the voltage of the first node S is written to the second end of the capacitor C.
  • the illumination control unit 4 is connected to the third control signal terminal Sn3, the first node S, and the first end of the light emitting device 5.
  • the light emission control unit 4 is configured to supply a light-emitting current to the light-emitting device 5 to emit light under the control of the third control signal of the third control signal terminal Sn3, and to lower the voltage of the first node S.
  • the first end of the capacitor C is connected to the control terminal of the driving transistor DTFT.
  • the second end of the light emitting device 5 is connected to the second power voltage terminal VSS.
  • FIG. 2 shows a schematic structural diagram of a pixel driving circuit according to an embodiment of the present disclosure.
  • the reset unit 1 includes a first transistor M1 and a second transistor M2.
  • the control terminal of the first transistor M1 receives the first control signal Scan1 input by the first control signal terminal Sn1, and the first electrode of the first transistor M1 receives the first power voltage VVDD input by the first power voltage terminal VDD, and the first transistor M1
  • the second pole is connected to the first pole of the driving transistor DTFT.
  • the control terminal of the second transistor M2 receives the second control signal Scan2 input by the second control signal terminal Sn2, the first pole of the second transistor M2 is connected to the second pole of the first transistor M1, and the second pole of the second transistor M2 is The first end of the capacitor C is connected.
  • the data writing unit 2 includes a third transistor M3.
  • Third crystal The control end of the body tube M3 receives the second control signal input by the second control signal terminal Sn2, the first electrode of the third transistor M3 receives the data signal Vdata input from the data signal terminal 7, the second electrode of the third transistor M3 and the capacitor C The second end is connected.
  • the compensation unit 3 includes a fourth transistor M4 and a fifth transistor M5.
  • the control terminal of the fourth transistor M4 receives the second control signal Scan2 input by the second control signal terminal Sn2, the first pole of the fourth transistor M4 receives the reference voltage signal Vref input by the reference voltage signal terminal 6, and the second transistor M4 The poles are respectively connected to the second pole of the driving transistor DTFT and the first pole of the light emission control unit 4.
  • the control terminal of the fifth transistor M5 receives the third control signal Scan3 input by the third control signal terminal Sn3, the first pole of the fifth transistor M5 is connected to the second pole of the fourth transistor M4, and the second pole of the fifth transistor M5 is The second end of the capacitor C is connected.
  • the illumination control unit 4 includes a sixth transistor M6.
  • the control terminal of the sixth transistor M6 receives the third control signal Scan3 input by the third control signal terminal Sn3, the first pole of the sixth transistor M6 is connected to the second pole of the driving transistor DTFT, and the second pole of the sixth transistor M6 is illuminated.
  • the first ends of the device 5 are connected.
  • the light emitting device 5 is an organic light emitting diode OLED
  • the anode of the organic light emitting diode OLED is connected to the second electrode of the sixth transistor M6, and the cathode of the organic light emitting diode OLED is connected to the second power supply voltage terminal VSS.
  • the first power voltage VVDD provided by the first power voltage terminal and the second power voltage VVSS provided by the second power voltage terminal provided by the second power voltage terminal are used in the pixel driving circuit provided by the above embodiment. , supplied by an external power supply.
  • the driving transistor DTFT can be selected from a variety of models.
  • the driving transistor DTFT provided in this embodiment is an N-type transistor, and specifically, can be an N-channel MOSFET.
  • the types of the first to sixth transistors M1 to M6 mentioned in the present disclosure may be various, and any one of the first to sixth transistors M1 to M6 may be an N-type transistor or a P.
  • the type transistor is only different in controlling the level signal in which each transistor is turned on or off, but the first to sixth transistors M1 to M6 must be ensured to be turned on or off quickly and reliably.
  • the present disclosure exemplifies, for example, two pixel drive circuit configurations in FIGS. 2 and 3.
  • the second transistor M2, the third transistor M3, and the fourth transistor M4 are controlled by the same control signal, that is, the second control signal, and thus the second transistor M2, the third transistor M3, and the fourth Transistor M4 is a P-type transistor; fifth transistor M5 and sixth transistor M6 Controlled by the same control signal, that is, the third control signal, the fifth transistor M5 and the sixth transistor M6 are both N-type transistors.
  • the first transistor M1 is also a P-type transistor.
  • FIG. 3 illustrates another structural diagram of a pixel driving circuit according to an embodiment of the present disclosure. Specifically, the first transistor M1 to the sixth transistor M6 of the pixel driving circuit in FIG. 3 are connected in the same manner as the pixel driving circuit provided in FIG. 2. The difference is that the first to sixth transistors M1 to M6 of the pixel driving circuit in FIG. 3 are all P-type transistors.
  • the first supply voltage VVDD is greater than the sum of the reference voltage Vref and the threshold voltage Vth of the drive transistor, and the voltage Vdata of the data signal is less than the sum of the reference voltage Vref and the threshold voltage Vth of the drive transistor.
  • the present disclosure also provides a driving method of the above pixel driving circuit.
  • the pixel driving circuit includes a capacitor C, a reset unit 1, a data writing unit 2, a compensation unit 3, an emission control unit 4, a driving transistor DTFT, and a light emitting device 5.
  • the driving method includes a plurality of driving cycles, each of which includes:
  • the reset unit 1 writes the first power voltage VVDD to the first end of the capacitor C to clear the voltage of the first end of the capacitor C in the third phase of the last driving cycle
  • the writing unit 2 writes the data signal Vdata to the second end of the capacitor C
  • the compensation unit 3 supplies the reference voltage signal Vref to the first node, wherein the first node S is the first of the driving transistor DTFT a connection point of the diode, the compensation unit 3, and the illumination control unit 4;
  • the reset unit 1 stops writing the first power voltage VVDD to the first end of the capacitor C, so that the first end of the capacitor C is discharged;
  • the illumination control unit 4 supplies a light-emitting current to the light-emitting device 5 to cause it to emit light, and reduces the voltage of the first node S, and the compensation unit 3 reduces the voltage of the first node S after the reduction.
  • the second end of the capacitor C is written such that the voltage of the first end of the capacitor C jumps according to the amount of change in the voltage of its second terminal.
  • FIG. 4 is a view showing a driving signal of the pixel driving circuit of FIG. 2.
  • the second transistor M2, the third transistor M3, and the fourth transistor M4 of the pixel driving circuit in FIG. 2 are all P-type transistors, and the fifth transistor M5 and the sixth transistor M6 are both N-type transistors, correspondingly, 4 for controlling the second transistor M2, the third transistor M3, and the fourth transistor M4
  • the second control signal and the third control signal for controlling the fifth transistor M5 and the sixth transistor M6 are the same.
  • the pixel driving circuit operates by sequentially including the following three phases in one driving cycle: a first phase T1, a second phase T2, and a third phase T3.
  • the first control signal Scan1 is at a low level
  • the second control signal Scan2 is at a low level
  • the third control signal Scan3 is at a low level.
  • the first transistor M1 is controlled to be turned on by the driving of the first control signal Scan1.
  • the second transistor M2 is controlled to be turned on under the driving of the second control signal Scan2, so that the first power voltage VVDD is output from the second pole of the first transistor M1 to the first pole of the second transistor M2, and then through the second transistor M2.
  • the second pole is output to the first end of the capacitor C and the second node G, and the voltage of the first end of the capacitor C in the third phase T3 of the last driving cycle is cleared.
  • the voltage at the second node G is VVDD. Since the control terminal of the driving transistor DTFT is connected to the second node G, that is, to the first terminal of the capacitor C, the driving transistor DTFT is turned on in this stage.
  • the third transistor M3 is turned on, and the data signal Vdata is output from the first pole of the third transistor M3 to the second end of the capacitor C and the third node N. At this time, the third node N The voltage at the location is Vdata.
  • the fourth transistor M4 is turned on by the driving of the second control signal Scan2, and the reference voltage signal Vref is output from the first pole of the fourth transistor M4 to the first node S. At this time, the voltage at the first node S is Vref.
  • the sixth transistor M6 is controlled to be turned off, so that the organic light emitting diode OLED does not emit light.
  • the first control signal Scan1 is at a high level
  • the second control signal Scan2 is at a low level
  • the third control signal Scan3 is at a low level.
  • the second transistor M2, the third transistor M3, and the fourth transistor M4 are controlled to be turned on under the driving of the second control signal Scan2.
  • the first transistor M1 Under the driving of the first control signal Scan1, the first transistor M1 is controlled to be turned off, so that the first power supply voltage VVDD cannot be output to the first end of the capacitor C and the second node G.
  • the first end of the capacitor C is discharged through a loop formed by the second transistor M2, the driving transistor DTFT, and the fourth transistor M4.
  • the driving transistor DTFT When the capacitor C is discharged until the voltage at its first terminal is less than Vref+Vth, the driving transistor DTFT is turned off, and the capacitor C stops discharging, where Vth is the threshold voltage of the driving transistor. In other words, the capacitor C is discharged until the drive transistor DTFT is turned off.
  • the voltage of the second node G is reduced from VVDD to Vref+Vth, and the voltage of the first node S is still Vref, and the third node N The voltage is still Vdata.
  • the sixth transistor M6 is controlled to be turned off, so that the organic light emitting diode OLED does not emit light.
  • the gate-source voltage Vgs of the driving transistor DTFT must be smaller than the threshold voltage Vth of the driving transistor DTFT.
  • the driving transistor DTFT is at the critical value of being turned on and off. Point, at this time, the voltage of the second node G is Vref+Vth.
  • the first control signal Scan1 is at a low level
  • the second control signal Scan2 is at a high level
  • the third control signal Scan3 is at a high level.
  • the first transistor M1 is controlled to be turned on by the driving of the first control signal Scan1.
  • the second transistor M2, the third transistor M3, and the fourth transistor M4 are controlled to be turned off by the driving of the second control signal Scan2.
  • the fifth transistor M5 and the sixth transistor M6 are controlled to be turned on, so that the voltage of the first node S falls to Vs. Since the second electrode of the driving transistor DTFT is connected to the first node S, the voltage of the second electrode of the driving transistor also drops, and at this time, the driving transistor DTFT is turned on again.
  • the voltage Vs of the first node S is transmitted to the second terminal of the capacitor C through the fifth transistor M5 such that the voltage of the second terminal of the capacitor C is Vs, that is, the voltage at the third node N is Vs.
  • the amount of change Vs-Vdata of the voltage at the second end of the capacitor C jumps to the first end of the capacitor C, and the voltage at the first end of the capacitor C is Vref+Vth+Vs-Vdata, so that the driving transistor DTFT remains turned on. status.
  • the first power source voltage is transmitted to the organic light emitting diode through the first transistor M1, the driving transistor DTFT, and the sixth transistor M6, so that the organic light emitting diode emits light.
  • I OLED 0.5 ⁇ nCox(W/L)(V gs -V th ) 2 Formula 1
  • I OLED is the current flowing through the driving transistor DTFT;
  • ⁇ n is the mobility of the carrier;
  • Cox is the insulating layer capacitance per unit area;
  • W is the channel width of the driving transistor;
  • L is the channel length of the driving transistor;
  • Gs is the gate-source voltage of the driving transistor;
  • Vth is the threshold voltage of the driving transistor;
  • I OLED 0.5 ⁇ nCox(W/L)(V ref -V data ) 2 Formula 2
  • Equation 2 It can be seen from Equation 2 that, under the condition that other parameters are unchanged, the magnitude of the current flowing through the driving transistor DTFT is controlled by the reference voltage signal and the data signal, and the threshold voltage of the driving transistor, the first power supply voltage VVDD, and the second power supply voltage. Regardless of VVSS, the influence of the threshold voltage of the driving transistor, the first power voltage VVDD, and the second power voltage VVSS on the current flowing through the light emitting device is eliminated, and the IR Drop compensation for the second power voltage is realized, thereby avoiding the problem that the power supply wire is too long. The problem of resistance voltage drop makes the normal output of the data signal ensure the brightness of the display screen is uniform.
  • the first supply voltage VVDD is greater than the sum of the reference voltage Vref and the threshold voltage Vth of the drive transistor, and the voltage Vdata of the data signal is less than the sum of the reference voltage Vref and the threshold voltage Vth of the drive transistor.
  • this embodiment only introduces the provided pixel driving circuit by taking the above specific circuit structure as an example.
  • the reset unit 1, the data writing unit 2, and the compensation unit 3 of the pixel driving circuit 3 The illumination control unit 4 can also be implemented by other structures, and will not be described in detail herein.
  • the driving transistor DTFT can be selected from a wide variety of models.
  • the driving transistor DTFT provided in this embodiment is an N-type transistor, specifically, an N-channel MOSFET; and the second pole and the first of the N-type transistor The node S is connected.
  • the voltage of the first node S is provided by the second power supply voltage, and in the formula 2 for calculating the current, the voltage of the first node S is eliminated, and therefore, the setting of the N-type transistor makes the second The supply voltage has no effect on the current flowing through the illuminating element, ie an IR Drop compensation of the second supply voltage is achieved.
  • FIG. 5 is a schematic diagram showing driving signals of the pixel driving circuit of FIG.
  • the second transistor M2 to the sixth transistor M6 of the pixel driving circuit in FIG. 3 are all P-type transistors, and correspondingly, the second transistor M2, the third transistor M3, and the fourth transistor M4 are controlled in FIG.
  • the second control signal and the third control signal for controlling the fifth transistor M5 and the sixth transistor M6 are opposite.
  • first control signal and the second control signal in the second circuit structure are completely the same as the first control signal and the second control signal of the first circuit structure, and the second circuit structure
  • the period of the three control signals is also the same as the period of the third control signal of the first circuit configuration, and only the level of the third control signal of the second circuit structure and the level of the third control signal of the first circuit structure are Conversely at the same time, in this case, in the first phase, when the third control signal When the potential is high, the fifth transistor M5 and the sixth transistor M6 are turned off; in the second phase, when the third control signal is high, the fifth transistor M5 and the sixth transistor M6 are turned off, in the third stage. When the third control signal is low, the fifth transistor M5 and the sixth transistor M6 are turned on.
  • the embodiment further provides a display device, which includes the pixel driving circuit as described in the first embodiment, and the display device can well avoid the problem of the voltage drop due to the excessive length of the power supply wire, so that the data signal The normal output ensures uniform brightness of the display screen.
  • the display device may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, or a navigator.
  • a display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, or a navigator.

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Abstract

一种像素驱动电路及其驱动方法、显示装置。该像素驱动电路包括电容器（C）、复位单元（1）、数据写入单元（2）、补偿单元（3）、发光控制单元（4）、驱动晶体管（DTFT）和发光器件（5），其中复位单元（1）被配置为将第一电源电压端（VDD）的第一电源电压（VVDD）写入电容器（C）的第一端，数据写入单元（2）被配置为将数据信号端（7）的数据信号（Vdata）写入电容器（C）的第二端；补偿单元（3）被配置为将参考电压信号端（6）的参考电压（Vref）提供至第一节点（S），并且将下降后的第一节点（S）的电压写入电容器（C）的第二端；发光控制单元（4）被配置为向发光器件（5）提供发光电流使其发光，并且降低第一节点（S）的电压。

Description

像素驱动电路及其驱动方法、显示装置
本申请要求2017年03月17日提交的申请号为201710161844.8且发明名称为“像素驱动电路及其驱动方法、显示装置”的中国优先申请的优先权，通过引用将其全部内容并入于此。
技术领域
本公开涉及有机发光显示技术领域，尤其涉及一种像素驱动电路及其驱动方法、显示装置。
背景技术
有机发光二极管(Organic Light-Emitting Diode，以下简称OLED)显示器具有自发光、反应速度快、对比度高、视角广等诸多优点，OLED已越来越广泛地应用于显示装置中。
由于普通OLED显示器的尺寸不是很大，因此，供电电路中的电源与每个像素点的电源导线的长度都不是很长，即电源导线的阻值很小，因此，OLED显示器在工作过程中，电源导线的电阻压降(IR drop)很小，每个像素点的电压基本一致，每个像素点发出相同亮度的光，所以不存在OLED显示器的亮度不均的问题；但是随着OLED显示器的尺寸逐渐增大，这就使得供电电路中的电源与每个像素点的电源导线的长度增长，即电源导线的阻值增加，导致OLED显示器在工作过程中，电源导线的电阻压降(IR drop)增加，这样就使得OLED显示器中不同区域的像素点的电压不一致，不同区域的像素点发出不同亮度的光，从而导致了OLED显示器在工作过程中屏幕的亮度不均匀。
发明内容
本公开提供了一种像素驱动电路及其驱动方法、显示装置，用于提高OLED显示器屏幕亮度的均匀性。
根据本公开的一方面，提供了一种像素驱动电路，包括：电容器、复位单元、数据写入单元、补偿单元、发光控制单元、驱动晶体管和发光器件； 所述复位单元，连接第一电源电压端、第一控制信号端、第二控制信号端、所述电容器的第一端、所述驱动晶体管的第一极以及所述驱动晶体管的控制端，并且被配置为在第一控制信号端的第一控制信号以及第二控制信号端的第二控制信号的控制下，将第一电源电压端的第一电源电压写入所述电容器的第一端，以清除上一驱动周期中所述电容器的第一端的电压；所述数据写入单元，连接第二控制信号端、数据信号端以及所述电容器的第二端，并且被配置为在第二控制信号端的第二控制信号的控制下，将数据信号端的数据信号写入所述电容器的第二端；所述补偿单元，连接第二控制信号端、第三控制信号端、参考电压信号端、所述电容器的第二端以及第一节点，其中所述第一节点为所述驱动晶体管的第二极、所述补偿单元以及所述发光控制单元的连接点，并且所述补偿单元被配置为在第二控制信号端的第二控制信号的控制下，将参考电压信号端的参考电压提供至第一节点，并且在第三控制信号端的第三控制信号的控制下，将第一节点的电压写入所述电容器的第二端；所述发光控制单元，连接第三控制信号端、第一节点以及发光器件的第一端，并且被配置为在第三控制信号端的第三控制信号的控制下，向发光器件提供发光电流使其发光，并且降低第一节点的电压；所述电容器的第一端连接所述驱动晶体管的控制端；所述发光器件的第二端连接第二电源电压端。
与现有技术相比，本公开提供的像素驱动电路具有如下有益效果：通过对驱动晶体管的阈值电压和电源导线的电阻压降进行补偿，使得流过驱动晶体管的电流的大小受到参考电压信号和数据信号的控制，与驱动晶体管的阈值电压Vth无关，与供电信号以及电源负极无关，消除了驱动晶体管的阈值电压、供电信号以及电源负极对流过发光元件的电流影响，避免了由于电源导线过长引起的电阻压降的问题，使得数据信号的正常输出，保证显示器屏幕亮度均匀。
根据本公开的又一方面，提供了一种上述像素驱动电路的驱动方法，所述驱动方法包括多个驱动周期，每个所述驱动周期包括：在第一阶段，所述复位单元将第一电源电压写入电容器的第一端，以清除上一驱动周期的第三阶段中所述电容器的第一端的电压，所述数据写入单元将数据信号写入所述电容器的第二端，所述补偿单元将参考电压提供至第一节点；在第二阶段，所述复位单元停止将第一电源电压写入电容器的第一端，使得跳变电压的第一端进行放电；在第三阶段，所述发光控制单元向所述发光器件提供发光电 流使其发光，并且降低所述第一节点的电压，所述补偿单元将降低后的第一节点的电压写入电容器的第二端，使得所述电容器的第一端的电压根据其第二端的电压的变化量发生跳变。
根据本公开的另一方面，提供了一种包含上述像素驱动电路的显示装置。
与现有技术相比，本公开提供的像素驱动电路的驱动方法以及显示装置的有益效果与上述技术方案提供的像素驱动电路的有益效果相同，在此不做赘述。
附图说明
通过结合附图对本发明的优选实施例进行详细描述，本发明的上述和其他目的、特性和优点将会变得更加清楚，其中相同的标号指定相同结构的单元，并且在其中：
图1示出了根据本公开实施例的像素驱动电路的框图；
图2示出了根据本公开实施例的像素驱动电路的结构示意图；
图3示出了根据本公开实施例的像素驱动电路的另一种结构示意图；
图4示出了图2中的像素驱动电路的驱动信号示意图；
图5示出了图3中的像素驱动电路的驱动信号示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本实施例中，每个晶体管的漏极和源极的连接方式可以互换，因此，本公开实施例中各晶体管的漏极、源极实际是没有区别的。这里，为了描述方便，将晶体管的漏极和源极之一称作晶体管的第一极，而将另一个称作晶体管的第二极。
图1示出了根据本公开实施例的像素驱动电路的框图。如图1所示，在一个实施例中，该像素驱动电路包括：电容器C、复位单元1、数据写入单元2、补偿单元3、发光控制单元4、驱动晶体管DTFT和发光器件5。
所述复位单元1，连接第一电源电压端VDD、第一控制信号端Sn1、第二控制信号端Sn2、所述电容器C的第一端、所述驱动晶体管DTFT的第一极以及所述驱动晶体管DTFT的控制端。所述复位单元1被配置为在第一控制信号端Sn1的第一控制信号以及第二控制信号端Sn2的第二控制信号的控制下，将第一电源电压端VDD的第一电源电压写入所述电容器C的第一端。
所述数据写入单元2，连接第二控制信号端Sn2、数据信号端7以及所述电容器C的第二端。所述数据写入单元2被配置为在第二控制信号端Sn2的第二控制信号的控制下，将数据信号端7的数据信号写入所述电容器C的第二端。
所述补偿单元3，连接第二控制信号端Sn2、第三控制信号端Sn3、参考电压信号端6、所述电容器C的第二端以及第一节点S，其中所述第一节点S为所述驱动晶体管DTFT的第二极、所述补偿单元3以及所述发光控制单元4的连接点。所述补偿单元3被配置为在第二控制信号端Sn2的第二控制信号的控制下，将参考电压信号端6的参考电压提供至第一节点S，并且在第三控制信号端Sn3的第三控制信号的控制下，将第一节点S的电压写入所述电容器C的第二端。
所述发光控制单元4，连接第三控制信号端Sn3、第一节点S以及发光器件5的第一端。所述发光控制单元4被配置为在第三控制信号端Sn3的第三控制信号的控制下，向发光器件5提供发光电流使其发光，并且降低第一节点S的电压。
所述电容器C的第一端连接所述驱动晶体管DTFT的控制端。
所述发光器件5的第二端连接第二电源电压端VSS。
图2示出了根据本公开实施例的像素驱动电路的结构示意图。
如图2所示，在一个实施例中，例如，复位单元1包括：第一晶体管M1和第二晶体管M2。第一晶体管M1的控制端接收第一控制信号端Sn1输入的第一控制信号Scan1，第一晶体管M1的第一极接收第一电源电压端VDD输入的第一电源电压VVDD，第一晶体管M1的第二极与驱动晶体管DTFT的第一极相连。第二晶体管M2的控制端接收第二控制信号端Sn2输入的第二控制信号Scan2，第二晶体管M2的第一极与第一晶体管M1的第二极相连，第二晶体管M2的第二极与电容器C的第一端相连。
在一个实施例中，例如，数据写入单元2包括：第三晶体管M3。第三晶 体管M3的控制端接收第二控制信号端Sn2输入的第二控制信号，第三晶体管M3的第一极接收数据信号端7输入的数据信号Vdata，第三晶体管M3的第二极与电容器C的第二端相连。
在一个实施例中，例如，补偿单元3包括：第四晶体管M4和第五晶体管M5。第四晶体管M4的控制端接收第二控制信号端Sn2输入的第二控制信号Scan2，第四晶体管M4的第一极接收参考电压信号端6输入的参考电压信号Vref，第四晶体管M4的第二极分别与驱动晶体管DTFT的第二极和发光控制单元4的第一极相连。第五晶体管M5的控制端接收第三控制信号端Sn3输入的第三控制信号Scan3，第五晶体管M5的第一极与第四晶体管M4的第二极相连，第五晶体管M5的第二极与电容器C的第二端相连。
在一个实施例中，例如，发光控制单元4包括：第六晶体管M6。第六晶体管M6的控制端接收第三控制信号端Sn3输入的第三控制信号Scan3，第六晶体管M6的第一极与驱动晶体管DTFT的第二极相连，第六晶体管M6的第二极与发光器件5的第一端相连。
在一个实施例中，例如，发光器件5为有机发光二极管OLED，有机发光二极管OLED的阳极与第六晶体管M6的第二极相连，有机发光二极管OLED的阴极与第二电源电压端VSS相连。
其中，可以理解的是，上述实施例提供的像素驱动电路中所利用的第一电源电压端提供的高电位的第一电源电压VVDD和第二电源电压端提供的低电位的第二电源电压VVSS，由外部供电电源提供。
需要说明的是，驱动晶体管DTFT可以有很多种型号选择，本实施例提供的驱动晶体管DTFT为N型晶体管，具体的，可以为N沟道的MOSFET。
此外，本公开中所提到的第一晶体管M1至第六晶体管M6的型号可以是多种多样的，第一晶体管M1至第六晶体管M6中的任意一个晶体管可以是N型晶体管也可以是P型晶体管，只是控制每个晶体管导通或关断的电平信号不同，但是第一晶体管M1至第六晶体管M6必须保证可以快速地、可靠地被导通或被关断。本公开示例性地列举例如图2和图3中的两种像素驱动电路结构。
在图2所示的实施例中，第二晶体管M2、第三晶体管M3和第四晶体管M4受控于同一控制信号，即第二控制信号，因此第二晶体管M2、第三晶体管M3和第四晶体管M4均为P型晶体管；第五晶体管M5和第六晶体管M6 受控于同一控制信号，即第三控制信号，因此第五晶体管M5和第六晶体管M6均为N型晶体管。可选地，在该实施例中，第一晶体管M1也是P型晶体管。
图3示出了根据本公开实施例的像素驱动电路的另一种结构示意图。具体地，图3中的像素驱动电路的第一晶体管M1至第六晶体管M6的连接方式与图2中所提供的像素驱动电路的连接方式相同。不同的是，图3中的像素驱动电路的第一晶体管M1至第六晶体管M6均为P型晶体管。
在一个实施例中，第一电源电压VVDD大于参考电压Vref与驱动晶体管的阈值电压Vth的总和，数据信号的电压Vdata小于参考电压Vref与驱动晶体管的阈值电压Vth的总和。
本公开还提供了一种上述像素驱动电路的驱动方法。在一个实施例中，该像素驱动电路包括：电容器C、复位单元1、数据写入单元2、补偿单元3、发光控制单元4、驱动晶体管DTFT和发光器件5。所述驱动方法包括多个驱动周期，每个所述驱动周期包括：
在第一阶段，所述复位单元1将第一电源电压VVDD写入电容器C的第一端，以清除上一驱动周期的第三阶段中所述电容器C的第一端的电压，所述数据写入单元2将数据信号Vdata写入所述电容器C的第二端，所述补偿单元3将参考电压信号Vref提供至第一节点，其中所述第一节点S为所述驱动晶体管DTFT的第二极、所述补偿单元3以及所述发光控制单元4的连接点；
在第二阶段，所述复位单元1停止将第一电源电压VVDD写入电容器C的第一端，使得电容器C的第一端进行放电；
在第三阶段，所述发光控制单元4向所述发光器件5提供发光电流使其发光，并且降低所述第一节点S的电压，所述补偿单元3将降低后的第一节点S的电压写入电容器C的第二端，使得所述电容器C的第一端的电压根据其第二端的电压的变化量发生跳变。
下面结合图2和图4对用于驱动本公开所示例的第一种电路结构的方法进行说明。图4示出了图2中的像素驱动电路的驱动信号示意图。其中，图2中的像素驱动电路的第二晶体管M2、第三晶体管M3和第四晶体管M4均为P型晶体管并且第五晶体管M5和第六晶体管M6均为N型晶体管，相对应地，图4中的用于控制第二晶体管M2、第三晶体管M3和第四晶体管M4 的第二控制信号以及用于控制第五晶体管M5和第六晶体管M6的第三控制信号相同。
在一个实施例中，像素驱动电路的工作过程为：在一个驱动周期内，依次包括以下三个阶段：第一阶段T1、第二阶段T2和第三阶段T3。
在第一阶段T1，第一控制信号Scan1为低电平，第二控制信号Scan2为低电平，第三控制信号Scan3为低电平。
在第一控制信号Scan1的驱动下，控制第一晶体管M1导通。
在第二控制信号Scan2的驱动下，控制第二晶体管M2导通，从而第一电源电压VVDD从第一晶体管M1的第二极输出到第二晶体管M2的第一极，再经第二晶体管M2的第二极输出至电容器C的第一端和第二节点G，清除上一驱动周期的第三阶段T3中电容器C的第一端的电压。此时，第二节点G处的电压为VVDD。由于驱动晶体管DTFT的控制端连接到第二节点G，即与电容器C的第一端相连，因此，在此阶段中，驱动晶体管DTFT导通。在第二控制信号Scan2的驱动下，第三晶体管M3导通，数据信号Vdata从第三晶体管M3的第一极输出到电容器C的第二端以及第三节点N，此时，第三节点N处的电压为Vdata。在第二控制信号Scan2的驱动下，第四晶体管M4导通，参考电压信号Vref从第四晶体管M4的第一极输出到第一节点S，此时，第一节点S处的电压为Vref。
在第三控制信号Scan3的驱动下，控制第六晶体管M6关断，使得有机发光二极管OLED不发光。
在第二阶段T2，第一控制信号Scan1为高电平，第二控制信号Scan2为低电平，第三控制信号Scan3为低电平。
在第二控制信号Scan2的驱动下，控制第二晶体管M2、第三晶体管M3以及第四晶体管M4导通。
在第一控制信号Scan1的驱动下，控制第一晶体管M1关断，使得第一电源电压VVDD无法输出至电容器C的第一端以及第二节点G。电容器C的第一端通过第二晶体管M2、驱动晶体管DTFT以及第四晶体管M4构成的回路进行放电。当电容器C放电至其第一端的电压小于Vref+Vth时，驱动晶体管DTFT关断，电容器C停止放电，其中Vth为驱动晶体管的阈值电压。换言之，电容器C放电，直至驱动晶体管DTFT关断。此时，第二节点G的电压由VVDD降为Vref+Vth，第一节点S的电压仍然为Vref，第三节点N 的电压仍然为Vdata。
在第三控制信号Scan3的驱动下，控制第六晶体管M6关断，使得有机发光二极管OLED不发光。
值得注意的是，为使得驱动晶体管DTFT关断，驱动晶体管DTFT的栅源电压Vgs必须小于驱动晶体管DTFT的阈值电压Vth，当电容器C放电完成时，驱动晶体管DTFT处在导通和关断的临界点，此时，第二节点G的电压为Vref+Vth。
在第三阶段T3，第一控制信号Scan1为低电平，第二控制信号Scan2为高电平，第三控制信号Scan3为高电平。
在第一控制信号Scan1的驱动下，控制第一晶体管M1导通。
在第二控制信号Scan2的驱动下，控制第二晶体管M2、第三晶体管M3以及第四晶体管M4关断。
在第三控制信号Scan3的驱动下，控制第五晶体管M5和第六晶体管M6导通，使得第一节点S的电压下降至Vs。由于驱动晶体管DTFT的第二极连接到第一节点S，因此，驱动晶体管的第二极的电压也随之下降，此时驱动晶体管DTFT重新导通。第一节点S的电压Vs通过第五晶体管M5传输至电容器C的第二端，使得电容器C的第二端的电压为Vs，即第三节点N处的电压为Vs。这样，电容器C的第二端的电压的变化量Vs-Vdata跳变到电容器C的第一端，电容器C的第一端的电压为Vref+Vth+Vs-Vdata，使得驱动晶体管DTFT保持在导通状态。第一电源电压通过第一晶体管M1、驱动晶体管DTFT和第六晶体管M6传输至有机发光二极管，使得有机发光二极管发光。
值得注意的是，此阶段驱动晶体管DTFT的栅源电压为Vgs＝Vref+Vth-Vdata，由于流过驱动晶体管DTFT的电流的计算公式为：
IOLED＝0.5μnCox(W/L)(Vgs-Vth)2公式1
其中，IOLED为流过驱动晶体管DTFT的电流；μn为载流子的迁移率；Cox为单位面积的绝缘层电容；W为驱动晶体管的沟道宽度；L为驱动晶体管的沟道长度；Vgs为驱动晶体管的栅源电压；Vth为驱动晶体管的阈值电压；
将此阶段的驱动晶体管DTFT的栅源电压Vgs＝Vref+Vth-Vdata带入到公式1中得到流过驱动晶体管DTFT的电流为：
IOLED＝0.5μnCox(W/L)(Vref-Vdata)2公式2
由公式2可见，在其他参数不变的情况下，流过驱动晶体管DTFT的电流的大小受到参考电压信号和数据信号的控制，与驱动晶体管的阈值电压、第一电源电压VVDD以及第二电源电压VVSS无关，消除了驱动晶体管的阈值电压、第一电源电压VVDD以及第二电源电压VVSS对流过发光器件的电流影响，实现对第二电源电压的IR Drop补偿，避免了由于供电导线过长引起的电阻压降的问题，使得数据信号的正常输出，保证显示器屏幕亮度均匀。
在一个实施例中，第一电源电压VVDD大于参考电压Vref与驱动晶体管的阈值电压Vth的总和，数据信号的电压Vdata小于参考电压Vref与驱动晶体管的阈值电压Vth的总和。
另外，本实施例仅以上述具体的电路结构为例对所提供的像素驱动电路进行介绍，在本公开的其它实施例中，像素驱动电路的复位单元1、数据写入单元2、补偿单元3、发光控制单元4还可各自采用其它的结构实现，在此不再详述。
可以理解的是，驱动晶体管DTFT可以有很多种型号选择，本实施例提供的驱动晶体管DTFT为N型晶体管，具体的，可以为N沟道的MOSFET；由于N型晶体管的第二极与第一节点S相连，在第三阶段，第一节点S的电压为第二电源电压所提供，而计算电流的公式2中，第一节点S的电压被消除，因此，N型晶体管的设置使得第二电源电压对流过发光元件的电流没有影响，即实现对第二电源电压的IR Drop补偿。
下面结合图3和图5对用于驱动本公开所示例的第二种电路结构的方法进行说明。图5示出了图3中的像素驱动电路的驱动信号示意图。其中，图3中的像素驱动电路的第二晶体管M2至第六晶体管M6均为P型晶体管，相对应地，图5中的用于控制第二晶体管M2、第三晶体管M3和第四晶体管M4的第二控制信号以及用于控制第五晶体管M5和第六晶体管M6的第三控制信号相反。
值得注意的是，第二种电路结构中的第一控制信号、第二控制信号均与第一种电路结构的的第一控制信号、第二控制信号完全相同，第二种电路结构中的第三控制信号的周期与第一种电路结构的第三控制信号的周期也相同，仅第二种电路结构的第三控制信号的电平与第一种电路结构的第三控制信号的电平在同一时刻相反，这种情况下，在第一阶段时，当第三控制信号 为高电位时，第五晶体管M5与第六晶体管M6关断；在第二阶段时，当第三控制信号为高电位时，第五晶体管M5与第六晶体管M6关断，在第三阶段时，当第三控制信号为低电位时，第五晶体管M5与第六晶体管M6导通。
本实施例还提供了一种显示装置，该显示装置包括如实施例一所述的像素驱动电路，该显示装置很好的避免了由于供电导线过长引起的电阻压降的问题，使得数据信号的正常输出，保证显示器屏幕亮度均匀。
需要说明的是，上述实施例提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (13)

  1. 一种像素驱动电路，包括：电容器、复位单元、数据写入单元、补偿单元、发光控制单元、驱动晶体管和发光器件；
    所述复位单元，连接第一电源电压端、第一控制信号端、第二控制信号端、所述电容器的第一端、所述驱动晶体管的第一极以及所述驱动晶体管的控制端，并且被配置为在第一控制信号端的第一控制信号以及第二控制信号端的第二控制信号的控制下，将第一电源电压端的第一电源电压写入所述电容器的第一端；
    所述数据写入单元，连接第二控制信号端、数据信号端以及所述电容器的第二端，并且被配置为在第二控制信号端的第二控制信号的控制下，将数据信号端的数据信号写入所述电容器的第二端；
    所述补偿单元，连接第二控制信号端、第三控制信号端、参考电压信号端、所述电容器的第二端以及第一节点，其中所述第一节点为所述驱动晶体管的第二极、所述补偿单元以及所述发光控制单元的连接点，并且所述补偿单元被配置为在第二控制信号端的第二控制信号的控制下，将参考电压信号端的参考电压提供至第一节点，并且在第三控制信号端的第三控制信号的控制下，将第一节点的电压写入所述电容器的第二端；
    所述发光控制单元，连接第三控制信号端、第一节点以及发光器件的第一端，并且被配置为在第三控制信号端的第三控制信号的控制下，向发光器件提供发光电流使其发光，并且降低第一节点的电压；
    所述电容器的第一端连接所述驱动晶体管的控制端；
    所述发光器件的第二端连接第二电源电压端。
  2. 根据权利要求1所述的像素驱动电路，其中，所述复位单元包括第一晶体管和第二晶体管；其中，
    所述第一晶体管的控制端与第一控制信号端相连，所述第一晶体管的第一极与第一电源电压端相连，所述第一晶体管的第二极与所述驱动晶体管的第一极相连；
    所述第二晶体管的控制端与第二控制信号端相连，所述第二晶体管的第一极与所述第一晶体管的第二极相连，所述第二晶体管的第二极与所述电容器的第一端相连。
  3. 根据权利要求2所述的像素驱动电路，其中，所述数据写入单元包括第三晶体管；其中，
    所述第三晶体管的控制端与第二控制信号端相连，所述第三晶体管的第一极与所述数据信号端相连，所述第三晶体管的第二极与所述电容器的第二端相连。
  4. 根据权利要求3所述的像素驱动电路，其中，所述补偿单元包括第四晶体管和第五晶体管；其中，
    所述第四晶体管的控制端与第二控制信号端相连，所述第四晶体管的第一极与参考电压信号端相连，所述第四晶体管的第二极与所述第一节点相连；
    所述第五晶体管的控制端与第三控制信号端相连，所述第五晶体管的第一极与第四晶体管的第二极以及所述第一节点相连，所述第五晶体管的第二极与所述电容器的第二端相连。
  5. 根据权利要求4所述的像素驱动电路，其中，所述发光控制单元包括第六晶体管；其中，
    所述第六晶体管的控制端与第三控制信号端相连，所述第六晶体管的第一极与所述驱动晶体管的第二极相连，所述第六晶体管的第二极与所述发光器件的第一端相连。
  6. 根据权利要求5所述的像素驱动电路，其中，所述发光器件为有机发光二极管，所述有机发光二极管的阳极与发光控制单元相连，所述有机发光二极管的阴极与第二电源电压端相连。
  7. 根据权利要求6所述的像素驱动电路，其中，在第二晶体管、第三晶体管、第四晶体管、第五晶体管和第六晶体管均为P型晶体管的情况下，所述第二控制信号和第三控制信号相反；
    在第二晶体管、第三晶体管和第四晶体管均为P型晶体管并且第五晶体管和第六晶体管均为N型晶体管的情况下，所述第二控制信号和第三控制信号相同。
  8. 根据权利要求1所述的像素驱动电路，其中，第一电源电压大于参考电压与驱动晶体管的阈值电压的总和，数据信号的电压小于参考电压与驱动晶体管的阈值电压的总和。
  9. 一种如权利要求1-8中任一项所述的像素驱动电路的驱动方法，所述驱动方法包括多个驱动周期，每个所述驱动周期包括：
    在第一阶段，所述复位单元将第一电源电压写入电容器的第一端，以清除上一驱动周期的第三阶段中所述电容器的第一端的电压，所述数据写入单元将数据信号写入所述电容器的第二端，所述补偿单元将参考电压提供至第一节点；
    在第二阶段，所述复位单元停止将第一电源电压写入电容器的第一端，使得跳变电压的第一端进行放电；
    在第三阶段，所述发光控制单元向所述发光器件提供发光电流使其发光，并且降低所述第一节点的电压，所述补偿单元将降低后的第一节点的电压写入电容器的第二端，使得所述电容器的第一端的电压根据其第二端的电压的变化量发生跳变。
  10. 根据权利要求9所述的像素驱动电路的驱动方法，其中，
    在所述第一阶段，在所述复位单元将第一电源电压写入电容器的第一端时，所述驱动晶体管导通；
    在所述第二阶段，所述电容器的第一端进行放电，直至所述驱动晶体管关断；
    在所述第三阶段，在所述第一节点的电压降低之后，所述驱动晶体管再次导通。
  11. 根据权利要求9所述的像素驱动方法，其中，所述复位单元包括第一晶体管和第二晶体管，所述数据写入单元包括第三晶体管，所述补偿单元包括第四晶体管和第五晶体管，所述发光控制单元包括第六晶体管，以及
    在第二晶体管、第三晶体管、第四晶体管、第五晶体管和第六晶体管均为P型晶体管的情况下，所述第二控制信号和第三控制信号相反；
    在第二晶体管、第三晶体管和第四晶体管均为P型晶体管并且第五晶体管和第六晶体管均为N型晶体管的情况下，所述第二控制信号和第三控制信号相同。
  12. 根据权利要求9所述的像素驱动方法，其中，第一电源电压大于参考电压与驱动晶体管的阈值电压的总和，数据信号的电压小于参考电压与驱动晶体管的阈值电压的总和。
  13. 一种显示装置，其特征在于，所述显示装置包括如权利要求1-8任一项所述的像素驱动电路。
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