WO2016155205A1 - 移位寄存器、栅极驱动电路、显示装置及栅极驱动方法 - Google Patents

移位寄存器、栅极驱动电路、显示装置及栅极驱动方法 Download PDF

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Publication number
WO2016155205A1
WO2016155205A1 PCT/CN2015/087509 CN2015087509W WO2016155205A1 WO 2016155205 A1 WO2016155205 A1 WO 2016155205A1 CN 2015087509 W CN2015087509 W CN 2015087509W WO 2016155205 A1 WO2016155205 A1 WO 2016155205A1
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Prior art keywords
signal
control
pull
pole
transistor
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PCT/CN2015/087509
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English (en)
French (fr)
Inventor
陈华斌
封宾
袁剑峰
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Display Technology Co Ltd
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Priority to US14/908,703 priority Critical patent/US20170039968A1/en
Publication of WO2016155205A1 publication Critical patent/WO2016155205A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display

Definitions

  • the invention belongs to the technical field of display, and particularly relates to a shift register, a gate driving circuit, a display device and a gate driving method.
  • the basic principle of the TFT-LCD (Thin Film Transistor-Liquid Crystal Display) to realize one-frame display is to input a square wave of a certain width to each row of pixels in order from the top to the bottom by gate driving.
  • the gate is strobed, and the signal for each row of pixels is sequentially driven from the top to the bottom by the source.
  • a display device of such a structure is usually manufactured by using a COF (Chip On Film) or a COG (Chip On Glass) directly on a glass substrate by a gate driving circuit and a source driving circuit.
  • COF Chip On Film
  • COG Chip On Glass
  • the existing display device is manufactured by using a GOA (Gate Drive On Array) circuit design, which not only saves cost but also can be implemented on both sides of the panel compared with the existing COF or COG process.
  • the symmetrical aesthetic design can also eliminate the bonding area of the gate driving circuit and the peripheral wiring space, thereby realizing the design of the narrow frame of the display device and improving the productivity and yield of the display device.
  • TFTs thin film transistors
  • M8-M11 M8-M11
  • the present invention provides a shift register, a gate driving circuit, a display device, and a gate driving method that can realize a narrow bezel design in view of the above technical problems existing in the conventional gate driving circuit.
  • An aspect of the technical solution adopted to solve the technical problem of the present invention is to provide a shift register including a gate driving signal generating unit for outputting a gate driving signal, the shift register further comprising a plurality of signal output control modules, a plurality of signal output reset modules and a plurality of signal outputs; wherein
  • Each of the plurality of signal output control modules is connected to the gate drive signal generating unit at one end and to a corresponding one of the plurality of signal outputs at the other end, and each signal output control module And a control signal input end for outputting the gate driving signal outputted from the gate driving signal generating unit through the corresponding signal under the control of the control signal input by the control signal input end Terminal output
  • One end of each of the plurality of signal output reset modules is connected between a respective signal output control module and a signal output terminal for resetting an output signal of the signal output terminal connected thereto.
  • each of the signal output control modules includes a switching transistor, a first pole of the switching transistor is connected to the gate driving signal generating unit, and a second pole is connected to the signal output end and the corresponding The signal output reset module is connected to the control signal input terminal.
  • each of the signal output reset modules includes a fourth transistor; a first pole of the fourth transistor is connected between the signal output control module corresponding thereto and the signal output terminal, and second The pole is connected to the low voltage signal, and the control pole is connected to the reset signal input terminal.
  • the shift register further includes: a plurality of output noise reduction modules;
  • One end of each of the plurality of output noise reduction modules is coupled between a respective signal output control module and a signal output for denoising an output signal of the signal output connected thereto.
  • each of the output noise reduction modules includes an eleventh transistor, and the first pole of the eleventh transistor is connected between the signal output control module corresponding thereto and the signal output end, The two poles are connected to the low voltage signal, and the control pole is connected to the pull-down node of the gate drive signal generating unit.
  • the gate driving signal generating unit includes: an input module, a pull-up module, an input reset module, a pull-down control module, a pull-down module, and an input noise reduction module; wherein
  • the input module is connected to a signal input end of the shift register and a pull-up control node And controlling a potential of the pull-up control node according to a signal input by the signal input end, where the pull-up control node is a connection point between the input module and the pull-up module;
  • the pull-up module is connected between the pull-up control node and each signal output control module, and the control end is connected to the first clock signal input end for the potential of the pull-up control node and the first clock signal input end. Control of the input first clock signal to pull up the gate drive signal to be output to the signal output;
  • One end of the input reset module is connected to the pull-up control node, and the control end thereof is connected to the reset signal input end for pulling down the potential of the pull-up control node under the control of the reset signal input by the reset signal input end Reset
  • the pull-down control module is connected to the pull-down node, and its control end is connected to the second clock signal input terminal for controlling the potential of the pull-down node according to the second clock signal input from the second clock signal input end,
  • the pull-down node is a connection point of the pull-down control module and the pull-down module;
  • the pull-down module is connected between the pull-down node and the pull-up control node, and is configured to pull down the potential of the pull-down node under the control of the potential of the pull-up control node;
  • the input noise reduction module is connected between the pull-up control node and the pull-down node for reducing output noise of the pull-up control node under the control of the potential of the pull-down node.
  • the input module includes a first transistor; the input reset module includes a second transistor; the pull-up module includes a third transistor and a storage capacitor; and the pull-down control module includes a fifth transistor and a ninth transistor
  • the pull-down module includes a sixth transistor and an eighth transistor; the input noise reduction module includes a tenth transistor;
  • the first pole and the control pole of the first transistor are connected to the signal input end of the shift register, and the second pole is connected to the pull-up control node;
  • the first pole of the second transistor is connected to the pull-up control node, the second pole is connected to a low voltage signal, and the control pole is connected to the reset signal input end;
  • a first pole of the third transistor is connected to the first clock signal input end, a second pole is connected to the second end of the storage capacitor and the plurality of signal output control modules, and the control pole is connected to the pull-up control node And a first end of the storage capacitor;
  • a first pole of the fifth transistor and a first pole and a control pole of the ninth transistor are connected to the second clock signal input end, and a second pole of the fifth transistor is connected to the pull-down section Point, the control electrode of the fifth transistor is connected to the second pole of the ninth transistor;
  • a first pole of the sixth transistor is connected to the pull-down node, a second pole of the sixth transistor and the eighth transistor is connected to a low voltage signal, and a control electrode of the sixth transistor and the eighth transistor is connected The pull-up control node, the first pole of the eighth transistor is connected to the gate of the fifth transistor and the second pole of the ninth transistor;
  • the first pole of the tenth transistor is connected to the pull-up control node, the second pole is connected to a low voltage signal, and the control pole is connected to the pull-down node.
  • each of the signal output control modules includes a switching transistor; each of the signal output reset modules includes a fourth transistor, and each of the output noise reduction modules includes an eleventh transistor;
  • each of the switching transistors is connected to a second end of the storage capacitor, and a second end is respectively connected to the corresponding signal output end, and the control poles are respectively connected to the corresponding control signal input ends;
  • a first pole of each of the fourth transistors is connected between the corresponding signal output terminal and the second pole of the switching transistor, the second pole is connected to a low voltage signal, and the control poles are all connected to the reset signal input end.
  • a first pole of each of the eleventh transistors is connected between a second pole of the switching transistor corresponding thereto and the signal output terminal, a second pole is connected to the low voltage signal, and a control pole is connected to the pull-down node.
  • the shift register comprises two of said signal output control modules, two of said signal output reset modules and two of said signal outputs.
  • a second aspect of the technical solution adopted to solve the technical problem of the present invention is a gate driving circuit including a plurality of cascaded shift registers as described above,
  • the signal output by each of the plurality of signal outputs of each stage of the shift register is used to drive a gate line.
  • a third aspect of the technical solution adopted to solve the technical problem of the present invention is a display device including the above-described gate driving circuit.
  • a fourth aspect of the technical solution adopted to solve the technical problem of the present invention is a gate drive Methods, including:
  • the plurality of signal output terminals in the shift register output the plurality of gate drive signals in a time-sharing manner by using the respective connected signal output control modules, and output the reset module to the plurality of signals by using the respective connected signals.
  • the output signals of the signal outputs are reset.
  • said gate drive circuit comprises a plurality of cascaded shift registers
  • said gate drive method comprises using a signal output by each of a plurality of signal outputs of each stage of the shift register for Drive a grid line.
  • the shift register of the present invention has a plurality of signal outputs, and has a plurality of signal output control modules and a plurality of signal output reset modules for controlling the plurality of signal outputs to output signals, that is, in the present invention
  • Each shift register can be used to drive a plurality of gate lines, so applying the shift register to the display panel can reduce the number of shift registers used, thereby further reducing the footprint of the GOA circuit, thereby enabling The design of the ultra-narrow bezel of the display device in the true sense.
  • 1 is a circuit schematic diagram of a conventional shift register
  • Figure 2 is a schematic illustration of a shift register in accordance with the present invention.
  • Figure 3 is a schematic illustration of a preferred form of a shift register in accordance with the present invention.
  • FIG. 4 is a schematic diagram of another preferred mode of a shift register in accordance with the present invention.
  • FIG. 5 is a circuit schematic diagram of a shift register in accordance with some embodiments of the present invention.
  • FIG. 6 is a timing diagram showing the operation of a shift register in accordance with some embodiments of the present invention.
  • the transistor used in some embodiments of the present invention may be a thin film transistor or a field effect transistor or a similar device having equivalent characteristics, which is not specifically limited in the present invention. Due to the crystal used The source and drain of the tube are symmetrical, so the source and drain are indistinguishable. In the embodiment of the present invention, in order to distinguish the source and the drain of the transistor, one of the poles is referred to as a first pole, the other pole is referred to as a second pole, and the gate is referred to as a gate. Further, the transistors can be classified into an N-type and a P-type according to the characteristics of the transistors, and the following embodiments are described as N-type transistors.
  • the source of the first very N-type transistor and the drain of the second N-type transistor are turned on when the gate of the control electrode is at a high level.
  • the state of each pole is opposite to that of the above-described N-type transistor. It is conceivable that the implementation of the P-type transistor is easily conceivable by those skilled in the art without any creative work, and therefore falls within the protection scope of the embodiments of the present invention.
  • a shift register in accordance with one embodiment of the present invention is described with reference to FIG.
  • the shift register includes a gate driving signal generating unit for outputting a gate driving signal, and includes a plurality of signal output control modules, a plurality of signal output resetting modules, and a plurality of signal output terminals (OUTPUT- 1, OUTPUT-2).
  • 2 is a diagram showing two signal output control modules, two signal output reset modules, and two signal output terminals respectively, but the example does not constitute a limitation of the present invention, and the present invention can output signals. The line is expanded to more.
  • Each of the signal output control modules is connected to the gate drive signal generating unit at one end and to a corresponding one of the signal outputs at the other end. And each signal output control module further has a respective control signal input end (Control-1, Control-2) for controlling under the control signal input by the control signal input end (Control-1, Control-2), The gate drive signal output from the gate drive signal generating unit is output through the corresponding signal output terminals (OUTPUT-1, OUTPUT-2). One end of each signal output reset module is connected between the corresponding signal output control module and the signal output terminal for resetting the output signal of the signal output terminal connected thereto.
  • the shift register includes a gate drive signal generating unit, a plurality of signal output control modules, and a plurality of signal output reset modules, and has a plurality of signal output terminals, it can be understood that each signal output end is a gate.
  • the line provides a gate drive signal, so a shift register can provide a gate drive signal for a plurality of gate lines, so applying the shift register to the display panel can reduce the number of shift registers used, thereby further The footprint of the GOA circuit is reduced, thereby enabling the design of a narrow frame of the display device in a true sense.
  • the above shift The specific implementation of the memory is shown in the following embodiment.
  • each of the signal output control modules includes a switching transistor, a first pole of the switching transistor is connected to the gate driving signal generating unit, and a second pole is connected to the signal output corresponding thereto. And the signal output reset module, and the control pole is connected to the control signal input end.
  • each signal output control module includes only one switching transistor. By controlling the opening and closing of the switching transistor, it is possible to control whether the corresponding signal output terminal outputs a gate driving signal.
  • the signal output control module has a simple structure and is easy to control. , the cost is lower.
  • each of the signal output reset modules includes a fourth transistor; a first pole of the fourth transistor is coupled between the signal output control module corresponding thereto and the signal output terminal The second pole is connected to the low voltage signal, and the control pole is connected to the reset signal input terminal.
  • each signal output reset module includes only a fourth transistor, and the signal outputted by the signal output terminal can be reset by controlling a fourth transistor, and the signal output reset module has a simple structure and is easy to control. The cost is lower.
  • the embodiment provides a shift register including a gate driving signal generating unit, a plurality of signal output control modules, a plurality of signal output reset modules, and a plurality of signal output terminals (OUTPUT-1, OUTPUT). -2), wherein the gate driving signal generating unit of the embodiment comprises: an input module, a pull-up module, and an input reset module.
  • the input module is connected between the signal input terminal INPUT of the shift register and the pull-up control node PU, and is configured to control the potential of the pull-up control node PU according to the signal input by the signal input terminal INPUT, and pull up the control node.
  • the PU is the connection point between the input module and the pull-up module.
  • the pull-up module is connected between the pull-up control node PU and each signal output control module, and its control end is connected to the first clock signal input terminal CLK for the potential of the pull-up control node PU and the first clock signal input end.
  • the control of the first clock signal input by CLK pulls up the gate drive signal to be output to the signal output terminal (that is, the pull-up is high).
  • Each signal output control module is connected to the pull-up module at one end and to the corresponding one of the signal outputs OUTPUT(N) at the other end (where the signal outputs are all represented by OUTPUT(N)), each signal controlling the output module Also connected to the respective control signal input Control (N) for control signal input Control (N) Under the control of the input control signal, the pull-up gate drive signal output from the pull-up module is output through the corresponding signal output terminal OUTPUT(N).
  • One end of the input reset module is connected to the pull-up control node PU, and the control end thereof is connected to the reset signal input terminal RESET for pulling down and resetting the potential of the pull-up control node PU according to the control of the reset signal input by the reset signal input terminal RESET ( That is, the pull-down is low level.
  • the other end of the input reset module is connected to the low voltage signal VSS.
  • One end of each signal output reset module is connected between the corresponding signal output terminal OUTPUT (N) and the output control module, and its control terminal is connected to the reset signal input terminal RESET for reset signal input according to the reset signal input terminal RESET.
  • the control is to reset the potential of the output signal of the signal output terminal OUTPUT (N) (that is, pull down to a low level).
  • the other end of the signal output reset module is connected to the low voltage signal VSS.
  • the shift register of the embodiment has a plurality of signal output terminals, and has a plurality of signal output control modules for controlling the output of the plurality of signal output terminals and a plurality of signal output reset modules
  • the present embodiment is also said to be
  • a shift register in the example can be used to drive a plurality of gate lines, so applying the shift register to the display panel can reduce the number of shift registers used, thereby further reducing the footprint of the GOA circuit. It is possible to realize the design of the ultra-narrow bezel of the display device in the true sense.
  • the gate driving signal generating unit of the shift register of this embodiment further includes: a pull-down control module and a pull-down module.
  • One end of the pull-down control module is connected to the pull-down node PD, and its control terminal is connected to the second clock signal input terminal CLKB for controlling the potential of the pull-down node PD according to the second clock signal input from the second clock signal input terminal CLKB.
  • the pull-down node PD is the connection point of the pull-down control module and the pull-down module.
  • the pull-down module is connected between the pull-down node PD and the pull-up control node PU for turning on the control of the potential of the pull-up control node PU, and pulls the potential of the pull-down node PD to a low level by connecting to the low voltage signal VSS. To reduce the output noise of the pull-down node PD.
  • the shift register further comprises: an input noise reduction module and a plurality of output noise reduction modules.
  • the input noise reduction module is connected between the pull-up control node PU and the pull-down node PD for turning on under the control of the potential of the pull-down node PD, and reduces the output noise of the pull-up control node PU by connecting to the low voltage signal VSS.
  • each of the plurality of output noise reduction modules is connected between the respective corresponding signal output terminal OUTPUT(N) and the signal output control module, and the control terminal is connected to the pull-down node PD for pulling down the potential of the node PD Control open, pass through A low voltage signal VSS is received to reduce the output noise of the signal output terminal OUTPUT(N) connected thereto.
  • the shift register in this embodiment includes two signal output control modules and two signal output reset modules, and corresponding two signal output ends. That is to say, each shift register is used to drive two gate lines.
  • the shift register of this embodiment is not limited to the structure including only two signal output control modules and two signal output reset modules, and may also include three, four or more signal output control modules and signal outputs. Reset the module to drive multiple gate lines.
  • the shift register of this embodiment can drive a plurality of gate lines, so that a smaller number of shift register units can be used to drive the gate lines on the display panel, thereby reducing the number of shift registers used. Thereby, the occupied space of the GOA circuit is further reduced, thereby enabling the design of the ultra-narrow bezel of the display device in a true sense.
  • the input module includes a first transistor M1; the input reset module includes a second transistor M2; and the pull-up module includes a third transistor M3 and a storage capacitor C1; each signal output
  • the control modules each include a switching transistor M12/M13; each of the signal output reset modules includes a fourth transistor M4; the pull-down control module includes a fifth transistor M5 and a ninth transistor M9; and the pull-down module includes a sixth transistor M6 and an eighth transistor M8;
  • the input noise reduction module includes a tenth transistor M10; each of the output noise reduction modules includes an eleventh transistor M11.
  • the shift register is used to output two driving signals, that is, two signal output control modules, two signal output reset modules, two output noise reduction modules, and two signal output terminals (OUTPUT-1, OUTPUT-2)
  • driving signals that is, two signal output control modules, two signal output reset modules, two output noise reduction modules, and two signal output terminals (OUTPUT-1, OUTPUT-2)
  • the first pole and the control pole of the first transistor M1 are connected to the signal input terminal INPUT of the shift register, and the second pole is connected to the pull-up control node PU.
  • the first pole of the second transistor M2 is connected to the pull-up control node PU, the second pole is connected to the low voltage signal VSS, and the gate is connected to the reset signal input terminal RESET.
  • the first pole of the third transistor M3 is connected to the first clock signal input terminal CLK, the second pole is connected to the second end of the storage capacitor and the first pole of the plurality of switching transistors M12 and M13, and the control pole is connected to the pull-up control node PU and the storage The first end of capacitor C1.
  • the two switching transistors that is, the first poles of the switching transistor M12 and the switching transistor M13 are connected to the second pole of the third transistor M3, and the second poles of the two switching transistors are respectively connected to the respective signal output terminals OUTPUT-1 and signals Output terminal OUTPUT-2 (ie: the second pole of the switching transistor M12 is connected to the signal output OUTPUT-1; the second pole of the switching transistor M13 is connected to the signal output terminal OUTPUT-2), and the corresponding signal is outputted to the first pole of the fourth transistor M4 in the reset module, and the control poles of the two switching transistors are respectively connected and controlled
  • the signal input terminal Control-1 and the control signal input terminal Control-2 ie, the control electrode of the switching transistor M12 is connected to the control signal input terminal Control-1; the control electrode of the switching transistor M13 is connected to the control signal input terminal Control-2).
  • the first poles of the fourth transistors M4 of the two signal output reset modules are respectively connected to the second poles of the switching transistors M12 and M13 of the respective corresponding signal output control modules, and the tenth of the corresponding output noise reduction modules respectively
  • the first pole of one transistor M11 is connected
  • the second pole of each fourth transistor M4 is connected to the low voltage signal VSS
  • the gate is connected to the reset signal input terminal RESET.
  • the first pole of the fifth transistor M5 and the first pole and the control pole of the ninth transistor M9 are connected to the second clock signal input terminal CLKB
  • the second pole of the fifth transistor M5 is connected to the pull-down node PD
  • the control electrode of the fifth transistor M5 is connected.
  • the first pole of the sixth transistor M6 is connected to the pull-down node PD
  • the second pole of the sixth transistor M6 and the eighth transistor M8 is connected to the low voltage signal VSS
  • the sixth transistor M6 and the eighth transistor M8 are connected to the pull-up control node PU
  • the first pole of the eight transistor M8 is connected to the gate of the fifth transistor M5 and the second pole of the ninth transistor M9.
  • the first pole of the tenth transistor M10 is connected to the pull-up control node PU
  • the second pole is connected to the low voltage signal VSS
  • the control pole is connected to the pull-down node PD.
  • the first poles of the eleventh transistor M11 of the two output noise reduction modules are all connected to the second transistor of the switching transistor M12 and the switching transistor M13 in the corresponding signal output control module, and the second pole of the eleventh transistor is connected
  • the low voltage signal VSS is connected to the pull-down node PD.
  • a gate driving circuit is further provided, the gate driving circuit includes a plurality of cascaded shift registers, and a signal output by the gate driving signal generating unit of each stage shift register is used as An input signal of the signal input terminal INPUT of the shift register of the shift register of the shift register; a signal outputted by each of the plurality of signal output terminals OUTPUT (N) of each shift register is used to drive a row of gate lines .
  • the gate driving circuit in this embodiment has a simple structure, is easy to implement, and can reduce the number of shift registers used, thereby further reducing the occupied space of the GOA circuit, thereby being applicable to a display device for realizing The design of the ultra-narrow bezel of the display device in the true sense.
  • the present embodiment further provides a display device including the above-described gate driving circuit.
  • the display device can be: mobile phone, tablet computer, television, display, notebook Any product or component that has a display function, such as a computer, digital photo frame, and navigator.
  • the display device of the present embodiment includes the above-described gate driving circuit, an ultra-narrow bezel design can be realized.
  • the embodiment further provides a gate driving method, including:
  • the plurality of signal output terminals in the shift register output the plurality of gate drive signals in a time-sharing manner by using the respective connected signal output control modules, and output the reset module to the plurality of signals by using the respective connected signals.
  • the output signals of the signal outputs are reset.
  • said gate drive circuit comprises a plurality of cascaded shift registers
  • said gate drive method comprises using a signal output by each of a plurality of signal outputs of each stage of the shift register for Drive a grid line.
  • the shift register when displaying a picture by the shift register of this embodiment, since the shift register has, for example, two output terminals, one shift register can input a scan signal to two gate lines.
  • the signal output terminal connected to the signal output control module controlled by the first control signal input terminal Control-1 is outputted when the first frame picture is displayed, and the frame picture is defined as an odd frame at this time;
  • the signal output terminal connected to the signal output control module controlled by the two control signal input terminals Control-2 is outputted when the second frame picture is displayed, and the frame picture is defined as an even frame at this time. That is to say, the picture is composed of two frames, and the two outputs of the shift register are used for display of different frames, as follows.
  • the first signal output terminal OUTPUT-1 of the shift register When the odd frame is displayed, the first signal output terminal OUTPUT-1 of the shift register outputs a signal.
  • the signal input terminal INPUT (or the frame strobe signal STV) inputs a high level signal, at which time the first transistor M1 is turned on and the pull-up control node PU is charged.
  • the first clock signal input terminal CLK inputs a high level signal
  • the first control signal input terminal Control-1 inputs a high level signal, so that the switching transistor M12 controlled by the control signal input terminal Control-1 is turned on. Since the pull-up control node PU is charged at the first moment, it is at a high level, at which time the third transistor M3 is turned on, the signal output terminal OUTPUT-1 outputs a high level signal, and at the same time, due to the bootstrap function of the storage capacitor.
  • the potential of the pull-up control node PU is further pulled high, the sixth transistor M6 and the eighth transistor M8 are turned on, and the pull-down node PD is pulled down to a low level to avoid the signal interference signal input by the second signal input terminal INPUT.
  • the signal input by the first clock signal input terminal CLK changes from a high level to a low level
  • the signal input by the second clock signal input terminal CLKB and the reset signal input terminal RESET is a high level signal.
  • the ninth transistor M9 is turned on, the pull-down control node PD_CN is at a high level, so the fifth transistor M5 is turned on, so that the pull-down node PD is pulled up to a high level; at this time, the second transistor M2 and the fourth transistor M4 Is turned on, so the potential of the pull-up control node PU is pulled low to low level, and the potential outputted by the first signal output terminal OUTPUT-1 is also pulled low, that is, to the pull-up control node PU and The signal output terminal OUTPUT-1 is reset.
  • the first clock signal input terminal CLK inputs a high level signal
  • the second clock signal input terminal CLKB inputs a low voltage signal.
  • the potential of the pull-down node PD maintains the potential of the previous stage to maintain a high level, so The potential of the pull control node PU is still low at this time, and the tenth transistor M10 and the eleventh transistor M11 are turned on to denoise the signal output from the pull-up control node PU and the signal output terminal OUTPUT-1 to prevent noise. Error output. Therefore, the first signal output terminal OUTPUT-1 keeps outputting low until the next odd frame time comes.
  • the display of the odd frame is completed, the display of the even frame is started, and the display principle is the same as that of the odd frame, except that this is the signal output control module corresponding to the second signal output terminal OUTPUT-2 and the output reset control module. Work, so it is not described in detail here.

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Abstract

一种移位寄存器、栅极驱动电路、显示装置及栅极驱动方法，可解决现有的移位寄存器限制了显示装置的超窄边框设计的问题。所述移位寄存器包括用于输出栅极驱动信号的栅极驱动信号生成单元，并包括多个信号输出控制模块、多个信号输出复位模块及多个信号输出端（OUTPUT-1，OUTPUT-2）。每个信号输出控制模块均在一端连接到栅极驱动信号生成单元且在另一端连接到多个信号输出端（OUTPUT-1，OUTPUT-2）中对应的一个，且每个信号输出控制模块还具有各自的控制信号，用于在控制信号的控制下将从栅极驱动信号生成单元输出的栅极驱动信号通过对应的信号输出端（OUTPUT-1，OUTPUT-2）输出。每个信号输出复位模块的一端连接在各自对应的信号输出控制模块和信号输出端之间，用于对输出端的输出信号进行复位。

Description

移位寄存器、栅极驱动电路、显示装置及栅极驱动方法 技术领域
本发明属于显示技术领域，具体涉及移位寄存器、栅极驱动电路、显示装置及栅极驱动方法。
背景技术
TFT-LCD(Thin Film Transistor-Liquid Crystal Display，薄膜晶体管液晶显示装置)实现一帧画面显示的基本原理是通过栅极(gate)驱动从上到下依次对每一行像素输入一定宽度的方波进行选通，再通过源极(source)驱动针对每一行像素的信号依次从上往下输出。目前制造这样一种结构的显示器件通常是栅极驱动电路和源极驱动电路通过COF(Chip On Film，覆晶薄膜)或COG(Chip On Glass，芯片直接固定在玻璃上)工艺制作在玻璃基板上的，但是当分辨率较高时，栅极驱动电路和源极驱动电路的输出均较多，驱动电路的长度也将增大，这将使得对模组驱动电路执行压焊(Bonding)工艺变得困难。
为了克服以上问题，现有显示器件的制造采用GOA(Gate Drive On Array，栅极驱动阵列)电路的设计，相比现有的COF或COG工艺，其不仅节约了成本，而且可以做到面板两边对称的美观设计，同时也可省去栅极驱动电路的压焊(Bonding)区域以及外围布线空间，从而实现了显示装置窄边框的设计，提高了显示装置的产能和良率。但是现有的GOA电路的设计也存在着一定的问题，如图1所示，现有的GOA电路中的每个移位寄存器的薄膜晶体管(TFT)的个数较多(即M1-M6～M8-M11)，且每个移位寄存器只能用于驱动一行栅线，故占用空间较大。而只有进一步减小GOA电路的占用空间，才可以实现真正意义上的显示装置窄边框设计。
发明内容
本发明针对现有的栅极驱动电路存在的上述技术问题，提供一种可以实现窄边框设计的移位寄存器、栅极驱动电路、显示装置及栅极驱动方法。
解决本发明技术问题所采用的技术方案的一个方面是提供一种移位寄存器，包括用于输出栅极驱动信号的栅极驱动信号生成单元，该移位寄存器还包括多个信号输出控制模块、多个信号输出复位模块及多个信号输出端；其中，
所述多个信号输出控制模块中的每一个均在一端连接到所述栅极驱动信号生成单元且在另一端连接到所述多个信号输出端中对应的一个，并且每个信号输出控制模块还具有各自的控制信号输入端，用于在所述控制信号输入端所输入的控制信号的控制下，将从所述栅极驱动信号生成单元输出的栅极驱动信号通过所述对应的信号输出端输出；
所述多个信号输出复位模块中的每一个的一端连接在各自对应的信号输出控制模块和信号输出端之间，用于对与其连接的所述信号输出端的输出信号进行复位。
优选的是，每个所述信号输出控制模块均包括一个开关晶体管，所述开关晶体管的第一极连接所述栅极驱动信号生成单元，第二极连接与其对应的所述信号输出端和所述信号输出复位模块，控制极连接所述控制信号输入端。
优选的是，每个所述信号输出复位模块均包括一个第四晶体管；所述第四晶体管的第一极连接到与其对应的所述信号输出控制模块和所述信号输出端之间，第二极连接低电压信号，控制极连接复位信号输入端。
优选的是，所述移位寄存器还包括：多个输出降噪模块；
所述多个输出降噪模块中的每一个的一端连接到各自对应的信号输出控制模块和信号输出端之间，用于对与其连接的所述信号输出端的输出信号进行降噪。
进一步优选的是，每个输出降噪模块均包括一个第十一晶体管，所述第十一晶体管的第一极连接到与其对应的所述信号输出控制模块和所述信号输出端之间，第二极连接低电压信号，控制极连接栅极驱动信号生成单元的下拉节点。
优选的是，所述栅极驱动信号生成单元包括：输入模块、上拉模块、输入复位模块、下拉控制模块、下拉模块，以及输入降噪模块；其中，
所述输入模块连接在移位寄存器的信号输入端和上拉控制节点之 间，用于根据所述信号输入端输入的信号控制所述上拉控制节点的电位，所述上拉控制节点为所述输入模块与所述上拉模块的连接点；
所述上拉模块连接在所述上拉控制节点和各个信号输出控制模块之间，其控制端连接第一时钟信号输入端，用于根据上拉控制节点的电位和第一时钟信号输入端所输入的第一时钟信号的控制来对将被输出到信号输出端的栅极驱动信号进行上拉；
所述输入复位模块的一端连接到所述上拉控制节点，并且其控制端连接复位信号输入端，用于在复位信号输入端输入的复位信号的控制下将所述上拉控制节点的电位下拉复位；
所述下拉控制模块的一端连接到下拉节点，并且其控制端连接到第二时钟信号输入端，用于根据从第二时钟信号输入端所输入的第二时钟信号控制所述下拉节点的电位，所述下拉节点为下拉控制模块与下拉模块的连接点；
所述下拉模块连接在所述下拉节点和所述上拉控制节点之间，用于在上拉控制节点的电位的控制下将下拉节点的电位进行下拉；
所述输入降噪模块连接在所述上拉控制节点和所述下拉节点之间，用于在下拉节点的电位的控制下降低上拉控制节点的输出噪声。
进一步优选的是，所述输入模块包括第一晶体管；所述输入复位模块包括第二晶体管；所述上拉模块包括第三晶体管和存储电容；所述下拉控制模块包括第五晶体管和第九晶体管；所述下拉模块包括第六晶体管和第八晶体管；所述输入降噪模块包括第十晶体管；其中，
所述第一晶体管的第一极和控制极均连接所述移位寄存器的信号输入端，第二极连接所述上拉控制节点；
所述第二晶体管的第一极连接所述上拉控制节点，第二极连接低电压信号，控制极连接所述复位信号输入端；
所述第三晶体管的第一极连接所述第一时钟信号输入端，第二极连接所述存储电容的第二端和所述多个信号输出控制模块，控制极连接所述上拉控制节点和所述存储电容的第一端；
所述第五晶体管的第一极以及所述第九晶体管的第一极和控制极连接所述第二时钟信号输入端，所述第五晶体管的第二极连接所述下拉节 点，所述第五晶体管的控制极连接所述第九晶体管的第二极；
所述第六晶体管的第一极连接所述下拉节点，所述第六晶体管和所述第八晶体管的第二极连接低电压信号，所述第六晶体管和所述第八晶体管的控制极连接所述上拉控制节点，所述第八晶体管的第一极连接所述第五晶体管的控制极和所述第九晶体管的第二极；
所述第十晶体管的第一极连接所述上拉控制节点，第二极连接低电压信号，控制极连接所述下拉节点。
进一步优选的是，每个所述信号输出控制模块均包括一个开关晶体管；每个信号输出复位模块均包括一个第四晶体管，每个所述输出降噪模块均包括一个第十一晶体管；其中，
每个所述开关晶体管的第一极均连接存储电容的第二端，第二极分别连接对应的所述信号输出端，控制极分别连接对应的所述控制信号输入端；
每个所述第四晶体管的第一极连接到对应的所述信号输出端和所述开关晶体管的第二极之间，第二极连接低电压信号，控制极均连接复位信号输入端。
每个所述第十一晶体管的第一极连接到与其对应的所述开关晶体管的第二极和所述信号输出端之间，第二极连接低电压信号，控制极连接所述下拉节点。
优选的是，移位寄存器包括两个所述信号输出控制模块、两个所述信号输出复位模块以及两个所述信号输出端。
解决本发明技术问题所采用的技术方案的第二方面是一种栅极驱动电路，其包括级联的多个如上所述的移位寄存器，
每一级所述移位寄存器的栅极驱动信号生成单元所输出的信号作为该移位寄存器的下一级移位寄存器的信号输入端的输入信号；
每一级所述移位寄存器的多个信号输出端中的每一个所输出的信号用于驱动一根栅线。
解决本发明技术问题所采用的技术方案的第三方面是一种显示装置，其包括上述的栅极驱动电路。
解决本发明技术问题所采用的技术方案的第四方面是一种栅极驱动 方法，包括：
使栅极驱动电路的移位寄存器通过栅极驱动信号生成单元输出栅极驱动信号；
当显示一幅图像时，所述移位寄存器中的多个信号输出端利用各自连接的信号输出控制模块分时输出多个栅极驱动信号，并利用各自连接的信号输出复位模块对所述多个信号输出端的输出信号进行复位。
优选的，所述栅极驱动电路包括多个级联的移位寄存器，并且所述栅极驱动方法包括使每一级移位寄存器的多个信号输出端中的每一个所输出的信号用于驱动一根栅线。
本发明具有如下有益效果：
由于本发明的移位寄存器具有多个信号输出端，以及具有用于控制这多个信号输出端对信号进行输出的多个信号输出控制模块和多个信号输出复位模块，也就是说本发明中每个移位寄存器可以用于驱动多根栅线，因此将该移位寄存器应用于显示面板中可以减少所使用的移位寄存器的数量，从而进一步减小GOA电路的占用空间，由此能够实现真正意义上的显示装置超窄边框的设计。
附图说明
图1为现有的移位寄存器的电路原理图；
图2为根据本发明的移位寄存器的一种示意图；
图3为根据本发明的移位寄存器的一种优选方式的示意图；
图4为根据本发明的移位寄存器的另一种优选方式的示意图；
图5为根据本发明一些实施例的移位寄存器的电路原理图；
图6为根据本发明一些实施例的移位寄存器的工作时序图。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
本发明一些实施例中所采用的晶体管可以为薄膜晶体管或场效应管或具有等效特性的类似器件，本发明对此不作具体限制。由于采用的晶体 管的源极和漏极是对称结构，所以其源极、漏极是没有区别的。在本发明实施例中，为区分晶体管的源极和漏极，将其中一极称为第一极，另一极称为第二极，并且将栅极称为控制极。此外按照晶体管的特性区分可以将晶体管分为N型和P型，以下实施例中是以N型晶体管进行说明的。例如当采用N型晶体管时，第一极为N型晶体管的源极，第二极为N型晶体管的漏极，当作为控制极的栅极输入高电平时，源漏极导通。可选的是，在采用P型晶体管的情况下，各极状态与上述N型晶体管相反。可以想到的是采用P型晶体管实现是本领域技术人员可以在不付出创造性劳动前提下轻易想到的，因此也落入本发明实施例的保护范围内。
参考图2来描述根据本发明的一个实施例的移位寄存器。
如图2所示，该移位寄存器包括用于输出栅极驱动信号的栅极驱动信号生成单元，以及包括多个信号输出控制模块、多个信号输出复位模块和多个信号输出端(OUTPUT-1，OUTPUT-2)。图2是以分别提供两个信号输出控制模块、两个信号输出复位模块、以及两个信号输出端为例进行图示的，但是该示例并不构成对本发明的限制，本发明可以将信号输出线路扩展为更多个。
每个信号输出控制模块均在一端连接到栅极驱动信号生成单元且在另一端连接到对应的一个信号输出端。并且每个信号输出控制模块还具有各自的控制信号输入端(Control-1，Control-2)，用于在控制信号输入端(Control-1，Control-2)所输入的控制信号的控制下，将从栅极驱动信号生成单元输出的栅极驱动信号通过相应的信号输出端(OUTPUT-1，OUTPUT-2)输出。每个信号输出复位模块的一端连接到各自对应的信号输出控制模块和信号输出端之间，用于对与其连接的信号输出端的输出信号进行复位。
由于上述移位寄存器包括栅极驱动信号生成单元、多个信号输出控制模块和多个信号输出复位模块，且具有多个信号输出端，可以理解的是，每个信号输出端是为一根栅线提供栅极驱动信号的，因此一个移位寄存器可以为多根栅线提供栅极驱动信号，故将该移位寄存器应用于显示面板中，可以减少所使用的移位寄存器的数量，从而进一步减小GOA电路的占用空间，由此能够实现真正意义上的显示装置窄边框的设计。上述移位寄 存器的具体实现方式见下述实施例。
在一个优选实施例中，每个所述信号输出控制模块均包括一个开关晶体管，所述开关晶体管的第一极连接所述栅极驱动信号生成单元，第二极连接与其对应的所述信号输出端和所述信号输出复位模块，控制极连接控制信号输入端。
也就是说，每一个信号输出控制模块仅包括一个开关晶体管，通过控制开关晶体管的开启与关断即可控制相应的信号输出端是否输出栅极驱动信号，该信号输出控制模块结构简单，容易控制，成本较低。
在一个优选实施例中，每个所述信号输出复位模块均包括一个第四晶体管；所述第四晶体管的第一极连接在与其对应的所述信号输出控制模块和所述信号输出端之间，第二极连接低电压信号，控制极连接复位信号输入端。
也就是说，每一个信号输出复位模块仅包括一个第四晶体管，通过对一个第四晶体管的控制，即可对信号输出端所输出的信号进行复位，该信号输出复位模块结构简单，容易控制，成本较低。
结合附图和下述优选实施例对本发明的移位寄存器进行说明。
如图3所示，本实施例提供一种移位寄存器，其包括栅极驱动信号生成单元、多个信号输出控制模块、多个信号输出复位模块和多个信号输出端(OUTPUT-1，OUTPUT-2)，其中本实施例的栅极驱动信号生成单元包括：输入模块、上拉模块、输入复位模块。该实施例中，输入模块连接在移位寄存器的信号输入端INPUT和上拉控制节点PU之间，用于根据信号输入端INPUT输入的信号来控制上拉控制节点PU的电位，上拉控制节点PU为输入模块与上拉模块的连接点。上拉模块连接在上拉控制节点PU和各个信号输出控制模块之间，并且其控制端连接到第一时钟信号输入端CLK，用于根据上拉控制节点PU的电位和第一时钟信号输入端CLK所输入的第一时钟信号的控制来对将被输出到信号输出端的栅极驱动信号进行上拉(也就是上拉为高电平)。每个信号输出控制模块均在一端连接到上拉模块且在另一端连接到对应的一个信号输出端OUTPUT(N)(其中信号输出端均用OUTPUT(N)表示)，每个信号控制输出模块还连接到各自的控制信号输入端Control(N)，用于在控制信号输入端Control(N)所 输入的控制信号的控制下，将从上拉模块输出的上拉后的栅极驱动信号通过相应的信号输出端OUTPUT(N)输出。输入复位模块的一端连接到上拉控制节点PU，并且其控制端连接复位信号输入端RESET，用于根据复位信号输入端RESET输入的复位信号的控制来将上拉控制节点PU的电位下拉复位(也就是下拉为低电平)，在本实施例中，输入复位模块的另一端连接到低电压信号VSS。每个信号输出复位模块的一端连接在各自对应的信号输出端OUTPUT(N)和输出控制模块之间，并且其控制端连接复位信号输入端RESET，用于根据复位信号输入端RESET输入的复位信号的控制来将信号输出端OUTPUT(N)的输出信号的电位复位(也就是下拉为低电平)，在本实施例中，信号输出复位模块的另一端连接到低电压信号VSS。
由于本实施例的移位寄存器具有多个信号输出端，以及具有用于控制这多个信号输出端对信号进行输出的多个信号输出控制模块和多个信号输出复位模块，也就说本实施例中的一个移位寄存器可以用于驱动多根栅线，因此将该移位寄存器应用于显示面板中可以减少所使用的移位寄存器的数量，从而进一步减小GOA电路的占用空间，由此能够实现真正意义上的显示装置超窄边框的设计。
优选地，如图4所示，本实施例移位寄存器的栅极驱动信号生成单元还包括：下拉控制模块和下拉模块。下拉控制模块的一端连接到下拉节点PD，并且其控制端连接到第二时钟信号输入端CLKB，用于根据从第二时钟信号输入端CLKB输入的第二时钟信号来控制下拉节点PD的电位，下拉节点PD为下拉控制模块与下拉模块的连接点。下拉模块连接在下拉节点PD和上拉控制节点PU之间，用于在上拉控制节点PU的电位的控制下开启，通过连接到低电压信号VSS来将下拉节点PD的电位下拉为低电平，以降低下拉节点PD的输出噪声。
进一步优选地，移位寄存器还包括：输入降噪模块和多个输出降噪模块。输入降噪模块连接在上拉控制节点PU和下拉节点PD之间，用于在下拉节点PD的电位的控制下开启，通过连接到低电压信号VSS来降低上拉控制节点PU的输出噪声。多个输出降噪模块中的每一个的一端连接到各自对应的信号输出端OUTPUT(N)和信号输出控制模块之间，并且控制端连接到下拉节点PD，用于在下拉节点PD的电位的控制下开启，通过连 接到低电压信号VSS来降低与其连接的信号输出端OUTPUT(N)的输出噪声。
为了时序方便控制、布线简单、容易控制，本实施例中的移位寄存器包括两个信号输出控制模块和两个信号输出复位模块，以及相应的两个信号输出端。也就是说每一个移位寄存器用于驱动两根栅线。当然本实施例的移位寄存器也不局限于只包括两个信号输出控制模块和两个信号输出复位模块的结构，也可以是包括三个、四个或更多个信号输出控制模块和信号输出复位模块，以驱动多根栅线。
综上，本实施例的移位寄存器可以驱动多根栅线，因此可以采用个数较少的移位寄存单元以驱动显示面板上的栅线，从而可以减少所使用的移位寄存器的数量，从而进一步减小GOA电路的占用空间，由此能够实现真正意义上的显示装置超窄边框的设计。
作为本实施例的一种优选方式，如图5所示，输入模块包括第一晶体管M1；输入复位模块包括第二晶体管M2；上拉模块包括第三晶体管M3和存储电容C1；每个信号输出控制模块均包括一个开关晶体管M12/M13；每个信号输出复位模块均包括一个第四晶体管M4；下拉控制模块包括第五晶体管M5和第九晶体管M9；下拉模块包括第六晶体管M6和第八晶体管M8；输入降噪模块包括第十晶体管M10；每个输出降噪模块均包括一个第十一晶体管M11。该移位寄存器用于输出两个驱动信号，也就是以两个信号输出控制模块、两个信号输出复位模块、两个输出降噪模块、以及两个信号输出端(OUTPUT-1，OUTPUT-2)为例说明上述各器件的连接关系。
具体的，第一晶体管M1的第一极和控制极均连接移位寄存器的信号输入端INPUT，第二极连接上拉控制节点PU。第二晶体管M2的第一极连接上拉控制节点PU，第二极连接低电压信号VSS，控制极连接复位信号输入端RESET。第三晶体管M3的第一极连接第一时钟信号输入端CLK，第二极连接存储电容的第二端和多个开关晶体管M12和M13的第一极，控制极连接上拉控制节点PU和存储电容C1的第一端。两个开关晶体管，即开关晶体管M12和开关晶体管M13的第一极均连接第三晶体管M3的第二极，这两个开关晶体管的第二极分别连接各自对应的信号输出端OUTPUT-1和信号输出端OUTPUT-2(即：开关晶体管M12的第二极连接信号输出端 OUTPUT-1；开关晶体管M13的第二极连接信号输出端OUTPUT-2)、以及各自对应的信号输出复位模块中的第四晶体管M4的第一极，这两个开关晶体管的控制极分别连接控制信号输入端Control-1和控制信号输入端Control-2(即：开关晶体管M12的控制极连接控制信号输入端Control-1；开关晶体管M13的控制极连接控制信号输入端Control-2)。两个信号输出复位模块中的第四晶体管M4的第一极分别连接到各自对应的信号输出控制模块的开关晶体管M12和M13的第二极，并与各自对应的输出降噪模块中的第十一晶体管M11的第一极连接，每个第四晶体管M4的第二极连接低电压信号VSS，控制极连接复位信号输入端RESET。第五晶体管M5的第一极以及第九晶体管M9的第一极和控制极连接第二时钟信号输入端CLKB，第五晶体管M5的第二极连接下拉节点PD，第五晶体管M5的控制极连接第九晶体管M9的第二极。第六晶体管M6的第一极连接下拉节点PD，第六晶体管M6和第八晶体管M8第二极连接低电压信号VSS，第六晶体管M6和第八晶体管M8控制极连接上拉控制节点PU，第八晶体管M8的第一极连接第五晶体管M5的控制极和第九晶体管M9的第二极。第十晶体管M10的第一极连接上拉控制节点PU，第二极连接低电压信号VSS，控制极连接下拉节点PD。两个输出降噪模块中的第十一晶体管M11的第一极均连接到各自对应的信号输出控制模块中的开关晶体管M12和开关晶体管M13的第二极，第十一晶体管的第二极连接低电压信号VSS，控制极连接下拉节点PD。
相应的，本实施例中还提供一种栅极驱动电路，该栅极驱动电路包括多个级联的上述移位寄存器，每一级移位寄存器的栅极驱动信号生成单元所输出的信号作为该移位寄存器的下一级移位寄存器的信号输入端INPUT的输入信号；每一级移位寄存器的多个信号输出端OUTPUT(N)中的每一个所输出的信号用于驱动一行栅线。因此，本实施例中的栅极驱动电路的结构简单，易于实现，且可以减少所使用的移位寄存器的数量，从而进一步减小GOA电路的占用空间，由此能够应用于显示装置中以实现真正意义上的显示装置超窄边框的设计。
相应的，本实施例中还提供了一种显示装置，其包括上述的栅极驱动电路。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本 电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
由于本实施例的显示装置包括上述的栅极驱动电路，故可以实现超窄边框设计。
当然，本实施例的显示装置中还可以包括其他常规结构，如显示驱动单元等，为了不削弱对本发明所针对的发明点的理解，本说明书中将不再对这些常规结构进行冗述。
相应的，本实施例还提供了一种栅极驱动方法，其包括：
使栅极驱动电路的移位寄存器通过栅极驱动信号生成单元输出栅极驱动信号；
当显示一幅图像时，所述移位寄存器中的多个信号输出端利用各自连接的信号输出控制模块分时输出多个栅极驱动信号，并利用各自连接的信号输出复位模块对所述多个信号输出端的输出信号进行复位。
优选的，所述栅极驱动电路包括多个级联的移位寄存器，并且所述栅极驱动方法包括使每一级移位寄存器的多个信号输出端中的每一个所输出的信号用于驱动一根栅线。
具体的，根据如图6所示的时序图，对栅极驱动电路中的移位寄存的工作原理进行说明。
首先，需要说明的是，在通过本实施例的移位寄存器进行一幅画面的显示时，由于该移位寄存器例如具有两个输出端，因此一个移位寄存器可以对两根栅线输入扫描信号，其中，与通过第一个控制信号输入端Control-1控制的信号输出控制模块连接的信号输出端在显示第一帧画面时进行输出，此时将该帧画面定义为奇数帧；与通过第二个控制信号输入端Control-2控制的信号输出控制模块连接的信号输出端在显示第二帧画面时进行输出，此时将该帧画面定义为偶数帧。也就是说，该幅画面是由两帧画面组成的，且该移位寄存器的两个输出用于不同帧的显示，具体的如下。
奇数帧显示时，即移位寄存器的第一个信号输出端OUTPUT-1输出信号。
在第一时刻(初始化阶段)，信号输入端INPUT(或帧选通信号STV)输入高电平信号，此时，第一晶体管M1被打开，上拉控制节点PU被充电。
在第二时刻，第一时钟信号输入端CLK输入高电平信号，第一控制信号输入端Control-1输入高电平信号，因此通过该控制信号输入端Control-1控制的开关晶体管M12被打开，由于上拉控制节点PU在第一时刻时被充电，故处于高电平，此时第三晶体管M3被打开，信号输出端OUTPUT-1输出高电平信号，同时由于存储电容的自举作用，上拉控制节点PU的电位被进一步的拉高，第六晶体管M6和第八晶体管M8被打开，下拉节点PD被下拉为低电平，以避免第二信号输入端INPUT所输入的信号干扰信号输出端OUTPUT-1输出的信号。
在第三时刻，第一时钟信号输入端CLK所输入的信号从高电平变为低电平，第二时钟信号输入端CLKB和复位信号输入端RESET所输入的信号为高电平信号，此时第九晶体管M9被打开，下拉控制节点PD_CN为高电平，故第五晶体管M5被打开，从而使得下拉节点PD被上拉为高电平；此时，第二晶体管M2和第四晶体管M4被打开，故上拉控制节点PU的电位被拉低为低电平，并且第一个信号输出端OUTPUT-1所输出的电位也被拉为低电平，也就是对上拉控制节点PU和信号输出端OUTPUT-1进行复位。
在第四时刻，第一时钟信号输入端CLK输入高电平信号，第二时钟信号输入端CLKB输入低电压信号，此时下拉节点PD的电位维持上一阶段的电位保持高电平，故上拉控制节点PU的电位此时仍为低电平，同时，第十晶体管M10和第十一晶体管M11开启，以对上拉控制节点PU和信号输出端OUTPUT-1输出的信号进行降噪，防止误输出。因此第一个信号输出端OUTPUT-1保持输出低电平，直到下一个奇数帧时刻的到来。
同理，奇数帧显示完成后，开始偶数帧的显示，其显示原理与奇数帧相同，只不过此时是与第二个信号输出端OUTPUT-2对应的信号输出控制模块以及输出复位控制模块进行工作，因此在此不详细描述。
需要说明的是，在本实施例中也可以具有更多个信号输出端OUTPUT(N)，更多个信号输出端OUTPUT(N)均用于同一图像的不同帧画面的显示中。工作原理与上述相同，在此不详细描述。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和 改进，这些变型和改进也视为本发明的保护范围。

Claims (13)

  1. 一种移位寄存器，包括用于输出栅极驱动信号的栅极驱动信号生成单元，其中，所述移位寄存器还包括多个信号输出控制模块、多个信号输出复位模块及多个信号输出端，并且其中，
    所述多个信号输出控制模块中的每一个均在一端连接到所述栅极驱动信号生成单元且在另一端连接到所述多个信号输出端中对应的一个，并且每个信号输出控制模块还具有各自的控制信号输入端，
    用于在所述控制信号输入端所输入的控制信号的控制下，将从所述栅极驱动信号生成单元输出的栅极驱动信号通过对应的所述信号输出端输出；并且
    所述多个信号输出复位模块中的每一个的一端连接在各自对应的信号输出控制模块和信号输出端之间，用于对与其连接的所述信号输出端的输出信号进行复位。
  2. 根据权利要求1所述的移位寄存器，还包括：多个输出降噪模块；
    所述多个输出降噪模块中的每一个的一端连接到各自对应的信号输出控制模块和信号输出端之间，用于对与其连接的所述信号输出端的输出信号进行降噪。
  3. 根据权利要求2所述的移位寄存器，其中，每个输出降噪模块均包括一个第十一晶体管，
    所述第十一晶体管的第一极连接到与其对应的所述信号输出控制模块和所述信号输出端之间，第二极连接低电压信号，以通过低电压信号对与其连接的信号输出端的输出信号进行降噪。
  4. 根据权利要求1所述的移位寄存器，其中，所述栅极驱动信号生成单元包括：输入模块、上拉模块、输入复位模块、下拉控制模块、下拉模块，以及输入降噪模块，并且其中，
    所述输入模块连接在移位寄存器的信号输入端和上拉控制节点之 间，用于根据所述信号输入端输入的信号控制所述上拉控制节点的电位，所述上拉控制节点为所述输入模块与所述上拉模块的连接点；
    所述上拉模块连接在所述上拉控制节点和各个信号输出控制模块之间，其控制端连接第一时钟信号输入端，用于根据上拉控制节点的电位和第一时钟信号输入端所输入的第一时钟信号的控制来对将被输出到信号输出端的栅极驱动信号进行上拉；
    所述输入复位模块的一端连接到所述上拉控制节点，并且其控制端连接复位信号输入端，用于在复位信号输入端输入的复位信号的控制下将所述上拉控制节点的电位下拉复位；
    所述下拉控制模块的一端连接到下拉节点，并且其控制端连接到第二时钟信号输入端，用于根据从第二时钟信号输入端输入的第二时钟信号控制所述下拉节点的电位，所述下拉节点为所述下拉控制模块与所述下拉模块的连接点；
    所述下拉模块连接在所述下拉节点和所述上拉控制节点之间，用于所述在上拉控制节点的电位的控制下将所述下拉节点的电位进行下拉；并且
    所述输入降噪模块连接在所述上拉控制节点和所述下拉节点之间，用于在所述下拉节点的电位的控制下降低所述上拉控制节点的输出噪声。
  5. 根据权利要求4所述的移位寄存器，其中，所述输入模块包括第一晶体管；所述输入复位模块包括第二晶体管；所述上拉模块包括第三晶体管和存储电容；所述下拉控制模块包括第五晶体管和第九晶体管；所述下拉模块包括第六晶体管和第八晶体管；所述输入降噪模块包括第十晶体管，并且其中，
    所述第一晶体管的第一极和控制极均连接所述移位寄存器的信号输入端，第二极连接所述上拉控制节点；
    所述第二晶体管的第一极连接所述上拉控制节点，第二极连接低电压信号，控制极连接所述复位信号输入端；
    所述第三晶体管的第一极连接所述第一时钟信号输入端，第二极连接所述存储电容的第二端和所述多个信号输出控制模块，控制极连接所述 上拉控制节点和所述存储电容的第一端；
    所述第五晶体管的第一极以及所述第九晶体管的第一极和控制极连接所述第二时钟信号输入端，所述第五晶体管的第二极连接所述下拉节点，所述第五晶体管的控制极连接所述第九晶体管的第二极；
    所述第六晶体管的第一极连接所述下拉节点，所述第六晶体管和所述第八晶体管的第二极连接低电压信号，所述第六晶体管和所述第八晶体管的控制极连接所述上拉控制节点，所述第八晶体管的第一极连接所述第五晶体管的控制极和所述第九晶体管的第二极；
    所述第十晶体管的第一极连接所述上拉控制节点，第二极连接所述低电压信号，控制极连接所述下拉节点。
  6. 根据权利要求1所述的移位寄存器，其中每个所述信号输出控制模块均包括一个开关晶体管，
    所述开关晶体管的第一极连接所述栅极驱动信号生成单元，第二极连接与其对应的所述信号输出端和所述信号输出复位模块，控制极连接所述控制信号输入端。
  7. 根据权利要求1所述的移位寄存器，其中每个所述信号输出复位模块均包括一个第四晶体管；
    所述第四晶体管的第一极连接在与其对应的所述信号输出控制模块和所述信号输出端之间，第二极连接低电压信号，控制极连接复位信号输入端。
  8. 根据权利要求5所述的移位寄存器，还包括：多个输出降噪模块，其中，每个所述信号输出控制模块均包括一个开关晶体管，每个信号输出复位模块均包括一个第四晶体管，且每个所述输出降噪模块均包括一个第十一晶体管；其中，
    每个所述开关晶体管的第一极均连接存储电容的第二端，第二极分别连接对应的所述信号输出端，控制极分别连接对应的控制信号输入端；
    每个所述第四晶体管的第一极连接到对应的所述信号输出端和所述 开关晶体管的第二极之间，第二极均连接低电压信号，控制极均连接复位信号输入端；并且
    每个所述第十一晶体管的第一极连接到与其对应的所述开关晶体管的第二极和所述信号输出端之间，第二极连接所述低电压信号，控制极连接所述下拉节点。
  9. 根据权利要求1所述的移位寄存器，其中，所述移位寄存器包括两个所述信号输出控制模块、两个所述信号输出复位模块以及两个所述信号输出端。
  10. 一种栅极驱动电路，包括多个如权利要求1至9中任意一项的所述移位寄存器，并且所述多个移位寄存器相互级联，其中
    每一级所述移位寄存器的栅极驱动信号生成单元所输出的信号作为该移位寄存器的下一级移位寄存器的信号输入端的输入信号；
    每一级所述移位寄存器的多个信号输出端中的每一个所输出的信号用于驱动一根栅线。
  11. 一种显示装置，其特征在于，显示装置包括权利要求10的所述的栅极驱动电路。
  12. 一种栅极驱动方法，其特征在于，包括：
    使栅极驱动电路的移位寄存器通过栅极驱动信号生成单元输出栅极驱动信号；
    当显示一幅图像时，所述移位寄存器中的多个信号输出端利用各自连接的信号输出控制模块分时输出多个栅极驱动信号，并利用各自连接的信号输出复位模块对所述多个信号输出端的输出信号进行复位。
  13. 根据权利要求12所述的栅极驱动方法，其中所述栅极驱动电路包括多个级联的移位寄存器，并且所述栅极驱动方法包括使每一级移位寄存器的多个信号输出端中的每一个所输出的信号用于驱动一根栅线。
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Families Citing this family (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104464600B (zh) * 2014-12-26 2017-02-01 合肥鑫晟光电科技有限公司 移位寄存器单元及其驱动方法、移位寄存器电路以及显示装置
CN104732939A (zh) * 2015-03-27 2015-06-24 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路、显示装置及栅极驱动方法
CN104700769B (zh) * 2015-04-09 2017-03-15 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动装置以及显示装置
CN104835476B (zh) * 2015-06-08 2017-09-15 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及其驱动方法、阵列基板
CN104867439B (zh) * 2015-06-24 2017-04-05 合肥京东方光电科技有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
CN104966506B (zh) * 2015-08-06 2017-06-06 京东方科技集团股份有限公司 一种移位寄存器、显示面板的驱动方法及相关装置
US11127336B2 (en) 2015-09-23 2021-09-21 Boe Technology Group Co., Ltd. Gate on array (GOA) unit, gate driver circuit and display device
CN105118466B (zh) * 2015-09-23 2018-02-09 深圳市华星光电技术有限公司 扫描驱动电路及具有该电路的液晶显示装置
CN105096811B (zh) * 2015-09-23 2017-12-08 京东方科技集团股份有限公司 Goa单元、栅极驱动电路及显示装置
CN105118469B (zh) 2015-09-25 2017-11-10 深圳市华星光电技术有限公司 扫描驱动电路及具有该电路的液晶显示装置
US10332446B2 (en) * 2015-12-03 2019-06-25 Innolux Corporation Driving circuit of active-matrix organic light-emitting diode with hybrid transistors
CN205282053U (zh) * 2016-01-04 2016-06-01 北京京东方显示技术有限公司 移位寄存器单元、栅极驱动电路和显示装置
CN105427799B (zh) * 2016-01-05 2018-03-06 京东方科技集团股份有限公司 移位寄存单元、移位寄存器、栅极驱动电路及显示装置
CN105589604B (zh) * 2016-03-08 2018-06-01 京东方科技集团股份有限公司 复位电路及其驱动方法、移位寄存器单元、栅极扫描电路
CN105788555B (zh) * 2016-05-19 2018-04-10 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN105895047B (zh) 2016-06-24 2018-10-19 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动装置、显示装置、控制方法
CN106057147B (zh) * 2016-06-28 2018-09-11 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN105913826B (zh) * 2016-06-30 2018-05-08 京东方科技集团股份有限公司 移位寄存器单元及驱动方法、移位寄存器电路及显示装置
CN106057161B (zh) * 2016-08-09 2018-09-11 京东方科技集团股份有限公司 移位寄存器、栅线集成驱动电路、阵列基板及显示装置
CN106531107B (zh) * 2016-12-27 2019-02-19 武汉华星光电技术有限公司 Goa电路
CN106814911B (zh) * 2017-01-18 2019-10-08 京东方科技集团股份有限公司 触控式电子设备、触控显示装置及阵列基板栅极驱动电路
CN106710508B (zh) * 2017-02-17 2020-07-10 京东方科技集团股份有限公司 移位寄存器、栅线驱动方法、阵列基板和显示装置
CN106652964B (zh) 2017-03-10 2019-11-05 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN108694894B (zh) * 2017-04-05 2020-07-07 京东方科技集团股份有限公司 移位缓存及栅极驱动电路、显示面板及设备和驱动方法
CN106898292B (zh) * 2017-05-05 2018-07-20 合肥鑫晟光电科技有限公司 扫描驱动电路及其驱动方法、阵列基板和显示装置
CN106991958B (zh) * 2017-06-09 2020-07-17 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
CN107068106B (zh) * 2017-06-21 2019-06-07 京东方科技集团股份有限公司 移位寄存器单元、驱动方法、栅极驱动电路和显示装置
CN107204176A (zh) * 2017-07-20 2017-09-26 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路
CN109410810B (zh) 2017-08-16 2021-10-29 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
CN107369407B (zh) * 2017-09-22 2021-02-26 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示面板
CN107507553B (zh) * 2017-09-25 2019-12-03 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、阵列基板和显示装置
CN107833552B (zh) * 2017-11-17 2020-09-25 合肥鑫晟光电科技有限公司 栅极驱动单元、栅极驱动电路及其驱动方法、显示装置
CN108109593B (zh) * 2017-12-01 2020-11-03 昆山龙腾光电股份有限公司 栅极驱动电路以及显示装置
CN107799070A (zh) * 2017-12-08 2018-03-13 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路、显示装置及栅极驱动方法
CN107784977B (zh) * 2017-12-11 2023-12-08 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
US11004415B2 (en) 2017-12-26 2021-05-11 HKC Corporation Limited Shift register circuit and display panel using the same
CN108231021A (zh) * 2017-12-26 2018-06-29 惠科股份有限公司 移位暂存电路及显示面板
CN108182917B (zh) * 2018-01-02 2020-07-07 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路
CN108122529B (zh) * 2018-01-25 2021-08-17 京东方科技集团股份有限公司 栅极驱动单元及其驱动方法和栅极驱动电路
CN108320692B (zh) * 2018-02-14 2022-01-07 京东方科技集团股份有限公司 移位寄存器单元及驱动方法、栅极驱动电路、显示面板
CN108257578A (zh) * 2018-04-16 2018-07-06 京东方科技集团股份有限公司 移位寄存器单元及其控制方法、栅极驱动装置、显示装置
CN108597437B (zh) * 2018-06-20 2021-08-27 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路及其驱动方法、显示装置
CN109064960A (zh) * 2018-07-18 2018-12-21 深圳市华星光电技术有限公司 Goa电路及包括其的显示面板和显示装置
US10810923B2 (en) 2018-07-18 2020-10-20 Shenzhen China Star Optoelectronics Technology Co., Ltd. GOA circuit and display panel and display device including the same
CN109064993B (zh) * 2018-11-06 2020-01-21 合肥京东方光电科技有限公司 移位寄存器及其驱动方法、栅极驱动电路和显示装置
CN109584780B (zh) * 2019-01-30 2020-11-06 京东方科技集团股份有限公司 一种移位寄存器及其驱动方法、栅极驱动电路、显示装置
CN112309322B (zh) * 2019-07-31 2022-01-18 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路和显示装置
CN110599971B (zh) * 2019-08-02 2022-06-10 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路及显示装置
CN110706639A (zh) * 2019-11-15 2020-01-17 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN111210755A (zh) * 2020-02-25 2020-05-29 合肥京东方光电科技有限公司 移位寄存器、栅极驱动电路及显示面板
CN116343642A (zh) * 2023-03-28 2023-06-27 京东方科技集团股份有限公司 移位寄存器单元、显示面板及显示装置

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101221818A (zh) * 2006-10-03 2008-07-16 三菱电机株式会社 移位寄存器电路以及包括该移位寄存器电路的图像显示装置
CN101625833A (zh) * 2008-07-12 2010-01-13 索尼株式会社 半导体器件、显示面板和电子设备
KR20110077108A (ko) * 2009-12-30 2011-07-07 엘지디스플레이 주식회사 쉬프트 레지스터와 이를 이용한 표시장치
CN102903322A (zh) * 2012-09-28 2013-01-30 合肥京东方光电科技有限公司 移位寄存器及其驱动方法和阵列基板、显示装置
CN103065578A (zh) * 2012-12-13 2013-04-24 京东方科技集团股份有限公司 一种移位寄存器单元、栅极驱动电路和显示装置
CN103915058A (zh) * 2012-12-28 2014-07-09 乐金显示有限公司 移位寄存器
CN104299594A (zh) * 2014-11-07 2015-01-21 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及显示装置
CN104732939A (zh) * 2015-03-27 2015-06-24 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路、显示装置及栅极驱动方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW518532B (en) * 2000-12-26 2003-01-21 Hannstar Display Corp Driving circuit of gate control line and method
JP2005234057A (ja) * 2004-02-17 2005-09-02 Sharp Corp 画像表示装置
TWI294612B (en) * 2005-05-25 2008-03-11 Novatek Microelectronics Corp Apparatus for gate switch of amorphous lcd
CN101329484B (zh) * 2007-06-22 2010-10-13 群康科技(深圳)有限公司 液晶显示装置之驱动电路及其驱动方法
CN102012591B (zh) * 2009-09-04 2012-05-30 北京京东方光电科技有限公司 移位寄存器单元及液晶显示器栅极驱动装置
CN102629444B (zh) * 2011-08-22 2014-06-25 北京京东方光电科技有限公司 栅极集成驱动电路、移位寄存器及显示屏
KR101997775B1 (ko) * 2012-12-05 2019-10-01 엘지디스플레이 주식회사 쉬프트 레지스터 및 이를 포함하는 평판 표시 장치
CN103474040B (zh) * 2013-09-06 2015-06-24 合肥京东方光电科技有限公司 栅极驱动单元、栅极驱动电路和显示装置
CN103500551B (zh) * 2013-10-23 2015-12-30 合肥京东方光电科技有限公司 移位寄存器单元、goa电路、阵列基板以及显示装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101221818A (zh) * 2006-10-03 2008-07-16 三菱电机株式会社 移位寄存器电路以及包括该移位寄存器电路的图像显示装置
CN101625833A (zh) * 2008-07-12 2010-01-13 索尼株式会社 半导体器件、显示面板和电子设备
KR20110077108A (ko) * 2009-12-30 2011-07-07 엘지디스플레이 주식회사 쉬프트 레지스터와 이를 이용한 표시장치
CN102903322A (zh) * 2012-09-28 2013-01-30 合肥京东方光电科技有限公司 移位寄存器及其驱动方法和阵列基板、显示装置
CN103065578A (zh) * 2012-12-13 2013-04-24 京东方科技集团股份有限公司 一种移位寄存器单元、栅极驱动电路和显示装置
CN103915058A (zh) * 2012-12-28 2014-07-09 乐金显示有限公司 移位寄存器
CN104299594A (zh) * 2014-11-07 2015-01-21 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及显示装置
CN104732939A (zh) * 2015-03-27 2015-06-24 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路、显示装置及栅极驱动方法

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