WO2016120906A1 - Dispositif de conversion analogique-numérique, dispositif de conversion numérique-analogique et plc - Google Patents

Dispositif de conversion analogique-numérique, dispositif de conversion numérique-analogique et plc Download PDF

Info

Publication number
WO2016120906A1
WO2016120906A1 PCT/JP2015/000417 JP2015000417W WO2016120906A1 WO 2016120906 A1 WO2016120906 A1 WO 2016120906A1 JP 2015000417 W JP2015000417 W JP 2015000417W WO 2016120906 A1 WO2016120906 A1 WO 2016120906A1
Authority
WO
WIPO (PCT)
Prior art keywords
area
data
digital data
stored
converter
Prior art date
Application number
PCT/JP2015/000417
Other languages
English (en)
Japanese (ja)
Inventor
富仁 後藤
智 浮穴
Original Assignee
三菱電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to KR1020177020860A priority Critical patent/KR101781324B1/ko
Priority to JP2015553699A priority patent/JP5987203B1/ja
Priority to CN201580074927.2A priority patent/CN107210750A/zh
Priority to DE112015006089.8T priority patent/DE112015006089T5/de
Priority to PCT/JP2015/000417 priority patent/WO2016120906A1/fr
Priority to TW104143102A priority patent/TW201633168A/zh
Publication of WO2016120906A1 publication Critical patent/WO2016120906A1/fr

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
    • G05B19/054—Input/output
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6502—Reduction of hardware complexity or efficient processing
    • H03M13/6505—Memory efficient implementations
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/15—Plc structure of the system
    • G05B2219/15118—Shared memory
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/21—Pc I-O input output
    • G05B2219/21137—Analog to digital conversion, ADC, DAC
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/16—Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter

Definitions

  • the present invention relates to an A / D converter, a D / A converter, the A / D converter, and a programmable controller (PLC) including the D / A converter.
  • PLC programmable controller
  • an A / D converter that converts the input analog data into digital data is used.
  • the sampling period of A / D conversion of an A / D converter that converts input analog data into digital data and the control period of the CPU that controls the entire PLC are asynchronous, and the sampling period Is often short. Therefore, the A / D converter is provided with a shared memory that is always accessible from the CPU, and the A / D converted data is temporarily stored in the shared memory, so that analog data can be obtained without reducing the A / D conversion sampling rate.
  • Patent Document 1 Is known (for example, Patent Document 1).
  • a D / A converter that converts digital data processed in the PLC into analog data is used.
  • the sampling period of D / A conversion and the control period of the CPU are asynchronous and the sampling period is often shorter. Therefore, the D / A converter is provided with a shared memory that is always accessible from the CPU, and the data to be D / A converted is temporarily stored in the shared memory, so that the analog data can be obtained without reducing the sampling speed of the D / A conversion.
  • Patent Document 2 Is known (for example, Patent Document 2).
  • Japanese Patent No. 5122000 page 6, FIG. 1
  • Japanese Patent No. 5327395 page 6, FIG. 1
  • the present invention has been made to solve the above-described problems, and is capable of continuously executing high-speed A / D conversion without depending on the capacity of the shared memory of the A / D conversion device. Get a conversion device.
  • a D / A conversion device capable of continuously executing high-speed D / A conversion without depending on the capacity of the shared memory of the D / A conversion device is obtained.
  • a PLC capable of outputting a waveform of
  • An A / D conversion device includes an A / D conversion unit that converts analog data into digital data, and after the conversion by the A / D conversion unit that is divided into first and second regions.
  • a storage unit having a ring buffer structure temporary storage area for storing the digital data, and the digital data converted by the A / D conversion unit stored in the first area of the temporary storage area When the amount of data coincides with the amount of data allocated to the first area, the digital data stored in the first area can be output and converted by the A / D converter.
  • a controller for storing the digital data in the second area.
  • the D / A converter according to the second invention is a D / A converter that converts digital data into analog data, and is divided into first and second regions and converted into the D / A converter.
  • a storage unit having a temporary storage area of a ring buffer structure for storing digital data, and the digital data to be converted to the D / A conversion unit are stored in the first and second areas, respectively.
  • the PLC according to the third invention includes an A / D conversion device according to the first invention, a D / A conversion device according to the second invention, and an internal memory for storing digital data.
  • the D converter When the D converter outputs the digital data stored in the temporary storage area of the A / D converter, the digital data is stored in the internal memory and stored in the temporary storage area of the D / A converter Is output from the internal memory.
  • the digital data stored in the storage unit can be transferred to the CPU device while the A / D converted digital data is stored in the storage unit, so that high-speed A / D conversion is continued. Can be executed.
  • the digital data stored in the storage unit can be D / A converted while the digital data to be D / A converted from the CPU device is transferred to the storage unit. Can be executed continuously.
  • high-speed and large-capacity logging is possible without depending on the capacity of the storage unit of the A / D converter, and the capacity of the storage unit of the D / A converter is further increased.
  • a PLC capable of outputting a high-speed and large-capacity waveform without depending on it can be obtained.
  • FIG. 1 is a configuration diagram of a PLC system according to the present invention.
  • BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram of the A / D conversion device which shows Embodiment 1 of this invention. It is a figure which shows the structure of the data stored in the log data temporary storage area of the A / D converter which shows Embodiment 1 of this invention, and a log data temporary storage area. It is a flowchart which shows operation
  • FIG. 1 is a configuration diagram of a PLC system according to the present invention.
  • the PLC system includes a PLC 1000 and a peripheral device 2000.
  • the PLC 1000 includes at least an A / D conversion device 100, a D / A conversion device 200, and a CPU device 300.
  • the PLC 1000 may include, for example, an external memory 400, an I / O control device that implements input / output control of an external device, a network communication device that implements a PLC network, and the like.
  • the devices included in the PLC 1000 are connected to each other via an inter-unit bus 500.
  • the peripheral device 2000 is a personal computer, for example, and performs setting of a user program, display of the data state of the internal memory 330, and the like.
  • the D / A converter 200 outputs analog data such as a current value and a voltage value to industrial equipment and the like controlled by the PLC 1000.
  • the CPU device 300 includes an external memory I / F 310 that is an interface for accessing an external memory 400 that stores a user program, data necessary for executing the user program, and data that is the execution result of the user program, and a user program.
  • Execution unit 320 for controlling the entire CPU device 300, internal memory 330, which is a memory for storing data necessary for user program execution, user program execution results, and log data, and peripheral devices
  • a peripheral device I / F 340 that is an interface for connecting 2000 and a bus I / F 350 that is a communication interface for communicating with a device connected via the inter-unit bus 500.
  • the calculation unit 320 includes an interrupt program execution unit 321 that executes an interrupt program.
  • the CPU device 300 executes a user program that is a program for operating each device included in the PLC 1000 to control industrial equipment, outputs an execution result, and acquires an input value such as a value used by the user program. Are repeated at a predetermined cycle. This repeated operation is called cyclic processing.
  • FIG. 2 is a configuration diagram of the A / D conversion apparatus 100 according to this embodiment.
  • the A / D conversion apparatus 100 includes an arithmetic unit 110 that controls the entire A / D conversion apparatus 100, an input arithmetic unit 120 that calculates an A / D converted value, and an A / D conversion that performs A / D conversion on analog data.
  • Unit 130, A / D conversion device 100 can write data at high speed, and CPU device 300 can read the stored A / D conversion value without executing complicated communication processing,
  • a bus I / F 150 which is a communication interface for communicating with devices connected via the inter-unit bus 500 is provided.
  • the input computing unit 120 includes a counter 121, a control unit 122, a parameter storage area 123, and a digital value input unit 124.
  • the shared memory 140 is a storage unit.
  • the A / D conversion apparatus 100 inputs analog data from a sensor that observes various observation values relating to industrial equipment and the like to be controlled by the PLC 1000, for example, flow rate, pressure, temperature, etc., and outputs them as current values or voltage values.
  • the analog data is converted into digital data, and the digital data (A / D conversion value) is stored in the shared memory 140 provided inside.
  • the A / D conversion value stored in the shared memory 140 is read by the CPU device 300 as the acquisition of the input value included in the aforementioned cyclic processing.
  • FIG. 3 is a diagram illustrating a structure of data stored in the log data temporary storage area 141 and the log data temporary storage area 141 of the A / D conversion apparatus 100 according to this embodiment.
  • the shared memory 140 stores an A / D conversion value read by cyclic processing by the CPU device 300.
  • the cycle of sampling analog data and converting it into digital data is shorter than the cycle of cyclic processing, so the CPU device 300 does not miss the A / D conversion value stored in the shared memory 140. It is difficult to read and log.
  • the A / D conversion apparatus 100 can store data at high speed, and the CPU apparatus 300 can read the A / D conversion value without executing complicated communication processing in the shared memory 140.
  • a log data temporary storage area 141 which is a temporary recording area for storing the D conversion value as log data is secured. The log data stored in the log data temporary storage area 141 can be read out to the peripheral device 2000 via the inter-unit bus 500, the CPU device 300, and the peripheral device I / F 340.
  • the log data temporary storage area 141 has a ring buffer structure. That is, log data is written in the log data temporary storage area 141 in chronological order from the top address. When the storage address of the log data reaches the end, the log data is overwritten again from the top address after wrapping around.
  • the calculation unit 320 of the CPU device 300 is configured so that the log data stored in the log data temporary storage area 141 is overwritten by the control unit 122 before the log data is overwritten. It is necessary to read to the memory 330. Therefore, the log data temporary storage area 141 is divided into three or more areas, which are allocated to any one of the transfer area, the execution area, and the margin area. In FIG. 3, the log data temporary storage area 141 is divided into four areas.
  • the area (a) is an execution area
  • the area (b), the area (c), and the area (d) are margin areas.
  • the control unit 122 controls the digital value input unit 124 to store the log data in the execution area of the log data temporary storage area 141.
  • the control unit 122 controls the execution area as a transfer area and stores new log data in the next area.
  • the control unit 122 stores the log data in the area (b) using the area (a) as the transfer area, the area (b) as the execution area.
  • the control unit 122 of the input computing unit 120 confirms that the logging for the execution area of the log data temporary storage area 141 has been completed via the bus I / F 150, the inter-unit bus 500, and the bus I / F 350. To the arithmetic unit 320. In addition, the control unit 122 notifies the calculation unit 320 of the CPU device 300 of the data amount allocated to the area (a) and the address at which the log data is last stored in the log data temporary storage area 141. Upon receiving the notification, the arithmetic unit 320 causes the interrupt program execution unit 321 to execute the interrupt program. The arithmetic unit 320 reads the log data stored in the transfer area of the log data temporary storage area 141 to the internal memory 330 by the interrupt program.
  • the internal memory 330 generally has a larger area than the shared memory 140 of the A / D conversion device 100.
  • the external memory 400 may be a dedicated memory or a general-purpose storage medium such as an SD memory card or a CF card.
  • the A / D conversion device 100 continues logging. For this reason, when the control unit 122 finishes storing the log data in the execution area before the CPU device 300 finishes reading the log data stored in the transfer area, it is stored in the log data temporary storage area 141 and The log data that has not been read out to the memory 330 may be overwritten by newly A / D converted log data. In order to prevent this, the log data temporary storage area 141 includes a margin area in addition to the execution area and the transfer area. When the log data acquisition of the CPU device 300 is delayed, the digital value input unit 124 stores the newly A / D converted log data in the margin area of the log data temporary storage area 141.
  • the log data temporary storage area 141 is divided into four or more areas, one area is an execution area, the other area is a transfer area, and the remaining plurality of areas are margin areas. Thereby, the margin area can be enlarged. Note that the number of divisions of the log data temporary storage area 141 may be appropriately changed by the user.
  • FIG. 4 is a flowchart showing the operation of the control unit 122 of the A / D conversion apparatus 100 in this embodiment.
  • the log data temporary storage area 141 is divided into four areas, a first area, a second area, a third area, and a fourth area, and the log data is stored in the first area. Indicates a completed state.
  • step (hereinafter referred to as “S”) 101 the control unit 122 determines the data amount of each area in the log data temporary storage area 141. Specifically, the control unit 122 determines the data amount of each area by dividing the capacity N words of the log data temporary storage area 141 by the number of areas to be divided. In FIG. 3, since N words are divided into four areas, the data amount of each area is N / 4 words.
  • control unit 122 stores the data amount of each area determined in S101 in the shared memory 140 that is a storage unit.
  • control unit 122 activates the A / D conversion unit 130 and starts logging.
  • the control unit 122 controls the digital value input unit 124 to store the log data converted by the A / D conversion unit 130 in the execution area of the log data temporary storage area 141.
  • the digital value input unit 124 stores the log data converted by the A / D conversion unit 130 at the start address of the execution area.
  • the digital value input unit 124 stores the log data converted by the A / D conversion unit 130 at an address next to the address where the log data was last stored. One address stores log data of one word.
  • control unit 122 stores the address where the log data is stored in S104 in the shared memory 140 which is a storage unit.
  • control unit 122 increments the counter 121 by the amount of data stored in S104.
  • the control unit 122 determines whether the count value of the counter 121 has reached the data amount of the area stored in the shared memory 140. When the count value of the counter 121 reaches the data amount of the area stored in the shared memory 140, the control unit 122 proceeds to S108. On the other hand, when the count value of the counter 121 has not reached the data amount of the area stored in the shared memory 140, the control unit 122 returns to S105 and continues logging.
  • the control unit 122 notifies the CPU device 300 of the log data extraction request, the address where the log data was last stored, and the data amount of the area stored in the shared memory 140 in S102.
  • the control unit 122 sets the execution area of the log data temporary storage area 141 as the transfer area and the area including the address next to the address where the log data is stored last as the execution area.
  • the control unit 122 sets area (a) as a transfer area and area (b) as an execution area.
  • control unit 122 clears the count value of the counter 121, returns to S104, and continues logging.
  • FIG. 5 is a diagram for explaining the state transition of the log data temporary storage area 141 in this embodiment.
  • FIG. 6 is a flowchart showing the operation of the interrupt program execution unit 321 in this embodiment.
  • the interrupt program execution unit 321 executes an interrupt program that transfers log data in the transfer area to the internal memory 330.
  • the left diagram shows a state in which the log data has been stored in the execution area with the area (a) as the execution area, the area (b), the area (c), and the area (d) as the margin area.
  • the control unit 122 requests the CPU device 300 to retrieve the log data stored in the area (a), the address at which the log data is stored last, and the area (a). Notify the amount of data allocated to.
  • the address at which log data is stored last is the address at which log data at time (N / 4) T is stored in the left diagram of FIG.
  • the central diagram shows a state in which log data is stored in the area (b) with the area (a) as the transfer area, the area (b) as the execution area, the area (c) and the area (d) as the margin area. While the CPU device 300 reads the log data stored in the area (a), the control unit 122 stores the log data output from the A / D conversion unit 130 in the area (b).
  • the right figure shows a state in which log data is stored in the area (c) with the area (b) as the transfer area, the area (c) as the execution area, the areas (d) and (a) as the margin areas. While the CPU device 300 reads the log data stored in the area (b), the control unit 122 stores the log data output from the A / D conversion unit 130 in the area (c).
  • the interrupt program execution unit 321 reads log data from the transfer area of the log data temporary storage area 141 and stores it in the internal memory 330 in S201.
  • the interrupt program execution unit 321 determines whether the read data amount has reached the data amount of the area stored in the shared memory 140. When the read data amount reaches the data amount of the area stored in the shared memory 140, the interrupt program execution unit 321 proceeds to S203. On the other hand, when the read data amount does not reach the data amount of the area stored in the shared memory 140, the interrupt program execution unit 321 returns to S201 and continues reading the log data.
  • the interrupt program execution unit 321 determines whether the data amount stored in the internal memory 330 has reached a predetermined data amount. When the amount of data stored in the internal memory 330 reaches a predetermined data amount, the interrupt program execution unit 321 proceeds to S204. On the other hand, when the data amount stored in the internal memory 330 has not reached the predetermined data amount, the interrupt program execution unit 321 ends the interrupt program.
  • the interrupt program execution unit 321 transfers the log data stored in the internal memory 330 to the external memory 400, and ends the interrupt program. If the PLC system does not include the external memory 400, S203 and S204 are omitted.
  • the method of reading the log data from the transfer area of the log data temporary storage area 141 may read the log data one point at a time or read a plurality of points collectively.
  • the sampling rate of the A / D conversion unit 130 is reduced even when the sampling period is shorter than the cyclic processing period. Logging is possible without transferring the logged data to the internal memory 330 of the CPU 300. Further, by providing a margin area in the log data temporary storage area 141 in addition to the execution area and the transfer area, the arithmetic unit 320 of the CPU device 300 has a higher priority than the interrupt program for the log data extraction request notification. Even when this is executed, the log data stored in the transfer area can be prevented from being overwritten.
  • the log data stored in the internal memory 330 of the CPU device 300 is transferred to the external memory 400, and therefore depends on the capacity of the shared memory 140 of the A / D conversion device 100. And high-speed and large-capacity logging.
  • an A / D conversion unit 130 that converts analog data into digital data
  • an A / D conversion unit 130 that is divided into first and second regions.
  • a shared memory 140 having a log data temporary storage area 141 having a ring buffer structure for storing digital data after conversion by the A / D converter 130, and a first area of the log data temporary storage area 141 for digital data converted by the A / D converter 130
  • the data amount of the stored digital data matches the data amount assigned to the first area
  • the digital data stored in the first area can be output and the A / D converter
  • a control unit 122 that stores the digital data newly converted by 130 in the second area.
  • log data stored in the transfer area can be transferred to the internal memory 330 of the CPU device 300 while continuing A / D conversion, so that high-speed A / D conversion can be continuously executed.
  • the log data temporary storage area 141 is divided into first, second, and third areas, and the control unit 122 is divided into the second area. If the digital data stored in the first area is output when the data amount of the stored digital data matches the data amount allocated to the second area, the stored digital data is stored in the second area. The digital data stored in the first area is continuously output, and the digital data newly converted by the A / D converter 130 is stored in the third area. Thereby, when the transfer of the log data stored in the transfer area is not completed when the storage of the log data in the execution area is completed, the control unit 122 is the digital data after A / D conversion. Since the log data is stored in the margin area, there is no possibility that log data that has not been transferred is overwritten and erased by newly A / D converted log data.
  • the control unit 122 assigns to the storage unit the data amount allocated to each area constituting the log data temporary storage area 141 and the A / D conversion unit.
  • the address at which the digital data converted by 130 is stored last is stored, and the data amount of the digital data stored in any one of the log data temporary storage areas 141 matches the data amount allocated to the area.
  • a request for extracting the digital data stored in the area, the amount of data allocated to the area, and the address at which the digital data converted by the A / D converter 130 is stored last are output.
  • the CPU device 300 can acquire log data based on the information notified from the control unit 122.
  • the A / D conversion apparatus 100 includes a counter 121 that counts the amount of digital data stored in any one of the log data temporary storage areas 141, and the control unit 122 includes When the count value of the counter 121 matches the amount of data assigned to the area, the count value is reset. Thus, the control unit 122 can notify the CPU device 300 of a log data extraction request when the count value of the counter 121 reaches a predetermined value.
  • the log data temporary storage area 141 is divided into three or more areas, it may be divided into two areas.
  • the control unit 122 can transfer the log data stored in the other area to the internal memory 330 of the CPU device 300 while storing the log data in one area of the log data temporary storage area 141.
  • high-speed and large-capacity log data can be read out to the internal memory 330 without being affected by the difference between the sampling period and the cyclic processing period.
  • the internal memory 330 may have a ring buffer structure similar to the log data temporary storage area 141. In this case, when the log data stored in the internal memory 330 from the log data temporary storage area 141 reaches the end, the calculation unit 320 wraps around and overwrites the log data again from the top address.
  • the A / D conversion apparatus 100 includes a single ring buffer memory as the log data temporary storage area 141, the present invention is not limited thereto. Since the A / D conversion apparatus 100 generally includes a plurality of input channels, a plurality of ring buffer structure memories may be mounted and processing may be performed in parallel.
  • log data may be read by a data logger connected to the PLC system.
  • data may be read for each cyclic processing cycle of the CPU device 300 without using the interrupt program. In this case, the processing of S101 and S106 to S109 in FIG. 4 may be omitted.
  • FIG. FIG. 1 is a configuration diagram of a PLC system according to the present invention.
  • the PLC system in this embodiment is the same as that in the first embodiment.
  • FIG. 7 is a configuration diagram of the D / A conversion device 200 according to this embodiment.
  • the D / A converter 200 includes an arithmetic unit 210 that controls the entire D / A converter, an output calculator 220 for calculating a value that is output after D / A conversion, and a D / A that performs D / A conversion on digital data.
  • the shared memory 240 is a storage unit.
  • the D / A conversion device 200 converts the digital data processed in the CPU device 300 into analog data, and outputs the analog data (D / A conversion value) to industrial equipment or the like that is controlled by the PLC 1000. .
  • the digital data stored in the shared memory 240 is transferred from the CPU device 300 as an output of the execution result of the user program that is a program for controlling the industrial equipment included in the cyclic processing described above.
  • FIG. 8 is a diagram showing the structure of data stored in the waveform data string temporary storage area 241 and the waveform data string temporary storage area 241 of the D / A conversion device 200 in this embodiment.
  • the shared memory 240 includes a waveform data string temporary storage area 241 that is a temporary storage area for storing digital data output by cyclic processing by the CPU device 300 as a waveform data string.
  • the waveform data string is a digital data string composed of a plurality of digital values.
  • the waveform data string can be composed of an arbitrary number of points.
  • the score means the amount of data. One point corresponds to, for example, 16 bits or 32 bits, and corresponds to one digital value.
  • the cycle (sampling cycle) for sampling digital data and converting it into analog data is shorter than the cycle of cyclic processing. Therefore, in order for the D / A conversion device 200 to continuously output the waveform data sequence written in the waveform data sequence temporary storage area 241, the D / A conversion device 200 outputs the waveform while the CPU device It is necessary to read the waveform data string from the 300 internal memory 330. Therefore, the waveform data string is temporarily stored in the shared memory 240 in which the D / A conversion apparatus 200 can read data at high speed and the CPU apparatus 300 can write the waveform data string without performing complicated communication processing. Area 241 is secured.
  • the waveform data string temporary storage area 241 has a ring buffer structure. That is, the waveform data string stored in the waveform data string temporary storage area 241 is read in order from the head address. When the read address of the waveform data string reaches the end, the waveform data string is read again from the start address after wrapping around.
  • the arithmetic unit 320 of the CPU device 300 When high-speed and large-capacity continuous waveform output is performed from the D / A converter 200, the arithmetic unit 320 of the CPU device 300 first prepares a large-capacity waveform data string on the internal memory 330 and temporarily stores the waveform data string. The waveform data string corresponding to the capacity of the storage area 241 is transferred before the waveform output is started. After starting waveform output, the control unit 222 of the D / A converter 200 needs to read the waveform data string from the internal memory 330 before outputting all the waveform data strings stored in the waveform data string temporary storage area 241. There is. Therefore, the waveform data string temporary storage area 241 is divided into three or more areas, which are assigned to any one of the transfer area, the execution area, and the margin area.
  • the waveform data string temporary storage area 241 is divided into four areas.
  • the area (a) is an execution area
  • the area (b), the area (c), and the area (d) are margin areas.
  • the control unit 222 activates the D / A conversion unit 230 and starts waveform output
  • the control unit 222 controls the digital value output unit 224 to read the waveform data string from the execution area of the waveform data string temporary storage area 241.
  • the control unit 222 controls the execution area to be a transfer area and to read the waveform data string from the next area.
  • the control unit 222 uses the area (a) as the transfer area, the area (b) as the execution area, and the waveform stored in the area (b). Output data string.
  • the control unit 222 of the output computing unit 220 confirms that the reading of the waveform data string for the execution area of the waveform data string temporary storage area 241 is completed via the bus I / F 250, the inter-unit bus 500, and the bus I / F 350. And notifies the arithmetic unit 320 of the CPU device 300.
  • the control unit 222 also notifies the arithmetic unit 320 of the CPU device 300 of the data amount allocated to the execution area and the address at which the waveform data string was last output in the waveform data string temporary storage area 141.
  • the arithmetic unit 320 causes the interrupt program execution unit 321 to execute the interrupt program.
  • the arithmetic unit 320 transfers the waveform data string from the internal memory 330 to the transfer area of the waveform data string temporary storage area 241 by the interrupt program.
  • the internal memory 330 generally has a larger area than the shared memory 240 of the D / A conversion device 200.
  • a waveform data string having a capacity larger than the capacity of the internal memory 330 may be prepared in the external memory 400.
  • the external memory 400 may be a dedicated memory or a general-purpose storage medium such as an SD memory card or a CF card.
  • the D / A conversion device 200 continuously executes waveform output. Therefore, when the control unit 122 finishes outputting the waveform data string stored in the execution area before the CPU device 300 finishes transferring the waveform data string to the transfer area, it is stored in the waveform data string temporary storage area 241. There is a possibility that the waveform data string that has already been output will be output again. In order to prevent this, the waveform data string temporary storage area 241 includes a margin area in addition to the execution area and the transfer area. When the waveform data string transfer of the CPU device 300 is delayed, the digital value output unit 224 outputs the waveform data string stored in the margin area. As a result, the waveform data string stored in the waveform data string temporary storage area 241 can be prevented from being re-output.
  • the waveform data string temporary storage area 241 When the waveform data string temporary storage area 241 is divided into four or more areas, one area is an execution area, the other area is a transfer area, and the remaining plural areas are margin areas. Thereby, the margin area can be enlarged. Note that the number of divisions of the waveform data string temporary storage area 241 may be appropriately changed by the user.
  • FIG. 9 is a flowchart showing the operation of the control unit 222 of the D / A conversion device 200 in this embodiment.
  • the waveform data string temporary storage area 241 is divided into four areas of a first area, a second area, a third area, and a fourth area, and the waveform stored in the first area. This shows the state where the output of the data string has been completed.
  • the control unit 222 determines the data amount of each area in the waveform data string temporary storage area 241. Specifically, the control unit 222 determines the data amount of each area by dividing the size N words of the waveform data string temporary storage area 241 by the number of areas to be divided. In FIG. 8, since N words are divided into four areas, the data amount of each area is N / 4 words.
  • control unit 222 stores the data amount of the area determined in S301 in the shared memory 240 that is a storage unit.
  • control unit 222 reads out the waveform data string for the capacity of the waveform data string temporary storage area 241 from the internal memory 330 of the CPU device 300, and stores it in the waveform data string temporary storage area 241.
  • control unit 222 activates the D / A conversion unit 230 and starts waveform output.
  • step S ⁇ b> 305 the control unit 222 controls the digital value output unit 224 to read the waveform data string from the execution area of the waveform data string temporary storage area 241 and output the waveform data string to the D / A conversion unit 230.
  • the digital value output unit 224 reads the waveform data string stored at the start address of the execution area and outputs it to the D / A conversion unit 230.
  • the digital value output unit 224 reads the waveform data string stored at the address next to the waveform data string read last. Read and output to the D / A converter 230.
  • One address stores a waveform data string of one word.
  • control unit 222 stores the address at which the waveform data string is output in the shared memory 240 that is a storage unit.
  • control unit 222 increments the counter 221 by the amount of data output in S305.
  • the control unit 222 determines whether the count value of the counter 221 has reached the data amount of the area stored in the shared memory 240. When the count value of the counter 221 reaches the data amount of the area stored in the shared memory 240, the control unit 222 proceeds to S309. On the other hand, when the count value of the counter 221 has not reached the data amount of the area stored in the shared memory 240, the control unit 222 returns to S306 and continues waveform output.
  • the control unit 222 notifies the CPU device 300 of the waveform data string acquisition request, the address at which the waveform data string was last output, and the data amount of the area stored in the shared memory 240 in S302.
  • the control unit 222 sets the execution area of the waveform data string temporary storage area 241 as the transfer area and the area including the address next to the address where the data is stored last as the execution area.
  • the control unit 122 sets area (a) as a transfer area and area (b) as an execution area.
  • control unit 222 clears the count value of the counter 221, returns to S305, and continues waveform output.
  • FIG. 10 is a diagram for explaining the state transition of the waveform data string temporary storage area 241 in this embodiment.
  • FIG. 11 is a flowchart showing the operation of the interrupt program execution unit 321 in this embodiment.
  • the interrupt program execution unit 321 transfers the waveform data string stored in the internal memory 330 of the CPU device 300 to the transfer area. Execute the interrupt program to be transferred to.
  • the region (a) is the execution region
  • the region (b), the region (c), and the region (d) are the margin regions
  • the output of the waveform data string stored in the execution region is finished. Indicates the state.
  • the control unit 222 requests the CPU device 300 to acquire the waveform data string to the area (a), the address at which the waveform data string was last output, and the shared memory in S302.
  • the amount of data stored in the area 240 is notified.
  • the address at which the waveform data string is output last is the address storing the waveform data string (N / 4) in the left diagram of FIG.
  • the area (a) is the transfer area
  • the area (b) is the execution area
  • the area (c) is the margin area
  • the waveform data sequence stored in the area (b) is output.
  • the control unit 222 outputs the waveform data string stored in the area (b).
  • the right figure uses the area (b) as the transfer area, the area (c) as the execution area, the areas (d) and (a) as the margin areas, and outputs the waveform data string stored in the area (c).
  • the control unit 222 causes the waveform data string stored in the area (c) to be output.
  • the interrupt program execution unit 321 reads the waveform data string from the internal memory 330 and stores it in the transfer area of the waveform data string temporary storage area 241.
  • step S ⁇ b> 402 the interrupt program execution unit 321 determines whether the amount of data transferred from the internal memory 330 to the waveform data string temporary storage area 241 has reached the amount of data stored in the shared memory 240. If the transferred data amount reaches the data amount of the area stored in the shared memory 240, the interrupt program execution unit 321 proceeds to S403. On the other hand, when the transferred data amount does not reach the data amount of the area stored in the shared memory 240, the interrupt program execution unit 321 returns to S401 and continues to transfer the waveform data string.
  • the interrupt program execution unit 321 determines whether the data amount transferred from the internal memory 330 has reached a predetermined data amount. If the amount of data transferred from the internal memory 330 reaches a predetermined data amount, the interrupt program execution unit 321 proceeds to S404. On the other hand, when the data amount transferred from the internal memory 330 has not reached the predetermined data amount, the interrupt program execution unit 321 ends the interrupt program.
  • the interrupt program execution unit 321 reads the waveform data string from the external memory 400, stores it in the internal memory 330, and ends the interrupt program. If the PLC system does not include the external memory 400, S403 and S404 are omitted.
  • the method of transferring the waveform data string to the transfer area of the waveform data string temporary storage area 241 may transfer the waveform data string one point at a time, or may transfer a plurality of points collectively.
  • the sampling rate of the D / A converter 230 is reduced even when the sampling period is shorter than the cyclic process period. Waveform output is possible, and a large-capacity waveform data string can be read from the internal memory 330 of the CPU device 300. Further, by providing a margin area in addition to the waveform data string temporary storage area 241 execution area and the transfer area, the arithmetic unit 320 of the CPU device 300 executes a program having a higher priority than the interrupt program for the waveform data string acquisition request notification. Even if it is executed, it is possible to prevent the data stored in the transfer area from being re-output.
  • the waveform data string is transferred from the external memory 400 to the internal memory 330 of the CPU device 300, so that it does not depend on the capacity of the shared memory 240 of the D / A conversion device 200. High-speed and large-capacity waveform output can be executed.
  • a D / A converter 230 that converts digital data into analog data, and a D / A converter 230 that is divided into first and second regions.
  • a shared memory 240 having a waveform data string temporary storage area 241 having a ring buffer structure for storing digital data to be converted into digital data, and digital data to be converted into the D / A converter 230 are stored in the first and second areas, respectively.
  • the digital data stored in the first area of the waveform data string temporary storage area 241 is output to the D / A converter 230, and the data amount of the output digital data is assigned to the first area. When the amount of data matches, the digital data newly converted by the D / A converter 230 can be written to the first area.
  • the waveform data sequence transferred from the internal memory 330 of the CPU device 300 can be stored in the transfer area while continuing the D / A conversion, so that the high-speed D / A conversion can be continuously executed.
  • the waveform data string temporary storage area 241 is divided into first, second, and third areas, and the first, second, and third areas.
  • the digital data to be converted by the D / A converter 230 is stored in each area, and the controller 222 first outputs the digital data stored in the second area to the D / A converter 230.
  • the controller 222 first outputs the digital data stored in the second area to the D / A converter 230.
  • the digital data newly converted by the D / A converter 230 can be written in the second area
  • the digital data newly converted by the D / A converter 230 in the first area is continuously stored, and the digital data stored in the third area is output to the D / A converter 230.
  • the control unit 222 stores the data amount allocated to each area constituting the waveform data string temporary storage area 241 and the D / A conversion in the storage unit.
  • the address at which the digital data to be converted is last output is stored in the unit 230 and the digital data stored in any one of the waveform data string temporary storage area 241 is output, the digital data to the area
  • the data acquisition request, the amount of data allocated to the area, and the address at which the digital data converted by the D / A converter 230 is output last are output.
  • the CPU device 300 can transfer the waveform data string based on the information notified from the control unit 222.
  • the D / A conversion apparatus 200 in this embodiment includes a counter 221 that counts the amount of digital data output from any one of the waveform data string temporary storage areas 241, and includes a control unit 222. Resets the count value when the count value of the counter 221 matches the data amount allocated to the area. Thereby, the control part 222 can notify the acquisition request
  • the A / D conversion device 100 described in the first embodiment the D / A conversion device 200 described in the second embodiment, and an internal memory 330 for storing digital data.
  • the A / D converter 100 outputs the digital data stored in the log data temporary storage area 141 of the A / D converter 100, the digital data is stored in the internal memory 330, and the D / A converter 200 And a CPU device 300 for outputting digital data stored in the waveform data string temporary storage area 241 from the internal memory 330.
  • the PLC 1000 can acquire log data while continuously executing high-speed A / D conversion, and can output a waveform data string while continuously executing high-speed D / A conversion.
  • the waveform data string temporary storage area 241 is divided into three or more areas, it may be divided into two areas.
  • the control unit 222 outputs the waveform data string stored in one area of the waveform data string temporary storage area 241 while storing the waveform data string acquired from the internal memory 330 of the CPU device 300 in the other area. Be made. This enables high-speed and large-capacity waveform output without being affected by the difference between the sampling period and the cyclic processing period.
  • the internal memory 330 may have a ring buffer structure similar to the waveform data string temporary storage area 241. In this case, when the waveform data sequence stored from the external memory 400 to the internal memory 330 reaches the end, the calculation unit 320 wraps around and overwrites the waveform data sequence from the top address again.
  • the D / A conversion device 200 includes one ring buffer memory as the waveform data string temporary storage area 241, the present invention is not limited to this. Since the D / A conversion apparatus 200 generally includes a plurality of output channels, a plurality of ring buffer memories may be mounted to perform processing in parallel.
  • data transfer may be performed for each cyclic processing cycle of the CPU device 300 without using the interrupt program.
  • the processing of S301 and S307 to S310 and S108 in FIG. 9 may be omitted.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Probability & Statistics with Applications (AREA)
  • Automation & Control Theory (AREA)
  • Programmable Controllers (AREA)
  • Analogue/Digital Conversion (AREA)
  • Recording Measured Values (AREA)

Abstract

La présente invention concerne un dispositif de conversion analogique-numérique (A/N) pouvant exécuter en continu une conversion A/N à vitesse élevée; un dispositif de conversion numérique-analogique (N/A) pouvant exécuter en continu une conversion N/A à vitesse élevée; et un contrôleur programmable (PLC) muni des dispositifs de conversion A/N et N/A. Le PLC comprend : une unité de conversion de données (130, 230); une mémoire partagée (140, 240) comportant une zone de mise en mémoire temporaire (141, 241) divisée en des première et seconde zones; et une unité de commande (122) ou une unité de commande (222). Lorsqu'un accès à une quantité de données prédéfinie se produit dans la zone de mise en mémoire temporaire (141, 241), l'unité de commande (122) amène la livraison en sortie des données mises en mémoire à l'adresse accédée, ou l'unité de commande (222) amène la mise en mémoire de nouvelles données au niveau de ladite adresse.
PCT/JP2015/000417 2015-01-30 2015-01-30 Dispositif de conversion analogique-numérique, dispositif de conversion numérique-analogique et plc WO2016120906A1 (fr)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1020177020860A KR101781324B1 (ko) 2015-01-30 2015-01-30 A/d 변환장치, d/a 변환장치, 및 plc
JP2015553699A JP5987203B1 (ja) 2015-01-30 2015-01-30 Ａ／ｄ変換装置、ｄ／ａ変換装置、及びｐｌｃ
CN201580074927.2A CN107210750A (zh) 2015-01-30 2015-01-30 A/d变换装置、d/a变换装置以及plc
DE112015006089.8T DE112015006089T5 (de) 2015-01-30 2015-01-30 A/D-Wandler, D/A-Wandler und speicherprogrammierbare Steuerung
PCT/JP2015/000417 WO2016120906A1 (fr) 2015-01-30 2015-01-30 Dispositif de conversion analogique-numérique, dispositif de conversion numérique-analogique et plc
TW104143102A TW201633168A (zh) 2015-01-30 2015-12-22 Ａ／ｄ變換裝置、ｄ／ａ變換裝置及ｐｌｃ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2015/000417 WO2016120906A1 (fr) 2015-01-30 2015-01-30 Dispositif de conversion analogique-numérique, dispositif de conversion numérique-analogique et plc

Publications (1)

Publication Number Publication Date
WO2016120906A1 true WO2016120906A1 (fr) 2016-08-04

Family

ID=56542574

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2015/000417 WO2016120906A1 (fr) 2015-01-30 2015-01-30 Dispositif de conversion analogique-numérique, dispositif de conversion numérique-analogique et plc

Country Status (6)

Country Link
JP (1) JP5987203B1 (fr)
KR (1) KR101781324B1 (fr)
CN (1) CN107210750A (fr)
DE (1) DE112015006089T5 (fr)
TW (1) TW201633168A (fr)
WO (1) WO2016120906A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019200744A (ja) * 2018-05-18 2019-11-21 オムロン株式会社 制御装置及びデータ記録方法
JP2020184257A (ja) * 2019-05-09 2020-11-12 オムロン株式会社 制御装置、制御方法、制御プログラム
US11275356B2 (en) 2018-11-22 2022-03-15 Mitsubishi Electric Corporation Input-output control unit, PLC and data control method

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111313220A (zh) * 2020-04-15 2020-06-19 武汉博联特科技有限公司 基于三菱plc的qcw激光器控制系统

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002042422A (ja) * 2000-07-19 2002-02-08 Sharp Corp ディスク再生装置
JP2002374167A (ja) * 2001-06-12 2002-12-26 Nissin Electric Co Ltd 監視制御のアナログ入力装置
JP2008287559A (ja) * 2007-05-18 2008-11-27 Keyence Corp Ｐｌｃ動作表示システム
JP5122000B2 (ja) * 2009-03-23 2013-01-16 三菱電機株式会社 Ａ／ｄ変換装置およびプログラマブルコントローラシステム
JP5327395B2 (ja) * 2010-09-28 2013-10-30 三菱電機株式会社 Ｄ／ａ変換装置、周辺装置、及びｐｌｃ

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05289847A (ja) * 1992-04-06 1993-11-05 Toshiba Corp リングバッファ管理装置
JP3569592B2 (ja) * 1996-02-20 2004-09-22 ヤマハ株式会社 符復号装置
JP2959519B2 (ja) * 1997-04-24 1999-10-06 日本電気株式会社 グラフィックス表示装置
KR101077339B1 (ko) * 2007-12-28 2011-10-26 가부시끼가이샤 도시바 반도체 기억 장치
CN201345098Y (zh) * 2009-02-27 2009-11-11 武汉中岩科技有限公司 一种同时读写存储器的数据采集装置
WO2012098676A1 (fr) * 2011-01-21 2012-07-26 三菱電機株式会社 Unité d'entrée analogique et automate programmable
CN102157914B (zh) * 2011-04-02 2014-03-12 山东电力研究院 一种新的继电保护装置的半波快速检测方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002042422A (ja) * 2000-07-19 2002-02-08 Sharp Corp ディスク再生装置
JP2002374167A (ja) * 2001-06-12 2002-12-26 Nissin Electric Co Ltd 監視制御のアナログ入力装置
JP2008287559A (ja) * 2007-05-18 2008-11-27 Keyence Corp Ｐｌｃ動作表示システム
JP5122000B2 (ja) * 2009-03-23 2013-01-16 三菱電機株式会社 Ａ／ｄ変換装置およびプログラマブルコントローラシステム
JP5327395B2 (ja) * 2010-09-28 2013-10-30 三菱電機株式会社 Ｄ／ａ変換装置、周辺装置、及びｐｌｃ

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019200744A (ja) * 2018-05-18 2019-11-21 オムロン株式会社 制御装置及びデータ記録方法
WO2019221082A1 (fr) * 2018-05-18 2019-11-21 オムロン株式会社 Dispositif de commande et procédé d'enregistrement de données
JP7067260B2 (ja) 2018-05-18 2022-05-16 オムロン株式会社 制御装置及びデータ記録方法
US11275356B2 (en) 2018-11-22 2022-03-15 Mitsubishi Electric Corporation Input-output control unit, PLC and data control method
JP2020184257A (ja) * 2019-05-09 2020-11-12 オムロン株式会社 制御装置、制御方法、制御プログラム
JP7358772B2 (ja) 2019-05-09 2023-10-11 オムロン株式会社 制御装置、制御方法、制御プログラム

Also Published As

Publication number Publication date
TW201633168A (zh) 2016-09-16
JP5987203B1 (ja) 2016-09-07
CN107210750A (zh) 2017-09-26
KR101781324B1 (ko) 2017-09-22
KR20170093986A (ko) 2017-08-16
DE112015006089T5 (de) 2017-10-19
JPWO2016120906A1 (ja) 2017-04-27

Similar Documents

Publication Publication Date Title
US9934160B1 (en) Bit-mapped DMA and IOC transfer with dependency table comprising plurality of index fields in the cache for DMA transfer
JP5987203B1 (ja) Ａ／ｄ変換装置、ｄ／ａ変換装置、及びｐｌｃ
KR102564165B1 (ko) 비휘발성 메모리 익스프레스 컨트롤러에 의한 입출력 큐 관리 방법
JP2013149087A (ja) キャッシュ装置、キャッシュプログラム、及び通信装置
CN109558344B (zh) 一种适用于网络传输的dma传输方法及dma控制器
JP7216781B2 (ja) データ記憶方法、データ記憶装置、データ読み取り方法及びデータ読み取り装置
KR101812912B1 (ko) 자율 메모리를 위한 방법 및 시스템
KR20100077116A (ko) 반도체 기억 장치, 데이터 전송 장치 및 반도체 기억 장치의 제어 방법
JP2016045899A (ja) データ転送制御装置
JP4855864B2 (ja) ダイレクトメモリアクセスコントローラ
CN110968538B (zh) 一种数据缓冲方法和装置
JP6498557B2 (ja) プログラマブルコントローラ
US9767054B2 (en) Data transfer control device and memory-containing device
JP2018132948A (ja) 読込プログラム、読込方法および情報処理装置
JP7067260B2 (ja) 制御装置及びデータ記録方法
US20150006765A1 (en) Direct memory access descriptor-based synchronization
JP5404294B2 (ja) データ演算装置の制御回路及びデータ演算装置
JP4170330B2 (ja) 情報処理装置
US10169271B1 (en) Direct memory access descriptor
JPWO2014002222A1 (ja) リードリクエスト処理装置
JP5982148B2 (ja) 半導体記憶装置
JP5850724B2 (ja) データ処理装置およびその制御方法
JP2015185103A (ja) 記憶装置、情報処理装置、データアクセス方法、およびプログラム
JP7180681B2 (ja) 情報処理装置、制御方法、及びプログラム
JP2010134558A (ja) メモリ管理システム及びメモリ管理プログラム

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 2015553699

Country of ref document: JP

Kind code of ref document: A

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15879807

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 20177020860

Country of ref document: KR

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 112015006089

Country of ref document: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15879807

Country of ref document: EP

Kind code of ref document: A1