WO2016107062A1 - 一种在倒装芯片基板上小间距之间制备高凸点锡球的制备方法 - Google Patents

一种在倒装芯片基板上小间距之间制备高凸点锡球的制备方法 Download PDF

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WO2016107062A1
WO2016107062A1 PCT/CN2015/080305 CN2015080305W WO2016107062A1 WO 2016107062 A1 WO2016107062 A1 WO 2016107062A1 CN 2015080305 W CN2015080305 W CN 2015080305W WO 2016107062 A1 WO2016107062 A1 WO 2016107062A1
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substrate
solder
solder ball
steel mesh
bump
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PCT/CN2015/080305
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English (en)
French (fr)
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李志东
庭玉文
邱醒亚
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广州兴森快捷电路科技有限公司
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Priority to JP2017522707A priority Critical patent/JP2017522741A/ja
Publication of WO2016107062A1 publication Critical patent/WO2016107062A1/zh

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

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  • the invention relates to a chip solder ball preparation process, in particular to a preparation method for preparing a high bump solder ball between small pitches on a flip chip substrate.
  • Flip Chip is a connection method with higher density connection I/O than wire bonding; with the development of chip technology, the density of bump bumps connected to the chip on the package substrate is also higher. The higher it is.
  • the main processes for making bump balls are:
  • solder paste printing method printing solder paste on a steel mesh with a specific pattern (stencil opening), and forming a bump after reflow cleaning; the advantage is that the solder alloy can be easily changed, and the SRO (solder resist opening) can be absorbed. Window), MMO deviation, can use existing equipment, can form Bump on various shapes of Pad (pad), high production efficiency, high alignment accuracy.
  • the disadvantage is that there are Bump voids and Bump Heights (bump ht).
  • Tin ball method after the flux is applied to the metal mesh plate or grid, the solder ball is coated; after that, reflow soldering and cleaning are performed to form a bump; the advantage is that high Bump ht and Bump void can be formed; the disadvantage is accuracy The ability to align is limited, and it is impossible to absorb the deviation of SRO, and the possibility of contamination is large when the composition is changed.
  • the solder paste printing method has high precision of alignment, high production efficiency, and can be used for a variety of alloy solder pastes; with the development trend of high-precision connection of package substrates, the solder paste printing method has a greater development advantage.
  • the bump pitch is reduced, the gap between the bump pads is reduced.
  • the opening of the steel mesh is correspondingly reduced;
  • the thickness of the steel mesh should be correspondingly reduced.
  • the height of the bump produced by this process is also reduced with the development of small pitch. the trend of.
  • the Bump height is low, the problem of poor connection between the substrate and the chip is more likely to occur. Therefore, for small pitch bumps, by adopting a new fabrication method to increase the bump height, it is important to reduce the connection failure and connection reliability between the chip and the substrate.
  • the problem to be solved by the present invention is to provide a method for preparing a high bump solder ball between small pitches on a flip chip substrate, which can prepare a solder ball with a higher bump at a small pitch of the pad. And the connection between the chip and the substrate is reliable.
  • a method for preparing a high bump solder ball between small pitches on a flip chip substrate comprising the following steps
  • step S2 performing the first reflow soldering of the substrate of step S1, forming a solder joint on the substrate, and depositing a flux in the solder paste on the surface of the substrate;
  • step S5 placing the second steel mesh on the substrate obtained after the step S4 is leveled, and performing the second steel mesh printing. Place the solder paste on the solder joint on the substrate;
  • step S6 performing the second reflow soldering on the substrate of step S5, forming a new solder joint on the substrate, and depositing the flux in the solder paste again on the surface of the substrate;
  • the second steel mesh has a coefficient of expansion and contraction that is 100.01-100.02% smaller than that of the first steel mesh.
  • the thickness of the second steel mesh is 2/3 of the thickness of the first steel mesh.
  • the mesh of the second steel mesh is 10-20 ⁇ m smaller than the mesh of the first steel mesh.
  • the invention can make a high bump solder ball between the small pitch of the pad and the connection reliability between the chip and the substrate through the secondary printing process flow on the basis of the existing solder paste printing method.
  • the bump ball pitch can be made about 100-150 ⁇ m, and the solder ball height is 25-40 ⁇ m flip chip.
  • FIG. 1 is a flow chart showing a process for preparing a high bump solder ball between small pitches on a flip chip substrate according to the present invention
  • Fig. 2 is a view showing the comparison effect between the welded joint after the first flattening and the welded joint after the prior flattening in an embodiment.
  • the present invention Adopt the following production process:
  • a method for preparing a high bump solder ball between small pitches on a flip chip substrate comprising the following steps:
  • the first steel mesh and the flip chip substrate are selected, and the specifications of the two are basically the same; secondly, the first steel mesh is placed on the substrate, and the first steel mesh printing is performed, and the solder paste is printed. On the substrate, and try to thicken the thickness of the solder paste; the mesh of the first steel mesh may be circular, depending on the design of the pad, or other shapes, such as square, oval, etc., the aperture specifications are also specific Depending on the situation;
  • step S2 the substrate of step S1 is sent to a reflow soldering machine, and the first reflow soldering is performed.
  • the substrate also referred to as bump bumps, bump solder balls. , solder joints, solder balls, etc.
  • depositing flux in the solder paste on the surface of the substrate is also referred to as bump bumps, bump solder balls.
  • the mesh of the second steel mesh may be circular, depending on the design of the pad, or other shapes, such as a square shape, an elliptical shape, etc., and the aperture specifications are also determined according to specific conditions;
  • step S6 The substrate of step S5 is again sent to the reflow soldering machine for a second reflow soldering. After the second reflow soldering, a new solder joint is formed on the substrate, and the solder paste is again deposited on the surface of the substrate.
  • the inspection of the bump solder ball is performed using a solder paste inspection machine.
  • the process is to put the above-mentioned substrate with bump solder balls into the solder paste inspection machine, and inspect the bump solder balls one by one.
  • the inspection items include whether the height of the solder ball exceeds the standard, whether the diameter of the solder ball exceeds the standard, and whether the shape of the solder ball is abnormal.
  • the first and second flattening treatments of the solder joints are performed using the flattening pressure (the unit is the bulging solder ball flattening). Pressure 35-40g; Note: The same flattening pressure, 1000 ball balls are flattened once and 10000 balls are flattened once, and the height of the solder balls is different. The more the number of balls that are flattened at one time, the pressure required. It is also larger, so it is generally expressed by the pressure of a raised solder ball, that is, the unit is the flattening pressure of the raised solder ball.) The flattening pressure (in units of the raised pressure of the raised solder ball 25-30g) is higher than that of the general bump preparation.
  • the flattening pressure is related to the type of solder paste and the manufacturer, therefore, only a relative range is given here, and not all solder paste types.
  • a flat zone of larger diameter can be obtained; for example, the flat zone diameter D 2 after the first flattening is larger than the diameter D 1 of the bump flat zone after the flattening of the general product, but the height H 2 is more than H 1
  • the diameter of the solder ball is larger (ie, the height is smaller).
  • the purpose of this design is to reduce the risk of solder paste soldering in the second printing.
  • step S4 of the above preparation method the expansion and contraction coefficient of the second steel mesh is 100.01%-100.02% smaller than that of the first steel mesh; thus, after the first reflow, the substrate shrinkage becomes smaller by about 100.01. %-100.02%, reduce the shrinkage of the second stencil, so that the expansion and contraction of the second stencil can match the product's expansion and contraction during printing, so that the printed solder paste can be aligned with the first bulge. Thereby reducing the risk of tin.
  • the thickness of the second steel mesh is 2/3 of the thickness of the first steel mesh; the technical effect is that the lower tin of the second printing solder paste is lowered by reducing the thickness of the second steel mesh. the amount. Because the gap between the solder balls is reduced after the first bumping, it is easy to send if the amount of tin is too large. Raw lian tin.
  • the mesh of the second steel mesh is 10 to 20 ⁇ m smaller than that of the mesh of the first steel mesh.
  • the stencil mesh for the first printing is generally about 20-30 ⁇ m larger than the ridge pad, so the stencil mesh of the second printing is still larger than the ridge pad after being reduced by 10-20 ⁇ m.
  • the solder paste is printed, there is a gap between the steel mesh and the substrate, and the mesh does not need to be placed on the solder joint.
  • the mesh is shrunk because, because the bump has been formed for the first time, the mesh is shrunk in order to reduce the risk of shorting the solder paste during printing. The purpose of this design is twofold.
  • the mesh shrinkage can reduce the amount of tin to reduce the risk of tinning during the second printing; the second is to reduce the solder paste to the second tin after the second printing. The amount of void diffusion between the balls is reduced, and the purpose is to reduce the risk of solder paste.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

一种属于芯片锡球制备工艺以及在倒装芯片基板上小间距之间制备高凸点锡球的制备方法,步骤为:第一次锡膏印刷→第一次回流焊→助焊剂清洗→第一次锡球压平→第二次锡膏印刷→第二次回流焊→助焊剂清洗→第二次锡球压平→锡球检查。在现有锡膏印刷工法设备的基础上,通过二次印刷工艺流程,可以在焊盘的小间距之间制作出较高的凸点锡球,且芯片与基板之间的连接可靠性好,而又不需要增加新的设备投资,从而更加全面的对应客户多样化的凸点锡球高度规格要求;利用该工艺,可制作凸点锡球间距约为100~150μm、锡球高度为25~40μm的产品。

Description

一种在倒装芯片基板上小间距之间制备高凸点锡球的制备方法 技术领域
本发明涉及芯片锡球制备工艺,尤其涉及一种在倒装芯片基板上小间距之间制备高凸点锡球的制备方法。
背景技术
随着电子产品不断向多功能化、小型轻量化、高性能化的方向发展;芯片的布线越来越精细化,同时与芯片相连接的封装基板也越来越精细化。采用wire bonding(引线键合)的连接方式越来越不能满足高精度的要求。Flip Chip(倒装芯片)是比wire bonding具有更高密度连接I/O的一种连接方式;随着芯片技术的发展,封装基板上与芯片相连接的bump(隆起)凸点的密度也越来越高。
目前制作bump锡球的工艺主要有:
(1)锡膏印刷工法:在具有特定图形(钢网开口)的钢网上印刷锡膏,回流清洁后形成Bump;其优点是可以简易变更焊锡合金,可吸收SRO(solder resist opening,阻焊开窗)、MMO的偏差,可使用既有设备,可在各种形状的Pad(焊盘)上形成Bump,生产效率高,对位精度高。其缺点是有Bump void(锡球空洞)、Bump Height(隆起高度,简称bump ht)有界限。
(2)锡球工法:用在金属网板或格网涂敷助焊剂后涂锡球;之后,进行回流焊、清洁后形成Bump;其优点是可形成高Bump ht、Bump void少;其缺点是精度对位能力有限,无法吸收SRO的偏差,组成变更时污染的可能性大。
(3)SJ法(Super Jaffit):在Pad上选择性的涂敷粘着液,然后在Pad上涂锡粉,再涂助焊剂,回流清洗后形成bump;其优点是焊锡膜厚的均一性良好;缺点是焊锡的高度无法拉高,组成变更时污染的可能性大。
(4)SS工法(Super Solder):在基板上印刷Sn粉与有机酸Pb混合后的锡膏,进行回流焊及清洗后形成bump;其优点是不需要印刷精度;Pad间不发生Bridge (连锡),Bump的高度偏差小;缺点是无法对应多元系焊锡。
综合来看,锡膏印刷工法印刷对位精度高、生产效率高、可对应多样化的合金系锡膏;随着封装基板高精度连接的发展趋势,锡膏印刷工法具有更大的发展优势。但是,随着bump pitch(隆起或凸点间距)的减小,bump焊盘间的空隙减小,为了防止印刷时锡膏连桥,钢网的开口也要相应地减小;钢网开口减小以后,为了保证印刷时锡膏有很好的脱模效果,钢网的厚度也要相应地减小,综合起来,这种工艺制作出来的bump的高度随着小pitch化的发展也有减小的趋势。
在Bump高度较低的情况下,更容易出现基板与芯片连接不良的问题。因此对小间距的凸点,通过采用新的制作方法以增加bump高度,对减少芯片与基板的连接不良及连接可靠性有重要作用。
发明内容
本发明所要解决的问题在于提供一种在倒装芯片基板上小间距之间制备高凸点锡球的制备方法,该方法可以在焊盘的小间距上制备出较高凸点的焊锡球,且芯片与基板之间的连接可靠性好。
本发明的技术方案如下:
一种在倒装芯片基板上小间距之间制备高凸点锡球的制备方法,包括如下步
骤:
S1、将第一钢网置于倒装芯片的基板上,进行第一次钢网印刷,将锡膏印置于倒装芯片的基板上;
S2、将步骤S1的基板进行第一次回流焊接,在基板上形成焊接点,并在基板表面析出锡膏内的助焊剂;
S3、第一次清洗基板,去除助焊剂;
S4、将第一次清洗后的基板送入压平机中,对基板上的焊接点进行第一次压平处理,并在每一个焊接点顶端部形成一平坦区;
S5、将第二钢网置于经步骤S4平整后得到的基板上,进行第二次钢网印刷, 将锡膏印置于基板上的焊接点上;
S6、将步骤S5的基板进行第二次回流焊接,在基板上形成新焊接点,并在基板表面再次析出锡膏内的助焊剂;
S7、第二次清洗基板,去除助焊剂;
S8、将第二次清洗后的基板送入压平机中,对基板上的新焊接点再次进行第二次压平处理,并在每一个焊接点顶端部再次形成一新的平坦区;
待上述步骤结束后,得到在倒装芯片基板上小间距之间制备高凸点锡球。
上述在倒装芯片基板上小间距之间制备高凸点锡球的制备方法中,所述第二钢网的涨缩系数比第一钢网的涨缩系数小100.01-100.02%。
上述在倒装芯片基板上小间距之间制备高凸点锡球的制备方法中,所述第二钢网的厚度是第一钢网厚度的2/3。
上述在倒装芯片基板上小间距之间制备高凸点锡球的制备方法中,所述第二钢网的网孔比第一钢网网孔的小10~20μm。
本发明在现有锡膏印刷工法设备的基础上,通过二次印刷工艺流程,可以在焊盘的小间距之间制作出较高的凸点锡球,且芯片与基板之间的连接可靠性好,而又不需要增加新的设备投资,从而更加全面地对应客户多样化的凸点锡球高度规格要求;利用该工艺,可制作凸点锡球间距约为100~150μm、锡球高度为25-40μm的倒装芯片。
附图说明
图1为本发明的在倒装芯片基板上小间距之间制备高凸点锡球的制备工艺流程图;
图2为一实施例中,第一次压平后的焊接点与现有压平后的焊接点的对比效果图。
具体实施方式
为提高倒装芯片的焊接盘上小间距凸点锡球的高度,如图1所示,本发明 采用如下制作工艺:
第一次锡膏印刷→第一次回流焊→助焊剂清洗→第一次锡球压平→第二次锡膏印刷→第二次回流焊→助焊剂清洗→第二次锡球压平→锡球检查。
下面对本发明作进一步详细说明。
一种在倒装芯片基板上小间距之间制备高凸点锡球的制备方法,包括如下步骤:
S1、首先,选用第一钢网和倒装芯片的基板,且两者的规格尺寸基本相同;其次,将第一钢网置于基板上,进行第一次钢网印刷,将锡膏印置于基板上,且尽量将锡膏的厚度刷厚一点;第一钢网的网孔可以为圆形,根据焊盘设计决定,也可以其他形状,如方形、椭圆形等,孔径规格也视具体情况而定;
S2、将步骤S1的基板送入回流焊机中,进行第一次回流焊接,经第一次回流焊接后将在基板上形成球状的焊接点(也可以称为隆起凸点、凸点锡球、焊点、锡球等),并在基板表面析出锡膏内的助焊剂;
S3、进行第一次清洗基板,以便去除基板表面上锡膏析出的助焊剂;
S4、将第一次清洗后的基板送入压平机中,对基板上的焊接点进行第一次压平处理,并在每一个焊接点顶端部形成一平坦区,且该平坦区域比一般产品的平坦区大,这样的一个平坦区有利于后续第二次上锡膏并形成良好的凸点锡球,还可降低连锡风险;
S5、选用第二钢网,其大小规格与基板基本相同;将第二钢网置于经步骤S4平整后得到的基板上,进行第二次钢网印刷,将锡膏再次印置于基板上的焊接点上;第二钢网的网孔可以为圆形,根据焊盘设计决定,也可以其他形状,如方形、椭圆形等,孔径规格也视具体情况而定;
S6、将步骤S5的基板再次送入回流焊机中,进行第二次回流焊接,经第二次回流焊接后将在基板上形成新的焊接点,同时在基板表面再次析出锡膏内的助焊剂;
S7、再次清洗基板,以便第二次去除基板表面上锡膏析出的助焊剂;
S8、将第二次清洗后的基板再次送入压平机中,对基板上的新焊接点再次 进行第二次压平处理,并再次在每一个焊接点顶端部形成一新的平坦区,且第二次压平以后的锡球直径要根据客户的规格来设定,最好对准规格中心值;
待上述步骤结束后,得到在高凸点锡球,并对凸点锡球进行检查。
上述步骤中,对凸点锡球的检查,使用的是锡膏检查机检查。过程就是将上述焊接有凸点锡球的基板投入锡膏检查机,对凸点锡球逐一检查,检查项目包括锡球高度是否超标、锡球直径是否超标、锡球形状是否异常等。
下面再结合图2所示来解释一下,在上述制备方法的步骤S4中,所述的焊接点的第一、二次压平处理,其所采用的压平压力(单位为隆起锡球压平压力35-40g;注:同样的压平压力,一次压平1000个锡球跟一次压平10000个锡球,得到的锡球高度不一样;一次压平的锡球数越多,需要的压力也越大,因此一般用一个隆起锡球的压力来表示,即单位为隆起锡球压平压力)较一般凸点制备时的压平压力(单位为隆起锡球压平压力25-30g)要大;鉴于压平压力与锡膏的类型及厂家有关,因此,此处给出的只是一个相对范围,并不能包含所有的锡膏类型。这样就可以得到一个更大直径的平坦区;如,第一次压平后的平坦区直径D2比一般产品压平后凸点平坦区直径D1更大,但高度H2比H1更小;其结果就是,第一次压平后锡球直径更大(即高度小)的话,第二次印刷时,更多的锡膏可以落在锡球上而不是向锡球边上扩散;以避免因锡球边上扩散后增加锡膏连锡(短路)的风险,即这样设计的目的是降低第二次印刷时锡膏连锡的风险。
在上述制备方法的步骤S4中,第二钢网的涨缩系数比第一钢网的涨缩系数小100.01%-100.02%;这样,经过第一回流后,基板的涨缩会变小约100.01%-100.02%,减小第二张钢网的涨缩,以便印刷时第二钢网的涨缩能与产品的涨缩匹配,这样可以使印刷的锡膏对准第一次制作的隆起,从而降低连锡的风险。
在上述制备方法的步骤S4中,第二钢网的厚度是第一钢网厚度的2/3;其技术效果就是,通过降低第二钢网的厚度以降低第二次印刷锡膏的下锡量。因为经过第一次隆起的制作,锡球间的间隙减小,如果下锡量太大的话很容易发 生连锡。
在上述制备方法的步骤S4中,第二钢网的网孔比第一钢网网孔的小10~20μm。第一次印刷的钢网网孔一般比隆起焊盘大20-30μm左右,所以第二次印刷的钢网网孔缩小10-20μm后仍然比隆起焊盘大。另外,锡膏印刷的时候钢网与基板是有间隙的,网孔并不需要套在焊点上。缩小网孔是因为,由于第一次bump已经形成,为了降低印刷时锡膏短路的风险,将网孔缩小。这样设计的目的有两点,一是网孔缩小可以缩小下锡量从而降低第二次印刷时连锡的风险;二是减小网孔以后,第二次印刷时的锡膏向两个锡球间的空隙扩散的量会减少,目的也是降低锡膏连锡的风险。

Claims (4)

  1. 一种在倒装芯片基板上小间距之间制备高凸点锡球的制备方法,其特征在于,包括如下步骤:
    S1、将第一钢网置于倒装芯片的基板上,进行第一次钢网印刷,将锡膏印置于倒装芯片的基板上;
    S2、将步骤S1的基板进行第一回流焊接,在基板上形成焊接点,并在基板表面析出锡膏内的助焊剂;
    S3、第一次清洗基板,去除助焊剂;
    S4、将第一清洗后的基板送入压平机中,对基板上的焊接点进行第一次压平处理,并在每一个焊接点顶端部形成一平坦区;
    S5、将第二钢网置于经步骤S4平整后得到的基板上,进行第二次钢网印刷,将锡膏印置于基板上的焊接点上;
    S6、将步骤S5的基板进行第二次回流焊接,在基板上形成新焊接点,并在基板表面再次析出锡膏内的助焊剂;
    S7、第二次清洗基板,去除助焊剂;
    S8、将第二次清洗后的基板再次送入压平机中,对基板上的新焊接点再次进行第二次压平处理,并在每一个焊接点顶端部再次形成一新的平坦区;
    待上述步骤结束后,得到所述高凸点锡球。
  2. 根据权利要求1所述的在倒装芯片基板上小间距之间制备高凸点锡球的制备方法,其特征在于,所述第二钢网的涨缩系数比第一钢网的涨缩系数小100.01%~100.02%。
  3. 根据权利要求1所述的在倒装芯片基板上小间距之间制备高凸点锡球的制备方法,其特征在于,所述第二钢网的厚度是第一钢网厚度的2/3。
  4. 根据权利要求1所述的在倒装芯片基板上小间距之间制备高凸点锡球的制备方法,其特征在于,所述第二钢网的网孔比第一钢网网孔的小10~20μm。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114880853A (zh) * 2022-05-09 2022-08-09 江西兆驰半导体有限公司 一种刷锡工艺的钢网厚度确定方法及系统
CN114880853B (zh) * 2022-05-09 2024-05-28 江西兆驰半导体有限公司 一种刷锡工艺的钢网厚度确定方法及系统

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104599978B (zh) * 2014-12-31 2017-08-01 广州兴森快捷电路科技有限公司 一种在倒装芯片基板上小间距之间制备高凸点锡球的制备方法
CN105562863B (zh) * 2016-02-02 2019-02-26 青岛歌尔声学科技有限公司 一种器件焊接方法
CN106847772B (zh) * 2016-12-20 2019-12-20 中国电子科技集团公司第五十八研究所 用于陶瓷外壳的无助焊剂倒装焊方法
CN107347232A (zh) * 2017-08-10 2017-11-14 乐依文半导体(东莞)有限公司 固定晶圆的表面粘贴方法、smt印刷钢网及晶圆固定装置
CN107346748B (zh) * 2017-08-10 2023-11-21 联测优特半导体(东莞)有限公司 固定晶圆的表面粘贴方法及smt晶圆固定装置
US10790261B2 (en) * 2018-03-12 2020-09-29 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding through multi-shot laser reflow
CN112331619B (zh) * 2020-11-04 2023-08-15 华天科技(南京)有限公司 一种重力磁感应芯片侧装结构及提升侧装良率的方法
CN115302121B (zh) * 2022-07-26 2024-02-27 德中(天津)技术发展股份有限公司 一种印制电路板可焊性测试的回流焊试验方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101217135A (zh) * 2008-01-02 2008-07-09 友达光电股份有限公司 薄膜覆晶封装结构
CN103474367A (zh) * 2013-09-27 2013-12-25 江阴长电先进封装有限公司 一种芯片的微凸点封装结构的成形方法
CN104599978A (zh) * 2014-12-31 2015-05-06 广州兴森快捷电路科技有限公司 一种在倒装芯片基板上小间距之间制备高凸点锡球的制备方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06204322A (ja) * 1991-11-12 1994-07-22 Nec Corp 基板位置合せ装置
JPH0883799A (ja) * 1994-09-12 1996-03-26 Toshiba Corp はんだバンプの形成方法
JPH11145176A (ja) * 1997-11-11 1999-05-28 Fujitsu Ltd ハンダバンプの形成方法及び予備ハンダの形成方法
JP2001230537A (ja) * 2000-02-17 2001-08-24 Ngk Spark Plug Co Ltd ハンダバンプの形成方法
US10388626B2 (en) * 2000-03-10 2019-08-20 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming flipchip interconnect structure
JP3631230B2 (ja) * 2002-11-21 2005-03-23 富士通株式会社 予備ハンダの形成方法
CN101408688B (zh) * 2003-03-31 2011-10-12 德塞拉互连材料股份有限公司 布线电路基板、布线电路基板的制造方法和电路模块
US20100029074A1 (en) * 2008-05-28 2010-02-04 Mackay John Maskless Process for Solder Bump Production
JP5649805B2 (ja) * 2009-08-12 2015-01-07 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
CN102339759B (zh) * 2011-10-24 2012-12-26 深南电路有限公司 一种倒装基板的植球方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101217135A (zh) * 2008-01-02 2008-07-09 友达光电股份有限公司 薄膜覆晶封装结构
CN103474367A (zh) * 2013-09-27 2013-12-25 江阴长电先进封装有限公司 一种芯片的微凸点封装结构的成形方法
CN104599978A (zh) * 2014-12-31 2015-05-06 广州兴森快捷电路科技有限公司 一种在倒装芯片基板上小间距之间制备高凸点锡球的制备方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114880853A (zh) * 2022-05-09 2022-08-09 江西兆驰半导体有限公司 一种刷锡工艺的钢网厚度确定方法及系统
CN114880853B (zh) * 2022-05-09 2024-05-28 江西兆驰半导体有限公司 一种刷锡工艺的钢网厚度确定方法及系统

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