WO2016103536A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- WO2016103536A1 WO2016103536A1 PCT/JP2015/003933 JP2015003933W WO2016103536A1 WO 2016103536 A1 WO2016103536 A1 WO 2016103536A1 JP 2015003933 W JP2015003933 W JP 2015003933W WO 2016103536 A1 WO2016103536 A1 WO 2016103536A1
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- Prior art keywords
- electrode block
- region
- electrode
- bump
- submount
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 159
- 229910052751 metal Inorganic materials 0.000 claims abstract description 105
- 239000002184 metal Substances 0.000 claims abstract description 105
- 239000000463 material Substances 0.000 claims description 32
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 13
- 239000010931 gold Substances 0.000 claims description 13
- 229910052737 gold Inorganic materials 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 description 18
- 238000000034 method Methods 0.000 description 16
- 239000011810 insulating material Substances 0.000 description 8
- 238000000605 extraction Methods 0.000 description 7
- 229910000679 solder Inorganic materials 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 239000004642 Polyimide Substances 0.000 description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 229920001721 polyimide Polymers 0.000 description 5
- 238000003825 pressing Methods 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000000945 filler Substances 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 239000000919 ceramic Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000005304 joining Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- 229910001182 Mo alloy Inorganic materials 0.000 description 1
- 229910001080 W alloy Inorganic materials 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- WUUZKBJEUBFVMV-UHFFFAOYSA-N copper molybdenum Chemical compound [Cu].[Mo] WUUZKBJEUBFVMV-UHFFFAOYSA-N 0.000 description 1
- SBYXRAKIOMOBFF-UHFFFAOYSA-N copper tungsten Chemical compound [Cu].[W] SBYXRAKIOMOBFF-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
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- H—ELECTRICITY
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/16235—Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/022—Mountings; Housings
- H01S5/0233—Mounting configuration of laser chips
- H01S5/02345—Wire-bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/022—Mountings; Housings
- H01S5/0235—Method for mounting laser chips
- H01S5/02355—Fixing laser chips on mounts
- H01S5/0237—Fixing laser chips on mounts by soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/024—Arrangements for thermal management
- H01S5/02476—Heat spreaders, i.e. improving heat flow between laser chip and heat dissipating elements
- H01S5/02492—CuW heat spreaders
Definitions
- the present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device including a semiconductor element that generates a large amount of heat.
- a current flowing through the semiconductor element has increased, and accordingly, the amount of heat generated from the semiconductor element has increased.
- a high-power semiconductor laser device used for laser processing has a large current flowing through the mounted semiconductor laser element in order to obtain a high-power laser beam, and accordingly, the semiconductor laser element generates a large amount of heat.
- the semiconductor laser device has a cooling function for releasing heat from both sides of the semiconductor laser element.
- FIG. 18 is a perspective view and a side view of a conventional semiconductor laser device 900.
- a conventional semiconductor laser device 900 is provided with a submount 902 and an LD (Laser Diode) bar 903 on the end of a heat sink 901.
- An insulating layer 904 is provided in a region on the heat sink 901 where the submount 902 is not provided.
- a bump 905 is formed on the LD bar 903, and an extraction electrode 906 is provided on the insulating layer 904 and the bump 905. Further, between the LD bar 903 and the extraction electrode 906, a filler 907 is filled in a space where the bump 905 does not exist.
- a filler 907 made of Ag paste or a solder material is filled between the LD bar 903 and the extraction electrode 906 to improve thermal conductivity.
- the space between the LD bar 903 and the extraction electrode 906 is filled with Ag paste or a solder material, the interface between the extraction electrode 906 and the filler 907 or the filling due to the difference in thermal expansion coefficient between the LD bar 903 and the extraction electrode 906.
- a semiconductor device includes a first electrode block, a submount, an insulating layer, a semiconductor element, a bump, and a second electrode block.
- the first electrode block has conductivity.
- the submount is provided in the first region on the upper surface of the first electrode block, is electrically connected to the first electrode block, and has conductivity.
- the insulating layer is provided in a second region different from the first region on the upper surface of the first electrode block.
- the semiconductor element has a first electrode provided on the submount and electrically connected to the submount.
- the bump is provided on the upper surface of the second electrode opposite to the first electrode of the semiconductor element, is electrically connected to the second electrode, and has conductivity.
- the second electrode block is provided on the bump and the insulating layer and has conductivity. Further, the lower surface of the second electrode block is electrically connected to the bump via a conductive metal layer in the third region. The lower surface of the second electrode block is mounted on the insulating layer in the fourth region. In addition, a conductive metal sheet is provided between the metal layer and the bump.
- the present disclosure alleviates stress due to the difference in thermal expansion coefficient between the semiconductor element and the second electrode block by providing a metal layer and a metal sheet between the bump and the second electrode block.
- the electrical connection between the semiconductor element and the second electrode block can be secured stably.
- FIG. 1 is a cross-sectional view showing a schematic configuration of a semiconductor laser device 1 according to the first embodiment.
- FIG. 2 is a perspective view showing a method for manufacturing the semiconductor laser device 1 according to the first embodiment.
- FIG. 3 is a perspective view showing a method for manufacturing the semiconductor laser device 1 according to the first embodiment.
- FIG. 4 is a perspective view showing a method for manufacturing the semiconductor laser device 1 according to the first embodiment.
- FIG. 5 is a perspective view showing a method for manufacturing the semiconductor laser device 1 according to the first embodiment.
- FIG. 6 is a perspective view showing a method for manufacturing the semiconductor laser device 1 according to the first embodiment.
- FIG. 7 is a perspective view showing a method for manufacturing the semiconductor laser device 1 according to the first embodiment.
- FIG. 8 is a cross-sectional view showing a schematic configuration of power semiconductor device 2 in the second embodiment.
- FIG. 9 is a perspective view showing a method for manufacturing power semiconductor device 2 in the second embodiment.
- FIG. 10 is a perspective view showing a method for manufacturing power semiconductor device 2 in the second embodiment.
- FIG. 11 is a perspective view showing a method for manufacturing power semiconductor device 2 in the second embodiment.
- FIG. 12 is a perspective view showing a method for manufacturing power semiconductor device 2 in the second embodiment.
- FIG. 13 is a perspective view showing a method for manufacturing power semiconductor device 2 in the second embodiment.
- FIG. 14 is a perspective view showing a method for manufacturing power semiconductor device 2 in the second embodiment.
- FIG. 15 is a cross-sectional view showing a schematic configuration of the semiconductor laser device 3 according to the third embodiment.
- FIG. 16 is a perspective view showing a schematic configuration of the semiconductor laser apparatus 3 according to the third embodiment.
- FIG. 17 is a cross-sectional view showing a schematic configuration of power semiconductor device 4 in the fourth embodiment.
- FIG. 18 is a diagram showing a schematic configuration (a perspective view and a side view) of a conventional semiconductor laser device 900.
- FIG. 1 is a cross-sectional view showing a schematic configuration of a semiconductor laser device 1 according to the present embodiment.
- 2 to 7 are perspective views showing a method of manufacturing the semiconductor laser device 1 according to the present embodiment.
- a semiconductor laser device 1 semiconductor device includes an electrode block 10 (first electrode block), a submount 20, an insulating layer 30, a semiconductor laser element 40 (semiconductor element), and bumps. 50 and an electrode block 60 (second electrode block). Further, a metal sheet 70 and a metal layer 80 are provided between the bump 50 and the electrode block 60 in order from the bump 50 side.
- the electrode block 10 has conductivity, the main material is copper (Cu), and nickel (Ni) and gold (Au) are plated on the copper block in this order.
- a recess 11 is provided at an end of the upper surface of the electrode block 10
- a submount 20 is provided in a region (first region) in the recess 11, and the recess 11 of the electrode block 10 is provided.
- An insulating layer 30 is provided in the upper surface region (second region) other than. That is, the insulating layer 30 surrounds the recess 11 in a U shape (see FIGS. 2 to 5). Further, the upper surface of the recess 11 is positioned lower than the upper surface other than the recess 11.
- the submount 20 has conductivity, and the main material is copper tungsten alloy (CuW). As shown in FIG. 1, the submount 20 is arranged in a region in the recess 11 so that the side surface of the electrode block 10 and the side surface of the submount 20 coincide.
- the submount 20 is electrically connected to the electrode block 10, and the electrode block 10 is a solder material (not shown) containing 96.5% tin (Sn) and 3.5% silver (Ag). Z)).
- the main material of the submount 20 may be a copper molybdenum alloy (CuMo).
- the insulating layer 30 has an insulating property, and the main material is polyimide or ceramic. As shown in FIG. 1, the electrode block 10 is provided on the upper surface other than the recess 11. In this embodiment, the insulating layer 30 is divided into two layers, ie, the insulating layer 31 and the insulating layer 32. However, the number may be one.
- the main material of the insulating layer 31 is polyimide
- the main material of the insulating layer 32 is aluminum nitride (AlN).
- the lower surface of the semiconductor laser element 40 is a positive electrode 41 (first electrode), and the upper surface is a negative electrode 42 (second electrode).
- the semiconductor laser element 40 When a current flows from the positive electrode 41 toward the negative electrode 42, the semiconductor laser element 40 outputs laser light from the light emitting surface (left side in FIG. 1).
- the semiconductor laser element 40 is disposed on the submount 20 so that the light emitting surface of the semiconductor laser element 40 coincides with the side surface of the submount 20.
- the positive electrode 41 of the semiconductor laser element 40 is electrically connected to the submount 20, and is bonded to the submount 20 by a solder material (not shown) containing 80% gold and 20% tin. ing.
- the bump 50 has conductivity and the main material is gold. As shown in FIG. 1, a plurality of bumps 50 are provided on the negative electrode 42 of the semiconductor laser element 40 and are electrically connected to the negative electrode 42 of the semiconductor laser element 40. The height of the bump 50 is about 80 ⁇ m to about 120 ⁇ m.
- the metal sheet 70 has conductivity and the main material is gold.
- the metal sheet 70 is a stack of 3 to 4 metal foils having a thickness of about 8 ⁇ m to about 12 ⁇ m, and the total thickness is about 24 ⁇ m to about 48 ⁇ m.
- the number of metal sheets 70 and the overall thickness are not limited to this.
- the metal sheet 70 is provided on the bump 50 so that the upper end of the bump 50 bites in, and is electrically connected to the bump 50.
- the tip of the bump 50 is provided by biting into the metal sheet 70, but the tip of the bump 50 is bitten into the metal sheet 70 and physically contacted without being chemically bonded (bonded) to the metal sheet 70. It is preferable. Thereby, even with respect to the difference in thermal expansion coefficient between the semiconductor laser element 40 and the electrode block 60, the bump 50 can move so as to push the metal sheet 70 in the horizontal plane direction, and the stress can be relieved.
- the metal layer 80 has conductivity and the main material is gold.
- the thickness of the metal layer 80 is about 50 ⁇ m to about 100 ⁇ m.
- the metal layer 80 is provided on the metal sheet 70 and is electrically connected to the metal sheet 70. Moreover, it is preferable that the surfaces of the metal layer 80 are in physical contact with each other without being chemically bonded (bonded) to the metal sheet 70. Thereby, even with respect to the difference in thermal expansion coefficient between the semiconductor laser element 40 and the electrode block 60, the metal sheet 70 can move along the metal layer 80 so as to be displaced in the horizontal plane direction, and the stress can be relaxed.
- the electrode block 60 is conductive, the main material is copper (Cu), and nickel (Ni) and gold (Au) are plated on the copper block in this order.
- the electrode block 60 is provided on the metal layer 80 and the insulating layer 30 and is electrically connected to the metal layer 80.
- the metal layer 80 is provided on the lower surface of the electrode block 60 and in a region facing the semiconductor laser element 40 (third region).
- the metal layer 80 is provided by pressing a thin metal plate having a thickness of about 50 ⁇ m to 100 ⁇ m to the electrode block 60.
- the metal layer 80 is not limited to this, and the metal layer 80 may be plated and grown on the lower surface of the electrode block 60 in a region facing the semiconductor laser element 40 with a thickness of about 50 ⁇ m to about 100 ⁇ m.
- the electrode block 60 is bonded to the insulating layer 30 in a region (fourth region) other than the region facing the semiconductor laser element 40 on the lower surface of the electrode block 60.
- the depth (height) of the recess 11 is set in consideration of the thicknesses of the submount 20, the semiconductor laser element 40, the bump 50, the metal sheet 70, the metal layer 80, and the insulating layer 30.
- the depth (height) of the recess 11 is, for example, the sum of the thicknesses of the submount 20, the semiconductor laser element 40, the bump 50, and the metal layer 80. In other words, the thickness of the insulating layer 30 is reduced.
- FIGS. 2 to 7 are perspective views showing a method for manufacturing the semiconductor laser device 1 of the present embodiment.
- the submount 20 on which the semiconductor laser element 40 is mounted is mounted in the recess 11 of the electrode block 10.
- the semiconductor laser element 40 is bonded to the submount 20 with a solder material containing gold and tin so that the positive electrode 41 is connected to the submount 20.
- the submount 20 is a little larger than the semiconductor laser element 40.
- the semiconductor laser element 40 is disposed so that the light emitting surface is flush with the side surface of the submount 20, and the other side surface of the semiconductor laser element 40 is disposed more inside than the side surface of the submount 20.
- the submount 20 is bonded to the recess 11 of the electrode block 10 with a solder material containing tin and silver.
- the recess 11 is formed larger than the submount 20.
- the submount 20 is disposed so that the light emitting surface of the semiconductor laser element 40 is flush with the side surface of the electrode block 10, and the other side surface of the submount 20 is disposed more inside than the side surface of the recess 11. .
- the electrode block 10 is provided with connection holes 12 on both sides of the recess 11 in which the semiconductor laser element 40 is disposed, and the connection hole 13 is provided on the opposite side of the connection hole 12 with respect to the laser beam emission direction. It has been. Further, a terminal hole 14 for connecting a wiring connected to a power source is provided at the end of the electrode block 10 opposite to the recess 11.
- the connection hole 12, the connection hole 13, and the terminal hole 14 are threaded on the inner side surface so as to be fastened with screws.
- a plurality of bumps 50 are formed on the negative electrode 42 of the semiconductor laser element 40.
- the bump 50 is bonded to the negative electrode 42 by bringing a gold wire having a spherical tip by melting into contact with the negative electrode 42 and applying ultrasonic waves. Then, by pulling the gold wire while applying an ultrasonic wave, the bump 50 having a sharp upper end is formed.
- an insulating layer 31 and an insulating layer 32 are formed on the upper surface of the electrode block 10 other than the recess 11.
- the insulating layer 31 is preferably made of, for example, an insulating material mainly made of polyimide and having little deformation (hard). Thereby, the electrode block 60 can be stabilized above the semiconductor laser element 40.
- the insulating layer 32 is preferably made of a soft insulating material mainly made of, for example, aluminum nitride and having high thermal conductivity. Thereby, the adhesiveness between the electrode block 60 and the insulating layer 32 is increased, and heat is easily conducted to the electrode block 10.
- the insulating layer 31 is a material harder than the insulating layer 32
- the insulating layer 32 is a material having a higher thermal conductivity than the insulating layer 31.
- a metal layer 80 is formed on the lower surface of the electrode block 60 and on the portion facing the semiconductor laser element 40.
- the metal layer 80 is formed by pressing a metal plate to the electrode block 60, but may be formed by metal plating growth.
- a metal sheet 70 is placed on the bump 50.
- a connection hole 61 is provided at a position corresponding to the connection hole 12 of the electrode block 10
- a connection hole 62 is provided at a position corresponding to the connection hole 13 of the electrode block 10.
- a terminal hole 63 for connecting a wiring connected to a power source is provided at the center of the electrode block 60.
- the connection hole 61, the connection hole 62, and the terminal hole 63 are threaded on the inner side surface so as to be fastened with screws.
- the electrode block 60 provided with the metal layer 80 is mounted on the electrode block 10 provided with the submount 20, the insulating layer 30, the semiconductor laser element 40, and the bump 50. At this time, the metal sheet 70 placed on the bump 50 is sandwiched between the bump 50 and the metal layer 80.
- the electrode block 10 and the electrode block 60 are integrated by a joining member. Specifically, the connection hole 12 of the electrode block 10 and the connection hole 61 of the electrode block 60 are connected by an insulating screw 90. Further, the connection hole 13 of the electrode block 10 and the connection hole 62 of the electrode block 60 are connected by the conductive screw 91. An insulating member 92 is provided between the conductive screw 91 and the electrode block 60. That is, the electrode block 10 and the electrode block 60 are not electrically connected by the insulating screw 90 or the insulating member 92.
- the conductive screw 91 and the insulating member 92 may be used, and instead of the conductive screw 91 and the insulating member 92, the insulating screw 90 may be used.
- the insulating screw 90 and the insulating member 92 are made of an insulating material mainly made of ceramic or resin.
- the semiconductor laser device 1 is completed as shown in FIG. 7 corresponds to the cross-sectional view in FIG.
- FIG. 8 is a cross-sectional view showing a schematic configuration of the power semiconductor device 2 in the present embodiment.
- 9 to 14 are perspective views showing a method for manufacturing the power semiconductor device 2 in the present embodiment.
- the semiconductor laser element 40 that outputs laser light is used as the semiconductor element, and the semiconductor laser element 40 and the submount 20 are mounted on the end of the upper surface of the electrode block 10.
- the power semiconductor element 140 is used as the semiconductor element, and the power semiconductor element 140 and the submount 20 are mounted at the center of the upper surface of the electrode block 110.
- the power semiconductor device 2 includes an electrode block 110 (first electrode block), a submount 20, an insulating layer 130, a power semiconductor element 140 (semiconductor element), and a bump. 50 and an electrode block 160 (second electrode block). Further, a metal sheet 70 and a metal layer 80 are provided between the bump 50 and the electrode block 160 in order from the bump 50 side. Since the submount 20, the bump 50, the metal sheet 70, and the metal layer 80 are the same as those in the first embodiment, the description thereof is omitted.
- the electrode block 110 has conductivity, and the material is the same as in the first embodiment.
- a recess 111 is provided in the center of the upper surface of the electrode block 110, and the submount 20 is provided in a region (first region) in the recess 111.
- An insulating layer 130 is provided in the upper surface region (second region) other than. That is, the insulating layer 130 surrounds the entire periphery of the recess 111 (see FIGS. 9 to 12).
- the upper surface of the recess 111 is positioned lower than the upper surface other than the recess 111.
- the insulating layer 130 has insulating properties, and the main material is polyimide. As shown in FIG. 8, the electrode block 110 is provided on the upper surface other than the recess 111.
- the power semiconductor element 140 is a power diode to which a high voltage of 60 V or more is input, the lower surface is a positive electrode 141 (first electrode), and the upper surface is a negative electrode 142 (second electrode). In the power semiconductor element 140, a current flows from the positive electrode 141 toward the negative electrode 142, and no current flows from the negative electrode 142 to the positive electrode 141. As shown in FIG. 8, the power semiconductor element 140 is disposed at the center of the submount 20 so that the side surface of the power semiconductor element 140 is located inside the side surface of the submount 20.
- the positive electrode 141 of the power semiconductor element 140 is electrically connected to the submount 20 and is bonded to the submount 20 by a solder material (not shown) containing 80% gold and 20% tin. Yes.
- the electrode block 160 has conductivity, and the material is the same as in the first embodiment. As shown in FIG. 8, the electrode block 160 is provided on the metal layer 80 and the insulating layer 130 and is electrically connected to the metal layer 80. The metal layer 80 is provided on the lower surface of the electrode block 160 and in a region facing the power semiconductor element 140 (third region). The metal layer 80 is provided by pressing a thin metal plate having a thickness of about 50 ⁇ m to 100 ⁇ m to the electrode block 160. The metal layer 80 is not limited to this, and a metal may be plated and grown on the lower surface of the electrode block 160 and in a region facing the power semiconductor element 140 with a thickness of about 50 ⁇ m to about 100 ⁇ m. The electrode block 160 is bonded to the insulating layer 130 in a region (fourth region) other than the region facing the power semiconductor element 140 on the lower surface of the electrode block 160.
- the depth (height) of the recess 111 may be set in the same manner as in the first embodiment by using the semiconductor laser element 40 as the power semiconductor element 140 and the insulating layer 30 as the insulating layer 130.
- FIGS. 9 to 14 are perspective views showing a method for manufacturing the power semiconductor device 2 of the present embodiment.
- the submount 20 on which the power semiconductor element 140 is mounted is mounted in the recess 111 of the electrode block 110.
- the semiconductor laser element 40 in the first embodiment is a power semiconductor element 140 in the present embodiment.
- the concave portion 11 is formed at the end of the electrode block 10 in the first embodiment, whereas the concave portion 111 is formed at the central portion of the electrode block 110 in the present embodiment. The other points are the same as in the first embodiment.
- a plurality of bumps 50 are formed on the negative electrode 142 of the power semiconductor element 140.
- the formation of the bump is the same as in the first embodiment.
- an insulating layer 130 is formed on the upper surface of the electrode block 110 other than the recess 111. Further, a metal layer 80 is formed on the lower surface of the electrode block 160 on the portion facing the power semiconductor element 140. In the present embodiment, the metal layer 80 is formed by press-bonding a metal plate to the electrode block 160, but it may be formed by metal plating growth. A metal sheet 70 is placed on the bump 50. The other points are the same as in the first embodiment.
- the electrode block 110 on which the submount 20, the insulating layer 130, the power semiconductor element 140, and the bump 50 are provided is provided with a metal layer 80 (not shown because it cannot be seen).
- a block 160 is mounted. At this time, the metal sheet 70 placed on the bump 50 is sandwiched between the bump 50 and the metal layer 80.
- the electrode block 110 and the electrode block 160 are integrated by a joining member. This is the same as in the first embodiment.
- FIG. 14 A cross section taken along line VIII-VIII in FIG. 14 corresponds to the cross sectional view in FIG.
- FIG. 15 is a cross-sectional view showing a schematic configuration of the semiconductor laser device 3 in the present embodiment.
- FIG. 16 is a perspective view showing a schematic configuration of the semiconductor laser apparatus 3 in the present embodiment.
- the recess 11 is provided on the upper surface of the electrode block 10 on which the submount 20 is mounted, and the lower surface of the opposing electrode block 60 is a flat surface.
- the upper surface of the electrode block 210 on which the submount 20 is mounted is a flat surface
- the concave portion 261 is provided on the lower surface of the opposing electrode block 260.
- the semiconductor laser device 3 includes an electrode block 210 (first electrode block), a submount 20, an insulating layer 30, a semiconductor laser element 40 (semiconductor element), and a bump. 50 and an electrode block 260 (second electrode block). Further, a metal sheet 70 and a metal layer 80 are provided between the bump 50 and the electrode block 260 in order from the bump 50 side. Since the submount 20, the insulating layer 30, the semiconductor laser element 40, the bump 50, the metal sheet 70, and the metal layer 80 are the same as those in the first embodiment, the description thereof is omitted.
- the electrode block 210 has conductivity, and the material is the same as in the first embodiment.
- the upper surface of the electrode block 210 is a plane
- the submount 20 is provided in the end region (first region)
- the upper surface region (second region) other than the end portion of the electrode block 210 is provided.
- the insulating layer 30 is provided in the region.
- the insulating layer 30 may also be divided into the insulating layer 31 and the insulating layer 32 as in the first embodiment, and the materials of the insulating layers 30 to 32 are the same as in the first embodiment.
- the electrode block 260 has conductivity, and the material is the same as in the first embodiment. As shown in FIG. 15, the electrode block 260 is provided on the metal layer 80 and the insulating layer 30 and is electrically connected to the metal layer 80. A recess 261 is provided at the end of the lower surface of the electrode block 260, and a metal layer 80 is provided in the recess 261 in a region (third region) facing the semiconductor laser element 40. A region (fourth region) on the lower surface other than the concave portion 261 of the electrode block 260 is bonded to the insulating layer 30. That is, the lower surface of the recess 261 is positioned higher than the lower surface other than the recess 261.
- the metal layer 80 is provided by pressing a thin metal plate having a thickness of about 50 ⁇ m to 100 ⁇ m to the electrode block 260.
- the metal layer 80 is not limited to this, and the metal layer 80 may be formed by plating and growing a metal with a thickness of about 50 ⁇ m to about 100 ⁇ m in the recess 261 on the lower surface of the electrode block 260 and facing the semiconductor laser element 40. good.
- the depth (height) of the recess 261 may be set in the same manner as in the first embodiment.
- FIG. 17 is a cross-sectional view showing a schematic configuration of the power semiconductor device 4 in the present embodiment.
- the concave portion 111 is provided on the upper surface of the electrode block 110 on which the submount 20 is mounted, and the lower surface of the opposing electrode block 160 is a flat surface.
- the upper surface of the electrode block 310 on which the submount 20 is mounted is a flat surface
- the concave portion 361 is provided on the lower surface of the opposing electrode block 360.
- the power semiconductor device 4 includes an electrode block 310 (first electrode block), a submount 20, an insulating layer 130, a power semiconductor element 140 (semiconductor element), and a bump. 50 and an electrode block 360 (second electrode block). Further, a metal sheet 70 and a metal layer 80 are provided between the bump 50 and the electrode block 360 in order from the bump 50 side. Since the submount 20, the insulating layer 130, the power semiconductor element 140, the bump 50, the metal sheet 70, and the metal layer 80 are the same as those in the second embodiment, the description thereof is omitted.
- the electrode block 310 has conductivity, and the material is the same as that of the second embodiment.
- the upper surface of the electrode block 310 is a flat surface
- the submount 20 is provided in the central region (first region), and the upper surface region (second region) other than the central portion of the electrode block 310.
- an insulating layer 130 is provided in the region.
- the insulating layer 130 is the same as that in the second embodiment.
- the electrode block 360 has conductivity, and the material is the same as that of the second embodiment. As shown in FIG. 17, the electrode block 360 is provided on the metal layer 80 and the insulating layer 130 and is electrically connected to the metal layer 80. A recess 361 is provided at the center of the lower surface of the electrode block 360, and a metal layer 80 is provided in the recess 361 in a region (third region) facing the power semiconductor element 140. A region (fourth region) on the lower surface other than the recess 361 of the electrode block 360 is bonded to the insulating layer 130. That is, the lower surface of the recess 361 is positioned higher than the lower surfaces other than the recess 361.
- the metal layer 80 is provided by pressing a thin metal plate having a thickness of about 50 ⁇ m to 100 ⁇ m to the electrode block 360.
- the metal layer 80 is not limited to this, and the metal layer 80 may be formed by plating and growing a metal with a thickness of about 50 ⁇ m to about 100 ⁇ m in the recess 361 on the lower surface of the electrode block 360 and facing the power semiconductor element 140. good.
- the depth (height) of the recess 361 may be set in the same manner as in the second embodiment.
- the insulating layer 31 is made of an insulating material such as polyimide or ceramic that is relatively less deformed by pressure
- the insulating layer 32 is made of a relatively soft insulating material such as aluminum nitride. Material was used. Due to the difference in hardness of the insulating material, the electrode block 60 (260) may be inclined. That is, the side on which the semiconductor laser element 40 is mounted (insulating layer 31 side) may float upward, and the opposite side (insulating layer 32 side) may sink downward.
- a spacer is provided on the lower surface of the electrode block 60 (260) on the side opposite to the semiconductor laser element 40.
- the spacer may be a relatively hard insulating material, or may be covered with an insulating material in a shape in which the lower surface of the electrode block 60 (260) is protruded.
- the upper and lower electrode blocks are fixed by the insulating screw 90, the conductive screw 91 and the insulating member 92 using the connection holes 12, 13, 61 and 62.
- the upper and lower electrode blocks may be fixed by bonding the insulating layers 30 and 130, or the upper and lower blocks may be fixed using another adhesive.
- the negative electrode 42 (142) and the metal layer 80 are connected by causing the bump 50 to bite into the metal sheet 70, but the negative electrode 42 (142) is connected only by the metal sheet 70. And the metal layer 80 may be connected.
- the semiconductor laser element 40 and the power semiconductor element 140 may have the positive electrode 41 (141) on the top and the negative electrode 42 (142) on the bottom.
- the stress due to the difference in expansion coefficient between the semiconductor element and the second electrode block is reduced, and the semiconductor
- the electrical connection between the element and the second electrode block can be secured stably, and is industrially useful as a semiconductor device using a high current.
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Abstract
Description
以下、本開示の実施の形態1について、図1~図7を用いて説明する。
次に、本開示の実施の形態2について、図8~図14を用いて説明する。なお、実施の形態1と共通する構成については同じ符号を付し、説明を省略する。図8は、本実施の形態におけるパワー半導体装置2の概略構成を示す断面図である。図9~図14は、本実施の形態におけるパワー半導体装置2の製造方法を示す斜視図である。
次に、本開示の実施の形態3について、図15および図16を用いて説明する。なお、実施の形態1と共通する構成については同じ符号を付し、説明を省略する。図15は、本実施の形態における半導体レーザ装置3の概略構成を示す断面図である。図16は、本実施の形態における半導体レーザ装置3の概略構成を示す斜視図である。
次に、本開示の実施の形態4について、図14および図17を用いて説明する。なお、実施の形態2と共通する構成については同じ符号を付し、説明を省略する。図17は、本実施の形態におけるパワー半導体装置4の概略構成を示す断面図である。
次に実施の形態1および3の変形例について説明する。実施の形態1および3では、絶縁層31の材料として、ポリイミドやセラミックなどの比較的、圧力による変形の少ない絶縁性材料を用い、絶縁層32の材料として、窒化アルミニウムなどの比較的柔らかい絶縁性材料を用いた。この絶縁性材料の固さの差から、電極ブロック60(260)が傾く恐れがある。すなわち、半導体レーザ素子40が搭載された側(絶縁層31側)が上方に浮きあがり、反対側(絶縁層32側)が下方に沈み込む恐れがある。本変形例では、電極ブロック60(260)の下面であって、半導体レーザ素子40とは反対側にスペーサを設ける。スペーサとしては、比較的固い絶縁性材料でもよく、電極ブロック60(260)の下面を突出させた形状として絶縁性材料で被覆しても構わない。
2,4 パワー半導体装置
10,60,110,160,210,260,310,360 電極ブロック
11,111,261,361 凹部
12,13,61,62 接続孔
14,63 端子孔
20 サブマウント
30,31,32,130 絶縁層
40 半導体レーザ素子
41,141 正電極
42,142 負電極
50 バンプ
70 金属シート
80 金属層
90 絶縁性ネジ
91 導電性ネジ
92 絶縁部材
140 パワー半導体素子
900 半導体レーザ装置
901 ヒートシンク
902 サブマウント
903 LDバー
904 絶縁層
905 バンプ
906 電極
907 充填材
Claims (10)
- 導電性を有する第1の電極ブロックと、
前記第1の電極ブロックの上面の第1の領域に設けられ、前記第1の電極ブロックと電気的に接続され、導電性を有するサブマウントと、
前記第1の電極ブロックの上面であって、前記第1の領域とは異なる第2の領域に設けられた絶縁層と、
前記サブマウントの上に設けられ、前記サブマウントと電気的に接続された第1の電極を有する半導体素子と、
前記半導体素子の前記第1の電極とは反対側の第2の電極の上面に設けられ、前記第2の電極と電気的に接続され、導電性を有するバンプと、
前記バンプおよび前記絶縁層の上に設けられ、導電性を有する第2の電極ブロックとを備え、
前記第2の電極ブロックの下面は、第3の領域において、導電性を有する金属層を介して前記バンプと電気的に接続され、
前記第2の電極ブロックの下面は、第4の領域において、前記絶縁層に搭載され、
前記金属層と前記バンプとの間には、導電性を有する金属シートが設けられている半導体装置。 - 前記金属層は、前記第3の領域に接合されている請求項1に記載の半導体装置。
- 前記金属層は、前記第3の領域にメッキ成長されている請求項1に記載の半導体装置。
- 前記半導体素子は、レーザ光を出力する半導体レーザ素子であり、
前記第1の領域は、前記第1の電極ブロックの上面の端部であり、
前記第2の領域は、前記第1の領域をコの字状に囲んでいる請求項1~3のいずれかに記載の半導体装置。 - 前記半導体素子は、60V以上の高電圧が入力されるパワー半導体素子であり、
前記第1の領域は、前記第1の電極ブロックの上面の中央部であり、
前記第2の領域は、前記第1の領域の全周囲を囲んでいる請求項1~3のいずれかに記載の半導体装置。 - 前記第1の領域の前記第1の電極ブロックの上面は、前記第2の領域の前記第1の電極の上面よりも低く、
前記第2の電極ブロックの下面は平面である請求項1~5のいずれかに記載の半導体装置。 - 前記第1の電極ブロックの上面は平面であり、
前記第3の領域の前記第2の電極ブロックの下面は、前記第4の領域の前記第2の電極の下面よりも高い請求項1~5のいずれかに記載の半導体装置。 - 前記金属シートの主な材料は金である請求項1~7のいずれかに記載の半導体装置。
- 前記バンプの主な材料は金である請求項1~8のいずれかに記載の半導体装置。
- 前記金属層の主な材料は金である請求項1~9のいずれかに記載の半導体装置。
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