WO2016038686A1 - Ｃｕカラム、Ｃｕ核カラム、はんだ継手およびシリコン貫通電極 - Google Patents

Ｃｕカラム、Ｃｕ核カラム、はんだ継手およびシリコン貫通電極 Download PDF

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Publication number
WO2016038686A1
WO2016038686A1 PCT/JP2014/073808 JP2014073808W WO2016038686A1 WO 2016038686 A1 WO2016038686 A1 WO 2016038686A1 JP 2014073808 W JP2014073808 W JP 2014073808W WO 2016038686 A1 WO2016038686 A1 WO 2016038686A1
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Prior art keywords
column
less
solder
layer
arithmetic average
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PCT/JP2014/073808
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English (en)
French (fr)
Inventor
浩由 川▲崎▼
六本木　貴弘
相馬　大輔
佐藤　勇
勇司 川又
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千住金属工業株式会社
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Application filed by 千住金属工業株式会社 filed Critical 千住金属工業株式会社
Priority to US15/509,333 priority Critical patent/US10811376B2/en
Priority to KR1020187004667A priority patent/KR102315758B1/ko
Priority to PCT/JP2014/073808 priority patent/WO2016038686A1/ja
Priority to EP14901571.1A priority patent/EP3193360B1/en
Priority to JP2015507277A priority patent/JP5733486B1/ja
Priority to CN201480081816.XA priority patent/CN106688085B/zh
Priority to PT149015711T priority patent/PT3193360T/pt
Priority to KR1020177009272A priority patent/KR20170042372A/ko
Priority to TW104128958A priority patent/TWI566650B/zh
Publication of WO2016038686A1 publication Critical patent/WO2016038686A1/ja

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/10—Electroplating with more than one layer of the same or of different metals
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B22—CASTING; POWDER METALLURGY
    • B22F—WORKING METALLIC POWDER; MANUFACTURE OF ARTICLES FROM METALLIC POWDER; MAKING METALLIC POWDER; APPARATUS OR DEVICES SPECIALLY ADAPTED FOR METALLIC POWDER
    • B22F1/00—Metallic powder; Treatment of metallic powder, e.g. to facilitate working or to improve properties
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/02—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
    • B23K35/0222—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape for use in soldering, brazing
    • B23K35/0227—Rods, wires
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24—Selection of soldering or welding materials proper
    • B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
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    • B23K35/262—Sn as the principal constituent
    • B—PERFORMING OPERATIONS; TRANSPORTING
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    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
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    • B—PERFORMING OPERATIONS; TRANSPORTING
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    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
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    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
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    • B23K35/3615—N-compounds
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    • B32B15/20—Layered products comprising a layer of metal comprising aluminium or copper
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Definitions

  • the present invention relates to a Cu column, a Cu core column, a solder joint, and a silicon through electrode.
  • the electronic components to be mounted have been rapidly downsized.
  • the electronic component uses a ball grid array (hereinafter referred to as “BGA”) in which electrodes are provided on the back surface. .
  • BGA ball grid array
  • An electronic component to which BGA is applied includes, for example, a semiconductor package.
  • a semiconductor package a semiconductor chip having electrodes is sealed with a resin.
  • Solder bumps are formed on the electrodes of the semiconductor chip. This solder bump is formed by joining a solder ball to an electrode of a semiconductor chip.
  • a semiconductor package to which BGA is applied is mounted on a printed board by bonding solder bumps melted by heating and conductive lands of the printed board. In order to meet the demand for higher density mounting, three-dimensional high density mounting in which semiconductor packages are stacked in the height direction has been developed.
  • solder bumps for electrically joining Cu balls on the electrodes of electronic components using solder paste are being studied.
  • Solder bumps formed using Cu balls can support the semiconductor package with Cu balls that do not melt at the melting point of the solder even when the weight of the semiconductor package is applied to the solder bumps when the electronic component is mounted on a printed circuit board. it can. Therefore, the solder bump is not crushed by the weight of the semiconductor package.
  • the stand-off height between the substrates is the ball diameter of the Cu ball, so when attempting to achieve the required stand-off height, the lateral width of the Cu ball becomes large, and it is not possible to support mounting with a narrow pitch.
  • a semiconductor package a semiconductor chip is bonded to a die pad electrode portion of a lead frame using a solder material for die bonding, and then sealed with a resin.
  • a solder material for mounting different from the solder material for die bonding is used.
  • the reason for this is to prevent the die bonding solder material from being melted by the heating conditions of the mounting solder material when the semiconductor package is mounted on the substrate.
  • a difference occurs in the thermal expansion coefficient of each substrate. (Thermal stress) occurs, and TCT (temperature cycle test) reliability sometimes decreases.
  • Patent Documents 1 to 5 describe columnar columns made of copper, solder, or the like.
  • Patent Document 6 describes a copper column for joining a ceramic substrate and a glass epoxy substrate having a Vickers hardness of 55 HV or less.
  • Japanese Unexamined Patent Publication No. 7-66209 Japanese Patent No. 3344295 JP 2000-232119 A Japanese Patent No. 444063 JP 2009-1474 A JP 2011-176124 A
  • Patent Documents 1 to 6 Although it is possible to cope with a narrow pitch mounting and to suppress thermal stress, there is no disclosure about the arithmetic average roughness of the Cu column. Therefore, when the Cu column of Patent Documents 1 to 6 is used, the fluidity of the Cu column when the Cu column is arranged on the substrate is reduced, or the adhesion between the Cu column and the electrode during mounting is reduced. There were cases where problems such as a drop occurred.
  • an object of the present invention is to provide a Cu column, a Cu core column, a solder joint, and a silicon through electrode having low Vickers hardness and low arithmetic average roughness in order to solve the above-described problems.
  • the inventors have made a selection for a Cu column. It has been found that when the Vickers hardness of the Cu column is 20 HV or more and 60 HV or less and the arithmetic average roughness is 0.3 ⁇ m or less, a preferable Cu column or the like for solving the problems of the present invention can be obtained.
  • the present invention is as follows.
  • a Cu column having a purity of 99.9% or more and 99.995% or less, an arithmetic average roughness of 0.3 ⁇ m or less, and a Vickers hardness of 20 HV or more and 60 HV or less.
  • the Cu column according to the above (1) or (2) which is composed of a column having a top surface and a bottom surface with a diameter of 1 to 1000 ⁇ m and a height of 1 to 3000 ⁇ m.
  • a Cu nucleus column comprising the Cu column according to any one of (1) to (4) above and a solder layer covering the Cu column.
  • a Cu nucleus column provided with the Cu column according to any one of (1) to (4) above and a plating layer made of one or more elements selected from Ni, Fe and Co covering the Cu column. .
  • the Vickers hardness of the Cu column is 20 HV or more and 60 HV or less, the drop impact resistance can be improved and an appropriate space between the substrates can be maintained.
  • the arithmetic average roughness of the Cu column is 0.3 ⁇ m or less, the fluidity when the Cu column is arranged on the substrate can be improved, and the adhesion between the Cu column and the electrode during mounting is improved. Can be made.
  • FIG. 1 is a diagram showing a configuration example of a Cu column according to the present invention.
  • FIG. 2 is a diagram showing a configuration example of a Cu nucleus column according to the present invention.
  • FIG. 3 is a diagram showing the relationship between temperature and time during the annealing process.
  • the unit (ppm, ppb, and%) related to the composition of the Cu column represents a ratio (mass ppm, mass ppb, and mass%) to the mass of the Cu column unless otherwise specified.
  • the Cu column 1 according to the present invention shown in FIG. 1 has a purity of 99.9% to 99.995%, an arithmetic average roughness of 0.3 ⁇ m or less, and a Vickers hardness of 20 HV to 60 HV. .
  • the Cu column 1 has, for example, a cylindrical shape. Since the Cu column 1 does not melt at the soldering temperature and can secure a certain standoff height (space between the substrates), it can be suitably used for three-dimensional mounting and narrow pitch mounting.
  • -Arithmetic mean roughness of Cu column 0.3 micrometer or less
  • the arithmetic mean roughness of Cu column 1 is 0.3 micrometer or less, More preferably, it is 0.2 micrometer or less.
  • the arithmetic average roughness of the Cu column 1 is 0.3 ⁇ m or less, the size of the crystal grains of the Cu column 1 is also reduced, so that the surface of the Cu column 1 can be made smoother (flat).
  • the fluidity of the Cu column 1 when the Cu column 1 is arranged on the substrate by a mounter or the like can be improved, and the adhesion between the Cu column 1 and the electrode on the substrate at the time of mounting is improved. You can also.
  • the Vickers hardness of the Cu column 1 which concerns on this invention is 60HV or less. This is because when the Vickers hardness is 60 HV or less, durability against external stress is increased, and the drop impact resistance is improved and cracks are hardly generated. In addition, when an auxiliary force such as pressurization is applied when forming bumps or joints for three-dimensional mounting, the possibility of causing electrode collapse or the like can be reduced by using a highly flexible Cu column 1. Because.
  • the Vickers hardness of the Cu column 1 needs to be at least a value larger than a typical Vickers hardness of 10 to 20 HV, preferably 20 HV or more.
  • a typical Vickers hardness of 10 to 20 HV preferably 20 HV or more.
  • the Vickers hardness of the Cu column 1 is 20 HV or more, deformation (collapse) of the Cu column 1 itself due to its own weight such as a semiconductor chip in three-dimensional mounting is prevented, and an appropriate space (standoff height) between the substrates is provided. Can hold.
  • a plating step is not required unlike Cu pillars or the like, it is possible to reduce the pitch of electrodes and the like by setting the Vickers hardness of the Cu column 1 to 20 HV or higher.
  • the Cu column 1 having a Vickers hardness of 60 HV or less is manufactured by promoting crystal growth of the manufactured Cu column 1.
  • An example of a means for promoting the crystal growth of the Cu column 1 is an annealing process.
  • the manufactured Cu column 1 is annealed, the Cu structure is recrystallized and crystal grains grow, thereby improving the flexibility of the Cu column 1.
  • a Cu column 1 containing a certain amount of impurities for example, a Cu column 1 having a purity of 3N, 4N, or 4N5
  • the contained impurities suppress excessive growth of crystal grains on the surface of the Cu column 1. Therefore, the crystal grains can be suppressed to a size below a certain value. Thereby, it is possible to provide a Cu column having both low Vickers hardness and low arithmetic average roughness.
  • U and Th are radioactive elements, and it is necessary to suppress their contents in order to suppress soft errors.
  • the contents of U and Th are required to be 5 ppb or less in order to make the ⁇ dose of the Cu column 1 0.0200 cph / cm 2 or less. Further, from the viewpoint of suppressing soft errors in current or future high-density mounting, the contents of U and Th are preferably 2 ppb or less, respectively.
  • the Cu column 1 constituting the present invention preferably has a purity of 99.9% or more and 99.995% or less.
  • the purity of the Cu column 1 is within this range, a sufficient amount of impurity element crystal nuclei can be secured in the Cu, so that the arithmetic average roughness of the Cu column 1 can be reduced.
  • the amount of impurity elements is small, the number of crystal nuclei is relatively small, and grain growth is not suppressed, and the crystal column grows in a certain direction. Therefore, the arithmetic average roughness of the Cu column 1 increases.
  • the lower limit of the purity of the Cu column 1 is not particularly limited, it is preferably 99.9% or more from the viewpoint of suppressing the ⁇ dose and suppressing the deterioration of the electrical conductivity and thermal conductivity of the Cu column 1 due to the decrease in purity.
  • the impurity element include Sn, Sb, Bi, Zn, As, Ag, Cd, Ni, Pb, Au, P, S, In, Co, Fe, U, and Th.
  • ⁇ dose 0.0200 cph / cm 2 or less
  • the ⁇ dose of the Cu column 1 constituting the present invention is 0.0200 cph / cm 2 or less. This is an ⁇ dose that does not cause a soft error in high-density mounting of electronic components.
  • the ⁇ dose is more preferably 0.0010 cph / cm 2 or less from the viewpoint of suppressing a soft error in further high-density mounting.
  • the total content of impurity elements is 1 ppm or more.
  • the Cu column 1 constituting the present invention has Sn, Sb, Bi, Zn, As, Ag, Cd, Ni, Pb, Au, P, S, In, and the like as impurity elements. Co, Fe, U, Th, etc. are contained, but the content of impurity elements is 1 ppm or more in total.
  • the contents of Pb and Bi that are impurity elements are preferably as low as possible.
  • the diameter ⁇ of the upper surface and the bottom surface of the Cu column 1 according to the present invention is preferably 1 to 1000 ⁇ m, more preferably 1 to 300 ⁇ m, more preferably 1 to 200 ⁇ m, most preferably when used for a fine pitch. Is 1 to 100 ⁇ m.
  • the height L of the Cu column 1 is preferably 1 to 3000 ⁇ m, particularly preferably 1 to 300 ⁇ m, more preferably 1 to 200 ⁇ m, and most preferably 1 to 100 ⁇ m when used for a fine pitch. Yes (see FIG. 1).
  • the diameter ⁇ and the height L of the Cu column 1 are in the above ranges, it is possible to mount with a narrow pitch between terminals, so that it is possible to suppress connection short circuit and to reduce the size and integration of the semiconductor package. Can be planned.
  • the layer may be coated on the outermost surface of the Cu column 1.
  • the flux layer is softer than the solder layer or the Ni plating layer, so that the fluidity is greatly affected.
  • the arithmetic average roughness of the Cu column 1 or Cu core column coated with the flux is 0.3 ⁇ m or less
  • the arithmetic average roughness of the Cu column 1 or Cu core column coated with the flux layer is 0.3 ⁇ m.
  • the flowability of the Cu column 1 when arranged on the substrate does not deteriorate so much, and the adhesion between the Cu column 1 and the electrode on the substrate during mounting can be improved.
  • the Vickers hardness of the Cu column 1 itself is 20 HV or more and 60 HV or less, the drop impact resistance after mounting the Cu column 1 is improved, and the solution to the problem of the present application that maintains an appropriate space between the substrates is achieved. Can do.
  • the Cu core column 3 includes a Cu column 1 and a solder layer 2 (metal layer) that covers the surface of the Cu column 1.
  • the composition of the solder layer 2 is not particularly limited as long as it is an alloy composition of a solder alloy containing Sn as a main component.
  • the solder layer 2 may be a Sn plating film.
  • Examples thereof include Sn, Sn—Ag alloy, Sn—Cu alloy, Sn—Ag—Cu alloy, Sn—In alloy, and those obtained by adding a predetermined alloy element thereto.
  • the Sn content is 40% by mass or more.
  • Sn—Bi alloy and Sn—Pb alloy can be used as the solder layer 2 when the ⁇ dose is not specified.
  • alloy elements to be added include Ag, Cu, In, Ni, Co, Sb, Ge, P, and Fe.
  • the alloy composition of the solder layer 2 is preferably a Sn-3Ag-0.5Cu alloy from the viewpoint of drop impact characteristics.
  • the thickness of the solder layer 2 is not particularly limited, but is preferably 100 ⁇ m or less on one side. Generally, it may be 20 to 50 ⁇ m on one side.
  • a Ni plating layer, a Fe plating layer, a Co plating layer, or the like can be provided in advance between the surface of the Cu column 1 and the solder layer 2. Thereby, the spreading
  • the thickness of the Ni plating layer, Fe plating layer, Co plating layer, etc. is generally 0.1 to 20 ⁇ m on one side.
  • the contents of U and Th in the solder layer 2 are each 5 ppb or less in order to set the ⁇ dose of the Cu nucleus column to 0.0200 cph / cm 2 or less. Further, from the viewpoint of suppressing soft errors in current or future high-density mounting, the contents of U and Th are preferably 2 ppb or less, respectively.
  • the Cu core column according to the present invention can also be constituted by a Cu column 1 and a plating layer (metal layer) composed of one or more elements selected from Ni, Fe and Co covering the Cu column 1. Moreover, you may coat
  • the Cu column 1 or the Cu core column 3 according to the present invention can also be used for forming a solder joint for joining electrodes.
  • a solder joint a structure in which a solder bump is mounted on an electrode of a printed board is called a solder joint.
  • the solder bump is a structure in which a Cu column 1 is mounted on an electrode of a semiconductor chip.
  • the Cu column 1 or the Cu core column 3 according to the present invention can be used as a through-silicon via (TSV) for connecting electrodes between stacked semiconductor chips.
  • TSV is manufactured by drilling holes in silicon, forming an insulating layer in the hole, and then forming through conductors in that order, polishing the top and bottom surfaces of silicon and exposing the through conductors on the top and bottom surfaces.
  • the through conductor is conventionally formed by filling the hole with Cu or the like by a plating method. In this method, the entire surface of silicon is immersed in the plating solution. There is a risk of adsorption and moisture absorption.
  • the column of the present invention can be directly inserted into a hole formed in silicon in the height direction and used as a through conductor.
  • the Cu column 1 When the Cu column 1 is inserted into silicon, it may be joined by a solder material such as a solder paste, and when the Cu core column is inserted into silicon, it can be joined only by flux. Thereby, defects such as impurity adsorption and moisture absorption can be prevented, and the manufacturing cost and time can be reduced by omitting the plating step.
  • the outermost surface of the above-described Cu column 1 or Cu core column may be covered with a flux layer.
  • the above-described flux layer is composed of one or more components including a compound that acts as an activator for preventing the metal surface of the Cu column 1 or the solder layer from being oxidized and removing the metal oxide film during soldering.
  • the flux layer may be composed of a plurality of components composed of a compound that acts as an activator and a compound that acts as an activity auxiliary agent.
  • any one of an amine, an organic acid, and a halogen, a combination of a plurality of amines, a combination of a plurality of organic acids, a combination of a plurality of halogens, and a simple substance can be used depending on the properties required in the present invention.
  • a combination of one or more amines, organic acids, halogens is added.
  • the active adjuvant that constitutes the flux layer is either an ester, an amide, or an amino acid, a combination of multiple esters, a combination of multiple amides, a combination of multiple amino acids, a single or multiple A combination of esters, amides, amino acids is added.
  • the flux layer may contain rosin or resin in order to protect the compound acting as an activator from heat during reflow. Further, the flux layer may include a resin that fixes a compound or the like acting as an activator to the solder layer.
  • the flux layer may be composed of a single layer composed of a single compound or a plurality of compounds.
  • the flux layer may be composed of a plurality of layers made of a plurality of compounds.
  • the components constituting the flux layer adhere to the surface of the solder layer in a solid state. However, in the step of attaching the flux to the solder layer, the flux needs to be liquid or gaseous.
  • the components constituting the flux layer need to be soluble in a solvent in order to coat with a solution.
  • a salt when a salt is formed, there is a component that becomes insoluble in the solvent.
  • the presence of components that are insoluble in the liquid flux makes it difficult to uniformly adsorb fluxes that contain poorly soluble components such as precipitates. For this reason, conventionally, a compound that forms a salt cannot be mixed to form a liquid flux.
  • the flux layer can be formed one by one to form a solid state, and a multilayer flux layer can be formed.
  • the compound which forms a salt is used, Comprising: Even if it is a component which cannot be mixed with a liquid flux, a flux layer can be formed.
  • the surface of the Cu column 1 or Cu core column that is easily oxidized is coated with a flux layer that acts as an activator, so that the surface of the Cu column 1 and the surface of the solder or metal layer of the Cu core column can be stored during storage. Can be suppressed.
  • the colors of the flux and the metal are generally different, and the colors of the Cu column 1 and the flux layer are also different. Therefore, the amount of adsorption of the flux can be confirmed by color saturation, for example, brightness, yellowness, and redness.
  • the above-described Cu column 1 may be covered with an organic film containing an imidazole compound. As a result, the outermost Cu layer of the Cu column 1 is bonded to the imidazole compound, so that an OSP coating (imidazole copper complex) is formed on the surface of the Cu column 1 and the surface of the Cu column 1 is prevented from being oxidized. can do.
  • OSP coating imidazole copper complex
  • a copper wire as a material is prepared, the prepared copper wire is extended by passing through a die, and then the copper wire is cut to a predetermined length by a cutting machine. In this way, the Cu column 1 having a predetermined diameter ⁇ and a predetermined length (height L) having a cylindrical shape is manufactured.
  • the manufacturing method of Cu column 1 is not limited to this Embodiment, You may employ
  • the produced Cu column 1 is subjected to an annealing treatment.
  • the annealing treatment the Cu column 1 is heated for a predetermined time at 700 ° C. where annealing can be performed, and then the heated Cu column 1 is gradually cooled over a long time. Thereby, recrystallization of the Cu column 1 can be performed, and gradual crystal growth can be promoted.
  • the impurity element contained in the Cu column 1 suppresses excessive growth of crystal grains, the extreme arithmetic average roughness of the Cu column 1 does not decrease.
  • the Vickers hardness of the Cu column 1 is 20 HV or more and 60 HV or less, it is possible to improve the drop impact resistance and to maintain an appropriate space between the substrates.
  • the arithmetic average roughness of the Cu column 1 is 0.3 ⁇ m or less, the fluidity when the Cu column 1 is arranged on the substrate can be improved, and the adhesion between the Cu column 1 and the electrode during mounting is improved. Can be improved.
  • a plurality of Cu columns were prepared using a plurality of copper wires having different purities, and the Vickers hardness, arithmetic average roughness, and ⁇ dose of each of the prepared Cu columns were measured.
  • Copper wires having a purity of 99.9%, 99.99%, and 99.995% were prepared. Next, by passing these copper wires through a die, the copper wires are extended so that the diameter ⁇ of the top surface and the bottom surface becomes 200 ⁇ m, and then the copper wire is placed at a position where the length (height L) is 200 ⁇ m.
  • the target Cu column was produced by cutting.
  • Arithmetic average roughness The arithmetic average roughness (image evaluation) of the Cu column was evaluated using a laser microscope (model number VK-9510 / JISB0601-1994) manufactured by KEYENCE. In this example, the measurement was performed in a range of 10 ⁇ 10 ⁇ m centering on the flattest portion of the upper surface of the Cu column. The measurement pitch on the z-axis (height direction) of the Cu column is 0.01 ⁇ m. Under such conditions, the arithmetic average roughness Ra of 10 arbitrary positions was measured as the arithmetic average roughness Ra of the Cu column, and those arithmetic averages were used as the true arithmetic average roughness.
  • arithmetic mean roughness Ra may measure the bottom face and peripheral surface of Cu column, and may use the value which averaged each measured value of the upper surface, bottom face, and peripheral surface of Cu column as a measured value.
  • ultrasonic waves are used to flatten the surface of the Cu column, but the present invention is not limited to this.
  • the Cu column can be immersed in a soluble liquid that lightly dissolves the surface of the Cu column and promotes smoothing.
  • a sulfonic acid (methanesulfonic acid or the like) or carboxylic acid (oxalic acid or the like) acidic solution can be used.
  • the Vickers hardness of the Cu column was measured according to "Vickers hardness test-test method JIS Z2244".
  • the equipment used was a micro Vickers hardness tester manufactured by Akashi Seisakusho and an AKASHI micro hardness tester MVK-F 12001-Q.
  • ⁇ ⁇ dose The measurement method of ⁇ dose is as follows. For measuring the ⁇ dose, an ⁇ ray measuring device of a gas flow proportional counter was used. The measurement sample is a 300 mm ⁇ 300 mm flat shallow container in which a Cu column is spread until the bottom of the container is not visible. This measurement sample was placed in an ⁇ -ray measuring apparatus and allowed to stand for 24 hours in a PR-10 gas flow, and then the ⁇ dose was measured.
  • the PR-10 gas used for the measurement (90% argon—10% methane) was obtained after 3 weeks or more had passed since the gas cylinder was filled with the PR-10 gas.
  • the cylinder that was used for more than 3 weeks was used because the JEDEC STANDARDE-Alpha Radiation Measuring Element was established by JEDEC (Joint Electron Engineering Engineering Coil) so that alpha rays would not be generated by radon in the atmosphere entering the gas cylinder. This is because JESD221 is followed.
  • Example 1 A Cu column manufactured using a copper wire having a purity of 99.9% was placed in a carbon bat, and then the bat was carried into a continuous conveyor type electric resistance heating furnace for annealing treatment. The annealing conditions at this time are shown in FIG. The inside of the furnace was in a nitrogen gas atmosphere in order to prevent oxidation of the Cu column. The room temperature was 25 ° C.
  • the heating time for heating from room temperature to 700 ° C. is 60 minutes
  • the holding time for holding at 700 ° C. is 60 minutes
  • the cooling time for cooling from 700 ° C. to room temperature is 120 minutes. Minutes.
  • the inside of the furnace was cooled using a cooling fan installed in the furnace.
  • the acid treatment was performed by immersing the Cu column subjected to the annealing treatment in dilute sulfuric acid. This is to remove the oxide film formed on the surface of the Cu column by the annealing process.
  • Table 1 below shows the Vickers hardness, arithmetic average roughness, and ⁇ dose before and after the annealing treatment of the Cu column thus obtained.
  • Example 2 In Example 2, an annealing process and an oxide film removal process were performed on a Cu column made of a copper wire having a purity of 99.99% by the same method as in Example 1. And the Vickers hardness, arithmetic mean roughness, and alpha dose of the obtained Cu column were measured. The measurement results are shown in Table 1 below.
  • Example 3 an annealing process and an oxide film removal process were performed on a Cu column made of a copper wire having a purity of 99.995% by the same method as in Example 1. And the Vickers hardness, arithmetic mean roughness, and alpha dose of the obtained Cu column were measured. The measurement results are shown in Table 1 below.
  • Comparative example 1 In Comparative Example 1, the Vickers hardness, arithmetic average roughness, and ⁇ dose of a Cu column made of a copper wire having a purity of 99.9% were measured. The measurement results are shown in Table 1 below.
  • Comparative example 2 In Comparative Example 2, the Vickers hardness, arithmetic average roughness, and ⁇ dose of a Cu column made of a copper wire with a purity of 99.99% were measured. The measurement results are shown in Table 1 below.
  • Comparative example 3 In Comparative Example 3, the Vickers hardness, arithmetic average roughness, and ⁇ dose of a Cu column made of a copper wire with a purity of 99.995% were measured. The measurement results are shown in Table 1 below.
  • Comparative example 4 In Comparative Example 4, the Vickers hardness, arithmetic average roughness, and ⁇ dose of a Cu column made of a copper wire having a purity exceeding 99.995% were measured. The measurement results are shown in Table 1 below.
  • Comparative example 5 In Comparative Example 5, an annealing process and an oxide film removal process were performed on a Cu column made of a copper wire having a purity exceeding 99.995% by the same method as in Example 1. And the Vickers hardness, arithmetic mean roughness, and alpha dose of the obtained Cu column were measured. The measurement results are shown in Table 1 below.
  • Example 1 As shown in Table 1, in Example 1, the arithmetic average roughness of the Cu column was 0.10 ⁇ m, in Example 2, the arithmetic average roughness of the Cu column was 0.17 ⁇ m, and in Example 3, the arithmetic average of the Cu column was The roughness was 0.28 ⁇ m, and the arithmetic average roughness was 0.3 ⁇ m or less in any of the examples.
  • the Vickers hardness of the Cu column is 57.1
  • Example 2 the Vickers hardness of the Cu column is 52.9
  • Example 3 the Vickers hardness of the Cu column is 50.2, In all examples, the Vickers hardness was 20 HV or more and 60 HV or less. From these results, it was confirmed that a Cu column having both physical properties of low Vickers hardness and low arithmetic average roughness can be obtained by subjecting the Cu column during production to annealing.
  • Comparative Examples 1 to 4 where the annealing treatment was not applied to the Cu column the arithmetic average roughness of the Cu column was 0.3 ⁇ m or less, but the Vickers hardness was over 60 HV, and the Vickers hardness was 20 HV or more and 60 HV. It was confirmed that the following conditions were not met.
  • Comparative Example 5 the Vickers hardness of the Cu column was in the range of 20 HV to 60 HV, but the arithmetic average roughness was over 0.3 ⁇ m. Thereby, even when annealing treatment was performed on the Cu column at the time of production, it was confirmed that the arithmetic average roughness does not satisfy the condition regarding 0.3 ⁇ m or less when a high purity Cu column is used.
  • alpha dose Cu column is less than 0.0010cph / cm 2 or less, which satisfies the ⁇ 0.0200cph / cm 2, further the ⁇ 0.0010cph / cm 2 It was confirmed that the result was satisfied.
  • a Cu core column was prepared by coating the surface of the Cu column after the annealing treatment of Example 1 described above with a solder plating layer made of an Sn-3Ag-0.5Cu alloy, and the Cu core column and the Cu core column.
  • the plating solution used at the time of production was collected in a 300 cc beaker as it was, and was applied to an ultrasonic machine and irradiated with ultrasonic waves for 60 minutes.
  • the ultrasonic machine a commercially available ultrasonic cleaning machine (US-CLEANER manufactured by AS ONE) was used, and the output was 80 W and the frequency of 40 kHz.
  • the arithmetic average roughness and ⁇ dose of the prepared Cu core column were measured.
  • the arithmetic average roughness of the Cu core column was 0.3 ⁇ m or less.
  • the Cu core column in which the surface of the Cu column of Example 1 is coated with the Ni plating layer, and the Cu core column in which the surface of the Cu column of Example 1 is sequentially coated with the Ni plating layer and the solder plating layer are also described above.
  • the arithmetic average roughness of the Cu core column was 0.3 ⁇ m or less.
  • alpha dose is less than 0.0010cph / cm 2, which satisfied the ⁇ 0.0200cph / cm 2, even more was confirmed to be the results which satisfy the ⁇ 0.0010cph / cm 2 .
  • the arithmetic average roughness was 0.3 ⁇ m or less as in the case of the Cu core column coated with the Ni plating layer. Further, the dose may be less than 0.0010cph / cm 2 ⁇ , which satisfies the ⁇ 0.0200cph / cm 2, even more was confirmed to be the results which satisfy the ⁇ 0.0010cph / cm 2.
  • a flux-coated Cu column was prepared by coating the surface of the Cu column after the annealing treatment of Example 1 described above with a flux, and the arithmetic average roughness and ⁇ dose of the prepared flux-coated Cu column were measured. Similar to Examples 1 to 3, the arithmetic average roughness of the flux-coated Cu column was 0.3 ⁇ m or less. Furthermore, in the flux-coated Cu column, the ⁇ dose is less than 0.0010 cph / cm 2 , which is confirmed to satisfy ⁇ 0.0200 cph / cm 2 and further satisfy ⁇ 0.0010 cph / cm 2. It was done.
  • the flux-coated Cu core column in which the surface of the Cu core column was coated with a flux also had an arithmetic average roughness of 0.3 ⁇ m or less, like the flux-coated Cu column.
  • alpha dose is less than 0.0010cph / cm 2, which is possible ⁇ meet 0.0200cph / cm 2, even at results which satisfy the ⁇ 0.0010cph / cm 2 confirmed.
  • Example 2 the surface of the Cu column after the annealing treatment of Example 1 was coated with an organic coating containing an imidazole compound to prepare an OSP-treated Cu column, and the arithmetic average roughness and ⁇ dose of the produced OSP-treated Cu column were respectively determined. It was measured. As in Examples 1 to 3, it was confirmed that the OSP-treated Cu column had an arithmetic average roughness of 0.3 ⁇ m or less and an ⁇ dose of 0.0010 cph / cm 2 or less.
  • the column of the present invention has a columnar shape, but the shape is not limited to a column, and the upper and lower surfaces that are in direct contact with the substrate, such as a triangular column or a quadrangular column, are three sides. If it is the pillar body comprised by the above, the effect of this invention can be acquired.

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Abstract

　ビッカース硬さが低く、かつ、算術平均粗さが小さいＣｕカラム、Ｃｕ核カラム、はんだ継手およびシリコン貫通電極を提供する。　本発明に係るＣｕカラム１は、純度が９９．９％以上９９．９９５％以下であり、算術平均粗さが０．３μｍ以下であり、ビッカース硬さが２０ＨＶ以上６０ＨＶ以下である。Ｃｕカラム１は、はんだ付けの温度で溶融せず、一定のスタンドオフ高さ（基板間の空間）を確保できるので、三次元実装や狭ピッチ実装に好適に用いられる。

Description

Ｃｕカラム、Ｃｕ核カラム、はんだ継手およびシリコン貫通電極
　本発明は、Ｃｕカラム、Ｃｕ核カラム、はんだ継手およびシリコン貫通電極に関する。
　近年、小型情報機器の発達により、搭載される電子部品では急速な小型化が進行している。電子部品は、小型化の要求により接続端子の狭小化や実装面積の縮小化に対応するため、裏面に電極が設置されたボールグリッドアレイ（以下、「ＢＧＡ」と称する。）が適用されている。
　ＢＧＡを適用した電子部品には、例えば半導体パッケージがある。半導体パッケージでは、電極を有する半導体チップが樹脂で封止されている。半導体チップの電極には、はんだバンプが形成されている。このはんだバンプは、はんだボールを半導体チップの電極に接合することによって形成されている。ＢＧＡを適用した半導体パッケージは、加熱により溶融したはんだバンプとプリント基板の導電性ランドが接合することにより、プリント基板に搭載される。また、更なる高密度実装の要求に対応するため、半導体パッケージが高さ方向に積み重ねられた３次元高密度実装が開発されている。
　しかし、３次元高密度実装がなされた半導体パッケージにＢＧＡを適用した場合、半導体パッケージの自重によりはんだボールが潰れてしまうことがある。もしそのようなことが起きると、基板間の適切な空間を保持できなくなる。
　そこで、はんだペーストを用いて電子部品の電極上にＣｕボールを電気的に接合するはんだバンプが検討されている。Ｃｕボールを用いて形成されたはんだバンプは、電子部品がプリント基板に実装される際、半導体パッケージの重量がはんだバンプに加わっても、はんだの融点では溶融しないＣｕボールにより半導体パッケージを支えることができる。したがって、半導体パッケージの自重によりはんだバンプが潰れることがない。
　ところが、上述したＣｕボールを用いた場合には以下のような問題があった。Ｃｕボールでは、基板間のスタンドオフ高さがＣｕボールの球径となるため、要求されるスタンドオフ高さを実現しようとするとＣｕボールの横幅が大きくなってしまい、狭ピッチ化実装に対応できない場合があった。また、一般に半導体パッケージにおいては、半導体チップをリードフレームのダイパッド電極部にダイボンド用のはんだ材料を用いて接合された後、樹脂で封止される。この半導体パッケージをプリント基板に実装する場合には、ダイボンド用のはんだ材料とは異なる実装用のはんだ材料が用いられている。この理由は、半導体パッケージを基板に実装する時の実装用のはんだ材料の加熱条件によって、ダイボンド用のはんだ材料が溶け出さないようにするためである。このように、ダイボンド用のはんだ材料と実装用のはんだ材料に異なる材料が使用される場合、各基板の熱膨張係数に差が生じるため、環境温度等の変化によりはんだバンプとの接合部に応力（熱ストレス）が発生してしまい、ＴＣＴ（温度サイクル試験）信頼性が低下してしまう場合があった。
　そのため、近年では、はんだボールよりも狭ピッチ化が可能であり、かつ、ＴＣＴ信頼性の向上を図ることが可能なＣｕカラムが開発されている。また、同一のピッチのＣｕボールとＣｕカラムを比較した場合、ボール形状よりカラム形状の方が安定して電極間を支持できるため、この点でもＣｕカラムの採用が検討されている。例えば、特許文献１から５には、銅やはんだ等からなる柱状のカラムが記載されている。特許文献６には、ビッカース硬さが５５ＨＶ以下である、セラミック基板とガラスエポキシ基板とを接合するための銅カラムが記載されている。
特開平７－６６２０９号公報 特許第３３４４２９５号 特開２０００－２３２１１９号公報 特許第４４０４０６３号 特開２００９－１４７４号公報 特開２０１１－１７６１２４号公報
　しかしながら、上記特許文献１から６によれば、狭ピッチ化実装に対応できると共に熱ストレスを抑制することができるが、Ｃｕカラムの算術平均粗さについては一切開示されていない。そのため、特許文献１から６のＣｕカラムを使用した場合には、Ｃｕカラムを基板上に配列する際のＣｕカラムの流動性が低下してしまったり、実装時におけるＣｕカラムと電極の密着性が低下してしまったりする等の問題が発生する場合があった。
　そこで、本発明は、上記課題を解決するために、ビッカース硬さが低く、かつ、算術平均粗さが小さいＣｕカラム、Ｃｕ核カラム、はんだ継手およびシリコン貫通電極を提供することを目的とする。
　本発明者らは、Ｃｕカラムについて選定を行った。Ｃｕカラムのビッカース硬さが２０ＨＶ以上６０ＨＶ以下であって、かつ、算術平均粗さが０．３μｍ以下であれば、本発明の課題解決のための好ましいＣｕカラム等が得られることを知見した。
　ここに、本発明は次の通りである。
　（１）純度が９９．９％以上９９．９９５％以下であり、算術平均粗さが０．３μｍ以下であり、ビッカース硬さが２０ＨＶ以上６０ＨＶ以下であるＣｕカラム。
　（２）α線量が０．０２００ｃｐｈ／ｃｍ２以下である上記（１）に記載のＣｕカラム。
　（３）上面および底面の径が１～１０００μｍであり、高さが１～３０００μｍである柱体からなる上記（１）または（２）に記載のＣｕカラム。
　（４）フラックス層が被覆されている上記（１）～（３）のいずれか一つに記載のＣｕカラム。
　（５）イミダゾール化合物を含有する有機被膜が被覆されている上記（１）～（３）のいずれか１項に記載のＣｕカラム。
　（６）上記（１）～（４）のいずれか一つに記載のＣｕカラムと、前記Ｃｕカラムを被覆するはんだ層とを備えるＣｕ核カラム。
　（７）上記（１）～（４）のいずれか一つに記載のＣｕカラムと、前記Ｃｕカラムを被覆するＮｉ、ＦｅおよびＣｏから選択される１元素以上からなるめっき層と備えるＣｕ核カラム。
　（８）前記めっき層を被覆するはんだ層をさらに備える上記（７）に記載のＣｕ核カラム。
　（９）α線量が０．０２００ｃｐｈ／ｃｍ２以下である上記（６）～（８）のいずれか一つに記載のＣｕ核カラム。
　（１０）フラックス層が被覆されている上記（６）～（９）のいずれか一つに記載のＣｕ核カラム。
　（１１）上記（１）～（５）のいずれか一つに記載のＣｕカラムを使用したはんだ継手。
（１２）上記（１）～（５）のいずれか一つに記載のＣｕカラムを使用したシリコン貫通電極。
　（１３）上記（６）～（１０）のいずれか一つに記載のＣｕ核カラムを使用したはんだ継手。
　（１４）上記（６）～（１０）のいずれか一つに記載のＣｕ核カラムを使用したシリコン貫通電極。
　本発明によれば、Ｃｕカラムのビッカース硬さが２０ＨＶ以上６０ＨＶ以下であるので、耐落下衝撃性を向上させることができると共に基板間の適切な空間を保持できる。また、Ｃｕカラムの算術平均粗さが０．３μｍ以下であるので、Ｃｕカラムを基板上に配列する際の流動性を向上させることができると共に、実装時におけるＣｕカラムと電極の密着性を向上させることができる。
図１は、本発明に係るＣｕカラムの構成例を示す図である。 図２は、本発明に係るＣｕ核カラムの構成例を示す図である。 図３は、アニーリング処理時における温度と時間の関係を示す図である。
　本発明を以下により詳しく説明する。本明細書において、Ｃｕカラムの組成に関する単位（ｐｐｍ、ｐｐｂ、および％）は、特に指定しない限りＣｕカラムの質量に対する割合（質量ｐｐｍ、質量ｐｐｂ、および質量％）を表す。
　図１に示す本発明に係るＣｕカラム１は、純度が９９．９％以上９９．９９５％以下であり、算術平均粗さが０．３μｍ以下であり、ビッカース硬さが２０ＨＶ以上６０ＨＶ以下である。Ｃｕカラム１は、例えば円柱形状からなる。Ｃｕカラム１は、はんだ付けの温度で溶融せず、一定のスタンドオフ高さ（基板間の空間）を確保できるので、三次元実装や狭ピッチ実装に好適に用いることができる。
　・Ｃｕカラムの算術平均粗さ：０．３μｍ以下
　Ｃｕカラム１の算術平均粗さは、０．３μｍ以下であり、より好ましくは、０．２μｍ以下である。Ｃｕカラム１の算術平均粗さが０．３μｍ以下である場合、Ｃｕカラム１の結晶粒の大きさも小さくなるので、Ｃｕカラム１の表面をより滑らか（平坦）にすることができる。これにより、Ｃｕカラム１をマウンター等により基板上に配列する際のＣｕカラム１の流動性を向上させることができると共に、実装時におけるＣｕカラム１と基板上の電極の密着性の向上を図ることもできる。
　・ビッカース硬さ２０ＨＶ以上６０ＨＶ以下
　本発明に係るＣｕカラム１のビッカース硬さは、６０ＨＶ以下であることが好ましい。ビッカース硬さが６０ＨＶ以下である場合、外部からの応力に対する耐久性が高くなり、耐落下衝撃性が向上すると共にクラックが発生しにくくなるからである。また、三次元実装のバンプや継手の形成時に加圧等の補助力を付与した場合において、柔軟性の高いＣｕカラム１を使用することで、電極潰れ等を引き起こす可能性を低下させることができるからである。
　また、本発明に係るＣｕカラム１のビッカース硬さは、少なくとも一般的なはんだのビッカース硬さ１０～２０ＨＶよりも大きい値であることが必要であり、好ましくは２０ＨＶ以上である。Ｃｕカラム１のビッカース硬さが２０ＨＶ以上である場合、３次元実装において半導体チップ等の自重によるＣｕカラム１自体の変形（潰れ）を防止し、基板間の適切な空間（スタンドオフ高さ）を保持できる。また、Ｃｕピラー等のように、めっき工程が不要であるため、Ｃｕカラム１のビッカース硬さを２０ＨＶ以上とすることにより電極等の狭ピッチ化を実現できる。
　本実施例では、Ｃｕカラム１を製造した後、製造したＣｕカラム１の結晶成長を促進させることによりビッカース硬さが６０ＨＶ以下となるＣｕカラム１を製造する。Ｃｕカラム１の結晶成長を促進させる手段としては、例えば、アニーリング処理が挙げられる。製造後のＣｕカラム１をアニーリング処理すると、Ｃｕ組織が再結晶化して結晶粒が成長することで、Ｃｕカラム１の柔軟性が向上する。一方で、不純物を一定量含有したＣｕカラム１、例えば純度が３Ｎ，４Ｎ，４Ｎ５のＣｕカラム１を使用する場合には、含有した不純物がＣｕカラム１表面において結晶粒の過度な成長を抑制するので結晶粒は一定値以下の大きさに抑えられる。これにより、低ビッカース硬さであって、かつ、低算術平均粗さの二つの条件を両立したＣｕカラムを提供することができる。
　・Ｕ：５ｐｐｂ以下、Ｔｈ：５ｐｐｂ以下
　ＵおよびＴｈは放射性元素であり、ソフトエラーを抑制するにはこれらの含有量を抑える必要がある。ＵおよびＴｈの含有量は、Ｃｕカラム１のα線量を０．０２００ｃｐｈ／ｃｍ２以下とするため、各々５ｐｐｂ以下にする必要がある。また、現在または将来の高密度実装でのソフトエラーを抑制する観点から、ＵおよびＴｈの含有量は、好ましくは、各々２ｐｐｂ以下である。
　・Ｃｕカラムの純度：９９．９％以上９９．９９５％以下
　本発明を構成するＣｕカラム１は純度が９９．９％以上９９．９９５％以下であることが好ましい。Ｃｕカラム１の純度がこの範囲であると、十分な量の不純物元素の結晶核をＣｕ中に確保することができるので、Ｃｕカラム１の算術平均粗さを小さくできる。一方、不純物元素が少ないと、相対的に結晶核となるものが少なく、粒成長が抑制されずにある方向性をもって成長するので、Ｃｕカラム１の算術平均粗さが大きくなってしまう。Ｃｕカラム１の純度の下限値は特に限定されないが、α線量を抑制し、純度の低下によるＣｕカラム１の電気伝導度や熱伝導率の劣化を抑制する観点から、好ましくは９９．９％以上である。不純物元素としては、Ｓｎ、Ｓｂ、Ｂｉ、Ｚｎ、Ａｓ、Ａｇ、Ｃｄ、Ｎｉ、Ｐｂ、Ａｕ、Ｐ、Ｓ、Ｉｎ、Ｃｏ、Ｆｅ、Ｕ、Ｔｈなどが挙げられる。
　・α線量：０．０２００ｃｐｈ／ｃｍ２以下
　本発明を構成するＣｕカラム１のα線量は、０．０２００ｃｐｈ／ｃｍ２以下である。これは、電子部品の高密度実装においてソフトエラーが問題にならない程度のα線量である。α線量は、更なる高密度実装でのソフトエラーを抑制する観点から、より好ましくは０．００１０ｃｐｈ／ｃｍ２以下である。
　・不純物元素の含有量が合計で１ｐｐｍ以上
　本発明を構成するＣｕカラム１は、不純物元素としてＳｎ、Ｓｂ、Ｂｉ、Ｚｎ、Ａｓ、Ａｇ、Ｃｄ、Ｎｉ、Ｐｂ、Ａｕ、Ｐ、Ｓ、Ｉｎ、Ｃｏ、Ｆｅ、Ｕ、Ｔｈなどを含有するが、不純物元素の含有量が合計で１ｐｐｍ以上含有する。なお、不純物元素であるＰｂおよびＢｉの含有量は、極力低い方が好ましい。
　・Ｃｕカラムの上面および底面の径：１～１０００μｍ，Ｃｕカラムの高さ：１～３０００μｍ
　本発明に係るＣｕカラム１の上面および底面の径φは１～１０００μｍであることが好ましく、特にファインピッチに用いる場合は１～３００μがより好ましく、さらに好ましくは１～２００μｍであり、最も好ましいのは１～１００μｍである。そして、Ｃｕカラム１の高さＬは１～３０００μｍであることが好ましく、特にファインピッチに用いる場合は１～３００μがより好ましく、さらに好ましくは１～２００μｍであり、最も好ましいのは１～１００μｍである（図１参照）。Ｃｕカラム１の径φおよび高さＬが上記範囲である場合、端子間を狭ピッチとした実装が可能となるので、接続短絡を抑制することができると共に半導体パッケージの小型化および高集積化を図ることができる。
　また、本発明に係るＣｕカラム１の最表面の算術平均粗さが０．３μｍ以下となるように、はんだめっき層やＮｉめっき層、Ｆｅめっき層、Ｃｏめっき層、イミダゾール化合物を含有する有機被膜層を、Ｃｕカラム１の最表面に被覆してもよい。本発明に係るＣｕカラム１に算術平均粗さが０．３μｍ以下となるような最表面層を設ければ、マウンター等により基板上に配列する際のＣｕカラム１の流動性を向上させ、実装時におけるＣｕカラム１と基板上の電極の密着性の向上を図ることができると共に、Ｃｕカラム１自体のビッカース硬さが２０ＨＶ以上６０ＨＶ以下であるため、Ｃｕカラム１実装後の耐落下衝撃性を向上させ、基板間の適切な空間を保持するという本願の課題解決を達成することができる。
　さらに、本発明に係るＣｕカラム１または、Ｃｕ核カラムの最表面をフラックス層で被覆する場合は、フラックス層ははんだ層やＮｉめっき層に比べて軟性があるので、流動性に大きく影響を与えず、実装時におけるＣｕカラム１と基板上の電極の密着性についても、フラックス層が電極に押し当てられた際、フラックス層は変形するので、フラックス層の算術平均粗さではなく、Ｃｕカラム１または、Ｃｕ核カラム自体の算術平均粗さが関係する。よって、フラックスで被覆したＣｕカラム１または、Ｃｕ核カラムの算術平均粗さが０．３μｍ以下であれば、フラックス層で被覆したＣｕカラム１または、Ｃｕ核カラムの算術平均粗さが０．３μｍを超えていたとしても、基板上に配列する際のＣｕカラム１の流動性はあまり悪化することがなく、実装時におけるＣｕカラム１と基板上の電極の密着性の向上を図ることができると共に、Ｃｕカラム１自体のビッカース硬さが２０ＨＶ以上６０ＨＶ以下であるため、Ｃｕカラム１実装後の耐落下衝撃性を向上させ、基板間の適切な空間を保持するという本願の課題解決を達成することができる。
　例えば、本発明に係るＣｕカラム１の表面を単一の金属または合金からなる金属層により被覆することにより、Ｃｕカラム１および金属層からなるＣｕ核カラムを構成することができる。図２に示すように、Ｃｕ核カラム３は、Ｃｕカラム１と、このＣｕカラム１の表面を被覆するはんだ層２（金属層）とを備えている。はんだ層２の組成は、合金の場合、Ｓｎを主成分とするはんだ合金の合金組成であれば特に限定されない。また、はんだ層２としては、Ｓｎめっき被膜であってもよい。例えば、Ｓｎ、Ｓｎ－Ａｇ合金、Ｓｎ－Ｃｕ合金、Ｓｎ－Ａｇ－Ｃｕ合金、Ｓｎ－Ｉｎ合金、およびこれらに所定の合金元素を添加したものが挙げられる。いずれもＳｎの含有量が４０質量％以上である。また、特にα線量を指定しない場合には、はんだ層２として、Ｓｎ－Ｂｉ合金、Ｓｎ－Ｐｂ合金も使用できる。添加する合金元素としては、例えばＡｇ、Ｃｕ、Ｉｎ、Ｎｉ、Ｃｏ、Ｓｂ、Ｇｅ、Ｐ、Ｆｅなどがある。これらの中でも、はんだ層２の合金組成は、落下衝撃特性の観点から、好ましくはＳｎ－３Ａｇ－０．５Ｃｕ合金である。はんだ層２の厚さは特に制限されないが、好ましくは片側で１００μｍ以下であれば十分である。一般には片側で２０～５０μｍであればよい。
　また、Ｃｕ核カラムにおいて、Ｃｕカラム１の表面とはんだ層２との間に予めＮｉめっき層、Ｆｅめっき層やＣｏめっき層等を設けることができる。これにより、電極への接合時においてはんだ中へのＣｕの拡散を低減することができ、Ｃｕカラム１のＣｕ食われを抑制することができる。Ｎｉめっき層、Ｆｅめっき層やＣｏめっき層等の膜厚は一般的には片側０．１～２０μｍである。
　また、上述したＣｕ核カラムにおいて、はんだ層２のＵおよびＴｈの含有量は、Ｃｕ核カラムのα線量を０．０２００ｃｐｈ／ｃｍ２以下とするため、各々５ｐｐｂ以下である。また、現在または将来の高密度実装でのソフトエラーを抑制する観点から、ＵおよびＴｈの含有量は、好ましくは、各々２ｐｐｂ以下である。
　本発明に係るＣｕ核カラムは、Ｃｕカラム１と、このＣｕカラム１を被覆するＮｉ、ＦｅおよびＣｏから選択される１元素以上からなるめっき層（金属層）により構成することもできる。また、Ｃｕ核カラムを構成するめっき層の表面に、はんだ層を被覆しても良い。はんだ層は、上述したはんだ層と同様のものを採用することができる。
　本発明に係るＣｕカラム１またはＣｕ核カラム３は、電極間を接合するはんだ継手の形成に使用することもできる。本例では、例えば、はんだバンプをプリント基板の電極上に実装した構造をはんだ継手と呼ぶ。はんだバンプとは、半導体チップの電極上にＣｕカラム１が実装された構造である。
　また、本発明に係るＣｕカラム１またはＣｕ核カラム３は、積層される半導体チップ間の電極を接続するためのシリコン貫通電極（through-silicon via：ＴＳＶ）に使用することもできる。ＴＳＶは、シリコンにエッチングで穴を開け、穴の中に絶縁層、その上より貫通導電体の順に形成し、シリコンの上下面を研磨して、貫通導電体を上下面で露出させて製造される。この工程のうち貫通導電体は、従来、Ｃｕ等をめっき法によって穴の中に充填して形成する方法がとられているが、この方法では、シリコン全面をめっき液に浸漬させるため、不純物の吸着や吸湿の恐れがある。そこで本発明のカラムを直接、シリコンに形成された穴に高さ方向に差し込んで、貫通導電体として使用することができる。Ｃｕカラム１をシリコンに差し込む際は、はんだペースト等のはんだ材料によって接合するようにしても良く、またＣｕ核カラムをシリコンに差し込む際は、フラックスのみで接合させることもできる。これにより不純物の吸着や吸湿等の不良を防止でき、めっき工程を省略することによって、製造コストや製造時間も削減することができる。
　また、上述したＣｕカラム１やＣｕ核カラムの最表面をフラックス層により被覆しても良い。上述したフラックス層は、Ｃｕカラム１やはんだ層等の金属表面の酸化を防止すると共にはんだ付け時に金属酸化膜の除去を行う活性剤として作用する化合物を含む１種類あるいは複数種類の成分により構成される。例えば、フラックス層は、活性剤として作用する化合物と、活性補助剤として作用する化合物等からなる複数の成分により構成されていても良い。
　フラックス層を構成する活性剤としては、本発明で要求される特性に応じてアミン、有機酸、ハロゲンのいずれか、複数のアミンの組み合わせ、複数の有機酸の組み合わせ、複数のハロゲンの組み合わせ、単一あるいは複数のアミン、有機酸、ハロゲンの組み合わせが添加される。
　フラックス層を構成する活性補助剤としては、活性剤の特性に応じてエステル、アミド、アミノ酸のいずれか、複数のエステルの組み合わせ、複数のアミドの組み合わせ、複数のアミノ酸の組み合わせ、単一あるいは複数のエステル、アミド、アミノ酸の組み合わせが添加される。
　また、フラックス層は、活性剤として作用する化合物等を、リフロー時の熱から保護するため、ロジンや樹脂を含むものであっても良い。更に、フラックス層は、活性剤として作用する化合物等を、はんだ層に固着させる樹脂を含むものであっても良い。
　フラックス層は、単一あるいは複数の化合物からなる単一の層で構成されても良い。また、フラックス層は、複数の化合物からなる複数の層で構成されても良い。フラックス層を構成する成分は、固体の状態ではんだ層の表面に付着するが、フラックスをはんだ層に付着させる工程では、フラックスが液状またはガス状となっている必要がある。
　このため、フラックス層を構成する成分は、溶液でコーティングするには溶剤に可溶である必要があるが、例えば、塩を形成すると、溶剤中で不溶となる成分が存在する。液状のフラックス中で不溶となる成分が存在することで、沈殿物が形成される等の難溶解性の成分を含むフラックスでは、均一な吸着が困難になる。このため、従来、塩を形成するような化合物を混合して、液状のフラックスを構成することはできない。
　これに対し、本発明のフラックス層を備えたＣｕカラム１やＣｕ核カラムでは、１層ずつフラックス層を形成して固体の状態とし、多層のフラックス層を形成することができる。これにより、塩を形成するような化合物を使用する場合であって、液状のフラックスでは混合できない成分であっても、フラックス層を形成することができる。
　酸化しやすいＣｕカラム１やＣｕ核カラムの表面が、活性剤として作用するフラックス層で被覆されることで、保管時等に、Ｃｕカラム１の表面およびＣｕ核カラムのはんだ層または金属層の表面の酸化を抑制することができる。
　ここで、フラックスと金属の色は一般的に異なり、Ｃｕカラム１等とフラックス層の色も異なることから、色彩度、例えば、明度、黄色度、赤色度でフラックスの吸着量を確認できる。なお、着色を目的に、フラックス層を構成する化合物に色素を混合しても良い。
　上述したＣｕカラム１をイミダゾール化合物を含有する有機被膜により被覆しても良い。これにより、Ｃｕカラム１の最表面のＣｕ層とイミダゾール化合物とが結合することで、Ｃｕカラム１の表面にＯＳＰ被膜（イミダゾール銅錯体）が形成され、Ｃｕカラム１の表面が酸化するのを抑制することができる。
　次に、本発明に係るＣｕカラム１の製造方法の一例を説明する。材料となる銅線を用意し、用意した銅線をダイスを通すことにより伸ばし、その後、切断機により所定の長さで銅線を切断する。このようにして、円柱形状からなる所定の径φおよび所定の長さ（高さＬ）のＣｕカラム１を作製する。なお、Ｃｕカラム１の製造方法は、本実施の形態に限定されることはなく、他の公知の方法を採用しても良い。
　本実施例では、低算術平均粗さおよび低ビッカース硬さのＣｕカラム１を得るために、作製したＣｕカラム１に対してアニーリング処理を施す。アニーリング処理では、アニーリング可能な７００℃にてＣｕカラム１を所定時間加熱し、その後、加熱したＣｕカラム１を長い時間をかけて徐冷する。これにより、Ｃｕカラム１の再結晶を行うことができ、緩やかな結晶成長を促進できる。一方で、Ｃｕカラム１に含有される不純物元素が結晶粒の過度な成長を抑制するので、Ｃｕカラム１の極度な算術平均粗さの低下は起こらない。
　本実施の形態によれば、Ｃｕカラム１のビッカース硬さが２０ＨＶ以上６０ＨＶ以下であるので、耐落下衝撃性を向上させることができると共に基板間の適切な空間を保持できる。また、Ｃｕカラム１の算術平均粗さが０．３μｍ以下であるので、Ｃｕカラム１を基板上に配列する際の流動性を向上させることができると共に、実装時におけるＣｕカラム１と電極の密着性を向上させることができる。
　以下に本発明の実施例を説明するが、本発明はこれらに限定されるものではない。以下に示す実施例では、純度の異なる複数の銅線を使用して複数のＣｕカラムを作製し、これら作製した各Ｃｕカラムのビッカース硬さ、算術平均粗さおよびα線量を測定した。
　・Ｃｕカラムの作製
　純度が９９．９％、９９．９９％、９９．９９５％の銅線を準備した。次に、これら銅線をダイスを通過させることにより、上面および底面の径φが２００μｍとなるように銅線を伸ばし、その後、２００μｍの長さ（高さＬ）となる位置にて銅線を切断することにより、目的とするＣｕカラムを作製した。
・算術平均粗さ
　Ｃｕカラムの算術平均粗さの評価（画像評価）は、ＫＥＹＥＮＣＥ社製のレーザ顕微鏡（型番ＶＫ－９５１０／ＪＩＳＢ０６０１－１９９４対応）を使用して行った。本実施例では、Ｃｕカラムの上面の最も平坦な部分を中心として、１０×１０μｍの範囲で測定した。Ｃｕカラムのｚ軸上（高さ方向）における測定ピッチは０．０１μｍである。このような条件でＣｕカラムの算術平均粗さＲａとして、任意の１０個所の算術平均粗さＲａを測定し、それらの算術平均を真の算術平均粗さとして使用した。
　なお、算術平均粗さＲａは、Ｃｕカラムの底面や周面を測定しても良いし、Ｃｕカラムの上面、底面および周面の各測定値を平均した値を測定値として使用しても良い。また、上記例では、Ｃｕカラムの表面を平坦化するために超音波を利用したが、これに限定されることはない。例えば、Ｃｕカラムの表面を軽く溶解して平滑化加工を促進する溶解性の液体にＣｕカラムを浸漬させることもできる。液体としては、スルホン酸系（メタンスルホン酸など）やカルボン酸系（シュウ酸など）の酸性溶液を用いることができる。
　・ビッカース硬さ
　Ｃｕカラムのビッカース硬さは、「ビッカース硬さ試験－試験方法　ＪＩＳ　Ｚ２２４４」に準じて測定した。装置は、明石製作所製のマイクロビッカース硬度試験器、ＡＫＡＳＨＩ微小硬度計ＭＶＫ－Ｆ　１２００１－Ｑを使用した。
　・α線量
　α線量の測定方法は以下の通りである。α線量の測定にはガスフロー比例計数器のα線測定装置を使用した。測定サンプルは３００ｍｍ×３００ｍｍの平面浅底容器にＣｕカラムを容器の底が見えなくなるまで敷き詰めたものである。この測定サンプルをα線測定装置内に入れ、ＰＲ－１０ガスフローにて２４時間放置した後、α線量を測定した。
　なお、測定に使用したＰＲ－１０ガス（アルゴン９０％－メタン１０％）は、ＰＲ－１０ガスをガスボンベに充填してから３週間以上経過したものである。３週間以上経過したボンベを使用したのは、ガスボンベに進入する大気中のラドンによりα線が発生しないように、ＪＥＤＥＣ（Ｊｏｉｎｔ　Ｅｌｅｃｔｒｏｎ　Ｄｅｖｉｃｅ　Ｅｎｇｉｎｅｅｒｉｎｇ　Ｃｏｕｎｃｉｌ）で定められたＪＥＤＥＣ　ＳＴＡＮＤＡＲＤ－Ａｌｐｈａ　Ｒａｄｉａｔｉｏｎ　Ｍｅａｓｕｒｅｍｅｎｔ　ｉｎ　Ｅｌｅｃｔｒｏｎｉｃ　Ｍａｔｅｒｉａｌｓ　ＪＥＳＤ２２１に従ったためである。
　・実施例１
　純度９９．９％の銅線を使用して製造したＣｕカラムをカーボン製バットに入れた後、このバットを連続コンベア式電気抵抗加熱炉に搬入してアニーリング処理を行った。このときの、アニーリング条件を図３に示す。なお、炉内は、Ｃｕカラムの酸化を防止するために窒素ガス雰囲気にした。室温は２５℃とした。
　アニーリング条件としては、図３に示すように、室温から７００℃に加熱する昇温時間を６０分間とし、７００℃で保持する保持時間を６０分間とし、７００℃から室温に冷却する冷却時間を１２０分間とした。炉内の冷却は、炉内に設置した冷却ファンを用いて行った。次に、アニーリング処理が施されたＣｕカラムを希硫酸に浸漬させることで酸処理を行った。これは、アニーリング処理によりＣｕカラム表面に形成された酸化膜を除去するためである。このようにして得られたＣｕカラムのアニーリング処理前後におけるビッカース硬さ、算術平均粗さおよびα線量を下記表１に示す。
　・実施例２
　実施例２では、純度が９９．９９％の銅線により作製されたＣｕカラムに対し、実施例１と同様の方法により、アニーリング処理を行うと共に酸化膜除去処理を行った。そして、得られたＣｕカラムのビッカース硬さ、算術平均粗さおよびα線量を測定した。これらの測定結果を下記表１に示す。
　実施例３では、純度が９９．９９５％の銅線により作製されたＣｕカラムに対し、実施例１と同様の方法により、アニーリング処理を行うと共に酸化膜除去処理を行った。そして、得られたＣｕカラムのビッカース硬さ、算術平均粗さおよびα線量を測定した。これらの測定結果を下記表１に示す。
　・比較例１
　比較例１では、純度が９９．９％の銅線により作製されたＣｕカラムのビッカース硬さ、算術平均粗さおよびα線量をそれぞれ測定した。これらの測定結果を下記表１に示す。
　・比較例２
　比較例２では、純度が９９．９９％の銅線により作製されたＣｕカラムのビッカース硬さ、算術平均粗さおよびα線量をそれぞれ測定した。これらの測定結果を下記表１に示す。
　・比較例３
　比較例３では、純度が９９．９９５％の銅線により作製されたＣｕカラムのビッカース硬さ、算術平均粗さおよびα線量をそれぞれ測定した。これらの測定結果を下記表１に示す。
　・比較例４
　比較例４では、純度が９９．９９５％を超える銅線により作製されたＣｕカラムのビッカース硬さ、算術平均粗さおよびα線量をそれぞれ測定した。これらの測定結果を下記表１に示す。
　・比較例５
　比較例５では、純度が９９．９９５％を超える銅線により作製されたＣｕカラムに対し、実施例１と同様の方法により、アニーリング処理を行うと共に酸化膜除去処理を行った。そして、得られたＣｕカラムのビッカース硬さ、算術平均粗さおよびα線量を測定した。これらの測定結果を下記表１に示す。
Figure JPOXMLDOC01-appb-T000001
　表１に示すように、実施例１ではＣｕカラムの算術平均粗さが０．１０μｍとなり、実施例２ではＣｕカラムの算術平均粗さが０．１７μｍとなり、実施例３ではＣｕカラムの算術平均粗さが０．２８μｍとなり、何れの実施例でも算術平均粗さが０．３μｍ以下となった。また、実施例１ではＣｕカラムのビッカース硬さが５７．１となり、実施例２ではＣｕカラムのビッカース硬さが５２．９となり、実施例３ではＣｕカラムのビッカース硬さが５０．２となり、何れの実施例でもビッカース硬さが２０ＨＶ以上６０ＨＶ以下となった。これらの結果から、製造時のＣｕカラムに対してアニーリング処理を施すことにより、低ビッカース硬さでかつ低算術平均粗さの両方の物性を有するＣｕカラムが得られることが確認された。
　一方、アニーリング処理をＣｕカラムに施さない比較例１～４では、Ｃｕカラムの算術平均粗さについては０．３μｍ以下となったが、ビッカース硬さが６０ＨＶ超となり、ビッカース硬さが２０ＨＶ以上６０ＨＶ以下に関する条件を満たさないことが確認された。また、比較例５では、Ｃｕカラムのビッカース硬さは２０ＨＶ以上６０ＨＶ以下の範囲内となったが、算術平均粗さが０．３μｍ超となった。これにより、作製時のＣｕカラムにアニーリング処理を施した場合でも高純度のＣｕカラムを使用した場合には、算術平均粗さが０．３μｍ以下に関する条件を満たさないことが確認された。
　また、実施例１～３のＣｕカラムでは、Ｃｕカラムのα線量が０．００１０ｃｐｈ／ｃｍ２以下未満となり、これは＜０．０２００ｃｐｈ／ｃｍ２を満たし、さらには＜０．００１０ｃｐｈ／ｃｍ２を満たす結果であることが確認された。
　次に、上述した実施例１のアニーリング処理後のＣｕカラムの表面にＳｎ－３Ａｇ－０．５Ｃｕ合金からなるはんだめっき層を被覆してＣｕ核カラムを作製し、このＣｕ核カラムとＣｕ核カラム製造時に使用しためっき液をそのまま３００ｃｃのビーカーに採取して超音波機に掛けて超音波を６０分間照射した。超音波機は市販の超音波洗浄機（アズワン社製ＵＳ－ＣＬＥＡＮＥＲ）を使用して、出力８０Ｗ、４０ｋＨｚの周波数で行った。６０分経過後イオン交換水で洗浄し、その後温風乾燥させて、作製したＣｕ核カラムの算術平均粗さおよびα線量をそれぞれ測定した。実施例１～３と同様に、Ｃｕ核カラムの算術平均粗さが０．３μｍ以下となった。また、実施例１のＣｕカラムの表面にＮｉめっき層を被覆したＣｕ核カラムや、実施例１のＣｕカラムの表面にＮｉめっき層およびはんだめっき層を順番に被覆したＣｕ核カラムについても、前記と同じ条件で超音波処理を行い、算術平均粗さおよびα線量をそれぞれ測定した所、実施例１～３と同様に、Ｃｕ核カラムの算術平均粗さが０．３μｍ以下となった。また、何れの場合でも、α線量が０．００１０ｃｐｈ／ｃｍ２未満となり、これは＜０．０２００ｃｐｈ／ｃｍ２を満たし、さらには＜０．００１０ｃｐｈ／ｃｍ２を満たす結果であることが確認された。
　なお、上記Ｎｉめっき層に代えて、Ｆｅめっき層、Ｃｏめっき層を被覆した場合でも、Ｎｉめっき層を被覆したＣｕ核カラムと同様に、算術平均粗さが０．３μｍ以下となった。また、α線量も０．００１０ｃｐｈ／ｃｍ２未満となり、これは＜０．０２００ｃｐｈ／ｃｍ２を満たし、さらには＜０．００１０ｃｐｈ／ｃｍ２を満たす結果であることが確認された。
　次に、上述した実施例１のアニーリング処理後のＣｕカラムの表面にフラックスを被覆してフラックスコートＣｕカラムを作製し、作製したフラックスコートＣｕカラムの算術平均粗さおよびα線量をそれぞれ測定した。実施例１～３と同様に、フラックスコートＣｕカラムでは、算術平均粗さが０．３μｍ以下となった。さらに、フラックスコートＣｕカラムにおいても、α線量が０．００１０ｃｐｈ／ｃｍ２未満となり、これは＜０．０２００ｃｐｈ／ｃｍ２を満たし、さらには＜０．００１０ｃｐｈ／ｃｍ２を満たす結果であることが確認された。
　また、上述したＣｕ核カラムの表面にフラックスを被覆したフラックスコートＣｕ核カラムについても、フラックスコートＣｕカラムと同様に、算術平均粗さが０．３μｍ以下となった。さらに、フラックスコートＣｕ核カラムにおいても、α線量が０．００１０ｃｐｈ／ｃｍ２未満となり、これは＜０．０２００ｃｐｈ／ｃｍ２を満たし、さらには＜０．００１０ｃｐｈ／ｃｍ２を満たす結果であることが確認された。
　別途、実施例１のアニーリング処理後のＣｕカラムの表面にイミダゾール化合物を含有する有機被膜を被覆してＯＳＰ処理Ｃｕカラムを作製し、作製したＯＳＰ処理Ｃｕカラムの算術平均粗さおよびα線量をそれぞれ測定した。実施例１～３と同様に、ＯＳＰ処理Ｃｕカラムでは、算術平均粗さが０．３μｍ以下となり、α線量が０．００１０ｃｐｈ／ｃｍ２以下となることが確認された。
　なお、本発明のカラムは実施例と比較例において、円柱状のものを挙げたが、形状が円柱に限定されるわけではなく、三角柱や四角柱等、基板に直接、接する上下面が３辺以上で構成されている柱体ならば本発明の効果を得ることができる。

Claims (14)

  1. 　純度が９９．９％以上９９．９９５％以下であり、
    　算術平均粗さが０．３μｍ以下であり、
    　ビッカース硬さが２０ＨＶ以上６０ＨＶ以下であるＣｕカラム。
  2. 　α線量が０．０２００ｃｐｈ／ｃｍ２以下である
    　請求項１に記載のＣｕカラム。
  3. 　上面および底面の径が１～１０００μｍであり、高さが１～３０００μｍである柱体からなる請求項１または２に記載のＣｕカラム。
  4. 　フラックス層が被覆されている請求項１～３のいずれか１項に記載のＣｕカラム。
  5. 　イミダゾール化合物を含有する有機被膜が被覆されている請求項１～３のいずれか１項に記載のＣｕカラム。
  6. 　請求項１～４のいずれか一項に記載のＣｕカラムと、
    　前記Ｃｕカラムを被覆するはんだ層とを備えるＣｕ核カラム。
  7. 　請求項１～４のいずれか一項に記載のＣｕカラムと、
    　前記Ｃｕカラムを被覆するＮｉ、ＦｅおよびＣｏから選択される１元素以上からなるめっき層と備えるＣｕ核カラム。
  8. 　前記めっき層を被覆するはんだ層をさらに備える請求項７に記載のＣｕ核カラム。
  9. 　α線量が０．０２００ｃｐｈ／ｃｍ２以下である
    　請求項６～８のいずれか一項に記載のＣｕ核カラム。
  10. 　フラックス層が被覆されている請求項６～９のいずれか１項に記載のＣｕ核カラム。
  11. 　請求項１～５のいずれか１項に記載のＣｕカラムを使用したはんだ継手。
  12. 　請求項１～５のいずれか１項に記載のＣｕカラムを使用したシリコン貫通電極。
  13. 　請求項６～１０のいずれか１項に記載のＣｕ核カラムを使用したはんだ継手。
  14. 　請求項６～１０のいずれか１項に記載のＣｕ核カラムを使用したシリコン貫通電極。
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US20170287862A1 (en) 2017-10-05
CN106688085A (zh) 2017-05-17
TW201630485A (zh) 2016-08-16
KR102315758B1 (ko) 2021-10-20
PT3193360T (pt) 2020-08-25
US10811376B2 (en) 2020-10-20
TWI566650B (zh) 2017-01-11
EP3193360A1 (en) 2017-07-19
EP3193360B1 (en) 2020-07-01
KR20170042372A (ko) 2017-04-18
JP5733486B1 (ja) 2015-06-10
JPWO2016038686A1 (ja) 2017-04-27
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