TW201630485A - 銅柱、銅核柱、焊接接頭以及矽貫通電極 - Google Patents

銅柱、銅核柱、焊接接頭以及矽貫通電極 Download PDF

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Publication number
TW201630485A
TW201630485A TW104128958A TW104128958A TW201630485A TW 201630485 A TW201630485 A TW 201630485A TW 104128958 A TW104128958 A TW 104128958A TW 104128958 A TW104128958 A TW 104128958A TW 201630485 A TW201630485 A TW 201630485A
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Taiwan
Prior art keywords
copper
column
pillar
less
layer
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TW104128958A
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English (en)
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TWI566650B (zh
Inventor
Hiroyoshi Kawasaki
Takahiro Roppongi
Daisuke Soma
Isamu Sato
Yuji Kawamata
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Senju Metal Industry Co
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Publication of TW201630485A publication Critical patent/TW201630485A/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/10—Electroplating with more than one layer of the same or of different metals
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B22—CASTING; POWDER METALLURGY
    • B22F—WORKING METALLIC POWDER; MANUFACTURE OF ARTICLES FROM METALLIC POWDER; MAKING METALLIC POWDER; APPARATUS OR DEVICES SPECIALLY ADAPTED FOR METALLIC POWDER
    • B22F1/00—Metallic powder; Treatment of metallic powder, e.g. to facilitate working or to improve properties
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/02—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
    • B23K35/0222—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape for use in soldering, brazing
    • B23K35/0227—Rods, wires
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24—Selection of soldering or welding materials proper
    • B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24—Selection of soldering or welding materials proper
    • B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
    • B23K35/262—Sn as the principal constituent
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
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    • B23K35/30—Selection of soldering or welding materials proper with the principal constituent melting at less than 1550 degrees C
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
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    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24—Selection of soldering or welding materials proper
    • B23K35/30—Selection of soldering or welding materials proper with the principal constituent melting at less than 1550 degrees C
    • B23K35/302—Cu as the principal constituent
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/36—Selection of non-metallic compositions, e.g. coatings, fluxes; Selection of soldering or welding materials, conjoint with selection of non-metallic compositions, both selections being of interest
    • B23K35/3612—Selection of non-metallic compositions, e.g. coatings, fluxes; Selection of soldering or welding materials, conjoint with selection of non-metallic compositions, both selections being of interest with organic compounds as principal constituents
    • B23K35/3615—N-compounds
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B15/00—Layered products comprising a layer of metal
    • B32B15/01—Layered products comprising a layer of metal all layers being exclusively metallic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B15/00—Layered products comprising a layer of metal
    • B32B15/20—Layered products comprising a layer of metal comprising aluminium or copper
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C13/00—Alloys based on tin
    • C—CHEMISTRY; METALLURGY
    • C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
    • C22C—ALLOYS
    • C22C9/00—Alloys based on copper
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/10—Electroplating with more than one layer of the same or of different metals
    • C25D5/12—Electroplating with more than one layer of the same or of different metals at least one layer being of nickel or chromium
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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    • B32B2255/00—Coating on the layer surface
    • B32B2255/06—Coating on the layer surface on metal layer
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    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
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    • B32B2255/20—Inorganic coating
    • B32B2255/205—Metallic coating
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    • H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B1/00—Conductors or conductive bodies characterised by the conductive materials; Selection of materials as conductors
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Abstract

提供維氏硬度低，且算術平均粗度小的銅柱、銅核柱、焊接接頭以及矽貫通電極。 與本發明有關之銅柱1，純度為99.9%以上99.995%以下，算術平均粗度為0.3μm以下，維氏硬度為20HV以上60HV以下。銅柱1，在焊接的溫度不會熔融，而可確保一定的浮高(基板間的空間)，因此適合用於三次元實裝或窄間距實裝。

Description

銅柱、銅核柱、焊接接頭以及矽貫通電極
本發明係關於銅柱、銅核柱、焊接接頭以及矽貫通電極。
近年來，由於小型情報機器的發達，所搭載之電子零件小型化也急速地進行。電子零件，為了對應由於小型化的要求之連接端子之狹小化或實裝面積之縮小化，在反面設置了電極之球柵陣列封裝(以下，稱為「BGA」)被應用。
應用了BGA之電子零件，例如有半導體封裝。在半導體封裝，具有電極之半導體晶片係以樹脂封裝。在半導體晶片的電極上，形成了焊料凸塊。此焊料凸塊，係藉由將焊料球接合於半導體晶片之電極而形成。應用了BGA的半導體封裝，係藉由由於加熱而熔融之焊料凸塊與印刷電路板之導電性焊墊接合，而搭載於印刷電路基板。又，為了對應更高密度實裝之要求，半導體封裝在高度方向堆疊之3次元高密度實裝也被開發。
然而，若將BGA應用於被3次元高密度實裝之半導體封裝，有由於半導體封裝之自重而焊料球被壓扁之情況。若發生如此情況，則變得無法在基板間保持適當的空間。
因此，使用軟焊膏在電子零件之電極上電氣上接 合了銅球之焊料凸塊被檢討。使用銅球所形成之焊料凸塊，在電子零件被實裝至印刷電路基板時，即使半導體封裝之重量施加在焊料凸塊，仍可藉由在焊料的熔點不會熔融之銅球來支撐半導體封裝。因此，不會由於半導體封裝之自重而焊料凸塊被壓扁。
然而，使用上述銅球之情況會有以下問題。在銅球，基板間的浮高為銅球的球徑，因此為了實現所要求之浮高，銅球的寬度變大，而有無法對應窄間距化實裝之情況。又，在一般的半導體封裝中，使用黏晶用之焊接材料將半導體晶片接合於導線架之晶粒座電極部後，以樹脂封裝。將此半導體封裝實裝於印刷電路基板時，係使用不同於黏晶用的焊接材料之實裝用的焊接材料。此理由，係為了不使在將半導體封裝實裝於基板時之實裝用的焊接材料之加熱條件造成黏晶用之焊接材料熔出。如此，黏晶用之焊接材料與實裝用之焊接材料使用不同材料之情況，由於各基板之熱膨脹係數產生差異，因此會由於環境溫度等之變化，在與焊料凸塊之接合部產生應力(熱應力)，而有TCT(溫度循環試驗)信賴性低下之情況。
因此，近年來，可較焊料球窄間距化，且可期待TCT信賴性之提升之銅柱被開發。又，比較同一間距之銅球與銅柱之情況，由於柱狀較球狀更能安定地支撐電極間，因此在這點，銅柱的採用也被檢討。例如，在專利文獻1至5，記載著由銅或焊料等所形成之柱狀的圓柱。在專利文獻6，記載著維氏應度55HV以下之為了接合陶瓷基板與玻璃環氧基板之銅柱。
【先前技術文獻】 【專利文獻】
專利文獻1：日本專利特開平7-66209號公報
專利文獻2：日本專利第3344295號公報
專利文獻3：日本專利特開2000-232119號公報
專利文獻4：日本專利第4404063號公報
專利文獻5：日本專利特開2009-1474號公報
專利文獻6：日本專利特開2011-176124號公報
然而，根據上述專利文獻1至6，雖不僅可對應窄間距化實裝，且可抑制熱應力，但關於銅柱之算術平均粗度完全沒有開示。因此，使用專利文獻1至6之銅柱之情況，有發生將銅柱配列於基板上時銅柱的流動性低下，或是在實裝時銅柱與電極之密著性低下等之問題之情況。
因此本發明，係為了解決上述課題，以提供維氏硬度低，且算術平均粗度小之銅柱、銅核柱、焊接接頭以及矽貫通電極為目的。
本發明者們，對於銅柱進行了選定。發現若銅柱之維氏硬度為20HV以上60HV，且算術平均粗度為0.3μm以下，則可得到為了解決本發明之課題之較佳的銅柱等。
在此，本發明係如下述。
(1)一種銅柱，純度為99.9%以上99.995%以下，算術平均粗度為0.3μm以下，維氏硬度為20HV以上60HV以下。
(2)如上述(1)所記載之銅柱，其中，α線量為0.0200cph/cm2以下。
(3)如上述(1)或(2)所記載之銅柱，其中，係由上面及底面之直徑為1~1000μm，高度1~3000μm之柱體所形成。
(4)如上述(1)~(3)所記載之任一項之銅柱，其中，係被覆了助焊劑層。
(5)如上述(1)~(3)所記載之任一項之銅柱，其中，係被覆了含有咪唑化合物之有機覆膜。
(6)一種銅核柱，具有上述(1)~(4)所記載之任一項之銅柱，與被覆前述銅核柱之焊料層。
(7)一種銅核柱，具有上述(1)~(4)所記載之任一項之銅柱，與被覆前述銅核柱之從Ni、Fe、Co所選出之1種元素以上所形成之電鍍層。
(8)如上述(7)所記載之銅核柱，其中，更具有被覆前述電鍍層之焊料層。
(9)如上述(6)~(8)所記載之任一項之銅核柱，其中，α線量為0.0200cph/cm2以下。
(10)如上述(6)~(9)所記載之任一項之銅核柱，其中，係被覆了助焊劑層。
(11)一種焊接接頭，使用了上述(1)~(5)所記載之任一項之銅柱。
(12)一種矽貫通電極，使用了上述(1)~(5)所記載之 任一項之銅柱。
(13)一種焊接接頭，使用了上述(6)~(10)所記載之任一項之銅核柱。
(14)一種矽貫通電極，使用了上述(6)~(10)所記載之任一項之銅核柱。
若根據本發明，由於銅柱之維氏硬度為20HV以上60HV以下，因此不僅可提升耐落下衝擊性，且可保持基板間之適當的空間。又，由於銅柱之算術平均粗度為0.3μm以下，因此不僅可提升將銅柱配列在基板上時之流動性，且可提升在實裝時之銅柱與電極之密著性。
1‧‧‧銅柱
ψ‧‧‧直徑
L‧‧‧高度
2‧‧‧焊料層
3‧‧‧銅核柱
第1圖係表示與本發明有關之銅柱之構成例之圖。
第2圖係表示與本發明有關之銅核柱之構成例之圖。
第3圖係表示在退火處理時溫度與時間之關係之圖。
以下，更詳細說明本發明。在本說明書中，關於銅柱之組成之單位(ppm、ppb、以及%)，若沒有特別指定，則表示對於銅柱之質量之比率(質量ppm、質量ppb以及質量%)。
第1圖所示之與本發明有關之銅柱1，純度為99.9%以上99.995%以下，算術平均粗度為0.3μm以下，維氏硬度為20HV以上60HV以下。銅柱1，例如為由圓柱形狀所形成。銅柱1，由於在焊接的溫度不會熔融，可確保一定的浮 高(基板間的空間)，因此可適合用於三次元實裝或窄間距實裝。
．銅柱之算術平均粗度：0.3μm以下
銅柱1之算術平均粗度為0.3μm以下，而以0.2μm以下更佳。銅柱1之算術平均粗度若為0.3μm以下之情況，則由於銅柱1之結晶粒的大小也變小，因此可使銅柱1之表面更平滑(平坦)。藉由此，不僅可在將銅柱1藉由置件機等配列在基板上時之銅柱1之流動性提升，且可得到在實裝時銅柱1與基板上的電極之密著性的提升。
．維氏硬度20HV以上60HV以下
與本發明有關之銅柱1之維氏硬度，以在60HV以下為佳。這是由於若維氏硬度在60HV以下之情況，對於來自外部的應力之耐久性變高，不僅耐落下衝擊性提升且不容易發生裂痕之故。又，在三次元實裝之凸塊或接頭之形成時施以加壓等之輔助力的情況，藉由使用柔軟性高之銅柱1，可使引起電極壓扁等之可能性變低之故。
又，與本發明有關之銅柱1之維氏硬度，至少必需為較一般的焊料球之維氏硬度10~20HV大之值，而以20HV以上為佳。銅柱1之維氏硬度若在20HV以上，則在3次元實裝時可防止由於半導體晶片等之自重造成之銅柱1本身的變形(壓扁)，而可保持基板間之適當的空間(浮高)。又，如銅圓柱等，由於不需要電鍍工程，因此藉由使銅柱1之維氏硬度在20HV以上，可實現電極等之窄間距化。
在本實施例，製造銅柱1後，藉由促進所製造之銅柱1的結晶成長，而製造維氏硬度為60HV以下之銅柱1。 作為促進銅柱1之結晶成長的手段，例如，可舉出退火處理。若將所製造之銅柱1退火處理，則由於銅組織再結晶化而結晶粒成長，銅柱1之柔軟性提升。另一方面，含有一定量之不純物之銅柱1，例如使用純度為3N、4N、4N5之銅柱1之情況，所含有之不純物在銅柱1表面抑制結晶粒之過度的成長，因此結晶粒的大小可控制在一定值以下之大小。藉由此，可提供兼顧低維氏硬度，且低算術平均粗度之二個條件之銅柱。
．鈾：5ppb以下，釷：5ppb以下
鈾以及釷為放射性元素，為了抑制軟錯誤而有必要抑制其含有量。鈾以及釷之含有量，為了使銅柱1之α線量為0.0200cph/cm2以下，而必須使其各為5ppb以下。又，從抑制在現在或將來之高密度實裝之軟錯誤之觀點來看，鈾以及釷之含有量，各在2ppb以下為佳。
．銅柱純度：99.9%以上99.995%以下
構成本發明之銅柱1之純度以在99.9%以上99.995%以下為佳。若使銅柱1之純度在此範圍，可在銅中確保充分的量之不純物元素之結晶核，因此可使銅柱1之算術平均粗度小。另一方面，若不純物元素少，則相對的成為結晶核之物也少，粒成長無法被抑制而會具有特定的方向性而成長，因此銅柱1之算術平均粗度會變大。銅柱1之純度的下限值雖沒有特別限定，但從抑制α線量，與由於純度的低下造成之銅柱1的電氣傳導度或熱傳導率之劣化的觀點來看，以在99.9%以上為佳。做為不純物，可考慮錫、銻、鉍、鋅、砷、銀、鎘、鎳、鉛、金、磷、硫、銦、鈷、鐵、鈾、釭等。
．α線量：0.0200cph/cm2以下
構成本發明之銅柱1之α線量，以在0.0200cph/cm2以下為佳。此為在電子零件之高密度實裝中軟錯誤不會成為問題之程度的α線量。α線量，從抑制在更高密度實裝之軟錯誤的觀點來看，以在0.0010cph/cm2以下更佳。
．不純物元素之含有量合計為1ppm以上
構成本發明之銅柱1，含有錫、銻、鉍、鋅、砷、銀、鎘、鎳、鉛、金、磷、硫、銦、鈷、鐵、鈾、釷等做為不純物元素，不純物元素之含有量合計含有1ppm以上。又，不純物元素之鉛及鉍的含有量愈低愈好。
．銅柱之上面及底面的直徑：1~1000μm，銅柱之高度：1~3000μm
與本發明有關之銅柱1之上面及底面的直徑ψ為1~1000μm為佳，特別用於窄間距之情況以1~300μm較佳，而以1~200μm更佳，1~100μm最佳。然後，銅柱1之高度L以1~3000μm為佳，特別用於窄間距之情況以1~300μm較佳，而以1~200μm更佳，1~100μm最佳(參照第1圖)。若銅柱1之直徑ψ及高度L在上述範圍，則使端子間窄間距之實裝變的可能，不僅可抑制連接短路，且可求得半導體封裝之小型化及高積體化。
又，為使與本發明有關之銅柱1之最表面的算術平均粗度為0.3μm以下，也可將銅柱1之最表面被覆焊料電鍍層或鎳電鍍層、鐵電鍍層、鈷電鍍層、含有咪唑化合物之有機覆膜層。只要使算術平均粗度在0.3μm以下而在與本發明有關 之銅柱1設置最表面層，不僅可在藉由置件機等在基板上配列時使銅柱1之流動性提升，可求得使在實裝時銅柱1與基板上之電極的密著性提高，且由於銅柱1本身之維氏硬度為20HV以上60HV以下，因此可達成使銅柱1實裝後之耐落下衝擊性提高，保持基板間之適當的空間之本申請書之課題解決。
更且，將與本發明有關之銅柱1或銅核柱之最表面以助焊劑層被覆之情況，助焊劑層由於相較於焊料層或鎳電鍍層具有軟性，因此對於流動性不會造成很大的影響，關於實裝時銅柱1與基板上的電極之密著性，也由於助焊劑層被電極擠壓時，助焊劑層會變形，因此並非與助焊劑層之算術平均粗度，而是與銅柱1或是銅核柱本身之算術平均粗度有關。因此，以助焊劑層被覆之銅柱1或是銅核柱之算術平均粗度若在0.3μm以下，則即使以助焊劑層被覆後之銅柱1或銅核柱之算術平均粗度超過0.3μm，配列在基板上時之銅柱1的流動性也不太會惡化，不僅可求得在實裝時銅柱1與基板上之電極的密著性之提升之同時，且由於銅柱1本身之維氏硬度為20HV以上60HV以下，因此可達成使銅柱1實裝後之耐落下衝擊性提高，保持基板間之適當的空間之本申請書之課題解決。
例如，藉由將與本發明有關之銅柱1之表面以單一的金屬或合金所形成之金屬層被覆，可構成銅柱1及金屬層所形成之銅核柱。如第2圖所示，銅核柱3係具有銅柱1，與被覆此銅柱1之表面之焊料層2(金屬層)。焊料層2之組成，若為合金的情況，只要是以錫為主成分之焊料合金之合金組成即可而沒有特別限定。又，做為焊料層2，也可為錫電鍍覆膜。 例如，可舉出錫、錫-銀合金、錫-銅合金、錫-銀-銅合金、錫-銦合金，以及對於這些添加既定的合金元素者。錫之含有量皆在40質量%以上。又，在沒有特別指定α線量之情況，也可使用錫-鉍合金、錫-鉛合金做為焊料層2。做為添加的合金元素，例如有銀、銅、銦、鎳、鈷、銻、鍺、鉛、鐵等。在其中，焊料層2之合金組成，以落下衝擊特性的觀點來看，以錫-3銀-0.5銅合金為佳。焊料層2之厚度雖沒有特別限制，但較佳的情況為單側在100μm以下即充分。一般而言單側為20~50μm即可。
又，在銅核柱中，可在銅柱1之表面與焊料層2之間預先設置鎳電鍍層、鐵電鍍層或鈷電鍍層等。藉由此，可使在電極之接合時之對於焊料中之銅的擴散減速，可抑制銅柱1之銅蝕。鎳電鍍層、鐵電鍍層或鈷電鍍層等之膜厚一般而言為單側0.1~20μmμm
又，在上述之銅核柱中，為了使銅核柱之α線量為0.0200cph/cm2以下，焊料層2之鈾及釷的含有量各為5ppb以下。又，從抑制在現在或將來之高密度實裝之軟錯誤之觀點來看，鈾以及釷之含有量，各在2ppb以下為佳。
與本發明有關之銅核柱，也可藉由銅柱1，與被覆此銅柱1之從鎳、鐵及鈷所選擇之1元素以上所形成之電鍍層(金屬層)來構成。又，在構成銅核柱之電鍍層之表面，也可被覆焊料層。焊料層，可採用與上述之焊料層相同之物。
與本發明有關之銅柱1或銅核柱3，也可使用於接合電極間之焊接接頭之形成。在本例，例如，係將焊料凸塊實 裝於印刷電路基板之電極上之構造稱為焊接接頭。焊接接頭，係指銅柱1實裝於半導體晶片之電極上之構造。
又，與本發明有關之銅柱1或銅核柱3，也可使用於為了連接層積之半導體晶片間之電極之矽貫通電極(through-silicon via：TSV)。TSV，係在矽以蝕刻開孔，依照在孔中形成絕緣層，從其上形成貫通導電體之順序來形成，將矽之上下面研磨，使貫通導電體在上下面露出而製造。此工程中，貫通導電體以往多採用將銅等藉由電鍍法充填於孔中而形成方法，但在此方法，由於需使矽全面浸漬於電鍍液，而有不純物之吸附或吸濕之虞。因此，將本發明之柱直接插入形成在矽之孔的高度方向，而可做為貫通導電體使用。將銅柱1插入矽時，可藉由軟焊膏等之焊接材料來接合，也可在將銅核柱插入矽時，僅藉由助焊劑來接合。藉由此，可防止不純物之吸著或吸濕等之不良，由於省略電鍍工程，因此也可削減製造成本或製造時間。
又，也可將上述銅柱1或銅核柱之最表面藉由助焊劑被覆。上述助焊劑層，係含有1種或複數種類之在防止銅柱1或焊料層等之金屬表面之氧化之同時，在焊接時做為進行金屬氧化膜之除去之活性劑作用之化合物之成分而構成。例如，助焊劑層，也可藉由做為活性劑作用之化合物與做為活性補助劑作用之化合物等所形成之複數的成分來構成。
做為構成助焊劑層之活性劑，可根據本發明所要求之特性而添加胺、有機酸、鹵素之任一種、複數之胺的組合、複數之有機酸的組合、複數之鹵素的組合、單一或複數的胺、 有機酸、鹵素的組合。
做為構成助焊劑層之活性補助劑，可根據活性劑的特性而添加上述酯、酰胺、氨基酸之任一種、複數之酯的組合、複數之酰胺的組合、複數之氨基酸的組合、單一或複數之酯、酰胺、氨基酸之組合。
又，助焊劑層，為了保護做為活性劑而作用之化合物等在回焊時不受到熱影響，也可為含有松香或樹脂之物。更且，助焊劑層，也可為含有將做為活性劑而作用之化合物等固定於焊料層之樹脂之物。
助焊劑層，也可為單一或複數的化合物所形成之單一的層所構成。又，助焊劑層，也可為複數之化合物所形成之複數的層所構成。構成助焊劑層之成分，雖以固體的狀態附著於焊料層之表面，但在使助焊劑附著於焊料層之工程，助焊劑必須呈液狀或汽狀。
因此，構成助焊劑層之成分，為了以溶液覆層，必須是對於溶劑為可溶，例如，若形成鹽，則在溶劑中會存在成為不溶之成分。液狀之助焊劑中由於存在成為不溶之成分，在含有會形成沉澱物等之難溶解性之成分之助焊劑，難以均一地吸著。因此，以往，無法混合會形成鹽之化合物來構成液狀之助焊劑。
對於此，本發明之具有助焊劑層之銅柱1或銅核柱，一層一層地形成助焊劑層成為固體的狀態，而可形成多層之助焊劑層。藉由此，在使用會形成鹽之化合物之情況，即使為在液狀的助焊劑無法混合之成分，也可形成助焊劑層。
藉由以做為活性劑作用之助焊劑層被覆容易氧化之銅柱1或銅核柱表面，可抑制在保管時等，銅柱1之表面及銅核柱之焊料層或金屬層之表面的氧化。
在此，助焊劑與金屬的顏色一般而言相異，由於銅柱1等與助焊劑層之顏色也不同。因此可以色彩度，例如明度、黃色度、紅色度來確認助焊劑之吸著量。又，也可以著色為目的，在構成助焊劑層之化合物中混合色素。
上述銅柱1也可以含有咪唑化合物之有機覆膜來被覆。藉由此，由於銅柱1之最表面的銅層與咪唑化合物結合，在銅柱1之表面上形成OSP覆膜(咪唑銅配合物)，而可抑制銅柱1之表面氧化。
接著，說明與本發明有關之銅柱1之製造方法之一例。準備做為材料之銅線，將所準備的銅線藉由通過擠出模具而拉伸，之後，藉由切斷機以既定的長度切斷銅線。如此，製作由圓柱形狀所形成之既定的直徑ψ及既定長度(高度L)之銅柱1。又，銅柱1之製造方法，並非限定於本實施形態，也可採用其他眾所周知之方法。
在本實施例，為了得到低算術平均粗度及低維氏硬度之銅柱1，對於所製作之銅柱1施以退火處理。在退火處理，係將銅柱1在可退火之700℃加熱既定時間，之後，將所加熱之銅柱1花長時間徐冷。藉由此，可進行銅柱1之再結晶，而可促進緩慢之結晶成長。另一方面，由於銅柱1所含有之不純物元素會抑制結晶粒之過度的成長，因此不會發生銅柱1之極度地算術平均粗度的低下。
若根據本實施形態，由於銅柱1之維氏硬度為20HV以上60HV以下，因此不僅可提升耐落下衝擊性，且可保持基板間之適當的空間。又，由於銅柱1之算術平均粗度為0.3μm以下，因此不僅可提升將銅柱配列在基板上時之流動性，且可提升在實裝時之銅柱1與電極之密著性。
【實施例】
以下說明本發明之實施例，但本發明並非限定於此。在以下所示之實施例，使用純度不同之複數的銅線而製作複數的銅柱，測定所製作之各銅柱之維氏硬度、算術平均粗度及α線量。
．銅柱之製作
準備純度為99.9%、99.99%、99.995%之銅線。接著，藉由使這些銅線通過擠出模具，使上面及底面之直徑ψ成為200μm而將銅線拉伸，之後，藉由在成為200μm之長度(高度L)之位置切斷銅線，製作目的之銅柱。
．算術平均粗度
銅柱之算術平均粗度之評價(照相評價)，係使用KEYENCE公司製之雷射顯微鏡(對應型號VK-9510/JISB0601-1994)來進行。在本實施例，以銅柱之上面的最平坦的部分為中心，在10×10μm之範圍測定。在銅柱之z軸上(高度方向)所測定之間距為0.01μm。在如此之條件下任意測定10處之算術平均粗度Ra做為銅柱之算術平均粗度Ra，將這些的算術平均粗度做為真的算術平均粗度使用。
又，算術平均粗度Ra，也可測定銅柱之底面或側 面，也可使用將銅柱之上面、底面及側面之各測定值平均之值做為測定值。又，在上述例，為了使銅柱之表面平坦化而利用超音波，但並非限定於此。例如，也可將銅柱浸漬於輕微溶解銅柱的表面而促進平滑化加工之溶解性的液體。做為液體，可使用磺酸系(甲磺酸等)或羧酸系(草酸等)之酸性溶液。
．維氏硬度
銅柱之維氏硬度，係根據「維氏硬度試驗-試驗方法JIS Z2244」來測定。使用明石製作所製之顯微維氏硬度試驗器，AKASHI微小硬度計MVK-F 12001-Q。
．α線量
α線量之測定方法係如下述。α線量之測定係使用氣體流量比例計數器之α線測定裝置。測定樣品係在300mm×300mm之平面淺底容器中將銅柱舖滿至看不到容器的底之物。將此測定樣品放入α線測定裝置內，在PR-10氣體流放置24小時後，測定α線量。
又，測定所使用之PR-10氣體(氬90%-甲烷10%)，係將PR-10氣體充填於氣瓶後經過3周以上之物。使用經過3周以上之氣瓶之原因，係為了不使由於進入氣瓶之大氣中之氡發生α線，依照JEDEC(Joint Electron Device Engineering Council)所制定之JDEDEC標準-Alpha Radiation Measurement in Electronic Materials JESD221之故。
．實施例1
接著，將使用純度99.9%之銅線所製造之銅柱放入碳製棒後，將此棒搬入連續輸送帶式電阻加熱爐進行退火處理。此時 之退火處理條件示於第3圖。又，爐內，為了防止銅柱之氧化而使其為氮氣氣氛。室溫為25℃。
做為退火的條件，係如第3圖所示，使從室溫加熱至700℃之升溫時間為60分鐘，保持在700℃之保持時間為60分鐘，從700℃冷卻至室溫之冷卻時間為120分鐘。爐內之冷卻，係使用設置於爐內之冷卻扇來進行。接著，藉由將實施了退火處理之銅柱浸漬於稀硫酸來進行酸處理。這是為了除去由於退火處理造成之形成於銅柱表面之氧化膜。如此所得到之銅柱之退火處理前後之維氏硬度、算術平均粗度及α線量，係示於下述表1。
．實施例2
在實施例2，對於藉由純度為99.99%的銅線所製作之銅柱，以同於實施例1之方法，在進行退火處理之同時，進行氧化膜除去處理。然後，測定所得到之銅柱之維氏硬度、算術平均粗度及α線量。將這些測定結果示於下述表1。
在實施例3，對於藉由純度為99.995%的銅線所製作之銅柱，以同於實施例1之方法，在進行退火處理之同時，進行氧化膜除去處理。然後，測定所得到之銅柱之維氏硬度、算術平均粗度及α線量。將這些測定結果示於下述表1。
．比較例1
在比較例1，分別測定藉由純度99.9%之銅線所製作之銅柱的維氏硬度、算術平均粗度及α線量。將這些測定結果示於下述表1。
．比較例2
在比較例2，分別測定藉由純度99.99%之銅線所製作之銅柱的維氏硬度、算術平均粗度及α線量。將這些測定結果示於下述表1。
．比較例3
在比較例3，分別測定藉由純度99.995%之銅線所製作之銅柱的維氏硬度、算術平均粗度及α線量。將這些測定結果示於下述表1。
．比較例4
在比較例4，分別測定藉由純度超過99.995%之銅線所製作之銅柱的維氏硬度、算術平均粗度及α線量。將這些測定結果示於下述表1。
．比較例5
在比較例5，對於藉由純度超過99.995%的銅線所製作之銅柱，以同於實施例1之方法，在進行退火處理之同時，進行氧化膜除去處理。然後，測定所得到之銅柱之維氏硬度、算術平均粗度及α線量。將這些測定結果示於下述表1。
如表1所示，在實施例1，銅柱之算術平均粗度為0.10μm，在實施例2，銅柱之算術平均粗度為0.17μm，在實施例3，銅柱之算術平均粗度為0.28μm，在任一實施例，算術平均粗度皆在0.3μm以下。又，在實施例1，銅柱之維氏硬度為57.1，在實施例2，銅柱之維氏硬度為52.9，在實施例3，銅柱之維氏硬度為50.2，任一實施例維氏硬度皆在20HV以上60HV以下。由此結果，可確認到藉由對於製造時之銅柱施以退火處理，可得到具有低維氏硬度且低算術平均粗度之兩方的物性之銅柱。
另一方面，在沒有對於銅柱施以退火處理之比較例1~4，雖然關於銅柱之算術平均粗度為0.3μm以下，但維氏硬度超過60HV，可確認到不滿足關於維氏硬度為20HV以上60HV以下之條件。又，在比較例5，雖然銅柱之維氏硬度在20HV以上60HV以下之範圍，但算術平均粗度超過0.3μm。藉由此，可確認到即使對於製作時之銅柱施以退火處理之情況，若在使用高純度之銅柱的情況，無法滿足關於算術平均粗度為0.3μm以下之條件。
又，在實施例1~3之銅柱，銅柱之α線量為未滿0.0010cph/cm2以下，可確認到此為滿足<0.0200cph/cm2，且滿足<0.0010cph/cm2之結果。
接著，在上述實施例1之退火處理後之銅柱的表面上被覆以錫-3銀-0.5銅合金所形成之焊料電鍍層而製作銅核柱，將此銅核柱與製造銅核柱時所使用之電鍍液直接採取於300cc的燒杯中放在超音波機照射60分鐘之超音波。超音波機 係使用市售之超音波洗淨機(AS ONE公司製US-CLEANER)，以輸出80W、40kHz之頻率進行。經過60分鐘後以離子交換水洗淨，之後使其溫風乾燥，分別測定所製作之銅核柱的算術平均粗度及α線量。同於實施例1~3，銅核柱之算術平均粗度為0.3μm以下。又，對於在實施例1之銅柱的表面被覆鎳電鍍層之銅核柱，或是在實施例1之銅柱的表面依照順序被覆了鎳電鍍層及焊料電鍍層之銅核柱，也以同於前述的條件進行超音波處理，分別測定算術平均粗度及α線量，同於實施例1~3，銅核柱之算術平均粗度為0.3μm以下。又，在任一情況，α線量皆未滿0.0010cph/cm2，可確認到此為滿足<0.0200cph/cm2，且滿足<0.0010cph/cm2之結果。
又，在被覆鐵電鍍層、鈷電鍍層來取代鎳電鍍層之情況，也同於被覆了鎳電鍍層之銅核柱，算術平均粗度在0.3μm以下。又，α線量未滿0.0010cph/cm2，可確認到此為滿足<0.0200cph/cm2，且滿足<0.0010cph/cm2之結果。
接著，製作對於上述之實施例1之退火處理後之銅柱表面被覆助焊劑之助焊劑覆層銅柱，分別測定所製作之助焊劑覆層銅柱之算術平均粗度及α線量。同於實施例1~3，在助焊劑覆層銅柱，算術平均粗度為0.3μm以下。更且，在助焊劑覆層銅柱，α線量也未滿0.0010cph/cm2，可確認到此為滿足<0.0200cph/cm2，且滿足<0.0010cph/cm2之結果。
又，對於上述銅核柱表面被覆助焊劑之助焊劑覆層銅核柱，也同於助焊劑覆層銅柱，算術平均粗度為0.3μm以下。更且，在助焊劑覆層銅核柱，α線量也未滿0.0010cph/cm2， 可確認到此為滿足<0.0200cph/cm2，且滿足<0.0010cph/cm2之結果。
另外，製作對於上述之實施例1之退火處理後之銅柱表面被覆含有咪唑化合物之有機覆膜之OSP處理銅柱，分別測定所製作之OSP處理銅柱之算術平均粗度及α線量。同於實施例1~3，在OSP處理銅柱，算術平均粗度為0.3μm以下，α線量為0.0010cph/cm2以下。
又，在本發明之銅柱在實施例與比較例，係舉出圓柱狀之物，但形狀並非限定於圓柱狀，也可為三角柱或四角柱等只要是直接與基板接觸之以上下面3邊以上所構成之柱體即可得到本發明的效果。
1‧‧‧銅柱
ψ‧‧‧直徑
L‧‧‧高度

Claims (14)

  1. 一種銅柱，純度為99.9%以上99.995%以下，算術平均粗度為0.3μm以下，維氏硬度為20HV以上60HV以下。
  2. 如申請專利範圍第1項之銅柱，其中，α線量為0.0200cph/cm2以下。
  3. 如申請專利範圍第1或2項之銅柱，其中，係由上面及底面之直徑為1~1000μm，高度1~3000μm之柱體所形成。
  4. 如申請專利範圍第1至3項中任一項之銅柱，其中，係被覆了助焊劑層。
  5. 如申請專利範圍第1至3項中任一項之銅柱，其中，係被覆了含有咪唑化合物之有機覆膜。
  6. 一種銅核柱，具有申請專利第1至4項中任一項之銅柱，與被覆前述銅核柱之焊料層。
  7. 一種銅核柱，具有申請專利第1至4項中任一項之銅柱，與被覆前述銅核柱之從鎳、鐵、鈷所選出之1種元素以上所形成之電鍍層。
  8. 如申請專利範圍第7項之銅核柱，其中，更具有被覆前述電鍍層之焊料層。
  9. 如申請專利範圍第6至8項中任一項之銅核柱，其中，α線量為0.0200cph/cm2以下。
  10. 如申請專利範圍第6至9項中任一項之銅核柱，其中，係被覆了助焊劑層。
  11. 種焊接接頭，使用了申請專利範圍第1至5項中任一項之銅柱。
  12. 一種矽貫通電極，使用了申請專利範圍第1至5項中任一項之銅柱。
  13. 一種焊接接頭，使用了申請專利範圍第6至10項中任一項之銅核柱。
  14. 一種矽貫通電極，使用了申請專利範圍第6至10項中任一項之銅核柱。
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