WO2015198435A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2015198435A1
WO2015198435A1 PCT/JP2014/066941 JP2014066941W WO2015198435A1 WO 2015198435 A1 WO2015198435 A1 WO 2015198435A1 JP 2014066941 W JP2014066941 W JP 2014066941W WO 2015198435 A1 WO2015198435 A1 WO 2015198435A1
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WIPO (PCT)
Prior art keywords
semiconductor device
transistor
region
electrode
current
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PCT/JP2014/066941
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English (en)
French (fr)
Inventor
伸介 神戸
河本　厚信
山本　剛司
Original Assignee
三菱電機株式会社
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Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to DE112014006764.4T priority Critical patent/DE112014006764B4/de
Priority to CN201480080154.4A priority patent/CN106463537B/zh
Priority to US15/121,499 priority patent/US9859238B2/en
Priority to JP2016528930A priority patent/JP6289635B2/ja
Priority to PCT/JP2014/066941 priority patent/WO2015198435A1/ja
Publication of WO2015198435A1 publication Critical patent/WO2015198435A1/ja

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Definitions

  • the present invention relates to a semiconductor device suitable for driving an inductive load in an ignition system of an internal combustion engine, for example.
  • a conductive wire (generally aluminum) is electrically connected to the emitter pad (reference potential region) by an ultrasonic bonding technique.
  • a layout in which a DMOS structure such as an IGBT cell (hereinafter simply referred to as an IGBT cell) is not provided in a region where the emitter pad is formed is adopted. There are many.
  • IGBT cell region Since the chip area of the semiconductor device is finite and the distance from the emitter pad to each region where the IGBT cell is formed (hereinafter referred to as IGBT cell region) is different, the portion closer to the emitter pad than the portion away from the emitter pad. However, the current load tends to increase. On the other hand, in the IGBT cell region in the vicinity of the emitter pad where the IGBT cell is not provided, it has been experimentally found that the current density is low due to the transient fluctuation of the carrier concentration in the semiconductor device that contributes to conductivity at the time of high-speed cutoff. . As a result, there is a region where the current density is maximized between a region away from the emitter pad and a region near the emitter pad, and this region becomes a starting point of the energization breakdown.
  • the present invention has been made to solve such a problem, and an object of the present invention is to provide a semiconductor device capable of eliminating the uneven current distribution in the surface.
  • a semiconductor device has a transistor cell region in which a plurality of transistor cells are arranged on a semiconductor substrate, and avoids the transistor cell region on the semiconductor substrate.
  • the transistor cell region comprises a plurality of regions having different current drive capabilities depending on the distance from the electrode pad, and an electrode pad electrically connected to one current electrode of each cell.
  • a semiconductor device is a semiconductor device having a transistor cell region in which a plurality of transistor cells are arranged on a semiconductor substrate, arranged on the semiconductor substrate so as to avoid the transistor cell region, and for each cell.
  • it has an electrode pad that is electrically connected to the current electrode, and the transistor cell area consists of multiple areas with different current drive capabilities depending on the distance from the electrode pad, eliminating the uneven current distribution in the plane. It becomes possible to do.
  • FIG. 16 is a diagram showing an example of a circuit configuration of an ignition system for an internal combustion engine.
  • FIG. 17 is a diagram showing an example of the operation in the circuit of FIG.
  • the control circuit 29 receives an ON signal from the control computer via the control terminal 30, and drives the transistor 31 (switching element) by a drive signal based on the received ON signal. Specifically, current is passed through the transformer 32 (inductive load) to accumulate energy.
  • the transistor 31 is, for example, an IGBT.
  • the control circuit 29 receives an off signal from the control computer via the control terminal 30 and turns off the transistor 31 by the drive signal based on the received off signal. .
  • the transistor 31 is turned off and the transistor 31 is cut off, the Vce voltage rises, and a high voltage multiplied by the turn ratio is excited to the secondary side of the transformer 32 (generally, V2 is about ⁇ 30 kV).
  • a clamp diode 34 (zener diode) is provided between the collector and the gate so that Vce is clamped at about 500V.
  • active clamp the drive signal of the transistor 31 is raised using the clamp diode 34 and the transistor 31 is turned on, which is called “active clamp”, and an excessive voltage is applied to the load (here, the transformer 32). Is set to such a voltage that does not occur (approximately 500 V in the example of FIG. 17).
  • the value of the load current Ic varies depending on the ON time of the drive signal and the power supply voltage Vp, but the fusing of the winding of the transformer 32 and the magnetic saturation of the core of the transformer 32 (usually a magnetic material such as iron). In order to avoid this risk, the current is controlled so as not to exceed a predetermined value.
  • the maximum allowable current value at this time is defined as a “current limit value”.
  • a transistor 31 for controlling a primary side current of a transformer 32 used in an ignition system for an internal combustion engine such as an automobile engine shuts off at the timing of ignition, and generates a high voltage on the secondary side of the transformer 32 to generate a spark plug.
  • arc discharge is generated.
  • the fuel is ignited by the occurrence of the arc discharge.
  • the transistor 31 performs an active clamping operation in order to avoid dielectric breakdown of the winding of the transformer 32.
  • the active clamp operation causes local heat generation in the transistor 31, and the energy at which the most heat generating portion is destroyed is defined as the rating of the transistor 31.
  • FIG. 18 is a diagram showing an example of the configuration of the semiconductor device 36 according to the base technology, and is an external view when the semiconductor device 36 is viewed from above.
  • FIG. 19 is a diagram showing an equivalent circuit of FIG.
  • the semiconductor device 36 includes an emitter pad 2 (reference potential region), a gate pad 3 (drive signal region), a clamp diode 4, a collector electrode 22, and a transistor 31.
  • a plurality of transistors 31 are formed in the transistor cell region 37.
  • the collector electrode 22 is formed on the back surface side of the semiconductor device 36 (the back surface side of the paper surface of FIG. 18), and is connected to the collector of each transistor 31.
  • the gate pad 3 is connected to the gate of each transistor 31.
  • the clamp diode 4 is connected between the gate and collector of each transistor 31.
  • a conductive wire is electrically connected to the emitter pad 2. Further, the transistor 31 is not formed in the region where the emitter pad 2 is formed.
  • the present invention has been made to solve such problems, and will be described in detail below.
  • FIG. 1 is a diagram showing an example of the configuration of the semiconductor device 1 according to the first embodiment of the present invention, and is an external view when the semiconductor device 1 is viewed from above.
  • FIG. 2 is a cross-sectional view taken along line A1-A2 of FIG. 3 is a cross-sectional view taken along B1-B2 of FIG.
  • the equivalent circuit of FIG. 1 is the same as that of FIG. Moreover, although IGBT is used as the transistor 31, it may be MOSFET (Metal
  • the semiconductor substrate 9 is a silicon substrate.
  • the semiconductor device 1 includes an emitter pad 2 (reference potential region, electrode pad), a gate pad 3 (drive signal region), a clamp diode 4, a collector electrode 22, and a transistor 31. Further, the semiconductor device 1 is used in an ignition system for an internal combustion engine as shown in FIG. 16 and operates as shown in FIG.
  • a plurality of transistors 31 are formed in regions 6 to 8 (corresponding to the transistor cell region 37 in FIG. 18) described later. That is, cells of a plurality of transistors 31 are arranged in the regions 6 to 8.
  • the emitter pad 2 has a rectangular or square shape, and the conductive wiring 15 (generally aluminum) is electrically connected by an ultrasonic bonding technique.
  • the conductive wiring 15 generally aluminum
  • an interlayer film 14 that is an oxide film is formed below the metal layer 12 that constitutes the emitter pad 2, but the semiconductor substrate 9 (specifically, the semiconductor substrate 9 is formed by contact processing).
  • the ohmic connection may be made directly to the field oxide film 13).
  • the transistor 31 is not formed in the region where the emitter pad 2 is formed. That is, the emitter pad 2 is disposed avoiding the regions 6 to 8 and is electrically connected to the emitter electrode E (one current electrode) of each transistor 31 through the metal layer 12.
  • the collector electrode 22 is formed on the back side of the semiconductor device 1 (the back side of the paper surface of FIG. 1) and is connected to the collector of each transistor 31.
  • the gate pad 3 is connected to the gate of each transistor 31.
  • the clamp diode 4 is connected between the gate and collector of each transistor 31.
  • region where the transistor 31 is formed there are a plurality of regions (region 6, region 7, region 8) having different current driving capabilities depending on the distance from the emitter pad 2. Is provided. In the first embodiment, a case where three regions are provided is described, but two or more regions may be used.
  • the region 6, the region 7, and the region 8 are adjusted so that the relationship of the current drive capability per unit area of the transistor 31 in each of the regions 6 ⁇ region 6 ⁇ region 8 is satisfied.
  • the current drive capability is adjusted by changing the pitch between the gates or the shape of the impurity implantation pattern of the emitter contact portion and the impurity region 11 in the vicinity of the emitter contact portion.
  • the semiconductor device 1 has a tendency to concentrate current in the region 7 in a transient state during the above-described active clamp operation, and to be a starting point of destruction under the conditions of the surrounding environment due to instantaneous heat generation. ing.
  • the breakdown tolerance of the semiconductor device 1 is limited by the breakdown tolerance of the transistor 31 provided in the region 7.
  • the semiconductor device 1 since the current burden in the region (region 7) where the current density is high is distributed to the surrounding regions (region 6, region 8), the entire semiconductor device 1 becomes a more uniform current burden and the same. If the semiconductor device has an area, higher breakdown tolerance can be realized.
  • the first embodiment it is possible to eliminate the uneven current distribution in the plane.
  • the regions 6 to 8 are provided so as to uniformly surround the emitter pad 2. However, depending on the layout pattern of the gate of the transistor 31 and the location of the pads, the regions from the emitter pad 2 are provided. Even if each region is provided as shown in FIGS. 4 to 6 (only regions 6 and 7 in FIGS. 4 and 5) depending on the distance, the same effect as described above can be obtained.
  • FIG. 7 is a diagram showing an example of the configuration of the semiconductor device 19 according to the second embodiment of the present invention, and is an external view when the semiconductor device 19 is viewed from above.
  • the second embodiment is characterized in that the shape of the emitter pad 2 is a circle, an ellipse, or a polygon having at least five vertices.
  • Other configurations are the same as those in the first embodiment, and thus description thereof is omitted here.
  • the emitter pad 2 is formed in an elliptical shape.
  • the regions 6 to 8 are provided so as to surround the emitter pad 2.
  • the shape of the emitter pad 2 is not limited to a round shape such as an ellipse or a circle, and may be a polygon having five or more vertices.
  • a pattern mask for an exposure apparatus used when a pattern of a semiconductor device is formed by a photoengraving technique is designed using an electronic computer. The circular pattern is actually converted into a shape approximated to a polygon, and a pattern mask is created based on the coordinate data of each vertex of the polygon. That is, when the number of polygon vertices is increased, the shape finally becomes an ellipse or a circle.
  • the distance between the boundaries of the regions 6 to 8 and the emitter pad 2 is more uniform than that of the first embodiment. ) Is alleviated, and the utilization efficiency of the transistor 31 can be further increased.
  • FIG. 8 is a diagram showing an example of the configuration of the semiconductor device 20 according to the third embodiment of the present invention, and is an external view when the semiconductor device 20 is viewed from above.
  • FIG. 9 is a diagram showing an equivalent circuit of FIG.
  • the third embodiment is characterized in that the transistor 31 (transistor cell) includes a current detection electrode having an area smaller than that of the emitter electrode in addition to the emitter electrode.
  • the transistor 31 transistor cell
  • Other configurations are the same as those in the first embodiment, and thus description thereof is omitted here.
  • the current detection electrode of the transistor 31 is connected to the current detection emitter pad 21. That is, the semiconductor device 20 includes a transistor 31 connected to each of the emitter electrode pad 2, the gate electrode pad 3, and the collector electrode 22, the current detection emitter pad 21, the gate electrode pad 3, and the collector electrode 22. And a current detection transistor configured to be connected to each. Further, the current detection transistor is smaller in size than the transistor 31. The current detection transistor is formed in a region indicated by a broken line in FIG.
  • the third embodiment by providing a current detection transistor having a smaller size than the transistor 31, current detection using a smaller detection resistor is possible, and signal transmission to the control circuit is possible. It becomes possible. Further, since the same effect as the conventional one can be realized with a resistance smaller than the conventional current detection resistor 35 as shown in FIG. 16, it is possible to realize a reduction in size and cost of the semiconductor device.
  • the current detection transistor is not limited to the area indicated by the broken line in FIG. 8 and may be provided in an arbitrary area.
  • FIG. 10 is a diagram showing an example of the configuration of the semiconductor device 23 according to the fourth embodiment of the present invention, and is an external view when the semiconductor device 23 is viewed from above.
  • FIG. 11 is a diagram showing an equivalent circuit of FIG.
  • the fourth embodiment is characterized in that a temperature detection diode 24 for detecting the temperature of the semiconductor device 23 is further provided.
  • Other configurations are the same as those in the first embodiment, and thus description thereof is omitted here.
  • the anode of the temperature detection diode 24 is connected to the anode electrode 25, and the cathode of the temperature detection diode 24 is connected to the cathode electrode 26.
  • the temperature detecting diode 24 is generally formed of polysilicon, but may be formed of a material other than polysilicon. Further, in the example of FIG. 11, the number of diodes is one, but they may be multistaged in series.
  • the anode electrode 25 and the cathode electrode are connected to the temperature detection circuit (not shown) provided in the control circuit 29, thereby enabling the temperature detection of the semiconductor device 23.
  • FIG. 12 is a diagram showing an example of the configuration of the semiconductor device 27 according to the fifth embodiment of the present invention, and is an external view when the semiconductor device 27 is viewed from above.
  • FIG. 13 is a diagram showing an equivalent circuit of FIG.
  • the fifth embodiment is characterized in that the anode of the temperature detection diode 24 is connected to the emitter pad 2.
  • Other configurations are the same as those in the fourth embodiment, and thus description thereof is omitted here.
  • the anode of the temperature detecting diode 24 is connected to the emitter pad 2. That is, the anode of the temperature detection diode 24 and the emitter electrode of the transistor 31 share the emitter pad 2.
  • the anode electrode 25 (see FIG. 11) provided in the fourth embodiment can be omitted, the semiconductor device 27 can be reduced in size and the cost can be reduced.
  • the temperature detection method generally measures the temperature of the semiconductor device 27 by flowing a constant current from the anode to the cathode of the temperature detection diode 24 and monitoring the voltage generated between the anode and the cathode. To do.
  • the number of diodes is one, but they may be multistaged in series.
  • a voltage is applied to the emitter pad 2 and the cathode electrode 26 of the temperature detection diode 24, and the current flowing in is monitored by the temperature detection circuit of the control circuit 29. It becomes possible to detect the overheating state of the semiconductor device 27.
  • FIG. 14 is a diagram showing an example of the configuration of the semiconductor device 28 according to the sixth embodiment of the present invention, and is an external view when the semiconductor device 28 is viewed from above.
  • FIG. 15 is a diagram showing an equivalent circuit of FIG.
  • the sixth embodiment is characterized in that the semiconductor device 28 includes a current detection transistor and a temperature detection diode. That is, the sixth embodiment is characterized in that the third embodiment (FIGS. 8 and 9) and the fifth embodiment (FIGS. 12 and 13) are combined. Since the configuration is the same as in the third and fifth embodiments, the description thereof is omitted here.
  • the sixth embodiment it is possible to detect the load current and temperature in the semiconductor device 28, which can be used for overcurrent protection and overheat protection. Therefore, it is possible to avoid a problem that occurs in a transistor during an abnormal operation and to provide a more reliable semiconductor device.
  • the seventh embodiment of the present invention is characterized in that the semiconductor substrate 9 in the first to sixth embodiments is a silicon carbide substrate instead of the silicon substrate. Since the configuration is the same as in the first to sixth embodiments, description thereof is omitted here.
  • the semiconductor device using the silicon substrate according to the first to sixth embodiments can be operated at a higher temperature, so that the size of the semiconductor device and the heat dissipation mechanism can be made smaller. Is possible. Therefore, it is possible to contribute to reduction in size and weight of a product using the semiconductor device.

Abstract

　本発明は、面内における電流分布の偏りを解消することが可能な半導体装置を提供することを目的とする。本発明による半導体装置は、半導体基板（９）上に複数のトランジスタのセルが配置されたトランジスタセル領域（３７）を有する半導体装置（１）であって、半導体基板（９）上にトランジスタセル領域（３７）を避けて配置され、かつ各セルの一方電流電極と電気的に接続された電極パッド（２）を備え、トランジスタセル領域（３７）は、電極パッド（２）からの距離に依存して電流駆動能力が異なる複数の領域（６，７，８）からなることを特徴とする。

Description

半導体装置
　本発明は、例えば内燃機関のイグニッションシステムにおいて誘導性負荷を駆動するのに適した半導体装置に関する。
　従来、イグナイタに用いられるＩＧＢＴ（Insulated Gate Bipolar Transistor）等のスイッチング素子を備える半導体装置（半導体チップ）のレイアウトでは、半導体装置の面内で同一の構造を採用しているが、半導体装置を通電する電流密度が面内において均一ではなく局所的に偏りが生じる。従って、半導体装置の破壊耐量は、局所的に電流密度が高くなる部分によって律速され、局所的に電流密度が高くなる部分以外の部分は、電流密度に対して余裕がある（例えば、特許文献１，２参照）。
特開昭５９－８７８２８号公報 特開平５－１６０４０９号公報
　上記の半導体装置では、エミッタパッド（基準電位領域）に対して、導電性のワイヤ（一般的にはアルミニウム）が超音波接合技術によって電気的に接続されている。当該接合時のストレスによってスイッチング素子の構造がダメージを受けないように、エミッタパッドが形成される領域には、ＩＧＢＴセル等のＤＭＯＳ構造（以下、単にＩＧＢＴセルという）を設けないレイアウトを採用することが多い。
　半導体装置のチップ面積は有限であり、エミッタパッドからＩＧＢＴセルが形成される各領域（以下、ＩＧＢＴセル領域という）までの距離が異なるため、エミッタパッドから離れた部分よりもエミッタパッドに近い部分の方が、電流負荷が大きくなる傾向がある。一方、ＩＧＢＴセルを設けないエミッタパッドの近傍のＩＧＢＴセル領域では、高速遮断時に導電性に寄与する半導体装置内のキャリア濃度の過渡的な変動によって、電流密度が低いことが実験で判明している。その結果、エミッタパッドから離れた領域と、エミッタパッド近傍の領域との間に電流密度が最大になる領域が存在することとなり、当該領域が通電破壊の起点になる。
　このように、半導体装置の面内の領域によって電流密度の違いがあるため、スイッチング素子の電流駆動能力と破壊耐量とのトレードオフの関係が生じ、半導体装置のサイズやコストに制約がかかるという問題があった。
　本発明は、このような問題を解決するためになされたものであり、面内における電流分布の偏りを解消することが可能な半導体装置を提供することを目的とする。
　上記の課題を解決するために、本発明による半導体装置は、半導体基板上に複数のトランジスタのセルが配置されたトランジスタセル領域を有する半導体装置であって、半導体基板上にトランジスタセル領域を避けて配置され、かつ各セルの一方電流電極と電気的に接続された電極パッドを備え、トランジスタセル領域は、電極パッドからの距離に依存して電流駆動能力が異なる複数の領域からなることを特徴とする。
　本発明によると、半導体装置は、半導体基板上に複数のトランジスタのセルが配置されたトランジスタセル領域を有する半導体装置であって、半導体基板上にトランジスタセル領域を避けて配置され、かつ各セルの一方電流電極と電気的に接続された電極パッドを備え、トランジスタセル領域は、電極パッドからの距離に依存して電流駆動能力が異なる複数の領域からなるため、面内における電流分布の偏りを解消することが可能となる。
　本発明の目的、特徴、態様、および利点は、以下の詳細な説明と添付図面とによって、より明白となる。
本発明の実施の形態１による半導体装置の構成の一例を示す図である。 図１のＡ１－Ａ２断面を示す図である。 図１のＢ１－Ｂ２断面を示す図である。 本発明の実施の形態１による半導体装置の構成の他の一例を示す図である。 本発明の実施の形態１による半導体装置の構成の他の一例を示す図である。 本発明の実施の形態１による半導体装置の構成の他の一例を示す図である。 本発明の実施の形態２による半導体装置の構成の一例を示す図である。 本発明の実施の形態３による半導体装置の構成の一例を示す図である。 図８の等価回路を示す図である。 本発明の実施の形態４による半導体装置の構成の一例を示す図である。 図１０の等価回路を示す図である。 本発明の実施の形態５による半導体装置の構成の一例を示す図である。 図１２の等価回路を示す図である。 本発明の実施の形態６による半導体装置の構成の一例を示す図である。 図１４の等価回路を示す図である。 内燃機関のイグニッションシステムの回路構成の一例を示す図である。 図１６の回路における動作の一例を示す図である。 前提技術による半導体装置の構成の一例を示す図である。 図１８の等価回路を示す図である。
　本発明の実施の形態について、図面に基づいて以下に説明する。
　＜前提技術＞
　まず、内燃機関のイグニションシステムについて説明する。
　図１６は、内燃機関のイグニションシステムの回路構成の一例を示す図である。また、図１７は、図１６の回路における動作の一例を示す図である。
　制御回路２９は、制御端子３０を介して制御コンピュータからのオン信号を受信し、受信したオン信号に基づく駆動信号によってトランジスタ３１（スイッチング素子）を駆動する。具体的には、トランス３２（誘導性負荷）に電流を流してエネルギーを蓄積させる。ここで、トランジスタ３１は、例えばＩＧＢＴである。
　点火タイミング時（図１７の駆動信号Ｖのオフ時）において、制御回路２９は、制御端子３０を介して制御コンピュータからオフ信号を受信し、受信したオフ信号に基づく駆動信号によってトランジスタ３１をターンオフする。ターンオフしてトランジスタ３１が遮断されるとＶｃｅ電圧が上昇し、巻き数比倍された高電圧がトランス３２の２次側に励起される（一般的には、Ｖ２は－３０ｋＶ程度）。
　一般的には、トランス３２の巻き線の絶縁破壊を防止するために、Ｖｃｅは５００Ｖ程度でクランプするように、コレクタ－ゲート間にクランプダイオード３４（ツェナーダイオード）が設けられる。このように、コレクタ電圧の上昇によって、クランプダイオード３４を用いてトランジスタ３１の駆動信号を上昇させ、トランジスタ３１がオンすることを「アクティブクランプ」といい、負荷（ここではトランス３２）に過剰な電圧が発生しないような電圧（図１７の例では約５００Ｖ）が設定される。
　負荷電流Ｉｃの値は、駆動信号のオン時間や電源電圧Ｖｐに依存して変動するが、トランス３２の巻き線の溶断や、トランス３２のコア（通常は、鉄などの磁性素材）の磁気飽和のリスク回避するために、電流が予め定められた値以上にならないように制御される。このときの最大許容電流値は、「電流制限値」と定義される。
　自動車エンジン等の内燃機関用のイグニションシステムに用いられるトランス３２の１次側電流を制御するトランジスタ３１は、点火のタイミングで遮断動作し、トランス３２の２次側に高電圧を発生させて点火プラグ３３でアーク放電を生じさせている。当該アーク放電が生じることによって燃料が着火される。このような点火時において、トランジスタ３１は、トランス３２の巻き線の絶縁破壊を回避するためにアクティブクランプ動作を行っている。当該アクティブクランプ動作は、トランジスタ３１に局所的な発熱をもたらしており、最も発熱する部分が破壊に至るエネルギーを、トランジスタ３１の定格として規定している。
　次に、上記のトランジスタ３１を含む前提技術による半導体装置について説明する。
　図１８は、前提技術による半導体装置３６の構成の一例を示す図であり、半導体装置３６を上方から見たときの外観図である。また、図１９は、図１８の等価回路を示す図である。
　半導体装置３６は、エミッタパッド２（基準電位領域）と、ゲートパッド３（駆動信号用領域）と、クランプダイオード４と、コレクタ電極２２と、トランジスタ３１とを備えている。
　トランジスタセル領域３７には、複数のトランジスタ３１が形成されている。コレクタ電極２２は、半導体装置３６の裏面側（図１８の紙面の裏面側）に形成されており、各トランジスタ３１のコレクタに接続されている。ゲートパッド３は、各トランジスタ３１のゲートに接続されている。クランプダイオード４は、各トランジスタ３１のゲート－コレクタ間に接続されている。
　エミッタパッド２には、導電性のワイヤが電気的に接続されている。また、エミッタパッド２が形成される領域には、トランジスタ３１が形成されていない。
　図１８に示すような前提技術による半導体装置３６では、上述の通り、半導体装置３６の面内の領域によって電流密度の違いがあるため、各領域においてトランジスタ３１の電流駆動能力と破壊耐量とのトレードオフの関係が生じ、半導体装置３６のサイズやコストに制約がかかるという問題があった。
　本発明は、このような問題を解決するためになされたものであり、以下に詳細に説明する。
　＜実施の形態１＞
　図１は、本発明の実施の形態１による半導体装置１の構成の一例を示す図であり、半導体装置１を上方から見たときの外観図である。図２は、図１のＡ１－Ａ２の断面図である。図３は、図１のＢ１－Ｂ２の断面図である。
　なお、図１の等価回路は、図１９と同様である。また、トランジスタ３１としてＩＧＢＴを用いているが、ＭＯＳＦＥＴ（Metal Oxide Semiconductor Field Effect Transistor）であってもよい。また、半導体基板９は、ケイ素基板である。
　半導体装置１は、エミッタパッド２（基準電位領域、電極パッド）と、ゲートパッド３（駆動信号用領域）と、クランプダイオード４と、コレクタ電極２２と、トランジスタ３１とを備えている。また、半導体装置１は、図１６に示すような内燃機関のイグニションシステムに用いられ、図１７に示すような動作を行う。
　トランジスタ３１は、後述の領域６～８（図１８のトランジスタセル領域３７に対応）に複数形成されている。すなわち、領域６～８には、複数のトランジスタ３１のセルが配置されている。
　エミッタパッド２は、長方形または正方形の形状であり、導電配線１５（一般的にはアルミニウム）が超音波接合技術によって電気的に接続されている。図３の例では、エミッタパッド２を構成する金属層１２の下層には、酸化膜である層間膜１４が形成されているが、コンタクト処理によって半導体基板９（具体的には、半導体基板９のフィールド酸化膜１３）に直接オーミック接続するようにしてもよい。
　また、エミッタパッド２が形成される領域には、トランジスタ３１が形成されていない。すなわち、エミッタパッド２は、領域６～８を避けて配置され、かつ金属層１２を介して各トランジスタ３１のエミッタ電極Ｅ（一方電流電極）と電気的に接続されている。
　コレクタ電極２２は、半導体装置１の裏面側（図１の紙面の裏面側）に形成されており、各トランジスタ３１のコレクタに接続されている。ゲートパッド３は、各トランジスタ３１のゲートに接続されている。クランプダイオード４は、各トランジスタ３１のゲート－コレクタ間に接続されている。
　トランジスタ３１が形成される領域（図１８のトランジスタセル領域３７に対応）には、エミッタパッド２からの距離に依存して電流駆動能力が異なる複数の領域（領域６、領域７、領域８）が設けられている。なお、本実施の形態１では、３つの領域を設ける場合について説明するが、２つ以上の領域であればよい。
　領域６、領域７、および領域８は、各々におけるトランジスタ３１の単位面積当たりの電流駆動能力の関係が、領域７＜領域６≦領域８となるように調整する。電流駆動能力の調整は、例えばトランジスタ３１がＩＧＢＴであれば、ゲート間ピッチ、あるいはエミッタコンタクト部および当該エミッタコンタクト部近傍の不純物領域１１の不純物注入パターンの形状を変更することによって行われる。
　上記の半導体装置１は、上述のアクティブクランプ動作時の過渡的な状態において、領域７に電流が集中しやすく、瞬間的な発熱によって周囲環境の条件における破壊の起点になることが実験から判明している。このことは、半導体装置１の面内で電流密度が不均一であるため、半導体装置１の破壊耐量が領域７に設けられるトランジスタ３１の破壊耐量で律速されることを意味している。しかし、半導体装置１では、電流密度が高い領域（領域７）における電流負担を周囲の領域（領域６、領域８）に分散させているため、半導体装置１全体がより均一な電流負担となり、同一面積の半導体装置であればより高い破壊耐量を実現することができる。
　以上のことから、本実施の形態１によれば、面内における電流分布の偏りを解消することが可能となる。また、従来問題となっていた、トランジスタの電流駆動能力と破壊耐量とのトレードオフの関係を改善することが可能となり、より低コストな半導体装置を提供することが可能となる。
　なお、上記の図１では、エミッタパッド２を均等に囲むように各領域６～８を設けているが、トランジスタ３１のゲートのレイアウトパターンや、各パッドの配置場所によっては、エミッタパッド２からの距離に依存するように、各領域を図４～６（図４，５では、領域６，７のみ）に示すように設けても、上記と同様の効果が得られる。
　＜実施の形態２＞
　図７は、本発明の実施の形態２による半導体装置１９の構成の一例を示す図であり、半導体装置１９を上方から見たときの外観図である。
　本実施の形態２では、エミッタパッド２の形状が、円形、楕円形、あるいは少なくとも５つ以上の頂点を有する多角形であることを特徴としている。その他の構成は、実施の形態１と同様であるため、ここでは説明を省略する。
　図７に示すように、エミッタパッド２は楕円形で形成されている。また、領域６～８は、エミッタパッド２の周囲を囲むように設けられている。
　エミッタパッド２の形状は、楕円形や円形などの丸みを帯びた形状に限らず、５つ以上の頂点を有する多角形であってもよい。半導体装置のパターンを写真製版技術によって形成する際に使用する露光装置用のパターンマスクは、電子計算機を用いてパターン形状が設計される。円形パターンは、実際には多角形に近似された形に変換され、多角形の各頂点の座標データに基づいてパターンマスクが作製される。すなわち、多角形の頂点の数を増やすと、最終的には楕円形あるいは円形に近い形状になる。
　以上のことから、本実施の形態２によれば、各領域６～８の境界とエミッタパッド２との距離が実施の形態１よりも均一になるため、各領域６～８内における電流（発熱）の偏りが緩和し、トランジスタ３１の利用効率をさらに高めることが可能となる。
　＜実施の形態３＞
　図８は、本発明の実施の形態３による半導体装置２０の構成の一例を示す図であり、半導体装置２０を上方から見たときの外観図である。また、図９は、図８の等価回路を示す図である。
　本実施の形態３では、トランジスタ３１（トランジスタのセル）が、エミッタ電極に加え、当該エミッタ電極よりも面積が小さい電流検出電極を備えることを特徴としている。その他の構成は、実施の形態１と同様であるため、ここでは説明を省略する。
　図８，９に示すように、トランジスタ３１の電流検出電極は、電流検出用エミッタパッド２１に接続されている。すなわち、半導体装置２０は、エミッタ電極パッド２、ゲート電極パッド３、およびコレクタ電極２２の各々に接続して構成されるトランジスタ３１と、電流検出用エミッタパッド２１、ゲート電極パッド３、およびコレクタ電極２２の各々に接続して構成される電流検出用トランジスタとを備えている。また、電流検出用トランジスタは、トランジスタ３１よりもサイズが小さい。電流検出用トランジスタは、図８の破線で示される領域に形成される。
　以上のことから、本実施の形態３によれば、トランジスタ３１よりもサイズが小さい電流検出用トランジスタを備えることによって、より小さな検出抵抗を用いた電流検出が可能となり、制御回路への信号伝達が可能となる。また、図１６に示すような従来の電流検出用抵抗３５よりも小さな抵抗で従来と同様の効果を実現することができるため、半導体装置の小型化および低コスト化を実現することができる。
　なお、上記では、実施の形態１に適用する場合について説明したが、実施の形態２にも適用可能である。また、電流検出用トランジスタは、図８の破線で示される領域に限らず、任意の領域に設けるようにしてもよい。
　＜実施の形態４＞
　図１０は、本発明の実施の形態４による半導体装置２３の構成の一例を示す図であり、半導体装置２３を上方から見たときの外観図である。また、図１１は、図１０の等価回路を示す図である。
　本実施の形態４では、半導体装置２３の温度を検出する温度検出用ダイオード２４をさらに備えることを特徴としている。その他の構成は、実施の形態１と同様であるため、ここでは説明を省略する。
　図１０，１１に示すように、温度検出用ダイオード２４のアノードはアノード電極２５に接続されており、温度検出用ダイオード２４のカソードはカソード電極２６に接続されている。
　なお、温度検出用ダイオード２４は、ポリシリコンで形成されることが一般的であるが、ポリシリコン以外の素材で形成してもよい。また、図１１の例では、ダイオードは１段であるが、直列に多段化してもよい。
　以上のことから、本実施の形態４によれば、アノード電極２５およびカソード電極と、制御回路２９が備える温度検出回路（図示せず）とを接続し、半導体装置２３の温度検出を可能とすることによって、発熱モニタや過熱遮断による事故保護が容易になるため、異常動作時のトランジスタにて生じる不具合を回避し、より信頼性の高い半導体装置を提供することができる。
　なお、上記では、実施の形態１に適用する場合について説明したが、実施の形態２にも適用可能である。
　＜実施の形態５＞
　図１２は、本発明の実施の形態５による半導体装置２７の構成の一例を示す図であり、半導体装置２７を上方から見たときの外観図である。また、図１３は、図１２の等価回路を示す図である。
　本実施の形態５では、温度検出用ダイオード２４のアノードがエミッタパッド２に接続されることを特徴としている。その他の構成は、実施の形態４と同様であるため、ここでは説明を省略する。
　図１２，１３に示すように、温度検出用ダイオード２４のアノードは、エミッタパッド２に接続されている。すなわち、温度検出用ダイオード２４のアノードと、トランジスタ３１のエミッタ電極とは、エミッタパッド２を共有している。このように、実施の形態４にて設けていたアノード電極２５（図１１参照）を省略することができるため、半導体装置２７を小型化することができ、低コスト化が図れる。
　温度検出方法は、一般的には、温度検出用ダイオード２４のアノードからカソードに向かって定電流を流し、アノードとカソードとの間にて発生する電圧をモニタすることによって半導体装置２７の温度を計測する。
　なお、図１３の例では、ダイオードは１段であるが、直列に多段化してもよい。
　以上のことから、本実施の形態５によれば、エミッタパッド２と、温度検出用ダイオード２４のカソード電極２６に電圧を印加し、流れ込む電流を制御回路２９の温度検出回路がモニタすることによって、半導体装置２７の過熱状態を検出することが可能となる。
　＜実施の形態６＞
　図１４は、本発明の実施の形態６による半導体装置２８の構成の一例を示す図であり、半導体装置２８を上方から見たときの外観図である。また、図１５は、図１４の等価回路を示す図である。
　本実施の形態６では、半導体装置２８が、電流検出用トランジスタと温度検出用ダイオードとを備えることを特徴としている。すなわち、本実施の形態６は、実施の形態３（図８，９）と実施の形態５（図１２，１３）とを組み合わせたものであることを特徴としている。構成は、実施の形態３および実施の形態５と同様であるため、ここでは説明を省略する。
　以上のことから、本実施の形態６によれば、半導体装置２８における負荷電流および温度検出が可能となり、過電流保護や過熱保護に利用することができる。従って、異常動作時のトランジスタにて生じる不具合を回避し、より信頼性の高い半導体装置を提供することができる。
　＜実施の形態７＞
　本発明の実施の形態７では、実施の形態１～６における半導体基板９を、ケイ素基板に代えて炭化ケイ素基板とすることを特徴としている。構成は、実施の形態１～６と同様であるため、ここでは説明を省略する。
　以上のことから、本実施の形態７によれば、実施の形態１～６によるケイ素基板を用いた半導体装置よりも高温で動作可能となるため、半導体装置のサイズおよび放熱機構をより小さくすることが可能となる。従って、当該半導体装置を用いた製品の小型化と軽量化に貢献することができる。
　なお、本発明は、その発明の範囲内において、実施の形態を適宜、変形、省略することが可能である。
　本発明は詳細に説明されたが、上記した説明は、すべての態様において、例示であって、本発明がそれに限定されるものではない。例示されていない無数の変形例が、本発明の範囲から外れることなく想定され得るものと解される。
　１　半導体装置、２　エミッタパッド、３　ゲートパッド、４　クランプダイオード、５　表面電界緩和領域、６　領域、７　領域、８　領域、９　半導体基板、１０　ゲート、１１　不純物領域、１２　金属層、１３　フィールド酸化膜、１４　層間膜、１５　導電性配線、１６　半導体装置、１７　半導体装置、１８　半導体装置、１９　半導体装置、２０　半導体装置、２１　電流検出量エミッタパッド、２２　コレクタ電極、２３　半導体装置、２４　温度検出用ダイオード、２５　アノード電極、２６　カソード電極、２７　半導体装置、２８　半導体装置、２９　制御回路、３０　制御端子、３１　トランジスタ、３２　トランス、３３　点火プラグ、３４　クランプダイオード、３５　電流検出用抵抗、３６　半導体装置、３７　トランジスタセル領域。

Claims (7)

  1. 　半導体基板（９）上に複数のトランジスタのセルが配置されたトランジスタセル領域（３７）を有する半導体装置（１）であって、
    　前記半導体基板（９）上に前記トランジスタセル領域（３７）を避けて配置され、かつ各前記セルの一方電流電極と電気的に接続された電極パッド（２）を備え、
    　前記トランジスタセル領域（３７）は、前記電極パッド（２）からの距離に依存して電流駆動能力が異なる複数の領域（６，７，８）からなることを特徴とする、半導体装置。
  2. 　前記電極パッド（２）の形状は、円形、楕円形、あるいは少なくとも５つ以上の頂点を有する多角形であることを特徴とする、請求項１に記載の半導体装置。
  3. 　少なくとも一部の前記セルは、前記一方電流電極に加え、当該一方電流電極よりも面積が小さい電流検出電極を備えることを特徴とする、請求項１に記載の半導体装置。
  4. 　前記半導体装置の温度を検出する温度検出用ダイオード（２４）をさらに備えることを特徴とする、請求項１に記載の半導体装置。
  5. 　前記温度検出用ダイオード（２４）のアノードは、前記電極パッド（２）に接続されることを特徴とする、請求項４に記載の半導体装置。
  6. 　前記半導体装置の温度を検出する温度検出用ダイオード（２４）をさらに備えることを特徴とする、請求項３に記載の半導体装置。
  7. 　前記半導体基板（９）は、炭化ケイ素基板であることを特徴とする、請求項１に記載の半導体装置。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016111239A (ja) * 2014-12-08 2016-06-20 富士電機株式会社 半導体装置
JP2020053605A (ja) * 2018-09-27 2020-04-02 富士電機株式会社 半導体素子及び半導体装置
JP2020113691A (ja) * 2019-01-16 2020-07-27 三菱電機株式会社 半導体装置
WO2020162013A1 (ja) * 2019-02-07 2020-08-13 富士電機株式会社 半導体装置

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102110249B1 (ko) * 2018-12-07 2020-05-13 현대오트론 주식회사 전력 반도체 칩

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10112541A (ja) * 1996-10-07 1998-04-28 Toshiba Corp 半導体装置
JP2000058820A (ja) * 1998-08-07 2000-02-25 Hitachi Ltd パワー半導体素子及びパワーモジュール
JP2007529115A (ja) * 2003-12-30 2007-10-18 フェアチャイルド・セミコンダクター・コーポレーション パワー半導体デバイスおよびその製造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5987828A (ja) 1982-11-12 1984-05-21 Hitachi Ltd 半導体装置
JP3144585B2 (ja) 1991-12-10 2001-03-12 日本インター株式会社 半導体装置
US6710405B2 (en) * 2001-01-17 2004-03-23 Ixys Corporation Non-uniform power semiconductor device
US7345342B2 (en) 2001-01-30 2008-03-18 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
JP5561922B2 (ja) * 2008-05-20 2014-07-30 三菱電機株式会社 パワー半導体装置
JP5677222B2 (ja) 2011-07-25 2015-02-25 三菱電機株式会社 炭化珪素半導体装置
JP2015135927A (ja) * 2014-01-20 2015-07-27 株式会社東芝 半導体装置、半導体モジュール、および電子回路

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10112541A (ja) * 1996-10-07 1998-04-28 Toshiba Corp 半導体装置
JP2000058820A (ja) * 1998-08-07 2000-02-25 Hitachi Ltd パワー半導体素子及びパワーモジュール
JP2007529115A (ja) * 2003-12-30 2007-10-18 フェアチャイルド・セミコンダクター・コーポレーション パワー半導体デバイスおよびその製造方法

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016111239A (ja) * 2014-12-08 2016-06-20 富士電機株式会社 半導体装置
US10439061B2 (en) 2014-12-08 2019-10-08 Fuji Electric Co., Ltd. Semiconductor device
JP2020053605A (ja) * 2018-09-27 2020-04-02 富士電機株式会社 半導体素子及び半導体装置
US11600722B2 (en) 2018-09-27 2023-03-07 Fuji Electric Co., Ltd. Semiconductor element and semiconductor device
JP7450330B2 (ja) 2018-09-27 2024-03-15 富士電機株式会社 半導体素子及び半導体装置
JP2020113691A (ja) * 2019-01-16 2020-07-27 三菱電機株式会社 半導体装置
US11322586B2 (en) 2019-01-16 2022-05-03 Mitsubishi Electric Corporation Semiconductor device
JP7076387B2 (ja) 2019-01-16 2022-05-27 三菱電機株式会社 半導体装置
WO2020162013A1 (ja) * 2019-02-07 2020-08-13 富士電機株式会社 半導体装置
JPWO2020162013A1 (ja) * 2019-02-07 2021-09-09 富士電機株式会社 半導体装置
JP7024891B2 (ja) 2019-02-07 2022-02-24 富士電機株式会社 半導体装置

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