JP2016111239A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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Abstract
Description
実施の形態1にかかる半導体装置の構造について、単位セル(素子の機能単位:不図示)をMOSFETとする場合を例に説明する。図1Aは、実施の形態1にかかる半導体装置の平面レイアウトを示す平面図である。図1Bは、図1Aの切断線A−A’におけるセルの断面位置を示す断面図である。図1Cは、図1Aの切断線A−A’、図1Bの切断線B−B’における断面構造を示す断面図である。図1Aに示すように、実施の形態1にかかる半導体装置において、略矩形状の平面形状を有する半導体素子(半導体チップ)1には、活性領域2に、半導体素子1を構成する複数の単位セルが所定の平面レイアウトで配置されている。図1Aの切断線A−A’を通るセルの断面位置は、図1Bの切断線B−B’の位置である。切断線B−B’は、ソース電極30、p+型コンタクト領域24、n+型ソース領域23、p-型ベース領域22、およびn-型ドリフト層21を縦断する位置にある。
次に、実施の形態2にかかる半導体装置として、上述した活性領域2に配置される単位セルの構造の一例について説明する。図4は、実施の形態2にかかる半導体装置の平面レイアウトを示す平面図である。図5は、図4の切断線C−C’における断面構造を示す断面図である。図6は、図4の切断線D−D’における断面構造を示す断面図である。図4には、半導体基板(半導体チップ)のおもて面(半導体部の表面)に露出された各半導体部の平面レイアウトを示す(図7,10においても同様)。図5,6には、オン状態のときに単位セルに流れる電流を順に符号31,32を付した矢印で示す(図8,9,11,12においても同様)。図4〜6に示すように、n-型ドリフト層21となるn-型半導体基板(半導体チップ)のおもて面側には、トレンチゲート型のMOSゲート構造が設けられている。
次に、実施の形態3にかかる半導体装置として、上述した活性領域2に配置する単位セルの構造の一例について説明する。図7は、実施の形態3にかかる半導体装置の平面レイアウトを示す平面図である。図8は、図7の切断線E−E’における断面構造を示す断面図である。図9は、図7の切断線F−F’における断面構造を示す断面図である。実施の形態3にかかる半導体装置が実施の形態2にかかる半導体装置と異なる点は、隣り合うメサ部にそれぞれ配置されたn+型ソース領域23同士がトレンチ25を挟んで第1方向に対向しないように配置されている点である。すなわち、n+型ソース領域23は、市松模様状の平面レイアウトで配置されている。
次に、実施の形態4にかかる半導体装置として、上述した活性領域2に配置する単位セルの構造の一例について説明する。図10は、実施の形態4にかかる半導体装置の平面レイアウトを示す平面図である。図11は、図10の切断線G−G’における断面構造を示す断面図である。図12は、図10の切断線H−H’における断面構造を示す断面図である。実施の形態4にかかる半導体装置が実施の形態2にかかる半導体装置と異なる点は、メサ部を挟んで対向するトレンチ25の各側壁にそれぞれ設けられたゲート絶縁膜26に、それぞれ第2方向に交互に接するようにp+型コンタクト領域33が選択的に配置されている点である。
次に、実施の形態5にかかる半導体装置として、上述した活性領域2に配置する単位セルの構造の一例について説明する。図13は、実施の形態5にかかる半導体装置の平面レイアウトを示す平面図である。図14は、図13の切断線I−I’における断面構造を示す断面図である。図15は、図13の切断線J−J’における断面構造を示す断面図である。図14,15には、オン状態のときに単位セルに流れる電流を順に符号51,52を付した矢印で示す。実施の形態5にかかる半導体装置は、実施の形態4にかかる半導体装置をプレーナゲート型MOSFETに適用した一例である。図13〜15に示すように、n-型ドリフト層41となるn-型半導体基板(半導体チップ)のおもて面側にはプレーナゲート型のMOSゲート構造が設けられている。MOSゲート構造は、例えば、p-型ベース領域42、n+型ソース領域43、ゲート絶縁膜44およびゲート電極45からなる。
2 活性領域
2a〜2f,12a〜12c 活性領域の区分
3,5 電極パッド
3a 電極パッドの端部
4 ワイヤー
6 ワイヤーと電極パッドとの接合部
6a ワイヤーと電極パッドとの接合部の端部
21,41 n-型ドリフト層
22,42 p-型ベース領域
23,34,43,43a,43b n+型ソース領域
24,33,33a,33b p+型コンタクト領域
25 トレンチ
26,44 ゲート絶縁膜
27,45 ゲート電極
28 高温酸化膜
29,46 層間絶縁膜
30,47 ソース電極
31,32 単位セルに流れる電流
X,Y,Z 境界領域
t1 n+型ソース領域の第2方向の幅
t2 n+型ソース領域の第2方向のピッチ
t3 p+型コンタクト領域の第2方向の幅
w1,w4 n+型ソース領域の第1方向の幅
w2 隣り合うトレンチ間の距離
w3 p+型コンタクト領域の第1方向の幅
w5 p-型ベース領域の第1方向の幅
Claims (6)
- 半導体基板に設けられた複数のセルと、
前記半導体基板のおもて面に、前記半導体基板の全体にわたって設けられた、複数の前記セルに共通のおもて面電極と、
前記半導体基板の中央部よりも外周部側に片寄って配置され、前記おもて面電極に接し、前記おもて面電極よりも前記半導体基板の表面積に対する占有面積が小さい電極パッドと、
前記電極パッドに接合され、前記セルに流れる電流を外部へ引き出すワイヤーと、
を備え、
前記ワイヤーと前記電極パッドとの接合部の付近に通電能力の高い前記セルが配置され、前記接合部から離れた位置に通電能力の低い前記セルが配置されていることを特徴とする半導体装置。 - 前記接合部から離れた位置から前記接合部へ向かって前記おもて面電極を流れる電流の経路に沿って、通電能力の異なる2種類以上の前記セルが配置されていることを特徴とする請求項1に記載の半導体装置。
- 前記接合部から離れるほど通電能力の低い前記セルが配置されていることを特徴とする請求項1または2に記載の半導体装置。
- 前記おもて面電極を流れる電流の経路に沿って並ぶ複数の区分にそれぞれ通電能力の異なる前記セルが配置されていることを特徴とする請求項1〜3のいずれか一つに記載の半導体装置。
- 前記セルは金属−酸化膜−半導体からなる絶縁ゲート構造を備え、
チャネルにおける電流密度を調整することにより前記セルの通電能力が設定されていることを特徴とする請求項1〜4のいずれか一つに記載の半導体装置。 - 前記セルは、
前記おもて面電極を流れる電流の経路に沿う方向に延びるストライプ状に設けられたトレンチと、
前記トレンチの内部に、ゲート絶縁膜を介して設けられたゲート電極が設けられたトレンチゲート構造を有することを特徴とする請求項1〜5のいずれか一つに記載の半導体装置。
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JP2014248431A JP6507609B2 (ja) | 2014-12-08 | 2014-12-08 | 半導体装置 |
US14/942,786 US10439061B2 (en) | 2014-12-08 | 2015-11-16 | Semiconductor device |
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2018125326A (ja) * | 2017-01-30 | 2018-08-09 | サンケン電気株式会社 | 半導体装置 |
JP2018152504A (ja) * | 2017-03-14 | 2018-09-27 | エイブリック株式会社 | 半導体装置 |
WO2020149212A1 (ja) * | 2019-01-16 | 2020-07-23 | 株式会社デンソー | 半導体装置およびその製造方法 |
JP2021005692A (ja) * | 2019-06-27 | 2021-01-14 | 株式会社デンソー | 半導体装置 |
JP2021111641A (ja) * | 2020-01-06 | 2021-08-02 | 株式会社デンソー | 半導体装置 |
WO2023127255A1 (ja) * | 2021-12-27 | 2023-07-06 | 富士電機株式会社 | 半導体装置 |
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Publication number | Priority date | Publication date | Assignee | Title |
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