WO2015133064A1 - 半導体エピタキシャルウェーハの製造方法及び半導体エピタキシャルウェーハ - Google Patents
半導体エピタキシャルウェーハの製造方法及び半導体エピタキシャルウェーハ Download PDFInfo
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- WO2015133064A1 WO2015133064A1 PCT/JP2015/000597 JP2015000597W WO2015133064A1 WO 2015133064 A1 WO2015133064 A1 WO 2015133064A1 JP 2015000597 W JP2015000597 W JP 2015000597W WO 2015133064 A1 WO2015133064 A1 WO 2015133064A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 116
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 42
- 238000000034 method Methods 0.000 title claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 40
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 32
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 32
- 239000010703 silicon Substances 0.000 claims abstract description 32
- 230000002093 peripheral effect Effects 0.000 claims abstract description 19
- 150000004767 nitrides Chemical class 0.000 claims description 21
- 238000005530 etching Methods 0.000 claims description 13
- 239000002253 acid Substances 0.000 claims description 8
- 239000013078 crystal Substances 0.000 claims description 6
- 238000005336 cracking Methods 0.000 abstract description 2
- 230000032798 delamination Effects 0.000 abstract 1
- 238000000227 grinding Methods 0.000 description 19
- 230000000052 comparative effect Effects 0.000 description 4
- 239000000428 dust Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910002704 AlGaN Inorganic materials 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 2
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 2
- 230000037303 wrinkles Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010410 dusting Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
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- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
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Definitions
- the present invention relates to a method for manufacturing a semiconductor epitaxial wafer having an epitaxial growth layer on a silicon-based substrate, and a semiconductor epitaxial wafer.
- a hetero-homo epitaxial wafer is manufactured by epitaxial growth on the surface of a silicon-based substrate (for example, a silicon substrate or a silicon carbide substrate) using a commercially available epitaxial manufacturing apparatus. .
- the thickness of the epitaxial growth layer is increased at the outer periphery, and a crown of the epitaxial growth layer (protrusions higher than the main surface of the growth layer) is generated.
- Conditions such as the thickness of each layer of the epitaxial growth layer are selected so that the warp of the silicon-based substrate and the stress of the epitaxial growth layer are optimized at the center of the wafer used as a semiconductor device.
- Patent Document 1 a method of chamfering the outer peripheral portion of a silicon substrate and forming an epitaxial growth layer thereon has been proposed (for example, Patent Document 1).
- Patent Document 2 As countermeasures against cracks, epitaxial growth is performed after roughening the vicinity of the edge of the Si substrate (Patent Document 2), and the ⁇ 111> direction is the rotation axis and the ⁇ 110> direction is 30 ° and 90 ° counterclockwise.
- a silicon substrate having a (111) plane having an orientation flat in a direction rotated by any angle of 150 ° as the main surface (Patent Document 3), or a peripheral portion of a silicon-based substrate It has been proposed to perform epitaxial growth with the ring covered with a ring (Patent Document 4).
- JP 59-227117 A International Publication No. 2011/161975 JP 2011-165902 A JP 2013-171898 A JP 2007-246289 A
- crack-free even in an epitaxial wafer generally called “crack-free”, cracks are present in an area of about several mm from the outer periphery due to the occurrence of a crown.
- the present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor epitaxial wafer manufacturing method capable of obtaining a complete crack-free semiconductor epitaxial wafer.
- the present invention comprises a step of epitaxially growing a semiconductor layer on a silicon-based substrate to produce an epitaxial wafer, an observation step of observing the outer peripheral portion of the produced epitaxial wafer, and the observation
- a method for producing a semiconductor epitaxial wafer comprising: a cracking process, an epitaxial layer peeling observed in the process, and a removing process of removing a part of a reaction trace.
- a complete crack-free semiconductor epitaxial wafer can be easily obtained by observing the outer periphery of the fabricated epitaxial wafer and removing the observed cracks, epitaxial layer peeling, and reaction traces.
- cracks can be prevented from extending or the epitaxial growth layer can be exfoliated to contaminate the manufacturing line.
- the removal step it is preferable to grind the crack, the epitaxial layer peeling, and the reaction trace portion without changing the outer diameter of the silicon-based substrate of the epitaxial wafer.
- the same apparatus and jig corresponding to the diameter of the silicon substrate before grinding can be used.
- the ground surface of the epitaxial wafer is made into a mirror surface or a quasi-mirror surface by mixed acid etching after the removing step.
- the grinding surface of the epitaxial wafer is made into a mirror surface or a quasi-mirror surface by mixed acid etching, dust generation from the ground portion can be suppressed.
- the eaves portion of the epitaxial layer formed by etching the silicon substrate by the mixed acid etching is removed by chamfering. In this way, by removing the ridge portion of the epitaxial layer by chamfering, chipping of the ridge portion in the subsequent process can be prevented.
- the semiconductor layer may be made of a nitride semiconductor.
- a nitride semiconductor can be suitably used as the semiconductor layer to be epitaxially grown.
- the nitride semiconductor can be any one or more of AlN, GaN, InN, or a mixed crystal thereof.
- the nitride semiconductor used for the semiconductor layer to be epitaxially grown the above materials can be suitably used.
- the present invention is a semiconductor epitaxial wafer in which a semiconductor layer is epitaxially grown on a silicon-based substrate, wherein at least a part of the semiconductor layer is removed from an outer peripheral portion of the semiconductor epitaxial wafer.
- a featured semiconductor epitaxial wafer is provided.
- the epitaxially grown semiconductor layer is removed at the outer peripheral portion of the semiconductor epitaxial wafer, so that cracks, epitaxial layer peeling, and reaction traces generated at the outer peripheral portion of the semiconductor epitaxial wafer are removed.
- the part can be removed, and it can be easily made into a complete crack-free semiconductor epitaxial wafer.
- cracks are stretched or the epitaxial growth layer is peeled off to contaminate the production line. It can be set as the semiconductor epitaxial wafer which does not carry out.
- the part from which at least a part of the semiconductor layer is removed is a mirror surface or a quasi-mirror surface. With such a configuration, dust generation from the removed portion can be suppressed.
- the silicon-based substrate may be exposed in a portion where at least a part of the semiconductor layer is removed.
- the semiconductor layer may be made of a nitride semiconductor.
- the present invention is particularly useful when the semiconductor layer to be epitaxially grown is a nitride semiconductor.
- the nitride semiconductor can be any one or more of AlN, GaN, InN, or a mixed crystal thereof.
- a complete crack-free semiconductor epitaxial wafer can be obtained more effectively.
- FIG. 1 It is a figure which shows an example of the manufacturing flow of the manufacturing method of the semiconductor epitaxial wafer of this invention. It is a figure which shows the semiconductor epitaxial wafer manufactured by the manufacturing method of the semiconductor epitaxial wafer of this invention. It is a figure which shows the crack and reaction trace which were observed in the peripheral part of the semiconductor epitaxial wafer of a comparative example. It is a figure which shows the collar part of the epitaxial layer formed at the manufacturing process of the manufacturing method of the semiconductor epitaxial wafer of this invention.
- the inventors can easily obtain a complete crack-free semiconductor epitaxial wafer, and in subsequent processes such as the device manufacturing process, cracks are stretched or the epitaxial growth layer is separated to contaminate the production line.
- the semiconductor epitaxial wafer manufacturing method that can suppress the occurrence of such a process has been intensively studied.
- it is possible to easily obtain a complete crack-free semiconductor epitaxial wafer by observing the outer peripheral portion of the fabricated epitaxial wafer and removing the observed crack, epitaxial layer peeling, and reaction trace portion.
- cracks can be prevented from extending in the subsequent process such as a device manufacturing process, or the epitaxial growth layer can be exfoliated to contaminate the production line, thereby achieving the present invention.
- a silicon substrate is prepared and placed in an epitaxial growth furnace.
- the silicon-based substrate is, for example, a silicon (Si) substrate or a silicon carbide (SiC) substrate.
- an epitaxial growth layer is formed on a silicon substrate set at 900 ° C. or more, for example, 1200 ° C. using an epitaxial growth method such as metal organic chemical vapor deposition (MOCVD).
- MOCVD metal organic chemical vapor deposition
- the composition of the epitaxial layer is not particularly limited, but can be a nitride semiconductor, and the nitride semiconductor can be any one or more of AlN, GaN, InN, or a mixed crystal thereof.
- a buffer layer in which AlGaN layers and GaN layers are alternately stacked can be grown, and a GaN layer can be formed on the surface of the buffer layer, with a total thickness of about 3 to 10 ⁇ m.
- the outer peripheral portion of the epitaxial wafer is observed to check for cracks, reaction traces, the presence or absence of epitaxial layer peeling, and the occurrence position.
- this observation method is not particularly limited, for example, cracks and reaction marks can be visually observed under a condenser lamp, and the film can be peeled off with a microscope to observe the reaction marks.
- production part, and epitaxial layer peeling are removed by grinding.
- the same apparatus and jig corresponding to the diameter of the silicon substrate before grinding can be used.
- the grinding can be performed by using a commercially available grinding wheel to grind the outer peripheral portion of the wafer in the range of 1 to 15 mm in width and deeper by about 1 to 250 ⁇ m in depth than the thickness of the epitaxial layer.
- the ground surface from which the epitaxial layer has been completely removed is in a state in which the silicon substrate is exposed, but it is not always necessary to completely remove the epitaxial layer if there are no defects such as cracks.
- the removing method is not limited to grinding, and etching or polishing may be used.
- the grinding surface of an outer peripheral part is etched, for example with a mixed acid, to make a mirror surface or a semi-mirror surface.
- a mixed acid for example, a mixed acid
- dusting from a grinding part can be suppressed by making a grinding surface into a mirror surface or a semi-mirror surface by etching.
- CMP chemical mechanical polishing
- the ridge portion (see FIG. 4) of the outer peripheral portion of the epitaxial layer formed by etching is chamfered and removed.
- a semiconductor epitaxial wafer is manufactured according to the manufacturing flow shown in FIG. 1, a complete crack-free semiconductor epitaxial wafer can be easily obtained. In subsequent processes such as a device manufacturing process, It is possible to suppress peeling and causing contamination of the production line.
- the semiconductor epitaxial wafer of the present invention is a semiconductor epitaxial wafer in which a semiconductor layer is epitaxially grown on a silicon-based substrate, and at least a part of the semiconductor layer is removed from the outer periphery of the semiconductor epitaxial wafer.
- At least a part of the epitaxially grown semiconductor layer is removed from the outer peripheral part of the semiconductor epitaxial wafer, thereby removing cracks, epitaxial layer peeling, and reaction traces occurring in the outer peripheral part of the semiconductor epitaxial wafer. It is possible to easily obtain a complete crack-free semiconductor epitaxial wafer, and in subsequent processes such as the device manufacturing process, cracks extend or the epitaxial growth layer is peeled off to contaminate the production line. Can be suppressed.
- the part from which at least a part of the epitaxially grown semiconductor layer is removed is a mirror surface or a quasi-mirror surface. With such a configuration, dust generation from the removed portion can be suppressed.
- the silicon-based substrate can be exposed in a portion where at least a part of the epitaxially grown semiconductor layer is removed.
- the epitaxially grown semiconductor layer can be made of a nitride semiconductor.
- the semiconductor layer to be epitaxially grown is a nitride semiconductor.
- the nitride semiconductor can be any one or more of AlN, GaN, InN, or a mixed crystal thereof.
- a complete crack-free semiconductor epitaxial wafer can be obtained more effectively.
- FIG. 3 shows the state of cracks and reaction marks in the periphery of the semiconductor epitaxial wafer fabricated as described above.
- Example 2A A semiconductor epitaxial wafer was produced in the same manner as in the comparative example. After observing the outer periphery of the fabricated semiconductor epitaxial wafer with a condenser lamp, the cracked portion, epitaxial layer peeling (epitaxial layer peeling) portion, and reaction trace portion of the outer periphery portion of the semiconductor epitaxial wafer were widened with a grinding wheel. Grinding (terrace chamfering) at 10 mm and a depth of 50 ⁇ m. The semiconductor epitaxial wafer after grinding is shown in FIG. 2A is a photograph of the semiconductor epitaxial wafer after grinding as viewed obliquely from above, and FIG.
- FIG. 2B is a cross-sectional view of the periphery of the semiconductor epitaxial wafer after grinding
- FIG. 2C and FIG. 2 (d) is an enlarged photograph of the vicinity of the boundary between the epitaxial layer portion and the terrace chamfered portion around the semiconductor epitaxial wafer after grinding.
- FIG. 2 it can be seen that the crack portion, epitaxial layer peeling (epitaxial layer curling) portion, and reaction trace portion on the outer peripheral portion of the wafer are all removed cleanly.
- the ground part was made into a mirror surface or a semi-mirror surface by performing the mixed acid etching of the ground part. Then, the ridge part of the epitaxial layer formed by the mixed acid etching was removed by tape chamfering.
- the present invention is not limited to the above embodiment.
- the above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.
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Abstract
Description
半導体装置として使用するウェーハ中央部でシリコン系基板の反りとエピタキシャル成長層の応力が最適になるように、エピタキシャル成長層の各層の厚みなどの条件が選択されている。このため、上記クラウンが発生すると、エピタキシャル成長層に生じる応力と基板の反りのバランスが崩れてエピタキシャル成長層に影響を与え、外周部近傍のエピタキシャル成長層に亀甲模様のクラックなどが生じる。
また、クラック対策としては、Si基板エッジ近傍を粗面化してからエピタキシャル成長を行うこと(特許文献2)や、<111>方向を回転軸として、<110>方向を左回りに30°、90°、150°のいずれかの角度だけ回転させた方向にオリフラを有する(111)面を主面とするシリコン基板をヘテロエピタキシャル成長用基板として使用すること(特許文献3)や、シリコン系基板の周辺部をリングで覆った状態でエピタキシャル成長を行うこと(特許文献4)等が提案されている。
このような反応痕への対策としては、SOI基板上にバッファ膜(AlN膜)を介して厚膜のGaN膜をエピタキシャル成長させることが提案されている(特許文献5)。
このように、エピタキシャルウェーハのシリコン系基板の外径を変えず、クラック、エピタキシャル層剥れ、及び、反応痕の部分を研削することで、後工程においてエピタキシャルウェーハの直径の変化を考慮する必要がなく、研削前のシリコン系基板の直径に対応した同一の装置、治具を使用することができる。
このようにエピタキシャルウェーハの研削面を混酸エッチングにより鏡面又は準鏡面にすることで、研削部分からの発塵を抑制することができる。
このようにエピタキシャル層の庇部を面取りにより除去することで後工程での庇部分の欠けを防止することができる。
エピタキシャル成長させる半導体層として、窒化物半導体を好適に用いることができる。
エピタキシャル成長させる半導体層に用いる窒化物半導体として、上記のような材料を好適に用いることができる。
このような構成により、除去部分からの発塵を抑制することができる。
このような構成により、半導体エピタキシャルウェーハの外周部に発生するクラック、エピタキシャル層剥れ、及び、反応痕の部分をより確実に取り除かれたものとすることができる。
窒化物半導体のエピタキシャルウェーハでは、周辺部にクラック、エピタキシャル層剥れ、反応痕が必ず発生するので、エピタキシャル成長させる半導体層が窒化物半導体である場合に本発明は特に有益である。
エピタキシャル成長させる半導体層に用いる窒化物半導体として上記のような材料を用いた半導体エピタキシャルウェーハに適用した場合に、より効果的に完全なクラックフリーの半導体エピタキシャルウェーハとすることができる。
前述のように、「クラックフリー」と呼ばれるエピタキシャルウェーハにおいても、クラウンの発生に起因して外周部から数mm程度の領域にはクラックが存在しているのが現状であり、このクラックはデバイスの製造工程において伸張したり、エピタキシャル成長層の剥離を誘発して製造ラインを汚染したりすることが懸念される。このため、完全にクラックフリーなエピタキシャル基板が望まれている。
その結果、作製されたエピタキシャルウェーハの外周部を観察し、観察されたクラック、エピタキシャル層剥れ、及び、反応痕の部分を取り除くことで、容易に完全なクラックフリーの半導体エピタキシャルウェーハを得ることができ、デバイス製造工程等の後工程において、クラックが伸張したり、エピタキシャル成長層の剥離を誘発して製造ラインを汚染したりすることが抑制できることを見出し、本発明をなすに至った。
まず、図1(a)に示すようにシリコン系基板を準備し、エピタキシャル成長炉に配置する。シリコン系基板は、例えばシリコン(Si)基板やシリコンカーバイド(SiC)基板などである。
このエピタキシャル層の組成は特に限定されないが、窒化物半導体とすることができ、また、この窒化物半導体を、AlN、GaN、InN、又はそれらの混晶のいずれか1つ以上とすることができる。例えば、AlN層を形成した後、AlGaN層とGaN層を交互に積層したバッファ層を成長させ、その表面にGaN層を形成することができ、全体として3~10μm程度の厚さで成長させる。
このとき、エピタキシャルウェーハのシリコン系基板の外径を変えず、クラック、エピタキシャル層剥れ、反応痕の部分を研削することが好ましい。
このように、エピタキシャルウェーハのシリコン系基板の外径を変えず、クラック、エピタキシャル層剥れ、反応痕の部分を研削することで、後工程においてエピタキシャルウェーハの直径の変化を考慮する必要がなく、研削前のシリコン系基板の直径に対応した同一の装置、治具を使用することができる。
ここで研削は市販の研削用ホイールを用いてウェーハ外周部を幅1~15mmの範囲で、深さをエピタキシャル層の厚さより1~250μm程度深く研削することができる。
この場合、エピタキシャル層を完全に除去した研削面はシリコン系基板が露出した状態となるが、クラック等の欠陥が無くなれば必ずしもエピタキシャル層を完全に除去する必要はない。
また、除去方法も研削に限定されず、エッチングや研磨を用いてもよい。
なお、細かな番手の研削ホイールを使った場合は、研削面の表面粗さが低減されているので、必ずしもエッチングする必要はない。
また、鏡面化はCMP(化学的機械的研磨)を用いてもよい。
本発明の半導体エピタキシャルウェーハは、シリコン系基板上に半導体層がエピタキシャル成長された半導体エピタキシャルウェーハであって、半導体エピタキシャルウェーハの外周部において、半導体層の少なくとも一部が除去されているものである。
このような構成により、除去部分からの発塵を抑制することができるものとなる。
このような構成により、半導体エピタキシャルウェーハの外周部に発生するクラック、エピタキシャル層剥れ、及び、反応痕の部分がより確実に取り除かれたものとなる。
窒化物半導体のエピタキシャルウェーハでは、周辺部にクラック、エピタキシャル層剥れ、反応痕が必ず発生するので、エピタキシャル成長させる半導体層が窒化物半導体である場合に本発明は特に有益である。
エピタキシャル成長させる半導体層に用いる窒化物半導体として上記のような材料を用いた半導体エピタキシャルウェーハに適用した場合に、より効果的に完全なクラックフリーの半導体エピタキシャルウェーハとすることができる。
直径150mmで厚さ1mmのシリコン基板上に、エピタキシャル成長によりAlN層を形成した後、AlGaN層とGaN層を交互に積層したバッファ層を成長させ、その表面にGaN層を形成した。
エピタキシャル層の厚さは全体で10μmであった。
また、エピタキシャル層剥がれが全周に散在し、反応痕が全周にまばらに散在した。
図3に上記のようにして作製した半導体エピタキシャルウェーハの周辺部のクラック及び反応痕の様子を示す。
比較例と同様にして、半導体エピタキシャルウェーハを作製した。
作製された半導体エピタキシャルウェーハの外周部を集光灯で観察した後、半導体エピタキシャルウェーハ外周部のクラック部分、エピタキシャル層剥れ(エピタキシャル層捲くれ)部分、及び、反応痕部分を研削用ホイールで幅10mm、深さ50μmで研削(テラス面取り)した。
研削後の半導体エピタキシャルウェーハを図2に示す。
図2(a)は研削後の半導体エピタキシャルウェーハを斜め上から見た写真であり、図2(b)は研削後の半導体エピタキシャルウェーハの周辺部の断面図であり、図2(c)及び図2(d)は研削後の半導体エピタキシャルウェーハの周辺部のエピタキシャル層部とテラス面取り部との境界付近の拡大写真である。
図2からわかるように、ウェーハ外周部のクラック部分、エピタキシャル層剥れ(エピタキシャル層捲くれ)部分、反応痕部分が全て綺麗に除去されていることがわかる。
その後、テープ面取りにより混酸エッチングで形成されたエピタキシャル層の庇部分を取り除いた。
Claims (11)
- シリコン系基板上に半導体層をエピタキシャル成長させて、エピタキシャルウェーハを作製する工程と、
前記作製されたエピタキシャルウェーハの外周部を観察する観察工程と、
前記観察工程において観察されたクラック、エピタキシャル層剥れ、及び、反応痕の部分を取り除く除去工程と
を有することを特徴とする半導体エピタキシャルウェーハの製造方法。 - 前記除去工程において、前記エピタキシャルウェーハの前記シリコン系基板の外径を変えず、前記クラック、前記エピタキシャル層剥れ、及び、前記反応痕の部分を研削することを特徴とする請求項1に記載の半導体エピタキシャルウェーハの製造方法。
- 前記除去工程の後に、前記エピタキシャルウェーハの研削面を混酸エッチングにより鏡面又は準鏡面にすることを特徴とする請求項2に記載の半導体エピタキシャルウェーハの製造方法。
- 前記混酸エッチングにより前記シリコン系基板がエッチングされたことで形成される前記エピタキシャル層の庇部を、面取りにより除去することを特徴とする請求項3に記載の半導体エピタキシャルウェーハの製造方法。
- 前記半導体層が窒化物半導体からなることを特徴とする請求項1から請求項4のいずれか一項に記載の半導体エピタキシャルウェーハの製造方法。
- 前記窒化物半導体が、AlN、GaN、InN、又はそれらの混晶のいずれか1つ以上であることを特徴とする請求項5に記載の半導体エピタキシャルウェーハの製造方法。
- シリコン系基板上に半導体層がエピタキシャル成長された半導体エピタキシャルウェーハであって、
前記半導体エピタキシャルウェーハの外周部において、前記半導体層の少なくとも一部が除去されているものであることを特徴とする半導体エピタキシャルウェーハ。 - 前記半導体層の少なくとも一部が除去されている部分が鏡面又は準鏡面になっていることを特徴とする請求項7に記載の半導体エピタキシャルウェーハ。
- 前記半導体層の少なくとも一部が除去されている部分は、前記シリコン系基板が露出していることを特徴とする請求項7又は請求項8に記載の半導体エピタキシャルウェーハ。
- 前記半導体層が窒化物半導体からなることを特徴とする請求項7から請求項9のいずれか一項に記載の半導体エピタキシャルウェーハ。
- 前記窒化物半導体が、AlN、GaN、InN、又はそれらの混晶のいずれか1つ以上であることを特徴とする請求項10に記載の半導体エピタキシャルウェーハ。
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Also Published As
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JP2015170648A (ja) | 2015-09-28 |
US20180245240A1 (en) | 2018-08-30 |
CN106068546A (zh) | 2016-11-02 |
JP6261388B2 (ja) | 2018-01-17 |
CN106068546B (zh) | 2019-04-26 |
DE112015000781B4 (de) | 2023-08-17 |
US20170029977A1 (en) | 2017-02-02 |
TW201538812A (zh) | 2015-10-16 |
KR20160130763A (ko) | 2016-11-14 |
US9938638B2 (en) | 2018-04-10 |
KR102143988B1 (ko) | 2020-08-12 |
DE112015000781T5 (de) | 2017-01-12 |
TWI604094B (zh) | 2017-11-01 |
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