WO2015098460A1 - 有芯構造はんだバンプ及びその製造方法 - Google Patents

有芯構造はんだバンプ及びその製造方法 Download PDF

Info

Publication number
WO2015098460A1
WO2015098460A1 PCT/JP2014/082181 JP2014082181W WO2015098460A1 WO 2015098460 A1 WO2015098460 A1 WO 2015098460A1 JP 2014082181 W JP2014082181 W JP 2014082181W WO 2015098460 A1 WO2015098460 A1 WO 2015098460A1
Authority
WO
WIPO (PCT)
Prior art keywords
powder
solder
group
core
sintered
Prior art date
Application number
PCT/JP2014/082181
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
将 中川
石川　雅之
司 八十嶋
Original Assignee
三菱マテリアル株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三菱マテリアル株式会社 filed Critical 三菱マテリアル株式会社
Priority to KR1020167004857A priority Critical patent/KR102122631B1/ko
Priority to CN201480053701.XA priority patent/CN105593980B/zh
Publication of WO2015098460A1 publication Critical patent/WO2015098460A1/ja

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11332—Manufacturing methods by local deposition of the material of the bump connector in solid form using a powder
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/115—Manufacturing methods by chemical or physical modification of a pre-existing or pre-deposited material
    • H01L2224/11505—Sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • H01L2224/11902—Multiple masking steps
    • H01L2224/11903—Multiple masking steps using different masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/13076—Plural core members being mutually engaged together, e.g. through inserts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13113—Bismuth [Bi] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13157—Cobalt [Co] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/1316—Iron [Fe] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13169—Platinum [Pt] as principal constituent

Definitions

  • the present invention relates to a cored structure solder bump and a method of manufacturing the same, and more particularly, to form a cored structure solder bump on a fine pitch of a solder bump for a semiconductor device and a cored structure solder bump on a pad electrode of a semiconductor device. It is related with the manufacturing method for doing.
  • This application claims priority based on Japanese Patent Application No. 2013-270852 filed in Japan on December 27, 2013, the contents of which are incorporated herein by reference.
  • solder bumps In recent years, bonding using solder bumps is generally used for high-density mounting of semiconductors, but in order to achieve higher density, a fine pitch for forming solder bumps is required. In order to meet this demand, several proposals have conventionally been made for solder bumps for realizing a fine pitch or a manufacturing method thereof.
  • a solder metal reflow process is performed by sequentially forming a pillar metal, an under bump metal layer covering the top surface of the pillar metal, and a solder metal layer having substantially the same diameter as the conductor pad on the conductor pad on the surface of the semiconductor substrate. It has been proposed to form solder bumps by performing the above. Further, in Patent Document 2, a solder metal layer (barrier metal layer 14) having substantially the same diameter as the conductor pad 13 is sequentially formed in the same manner as described in Patent Document 1, and then the diameter of the pillar metal layer 15 is reduced. Next, it has been proposed to achieve a fine pitch by performing a reflow process on the solder metal 17 to form solder bumps as shown in FIG.
  • a primary solder bump is formed on a pad electrode by making a pad electrode on a semiconductor chip face down and contacting a jet surface of molten solder, and the primary solder bump is formed. With the pad electrode facing upward, solder paste is placed on this by screen printing, this solder paste is facing downward, and the solder paste is reflowed in the state where it is directed downward and gravity is applied to form secondary solder bumps. It has also been proposed to produce solder bumps that enable the pad electrodes to have a fine pitch.
  • Japanese Unexamined Patent Publication No. 2013-187258 A) Japanese Unexamined Patent Publication No. 2006-332694 (A) Japanese Patent No. 3961876 (B)
  • the aspect ratio is naturally limited by the weight and surface tension of the solder metal, and contact with the adjacent molten solder metal bumps may cause poor electrical continuity. Therefore, in order to realize high-density mounting of semiconductors, a high aspect ratio solder bump capable of achieving a fine pitch and a simple manufacturing method thereof are desired.
  • a solder bump for example, a predetermined position of a semiconductor substrate (for example, a surface of a pad electrode formed on an organic substrate for a semiconductor package or an UBM (underlayer formed on a semiconductor package wafer). Bump metal)) is preliminarily coated with a core paste made of a predetermined material and reflowed to form a sintered core having a predetermined height, and then a printing method around the sintered core. It was found that a solder bump having a cored structure can be formed by applying a solder paste and then reflowing the solder paste.
  • this cored solder bump is hard to flatten due to its own weight, so it should be a high aspect ratio solder bump with high bump height, and select the material of the sintered core appropriately As a result, the adhesion to the solder metal is improved, and accordingly, the adhesion between the bump and the semiconductor substrate is also improved. Furthermore, this high aspect ratio cored structure solder bump is inferior to the conventional bump. It has been found that it has no electrical conductivity.
  • the present inventors have found that the solder bump with the core structure can be easily produced by a normal screen printing method. That is, as a first step, a pad is placed on a predetermined position of a semiconductor substrate (for example, a pad electrode surface formed on an organic substrate for a semiconductor package or an UBM (under bump metal) formed on a semiconductor package wafer). A mask having an opening that exposes the electrode or UBM slightly is attached, and a paste for core to be a sintered core is printed on the central portion of the pad electrode or UBM, and then the mask is removed and applied to the pad electrode or UBM.
  • a semiconductor substrate for example, a pad electrode surface formed on an organic substrate for a semiconductor package or an UBM (under bump metal) formed on a semiconductor package wafer.
  • a mask having an opening that exposes the electrode or UBM slightly is attached, and a paste for core to be a sintered core is printed on the central portion of the pad electrode or UBM, and then the mask is removed and applied to the pad electrode or UBM.
  • the core paste is sintered at a temperature near or below the reflow temperature of the solder paste to produce a sintered core having a predetermined height at the center portion of the pad electrode or UBM.
  • a mask having an opening with a diameter larger than the diameter of the pad electrode or UBM has a sintered core formed substantially at the center.
  • the pad electrode or UBM is attached so that it is exposed, and the solder paste is applied so as to cover the pad electrode or UBM and the entire sintered core, and then the mask is removed to cover the pad electrode or UBM and the entire sintered core.
  • the present inventors have found that a solder bump having a core structure can be manufactured by a simple process by reflowing the solder paste coated and printed at the reflow temperature of the solder paste.
  • a cored structure solder bump formed on a semiconductor substrate the solder bump being formed inside the solder bump and extending in a direction perpendicular to the semiconductor substrate, and the sintering It consists of a cored structure with a solder metal deposited around the core, and the sintered core is made of a sintered body sintered at a temperature near or below the reflow processing temperature of the solder paste.
  • Core bumped solder bump is made
  • the sintered core is composed of a powder sintered body of a first group powder and a second group powder, an alloy sintered body, or a mixed sintered body thereof, and the first group powder is a first group A Containing at least one of powder and first group B powder, and the first group A powder is one or two selected from Cu, Ag, Au, Pt, Pd, Ti, Ni, Fe, Co
  • the first group B powder is one or two selected from a brazing alloy powder having a liquidus temperature of 450 ° C. or higher and a high-temperature solder alloy powder having a liquidus temperature of 280 ° C. or higher.
  • the sintered core is composed of a powder sintered body of a first group powder and a second group powder, an alloy sintered body, or a mixed sintered body thereof, and the second group powder is a second group A Containing at least one of powder and second group B powder, wherein the second group A powder is composed of one or more metal powders selected from Sn, In, Bi, Ga, and 2nd group B powder consists of alloy powder of a solder alloy whose liquidus temperature is 240 degrees C or less,
  • the cored structure solder bump as described in said (1) characterized by the above-mentioned.
  • a method for producing a cored solder bump formed on a semiconductor substrate wherein a core paste is printed on the surface of a pad electrode or under bump metal formed on the semiconductor substrate, and the solder paste is reflowed.
  • the core paste is sintered at a temperature near or below the processing temperature to form a sintered core at a substantially central portion of the surface of the pad electrode or under bump metal, and then at a substantially central portion of the pad electrode or under bump metal.
  • the solder paste is printed and applied so as to cover the entire sintered core formed on the substrate, and the reflow treatment is performed at the solder paste reflow temperature, so that the cored solder bump is formed on the surface of the pad electrode or the surface of the under bump metal.
  • the cored structure solder bump which is an aspect of the present invention (hereinafter referred to as the cored structure bump of the present invention)
  • flattening due to the weight of the bump hardly occurs, and a solder bump having a high aspect ratio can be formed.
  • the sintered core formed inside the solder bump and the solder metal have excellent adhesion. As a result, the solder bump adheres firmly to the pad electrode and the semiconductor substrate, and also lowers the conductivity. Therefore, a fine pitch for realizing high-density mounting of semiconductors becomes possible.
  • a cored structure solder bump can be obtained by a simple manufacturing method in which a sintered core is formed by ligation and then solder paste 34 is applied and reflowed by the printing method, so that the solder bump manufacturing process is simplified. And cost reduction.
  • FIG. 2 shows a schematic explanatory view of the manufacturing process of the cored structure solder bump of the present invention
  • FIG. 3 shows a schematic cross-sectional view of the cored structure solder bump obtained by the manufacturing method of the present invention.
  • the cored solder bump of the present invention is manufactured by the steps (a) to (d) (referred to as the first step) and the steps (e) to (h) (referred to as the second step). can do.
  • the first step is as follows. First, the pad electrode is formed on the surface of the semiconductor substrate 1 on which the pad electrode 2 is formed (including the case where the UBM is provided on the semiconductor package wafer, but the description of the UBM is omitted below). 2 is attached (see FIG. 2A), and a squeegee 31 is used from the opening of the metal mask 33 to the surface of the pad electrode 2 at the substantially central portion.
  • the core paste 32 is printed (see FIG. 2B).
  • the core paste is printed and filled (S1) in the opening.
  • the metal mask 33 is removed (see FIG. 2C), and sintered (S2) at a temperature corresponding to the type of the core paste 32 (at or near the reflow temperature of the solder paste 34) (S2).
  • S2 sintered
  • FIG. 4 shows SEM images of nine sintered cores 3 formed at a sintering temperature of 240 ° C. using a core paste E (see Table 2) as an example of the sintered core 3.
  • the illustration of the UBM formed on the surface of the pad electrode 2 is omitted, but the case where the UBM is provided on the pad electrode 2 is also included in the scope of the present invention.
  • the sintered core 3 formed in the first step can be configured as a sintered body of a first group powder and a second group powder.
  • the sintered core 3 can be configured as an alloy sintered body containing the constituent elements constituting the first group powder and the second group powder, or alternatively, the powder sintered body and the alloy sintered body can be sintered.
  • the first group powder is a powder containing at least one of the first group A powder and the first group B powder, and examples of the first group A powder include Cu, Ag, Au, Pt, and Pd.
  • One, two or more metal powders selected from Ti, Ni, Fe, Co can be used, and as the first group B powder, a brazing alloy powder having a liquidus temperature of 450 ° C. or higher and One or two or more alloy powders selected from high-temperature solder alloy powders having a liquidus temperature of 280 ° C. or higher can be used.
  • the second group powder is a powder containing at least one of the second group A powder and the second group B powder, and the second group A powder includes Sn, In, Bi, and Ga.
  • One or two or more selected metal powders can be used, and as the second group B powder, an alloy powder of a solder alloy having a liquidus temperature of 240 ° C. or lower can be used.
  • the sintering temperature for forming the sintered core 3 must be near or lower than the temperature at which the solder paste 34 printed and applied around the sintered core 3 is reflowed in the second step. This is because the sintered core 3 is not softened or melted even during the solder paste reflow process, and the shape as the sintered core 3 is maintained as it is, and the solder metal 4 needs to be attached around the sintered core 3. Because. As a result, the solder bumps 5 having a high aspect ratio are formed, and the sintered core 3 has a wide contact area with the solder metal 4, thereby preventing the solder bumps from being flattened by their own weight. Furthermore, the adhesion between the solder metal 4 and the sintered core 3 is enhanced, and as a result, the effect of enhancing the adhesion between the bump and the pad electrode 2 and the semiconductor substrate 1 is exhibited.
  • the second group powder that melts at the time of reflow is too much, the core collapses, and the core columnar sintering It does not become core 3. Further, at the time of the second reflow, remelting due to the second group powder occurs in the first group powder and the second group powder constituting the core columnar sintered core 3. On the other hand, if the content of the first group powder exceeds 90% by mass, the second group powder that melts at the time of reflow is too little to sinter, and the shape collapses when the solder metal paste is printed in the second step.
  • the content of the first group powder in the mixed powder is desirably 10 to 90% by mass, and more desirably 30 to 80% by mass. Further, depending on the combination of the type of solder metal 4 and the material constituting the sintered core 3, a diffusion reaction occurs at the interface between the solder metal 4 and the sintered core 3, and the adhesion between the solder metal 4 and the sintered core 3 is improved. As a result, a solder bump having a high aspect ratio and further improved adhesion can be formed.
  • the sintered core 3 of the cored structure bump according to the present invention can be sintered at a relatively low temperature in view of the ease of forming the sintered core 3, that is, near or below the reflow temperature of the solder paste 34.
  • the first A group metal powder constituting the sintered core 3 is Cu, It is desirable to use one or more metal powders selected from Ag and Au, and the second A group metal powder is one or two metal powders selected from Sn, In and Bi. It is desirable to use the above metal powder.
  • the core paste 32 used to form the sintered core 3 can be prepared, for example, by the following procedure.
  • the core paste raw material powder the first group powder containing at least one of the first group A powder and the first group B powder, and at least one of the second group A powder and the second group B powder are contained.
  • prepare second group powder These powders are blended so that the total weight of the powder for core paste is 100% by mass, the first group powder is 10 to 90% by mass, and the remainder is the second group powder.
  • a mixed powder is prepared. This mixed powder is mixed in a commonly used powder mixer such as a V-type mixer.
  • the flux is preferably blended so as to be 5 to 40% by mass, and the rest is the mixed powder.
  • the core paste 32 is mechanically kneaded. By mixing in a commonly used kneader such as a machine, a core paste 32 used to form the sintered core 3 of the cored structure bump of the present invention is produced.
  • the flux of the core paste 32 a commonly used general flux can be used, and is not particularly limited, but RA or RMA flux is preferably used from the viewpoint of the wettability of the paste. .
  • the flux may contain rosin, activator, solvent, thixotropic agent and the like that are usually used. Further, when the flux content in the core paste 32 is less than 5% by mass, it does not become a paste. On the other hand, if the flux content exceeds 40% by mass, the viscosity of the core paste 32 is too low, causing sagging during printing, or causing the core to collapse during reflow. A sufficient height cannot be secured.
  • the flux content in the core paste 32 is preferably 5 to 40% by mass, and more preferably 6 to 15% by mass.
  • the sintered core 3 is formed by sintering the core paste 32 in the first step, and the sintering temperature for forming the sintered core 3 is the reflow treatment of the solder paste 34 used in the second step.
  • the temperature needs to be in the vicinity of the temperature (which depends on the type of the solder metal 4) or lower. Therefore, depending on the type of solder metal 4 to be used, the type and blending ratio of the mixed powder contained in the core paste 32 must be determined. For example, when a Pb—Sn alloy (reflow treatment temperature is about 210 ° C.) is used as the solder metal 4, it is necessary to use a core paste that is sintered at this reflow temperature.
  • Pb—Sn alloy paste is printed, and bumps are formed at this reflow temperature.
  • Sn, SnAg alloy, SnCu alloy, SnAgCu alloy reflow treatment temperature is about 240 ° C.
  • Sn, SnAg-based alloy, SnCu alloy, and SnAgCu-based alloy paste are printed, and bumps are formed at this reflow temperature.
  • the core paste 32 used in the present invention needs to determine the types and mixing ratios of the first group powder and the second group powder so that the sintering proceeds at these reflow treatment temperatures.
  • the sintering proceeds by reacting with the first group powder by melting the second group powder.
  • solder bumps are formed using the same component materials for the sintered core 3 (or the mixed powder of the core paste 32) and the solder metal 4, the solder metal 4 at the interface of the sintered core 3 is used. Therefore, it is possible to form solder bumps with even higher adhesion.
  • the solder paste 34 is printed and applied in the second step to produce a solder bump having a core structure. That is, a metal mask 35 having an opening larger than the diameter of the pad electrode 2 formed in the central portion of the sintered core 3 and having a thickness greater than the height of the sintered core 3 is attached (see FIG. 2E).
  • the solder paste 34 is printed and applied using a squeegee 36 so as to cover the exposed portion of the pad electrode 2 and the entire sintered core 3 from the opening of the metal mask 35 (see FIG. 2F). As a result, the solder paste 34 is printed and filled in the above-described opening (S3). Next, the metal mask 36 is removed (see FIG. 2 (g)), reflow treatment is performed at a reflow treatment temperature corresponding to the type of the solder paste 34 (S4), and the sintered core 3 is placed on the surface of the pad electrode 2 Solder bumps are formed so as to be confined inside (see FIG. 2H).
  • the cored structure solder bump of the present invention is formed by the first step (FIGS. 2A to 2D) and the second step (FIGS. 2E to 2H).
  • the longitudinal cross-section enlarged schematic diagram of the cored structure solder bump of this invention is shown.
  • the cored structure solder bump of the present invention includes a sintered core 3 inside the bump, and a solder metal 4 is deposited around the sintered core 3.
  • a solder bump having an egg shape and a core structure is formed.
  • the bump is flattened due to the weight of the solder bump itself, and the bump height cannot be increased.
  • the solder metal 4 is brought into close contact with the sintered core 3 inside the solder bump constituting the cored structure, so that the conductivity is not lowered, and the solder bump and the sintered core 3, and thus the solder bump and the pad electrode.
  • the height H of the solder bump can be increased.
  • the height of the solder bump in the prior art is h and the aspect ratio h / d of the conventional solder bump when the solder bump diameter is d is compared with the aspect of the core bumped solder bump of the present invention.
  • the ratio H / D between the height H and the solder bump diameter D is a large value (that is, H / D> h / d). Therefore, a fine pitch of the solder bumps can be realized.
  • the UBM formed on the surface of the pad electrode 2 is not shown, but the case where the UBM is provided on the pad electrode 2 is also included in the scope of the present invention. .
  • Table 1 shows the component compositions of five types of alloy powders as the solder metal used to form the solder bumps in Example 1.
  • the particle size of the solder metal alloy powder is 2 to 12 ⁇ m, and the average particle size is 7 ⁇ m.
  • Table 2 shows the types, combinations, and blending ratios of the powders contained in the core pastes A to M used for forming the sintered core in Example 1, and the types and content ratios of the flux. Show.
  • the powder contained in the core paste has a particle size of 1 to 5 ⁇ m and an average particle size of 2.5 ⁇ m.
  • an opening (opening) having a diameter smaller than the pad electrode diameter is formed on the surface of the semiconductor substrate 1 on which the pad electrode (diameter: 85 ⁇ m) 2 is formed.
  • a metal mask 33 with a thickness of 20 ⁇ m provided with a diameter of 43 ⁇ m and an opening pitch of 150 ⁇ m is placed, and a core paste 32 (core paste type symbols: A to M) shown in Table 2 is padded with a squeegee 31
  • the printed and coated core paste 32 is sintered (S2) at a temperature shown in Table 3 in a belt furnace in a nitrogen atmosphere.
  • the sintered core 3 having a height substantially corresponding to the thickness of the metal mask 33 is formed at the center of the pad electrode 2.
  • the sintered core 3 has an opening larger than the diameter of the pad electrode 2 formed substantially at the center, and the sintered core
  • a metal mask 35 (opening diameter: 110 ⁇ m, opening pitch: 150 ⁇ m, thickness: 30 ⁇ m) having a thickness greater than or equal to the height is placed to cover the exposed portion of the pad electrode 2 and the entire sintered core from the opening of the metal mask 35.
  • the solder paste 34 containing the solder metal powder shown in Table 1 is printed and applied (print filling (S3)), and the metal mask 35 is removed.
  • a reflow process (S4) is performed at the temperature shown in Table 3 according to the type of the paste 34.
  • the cored structure solder bumps 1 to 17 shown in Table 3 in which the sintered core is confined in the surface of the pad electrode 2 by the first step and the second step hereinafter referred to as “the present invention bumps 1 to 17”). Produced).
  • FIG. 4 shows SEM images of nine sintered cores formed at a sintering temperature of 240 ° C. using core paste E made of a mixture of Cu powder and Sn powder as an example of the sintered core.
  • core paste E made of a mixture of Cu powder and Sn powder as an example of the sintered core.
  • the sintered core is confined to form a cored bump. (This is a correction corresponding to the deletion of the text below the image in Fig. 4)
  • the bump height was measured in order to evaluate the bump height.
  • the measurement is performed by measuring the height from the top of the bump to the substrate by optical image analysis using NEXIV VMR-3030 (manufactured by Nikon), and averaging the measured values for 200 bumps. Bump height.
  • the pad electrode diameter and the metal mask opening diameter are constant, the aspect ratio increases as the bump height increases.
  • Table 3 shows the bump heights obtained for the bumps 1 to 17 of the present invention.
  • a metal mask (opening diameter: 110 ⁇ m, opening pitch: 150 ⁇ m, the same size as that used in the second step of Example 1 is formed on the surface of the semiconductor substrate on which pad electrodes (diameter: 85 ⁇ m) are formed. (Thickness: 30 ⁇ m), and using the squeegee from the opening of the metal mask, the solder paste shown in Table 1 was printed and applied. After removing the metal mask, the type of solder paste was changed in a belt furnace in a nitrogen atmosphere.
  • solder bumps 1 to 5 of comparative examples shown in Table 4 were produced on the surface of the pad electrode. That is, the bumps 1 to 5 of the comparative examples are greatly different from the bumps 1 to 17 of the present invention in the structure and manufacturing method of the solder bumps in that a sintered core using a core paste is not formed.
  • the bump height was obtained in the same manner as the bumps 1 to 17 of the present invention.
  • the pad electrode diameter and the metal mask opening diameter are constant, the aspect ratio increases as the bump height increases.
  • Table 4 shows the bump heights obtained for the comparative example bumps 1 to 5.
  • Example 2 As Example 2, the core pastes N to R of the present invention shown in Table 5 in which at least one of the first group powder or the second group powder is an alloy powder are used, and the results are shown in Table 6 as in Example 1.
  • Core-cored solder bumps 18 to 22 (hereinafter referred to as “present invention bumps 18 to 22”) were produced.
  • the particle diameter of the solder metal alloy powder is 2 to 12 ⁇ m
  • the average particle diameter is 7 ⁇ m
  • the particle diameter of the metal powder and alloy powder contained in the core paste is 1 to 5 ⁇ m.
  • the average particle size is 2.5 ⁇ m.
  • Table 6 shows the bump heights obtained for the bumps 18 to 22 of the present invention.
  • the bumps 1 to 5 of the comparative example are flattened by their own weight, and as a result, the bump height is as low as about 30 ⁇ m, and short-circuiting due to contact with other bumps
  • the cored solder bumps 1 to 22 according to the present invention have a high aspect ratio with a bump height of 40 ⁇ m or more, and a sintered core is formed inside the bump.
  • the adhesion between the sintered core and the solder metal, the adhesion between the solder bump and the pad electrode are excellent, and there is no risk of lowering the conductivity. It can be seen that a fine pitch can be achieved.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
PCT/JP2014/082181 2013-12-27 2014-12-04 有芯構造はんだバンプ及びその製造方法 WO2015098460A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1020167004857A KR102122631B1 (ko) 2013-12-27 2014-12-04 유심 구조 땜납 범프 및 그 제조 방법
CN201480053701.XA CN105593980B (zh) 2013-12-27 2014-12-04 有芯结构焊料凸点及其制造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013-270852 2013-12-27
JP2013270852A JP6226233B2 (ja) 2013-12-27 2013-12-27 有芯構造はんだバンプ及びその製造方法

Publications (1)

Publication Number Publication Date
WO2015098460A1 true WO2015098460A1 (ja) 2015-07-02

Family

ID=53478326

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2014/082181 WO2015098460A1 (ja) 2013-12-27 2014-12-04 有芯構造はんだバンプ及びその製造方法

Country Status (5)

Country Link
JP (1) JP6226233B2 (zh)
KR (1) KR102122631B1 (zh)
CN (1) CN105593980B (zh)
TW (1) TWI648835B (zh)
WO (1) WO2015098460A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210193607A1 (en) * 2019-12-18 2021-06-24 Micron Technology, Inc. Processes for forming self-healing solder joints and repair of same, related solder joints, and microelectronic components, assemblies and electronic systems incorporating such solder joints

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6379342B2 (ja) * 2014-07-09 2018-08-29 三菱マテリアル株式会社 半導体装置及びその製造方法
DE112016006717T5 (de) 2016-04-06 2019-01-03 Mitsubishi Electric Corporation Leistungs-halbleitereinheit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06140532A (ja) * 1992-10-28 1994-05-20 Ngk Insulators Ltd バンプ付基板
JP2005294482A (ja) * 2004-03-31 2005-10-20 Fujikura Ltd 電子部品及び電子装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5466635A (en) * 1994-06-02 1995-11-14 Lsi Logic Corporation Process for making an interconnect bump for flip-chip integrated circuit including integral standoff and hourglass shaped solder coating
JPH0997791A (ja) * 1995-09-27 1997-04-08 Internatl Business Mach Corp <Ibm> バンプ構造、バンプの形成方法、実装接続体
JP4047065B2 (ja) * 2002-05-17 2008-02-13 株式会社タムラ製作所 半導体装置用パット電極部の形成方法
JP3961876B2 (ja) 2002-05-17 2007-08-22 株式会社タムラ製作所 半導体装置用はんだバンプの製造方法
US7115998B2 (en) * 2002-08-29 2006-10-03 Micron Technology, Inc. Multi-component integrated circuit contacts
TWI281718B (en) * 2002-09-10 2007-05-21 Advanced Semiconductor Eng Bump and process thereof
US6992001B1 (en) * 2003-05-08 2006-01-31 Kulicke And Soffa Industries, Inc. Screen print under-bump metalization (UBM) to produce low cost flip chip substrate
JP4404063B2 (ja) * 2006-03-24 2010-01-27 株式会社村田製作所 接続構造、その形成方法、回路基板、および実装基板に表面実装された電子部品
JP2006332694A (ja) 2006-07-24 2006-12-07 Megic Corp 半導体表面上に金属バンプを形成する方法
KR101485105B1 (ko) * 2008-07-15 2015-01-23 삼성전자주식회사 반도체 패키지
JP2013187258A (ja) 2012-03-06 2013-09-19 Toshiba Corp 半導体装置および半導体装置の製造方法
JP6156136B2 (ja) * 2013-12-27 2017-07-05 三菱マテリアル株式会社 はんだバンプの焼結芯を形成するための芯用ペースト

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06140532A (ja) * 1992-10-28 1994-05-20 Ngk Insulators Ltd バンプ付基板
JP2005294482A (ja) * 2004-03-31 2005-10-20 Fujikura Ltd 電子部品及び電子装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210193607A1 (en) * 2019-12-18 2021-06-24 Micron Technology, Inc. Processes for forming self-healing solder joints and repair of same, related solder joints, and microelectronic components, assemblies and electronic systems incorporating such solder joints
US11646286B2 (en) * 2019-12-18 2023-05-09 Micron Technology, Inc. Processes for forming self-healing solder joints and repair of same, related solder joints, and microelectronic components, assemblies and electronic systems incorporating such solder joints

Also Published As

Publication number Publication date
JP2015126158A (ja) 2015-07-06
CN105593980B (zh) 2019-03-19
KR20160102150A (ko) 2016-08-29
TWI648835B (zh) 2019-01-21
CN105593980A (zh) 2016-05-18
KR102122631B1 (ko) 2020-06-12
JP6226233B2 (ja) 2017-11-08
TW201541594A (zh) 2015-11-01

Similar Documents

Publication Publication Date Title
JP4753090B2 (ja) はんだペースト、及び電子装置
TWI586811B (zh) Lead - free solder bump joint construction
JP5533665B2 (ja) 電子装置の製造方法、電子部品搭載用基板及びその製造方法
JP6004253B2 (ja) ペースト用はんだ合金粉末、ペースト及びこれを用いたはんだバンプ
WO2015098460A1 (ja) 有芯構造はんだバンプ及びその製造方法
JP6476823B2 (ja) ピラー形成用ペースト、ピラーの製造方法、バンプ構造体の製造方法、ピラー、及びバンプ構造体
JP2013237091A (ja) バンプ用はんだ合金粉末、ペースト及びこれを用いたはんだバンプ
JP6350967B2 (ja) 半導体装置及びその製造方法
JP6156136B2 (ja) はんだバンプの焼結芯を形成するための芯用ペースト
US8252677B2 (en) Method of forming solder bumps on substrates
KR101983510B1 (ko) 핵재료 및 납땜 이음 및 범프 전극의 형성 방법
JP5147349B2 (ja) バンプ形成用ペースト、及びバンプ構造体
JP2008238253A (ja) Ｐｂフリーはんだ接続材料及びこれを用いた半導体実装構造体の製造方法
JP2006165336A (ja) バンプ形成用ハンダペースト
JP6004254B2 (ja) ペースト用はんだ合金粉末、ペースト及びこれを用いたはんだバンプ
JP6379342B2 (ja) 半導体装置及びその製造方法
TWI479967B (zh) Solder precoating method
JP2013237088A (ja) バンプ用はんだ合金粉末、ペースト及びこれを用いたはんだバンプ
KR102389258B1 (ko) 고온 안정성과 필렛특성이 개선된 접합 페이스트 및 그의 제조방법
TWI613741B (zh) 銲點凸塊製造方法
JP2009200285A (ja) バンプ及びバンプ接続構造体
JP2015003323A (ja) ニードル低減はんだ合金粉末、ペースト及びこれを用いたはんだバンプ
JP2015000428A (ja) ニードル低減はんだ合金粉末、ペースト及びこれを用いたはんだバンプ

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14875419

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 20167004857

Country of ref document: KR

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 14875419

Country of ref document: EP

Kind code of ref document: A1