WO2015096264A1 - 一种低温多晶硅薄膜晶体管及其制造方法 - Google Patents

一种低温多晶硅薄膜晶体管及其制造方法 Download PDF

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WO2015096264A1
WO2015096264A1 PCT/CN2014/071266 CN2014071266W WO2015096264A1 WO 2015096264 A1 WO2015096264 A1 WO 2015096264A1 CN 2014071266 W CN2014071266 W CN 2014071266W WO 2015096264 A1 WO2015096264 A1 WO 2015096264A1
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dielectric layer
layer
film thickness
thin film
manufacturing
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French (fr)
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徐向阳
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/241,764 priority Critical patent/US9257290B2/en
Priority to RU2016124649A priority patent/RU2634087C1/ru
Priority to KR1020167019150A priority patent/KR101872629B1/ko
Priority to GB1610213.9A priority patent/GB2535404B/en
Priority to JP2016542976A priority patent/JP2017508275A/ja
Publication of WO2015096264A1 publication Critical patent/WO2015096264A1/zh
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    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
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    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
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    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
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    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
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    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
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    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
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    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6336—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H10P14/6927—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/20—Cleaning during device manufacture
    • H10P70/27—Cleaning during device manufacture during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]

Definitions

  • the present invention relates to the field of fraudulent processing of low temperature polysilicon thin film transistors, and more particularly to a low temperature polycrystalline thin film transistor which can provide electrical characteristics and reliability and a method of fabricating the same. Background technique
  • LCDs liquid crystal displays
  • mobile phones, digital cameras, video cameras, notebook computers, and monitors that are common in everyday life are utilized. Goods manufactured by this technology.
  • LTPS low temperature poly-silicon
  • the conventional LTPS TFT includes a glass substrate 01, a buffer layer 102 disposed on the glass substrate 01, and polysilicon formed on the buffer layer 102, including source electrodes and settings disposed in the source region 103.
  • a pole electrode 108 and a passivation layer 109 are formed on the GI layer.
  • the GI layer typically employs a two-layer composite structure: a dielectric layer 105 and a dielectric layer 107, typically Si02 and SiNx.
  • the gate insulating layer composed of ⁇ SiNx and SiO2 has surface contact characteristics and poor film continuity, while GI forms a via hole (VIA hoie), which is easy to produce an undercut, that is, the SiO 2 is more engraved than SiNx.
  • the high etch rate causes the SiO 2 hole to be larger than SiNx, resulting in poor contact.
  • One of the technical problems to be solved by the present invention is to provide a method for fabricating a low-temperature polysilicon thin film transistor, which results in a transistor having a strong contact continuity, which can effectively reduce parasitic capacitance and thereby enhance the response rate of the transistor.
  • a low temperature polysilicon thin film transistor is also provided.
  • the present invention provides a method for fabricating a low temperature polysilicon thin film transistor, comprising: providing an insulating substrate; forming at least one polysilicon layer on a buffer layer of the insulating substrate, the surface of the polysilicon layer comprising a source region, a drain region and a channel region of the associated low temperature polysilicon thin film transistor; at least three PECVD processes are sequentially performed to sequentially form at least three dielectric layers on the channel region, thereby forming a composite a gate insulating layer, wherein a density of each of the dielectric layers is sequentially increased in a sequence formed in the manufacturing process; and a gate electrode is formed over the composite gate insulating layer.
  • the composite drain insulating layer is composed of a first dielectric layer, a second dielectric layer and a third dielectric layer.
  • the electric layer is SiO 2
  • the second dielectric layer is SiON
  • the third dielectric layer is SiNx.
  • the first dielectric layer S)2 has a film thickness ranging from 1000 to 1500 angstroms, and the second The dielectric layer SiON film thickness ranges from 100 to 1000 angstroms, and the third dielectric layer SiNx film thickness ranges from 100 to 500 angstroms.
  • the forming the polysilicon layer comprises: performing a sputtering process on the surface of the insulating substrate Forming an amorphous silicon layer, and performing an annealing step to recrystallize the amorphous silicon layer to form the polysilicon layer, wherein the annealing step includes an excimer laser annealing process.
  • an ion implantation process using the cabinet electrode as the MASK is performed.
  • a source electrode and a drain electrode are respectively formed in the polysilicon in the source region and the drain region, and after the ion implantation process, an activation process is performed to activate the source The electrode and the dopant in the drain electrode.
  • a low temperature polysilicon thin film transistor including at least one gate
  • the pole insulating layer is a composite insulating layer, and the composite insulating layer comprises at least three dielectric layers, wherein the density of the dielectric layers of each layer is sequentially increased in the order formed in the manufacturing process.
  • the drain insulating layer is composed of a first dielectric layer, a second dielectric layer and a third dielectric layer, and the first dielectric layer
  • the layer is S 02
  • the second dielectric layer is SiON
  • the third dielectric layer is SiNx [:
  • the film thickness of the first dielectric layer is greater than that of the second dielectric layer and the third dielectric layer Film thickness.
  • the first dielectric layer S) 2 has a film thickness ranging from 1000 to 1500 angstroms
  • the second medium The electro-SiOON film thickness ranges from 100 to 1000 angstroms
  • the third dielectric layer SiNx film thickness ranges from 100 to 500 angstroms.
  • one or more embodiments of the present invention may have the following advantages: In the present invention, the compactness relationship of each layer in the composite insulating layer is considered, and thus the low temperature obtained by the manufacturing method of the present invention
  • the composite insulating layer of the polysilicon thin film transistor can enhance surface contact characteristics and film continuity of each layer.
  • the obtained low-temperature polysilicon thin film transistor can effectively reduce the parasitic capacitance, thereby enhancing the response rate of the transistor.
  • FIG. 1 is a partial structural diagram of a low-temperature polysilicon thin film transistor in the prior art
  • FIG. 2 is a flow chart showing a method of fabricating a low temperature polysilicon thin film transistor according to an embodiment of the present invention
  • FIG. 3 is a view showing an example of a structure of a low temperature polysilicon thin film transistor according to an embodiment of the present invention.
  • FIGS. 2 and 3 are flow charts showing a method of fabricating a low temperature polysilicon thin film transistor according to an embodiment of the present invention, and the steps of a method of fabricating an LTPS TFT are described below with reference to FIGS. 2 and 3.
  • the insulating substrate 101 includes a glass substrate or a quartz substrate, and the bufl3 ⁇ 4i" layer 102 is SiO 2 formed on the insulating substrate 10 by PECVD.
  • steps of forming the LTPS layer further include the following steps:
  • a sputtering process is performed to form an amorphous silicon layer (a-Si) on the surface of the insulating substrate 101, and then an annealing step is performed to recrystallize the a-Si layer to form the polycrystalline silicon.
  • the annealing step includes an excimer laser annealing process.
  • Step S220 sequentially performing a first PECVD process, a second PECVD process, and a third PECVD process to sequentially form the first dielectric layer 105, the second dielectric layer 106, and the third dielectric layer on the channel region 111.
  • the electrical layer 107, the three dielectric layers constitute a composite pole insulating (GI) layer, wherein the density of the dielectric layers of each layer is sequentially increased in the order of formation in the manufacturing process, that is, the first dielectric layer 105 ⁇ second dielectric layer 106 ⁇ dielectric layer 107
  • the first dielectric layer 105 is deposited on the surface of the polysilicon layer by a first PECVD process, and then the second dielectric layer 106 is deposited on the first dielectric layer 105 by a second PECVD process, and again passes through the third
  • the third dielectric layer 107 is deposited on the second dielectric layer 106 by a PECVD process.
  • the PECVD process of the composite GI layer is continuously performed in a single wafer reactor.
  • the first dielectric layer of the composite Gi: layer is Si()2
  • the second dielectric layer 106 is SiON
  • the third dielectric layer 107 is SiNxo, wherein the first of the composite G1 layers
  • the dielectric layer 105 and the S102 of the butter layer 102 are used to improve the interface characteristics with the LTPS.
  • the SiNx of the third dielectric layer 107 in the composite GI layer is used to block moisture and metal ions, and the SiON of the second dielectric layer 106. Mainly to improve the interface contact continuity of the first dielectric layer 105 and the third dielectric layer 107 (compactness: SiNx>SiON>SiO2).
  • the composite pole insulating layer composed of the above dielectric layers improves the connection between itself and the low temperature polysilicon. Touch characteristics and prevent moisture and metal ions from entering the low temperature polysilicon interface and interior, while also enhancing surface contact characteristics and film continuity.
  • the composite insulating layer may be other layers, for example, four or five layers, that is, a person skilled in the art may form four layers by PECVD such as four or five times.
  • a five-layer multilayer dielectric layer is: sequentially increasing in the order formed in the manufacturing process.
  • the film thickness of the first dielectric layer 105 is much larger than the film thickness of the second dielectric layer 106 and the third dielectric layer 107, so that the parasitic capacitance can be effectively reduced.
  • the first dielectric layer SiO 2 has a film thickness of about 1000 1500 ⁇
  • the second dielectric layer SION has a film thickness of about 100 ⁇ to 1000 ⁇
  • the third dielectric layer SiNx has a film thickness of about 100 ⁇ to 500 ⁇ .
  • Step S230 forming a gate electrode 108 on the composite GI layer.
  • the material of the above gate electrode preferably includes: tungsten, chromium, aluminum, molybdenum and copper.
  • Step S240 performing an ion implantation process using the gate electrode 108 as a MASK, and forming a source electrode and a source electrode in the polysilicon in the source region 03 and the drain region 104 through the via 110 Drain electrode
  • Step S250 an activation process is performed to activate the dopants in the source electrode and the drain electrode.
  • a PECVD process is performed to form a passivation layer, which may be SiO or Si: Nx. Then, according to the above manufacturing process, the junction of the low temperature polysilicon thin film transistor as shown in FIG. 3 is finally formed.
  • the present invention contemplates the compactness relationship of each layer in the composite insulating layer, the low temperature polysilicon thin film transistor produced by the manufacturing method of the present invention can enhance the surface contact characteristics and film continuity of the respective layers. Further considering the thickness of each layer in the composite insulating layer, it is also possible to effectively reduce the parasitic capacitance and thereby increase the response rate of the transistor. That is, by improving the quality of GI film formation, the electrical characteristics and reliability of the low temperature polysilicon thin film transistor are improved.
  • the above description is only a preferred embodiment of the present invention, but the protection model I of the present invention is not limited thereto, and any person skilled in the art can easily think of changes or within the technical scope of the present invention. Alternatives are intended to be covered by the scope of the present invention. Therefore, the scope of protection of the present invention should be protected by the scope of the claims.

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  • Thin Film Transistor (AREA)
  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Formation Of Insulating Films (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

提供一种低温多晶硅薄膜晶体管及其制造方法。低温多晶硅薄膜晶体管至少包括一栅极绝缘层，栅极绝缘层是至少包括三层介电层的复合绝缘层，其中各层介电层的致密性按照制造过程中形成的顺序依次增大。通过考虑复合绝缘层中每一层的致密性关系，增强各层表面接触特性和薄膜连续性，通过考虑复合绝缘层中每一层的厚度，有效降低寄生电容，增强晶体管的相应速率。

Description

种低温多晶硅薄膜晶体管及其制造方法 技术领域
本发明是关于低温多晶硅薄膜晶体管的制诈工艺领域， 尤其涉及一种可提供电气特 性以及可靠度的低温多晶 ¾薄膜晶体管及其制造方法。 背景技术
在现今的平板显示器技术中， 液晶显示器 (Liquid Crystal Display, LCD)可以说是其 中最为成熟的技术， 倒如， 日常生活中常见的手机、 数码相 、 摄影机、 笔记本电脑以 至于监视器均是利用此项技术所制造的商品。
然而， 随着人 ί门对于显示器视觉要求提高， 加上新技术应用领域不断扩展， 更高像 质、 高清晰度、 高亮度且具有低价位的平面显示器巳成为未来显示技术发展的趋势， 也 是新的显示技术发展的原动力。 而平面显示器中的低温多晶硅 (Low Temperature Poly-silicon, LTPS) 薄膜晶体管除了具有符合有源驱动潮流的特性外， 其技术也正是一 个可以达到上述目标的重要技术突破。
传统的 LTPS TFT如图 1所示， 包括玻璃基板 01、 置于玻璃基板 01的缓冲层 102, 在该缓冲层 102上形成多晶硅， 其上包含有设置在源极区域 103的源极电极和设置在漏极 区域 104的漏极电极以及设置在通道区域 111上的櫥极绝缘层 GI。 在该 GI层上形成有極 极电极 108和钝化层 109。 GI层通常采用两层复合结构： 介电层 105和介电层 107, —般 为 Si02和 SiNx。
但是， ώ SiNx与 Si02组成的栅极绝缘层具有表面接触特性与薄膜连续性不好， 而 ϋ在 GI形成通孔（VIA hoie ) ， 容易产生二段角 （undercut) ， 即 Si02比 SiNx的刻蚀 速度大造成 Si02孔大于 SiNx, 导致接触性不好。
因此， 如何解决上述问题， 以提供一种低温多晶硅薄膜晶体管的制造方法， 使得所 制造的晶体管具有较强的接触连续性、 有效降低寄生电容， 进而增强晶体管的响应速 率， 乃业界所致力的课题之一。 发明内容 本发明所要解决的技术 题之一是需要提供一种低温多晶硅薄膜晶体管的制造方 法, 使得制造得到的晶体管具有较强的接触连续性， 能够有效降低寄生电容， 进而增强 晶体管的响应速率。 另外， 还提供了一种低温多晶硅薄膜晶体管。
1 ) 为了解决上述技术问题， 本发明提供了一种低温多晶硅薄膜晶体管的制造方法， 包括： 提供一绝缘基板； 在所述绝缘基板的缓冲层上形成至少一多晶硅层， 该多晶硅层 的表面包含有所属低温多晶硅薄膜晶体管的一源极区域、 一漏极区域以及一通道区域； 依次迸行至少三次 PECVD 工序以在所述通道区域上依序形成至少三层介电层， 迸而构 成一复合栅极绝缘层， 其中， 各层介电层的致密性按照制造过程中形成的顺序依次增 大； 以及在该复合栅极绝缘层之上形成一栅极电极。
2) 在本发明的第 1 ) 项的一个优选实施方式中， 所述复合檝极绝缘层由一第一介电 层、 一第二介电层和一第三介电层组成， 第一介电层为 Si02, 第二介电层为 SiON, 第三介电层为 SiNx。
3 )在本发明的第 )项或第 2)项中的一个优选实施方式中， 所述第一介电层的膜厚 均大于所述第二介电层和所述第三介电层的膜厚。
4) 在本发明的第 1 ) 项-第 3 ) 项中任一项的一个优选实施方式中， 所述第一介电层 S )2膜厚的范围为 1000〜1500埃， 所述第二介电层 SiON膜厚的范围为 100〜1000埃， 所 述第三介电层 SiNx膜厚的范围为 100~500埃。
5 ) 在本发明的第 1 ) 项-第 4) 项中任一项的一个优选实施方式中， 形成所述多晶硅 层的步骤包括： 进行一溅射工序， 以便在所述绝缘基板的表面上形成一非晶硅层， 以及 进行 ·退火工序， 以使所述非晶硅层再结晶形成所述多晶硅层， 其中， 所述退火工序包 括一准分子激光退火工序。
6) 在本发明的第 1 ) 项-第 5 ) 项中任一项的一个优选实施方式中， 在形成所述栅极 电极之后， 再进行一利用所述櫥极电极作为 MASK的离子注入工序， 以便在所述源极区 域以及漏极区域内的上述多晶硅之内分别形成一源极电极以及一漏极电极， 在所述离子 注入工序之后， 再进行 ·活化工序， 以活化所述源极电极以及漏极电极内的掺杂剂。
7) 根据本发明的另一方面， 还提供了一种低温多晶硅薄膜晶体管， 其至少包括一栅 极绝缘层， 所述樋极绝缘层为复合绝缘层， 该复合绝缘层包括至少三层介电层， 其中， 各层介电层的致密性按照制造过程中形成的顺序依次增大。
8) 在本发明的第 7) 项的优选实施方式中， 所述檝极绝缘层由一第一介电层、 一第 二介电层和一第三介电层组成， 且第一介电层为 S 02, 第二介电层为 SiON, 第三介电 层为 SiNx[:
9)在本发明的第 7)项或第 8)项的一个优选实施方式中， 所述第一介电层的膜厚均 大于所述第二介电层和所述第三介电层的膜厚。
10) 在本发明的第 7) 项-第 9) 项中任一项的一个优选实施方式中所述第一介电层 S )2膜厚的范围为 1000〜1500埃， 所述第二介电层 SiON膜厚的范围为 100〜1000埃， 所 述第三介电层 SiNx膜厚的范围为 100~500埃。 与现有技术相比， 本发明的一个或多个实施例可以具有如下优点： 在本发明中， 考虑了复合绝缘层中每一层的致密性关系， 因此根据本发明的制造方 法得到的低温多晶硅薄膜晶体管的复合绝缘层能够增强各层表面接触特性和薄膜连续 性。 进一歩又考虑了复合绝缘层中每一层的厚度， 因此得到的低温多晶硅薄膜晶体管能 够有效地降低寄生电容， 进而增强晶体管的响应速率。 本发明的其它特征和优点将在随后的说明书中阐述， 并且， 部分地从说明 中变得 显而易见， 或者通过实施本发明而了解。 本发明的目的和其他优点可通过在说明书、 权 利要求书以及 ^图中所特别指出的结构来实现和获得。
^图说明 图用来提供对本发明的进一步理解， 并 ϋ构成说明 ^的一部分， 与本发明的实施 例共同 于解释本发明， 并不构成对本发明的限制。 在^图中： 图】是现有技术中低温多晶硅薄膜晶体管的部分结构示例图；
图 2是根据本发明一实施例的低温多晶硅薄膜晶体管的制造方法的流程示意图； 图 3是根据本发明一实施例的一低温多晶硅薄膜晶体管的部分结构示例图。
具体实施方式 为使本发明的目的、 技术方案和优点更加清楚， 以下结合跗图对本发明作进一步地 详细说明》
图 2 是根据本发明一实施例的低温多晶硅薄膜晶体管的制造方法的流程示意图， 下 面同时参考图 2和图 3来说明制造一 LTPS TFT的方法的各个步骤。
歩骤 S2i0, 提供一绝缘基板 :I Oi， 在该绝缘基板 10: 的缓冲 ( buffer) 层〗 02上形成 至少一多晶珪 (LTPS)层， 其中， 该多晶珪层的表面包含有所属 LTPS TFT 的一源极区域 103、 一漏极区域 104以及一通道区域 111 =
需要说明的是， 上述绝缘基板 101包括一玻璃基板或一石英基板， bufl¾i"层 102是通 过 PECVD在绝缘基板 10: 上形成的 Si02。
另外， 上述形成 LTPS层的歩骤还包括下列工序：
首先， 迸行一溅射工序， 以便在上述绝缘基板 101 的表面上形成一非晶硅层 (a- Si), 然后进行一退火工序， 以使上述 a- Si 层再结晶形成上述多晶硅。 其中上述退火工序包括 一准分子激光退火工序。
步骤 S220, 依次进行一第一 PECVD工序、 一第二 PECVD工序和一第三 PECVD工 序， 以在上述通道区域 111 上依序形成第一介电层 105、 第二介电层 106和第三介电层 107, 上述这三层介电层构成一复合極极绝缘 (简称 GI)层， 其中， 各层介电层的致密性按 照制造过程中形成的顺序依次增大， 即第一介电层 105<第二介电层 106<第 介电层 107
具体地， 首先在多晶硅层的表面上通过第一 PECVD工序沉淀第一介电层 105, 其次 通过第二 PECVD工序在该第一介电层 105上沉淀第二介电层 106, 再次通过第三 PECVD 工序在该第二介电层 106上沉淀第三介电层 107。
需要说明的是， 上述复合 GI层的 PECVD工序在单一晶片式反应器中连续进行。 并且优选地， 上述复合 Gi:层的第一介电层〗05为 Si()2， 第二介电层 106为 SiON, 第:三介电层 107为 SiNxo 其中上述复合 G1层中的第一介电层 105和 butter层 102的 S102 用干改善与 LTPS的界面特性， 上述复合 GI层中的第三介电层 107的 SiNx用于阻挡水气 以及金属离子， 第二介电层 106的 SiON主要起到改善第一介电层 105和第三介电层 107 界面接触连续性的作 ^ (致密性： SiNx>SiON>Si02)。
这样， 由上述 层介电层组成的复合極绝缘层在改善其自身与低温多晶硅之间的接 触特性并防止水气和金属离子进入到低温多晶硅界面和内部的同时， 还能够增强表面接 触特性和薄膜连续性。 当然， 容易理解， 本实施例仅是一个示例， 该复合绝缘层可以为其它多层， 例如四 层或五层， 即本领域技术人员可以通过 ^如四次或五次的 PECVD 形成四层或五层的多 层介电层。 需要注意的是， 该复合绝缘层的各个介电层的致密性关系为： 按照制造过程 中形成的顺序依次增大。
另外， 第一介电层 105的膜厚远大于第二介电层 106和第三介电层 107的膜厚， 这样 可以有效降低寄生电容。 优选地， 第一介电层 Si02膜厚约为 1000〜1500埃， 第二介电层 SION膜厚约为 100〜1000埃， 第三介电层 SiNx膜厚约为 100〜500埃。
歩骤 S230, 在该复合 GI层之上形成一栅极电极 (Gate) 108。 需要说明的是， 上述栅极电极的材料优选包括： 钨、 铬、 铝、 钼和铜。
步骤 S240, 进行一利用上述栅极电极 108作为 MASK的离子注入工序， 通过过孔 1 10以在上述源极区域】03以及漏极区域 104内的上述多晶硅之内分别形成一源极电极以 及一漏极电极》
步骤 S250, 迸行一活化工序， 以活化上述源极电极以及漏极电极内的掺杂剂。 最后， 再进行一 PECVD工序， 形成一钝化层， 该钝化层可以为 SiO或 Si:Nx。 那么， 根据上述的制造流程最终会形成如图 3 所示的低温多晶硅薄膜晶体管的结
综上所述， 由于本发明考虑了复合绝缘层中每一层的致密性关系， 因此根据本发明 的制造方法所制出的低温多晶硅薄膜晶体管能够增强各层表面接触特性和薄膜连续性。 进一步又考虑了复合绝缘层中每一层的厚度， 因此还能够有效地降低寄生电容， 进而增 强晶体管的响应速率。 即通过改善 GI成膜质量， 提高了低温多晶硅薄膜晶体管的电气特 性以及可靠度。 以上所述， 仅为本发明较佳的具体实施方式， 但本发明的保护范 I并不局限于此， 任何熟悉该技术的人员在本发明所揭露的技术范围内， 可轻易想到的变化或替换， 都应 涵盖在本发明的保护范围之内。 因此， 本发明的保护范围应该以权利要求的保护范围为

Claims

权利要求书
1、 一种低温多晶硅薄膜晶体管的制造方法， 其中， 包括：
提供一绝缘基板；
在所述绝缘基板的缓冲层上形成至少一多晶硅层，该多晶硅层的表面包含有所属低温 多晶硅薄膜晶体管的一源极区域、 一漏极区域以及一通道区域；
依次进行至少三次 PECVD工序以在所述通道区域上依序形成至少三层介电层，迸而 构成一复合 »极绝缘层,其中，各层介电层的致密性按照制造过程中形成的顾序依次增大； 以及
在该复合栅极绝缘层之上形成一栅极电极。
2、 根据权利要求 1所述的制造方法， 其中，
所述复合栅极绝缘层由一第一介电层、一第二介电层和一第三介电层组成，且第一介 电层为 Si()2, 第二介电层为 SiON, 第:三介电层为 SiNx。
3、 根据权利要求 2所述的制造方法， 其中，
所述第一介电层的膜厚均大于所述第二介电层和所述第 介电层的膜厚。
4、 根据权利要求 3所述的制造方法， 其中，
所述第一介电层 S )2膜厚的范围为 i000〜i500埃， 所述第二介电层 SiON膜厚的范 围为 iOC iOOO埃， 所述第三介电层 SiNx膜厚的范围为 i00〜500埃。
5、 根据权利要求 1所述的制造方法， 其中， 形成所述多晶珪层的步骤包括： 进行一溅射工序， 以便在所述绝缘基板的表面上形成一非晶硅层， 以及
进行一退火工序， 以使所述非晶硅层再结晶形成所述多晶硅层， 其中， 所述退火工序 包括一准分子激光退火工序。
6、 根据权利要求〗所述的刺造方法， 其中，
在形成所述櫥极电极之后，再进行一利用所述栅极电极作为 MASK的离子注入工序, 以便在所述源极区域以及漏极区域内的上述多晶硅之内分别形成一源极电极以及一漏极 电极， 在所述离子注入工序之后， 再进行一活化工序， 以活化所述源极电极以及漏极电极 内的掺杂剂。
7、 ·种低温多晶硅薄膜晶体管， 其中，
至少包括 ·栅极绝缘层，
所述栅极绝缘层为复合绝缘层， 该复合绝缘层包括至少三层介电层， 其中， 各层介电 层的致密性按照制造过程中形成的顺序依次增大。
8、 根据权利要求 7所述的低温多晶硅薄膜晶体管， 其中， 所述栅极绝缘层由一第一介电层、一第二介电层和一第三介电层组成，且第一介电层 为 Si02, 第二介电层为 SiON, 第 介电层为
9、 根据权利要求 8所述的低温多晶硅薄膜晶体管， 其中，
所述第一介电层的膜厚均大于所述第二介电层和所述第:三介电层的膜厚。
10、 根据权利要求 9所述的低温多晶硅薄膜晶体管， 其中，
所述第一介电层 Si(:)2膜厚的范圈为 1000〜1500埃， 所述第二介电层 SK)N膜厚的范 围为 100〜1000埃， 所述第≡介电层 SiNx膜厚的范围为 100〜500埃。
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