WO2021142868A1 - 一种显示面板以及电子装置 - Google Patents

一种显示面板以及电子装置 Download PDF

Info

Publication number
WO2021142868A1
WO2021142868A1 PCT/CN2020/074985 CN2020074985W WO2021142868A1 WO 2021142868 A1 WO2021142868 A1 WO 2021142868A1 CN 2020074985 W CN2020074985 W CN 2020074985W WO 2021142868 A1 WO2021142868 A1 WO 2021142868A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
metal
metal oxide
insulating layer
display panel
Prior art date
Application number
PCT/CN2020/074985
Other languages
English (en)
French (fr)
Inventor
陈远鹏
徐源竣
刘兆松
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US16/651,874 priority Critical patent/US20220005956A1/en
Publication of WO2021142868A1 publication Critical patent/WO2021142868A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00

Definitions

  • the present invention relates to the field of display technology, and in particular to a display panel and an electronic device.
  • TFT Thin Film Transistor
  • oxide semiconductors are susceptible to the influence of water and oxygen, which reduces the stability of the TFT device, thereby reducing the conductivity of the thin film transistor.
  • the object of the present invention is to provide a display panel and an electronic device that can improve the stability of thin film transistors and the conductivity of thin film transistors.
  • the present invention provides a display panel, including:
  • the metal oxide semiconductor layer is provided on the base substrate;
  • a gate insulating layer partly provided on the metal oxide semiconductor layer
  • a first metal layer partially disposed on the gate insulating layer, and the first metal layer includes a gate
  • a protective layer is provided on the gate, the gate insulating layer and the metal oxide semiconductor layer; the material of the protective layer is metal oxide;
  • the first insulating layer is provided on the protective layer.
  • the second metal layer is disposed on the first insulating layer, and the second metal layer includes a source electrode and a drain electrode.
  • the present invention also provides an electronic device, which includes the above-mentioned display panel.
  • the display panel and the electronic device of the present invention include a base substrate; a metal oxide semiconductor layer provided on the base substrate; a gate insulating layer partially provided on the metal oxide semiconductor layer; a first metal layer, Is partially disposed on the gate insulating layer, the first metal layer includes a gate; a protective layer is disposed on the gate, the gate insulating layer, and the metal oxide semiconductor layer; the protective layer is The material is metal oxide; the first insulating layer is provided on the protective layer; the second metal layer is provided on the first insulating layer, and the second metal layer includes a source electrode and a drain electrode; due to the protective layer
  • the material is also a metal oxide, so it can significantly enhance the protection of the metal oxide semiconductor layer, reduce the influence of external water and oxygen on the oxide material, and improve the stability of the thin film transistor and the conductivity of the thin film transistor.
  • FIG. 1 is a schematic diagram of the structure of a display panel according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a display panel according to another embodiment of the invention.
  • FIG. 3 is a schematic structural diagram of the first to fourth steps of the manufacturing method of the display panel in FIG. 2 of the present invention.
  • FIG. 4 is a schematic diagram of the structure of the fifth to sixth steps of the manufacturing method of the display panel in FIG. 2 of the present invention.
  • FIG. 5 is a schematic structural diagram of the seventh step of the manufacturing method of the display panel in FIG. 2 of the present invention.
  • FIG. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention.
  • the display panel of this embodiment includes: a base substrate 11, a metal oxide semiconductor layer 14, a gate insulating layer 15, a first metal layer 16, a protective layer 17, a first insulating layer 18, and a second metal Layer 19.
  • the metal oxide semiconductor layer 14 is provided on the base substrate 11;
  • the gate insulating layer 15 is partially disposed on the metal oxide semiconductor layer 14;
  • the first metal layer 16 is partially disposed on the gate insulating layer 15, and the first metal layer 16 includes a gate (not shown in the figure); the first metal layer 16 may be a single film layer.
  • the first metal layer in conjunction with FIG. 2, in order to reduce the resistance of the gate, the first metal layer includes a first sub-layer 161 and a second sub-layer 162, and the first sub-layer 161 is used to reinforce the second sub-layer 162.
  • the material of the first sub-layer 161 includes at least one of Mo, Ti, and Ni; in one embodiment, the thickness of the first sub-layer 161 is smaller than that of the second sub-layer.
  • the thickness of the first sub-layer 161 may be 50-500 ⁇
  • the material of the second sub-layer 162 may be Cu or Cu alloy
  • the thickness of the second sub-layer 162 may be 2000-10000 ⁇ .
  • the material of the first metal layer 16 may be copper or copper alloy.
  • the protective layer 17 is provided on the gate, the gate insulating layer 15 and the metal oxide semiconductor layer 14; the material of the protective layer 17 is metal oxide; in one embodiment, the protective layer 17 The material is amorphous metal oxide.
  • the material of the protective layer 17 includes at least one element of Al, Ca, Mg, Ti, Mo, and Ni.
  • the first insulating layer 18 is disposed on the protective layer 17; in one embodiment, the thickness of the protective layer 17 may be less than the thickness of the first insulating layer 18.
  • the thickness of the protective layer 17 ranges from 30 ⁇ to 500 ⁇ , and the thickness of the first insulating layer 18 ranges from 3000 ⁇ to 10000 ⁇ . Wherein, both the protective layer 17 and the first insulating layer 18 are provided with via holes.
  • the second metal layer 19 is disposed on the first insulating layer 18, and the second metal layer 19 includes a source electrode and a drain electrode.
  • the second metal layer 19 also includes a first sublayer and a second sublayer.
  • the first sublayer is used to enhance the adhesion between the second sublayer and the first insulating layer 18.
  • the material of a sub-layer includes at least one of Mo, Ti, and Ni; wherein in one embodiment, the thickness of the first sub-layer is smaller than the thickness of the second sub-layer, and the thickness of the first sub-layer may range from 50-500 ⁇
  • the material of the second sub-layer can be Cu or Cu alloy, and the thickness of the second sub-layer ranges from 2000-10000 ⁇ .
  • the second metal layer 19 may also be a single-layer film layer.
  • the material of the second metal layer 19 may be copper or a copper alloy.
  • the source electrode and the drain electrode are connected to the metal oxide semiconductor layer through the via hole.
  • the above-mentioned display panel may further include a light-shielding layer 12 provided between the base substrate 11 and the metal oxide semiconductor layer 14, and the light-shielding layer 12 covers the metal oxide semiconductor layer. 14.
  • the drain electrode may be connected to the light shielding layer 12.
  • the above-mentioned display panel may further include a buffer layer 13 and a second insulating layer 20, and the buffer layer 13 is provided between the light shielding layer 12 and the metal oxide semiconductor layer 14.
  • the second insulating layer 20 is provided on the second metal layer 19.
  • the protective layer 17 is prepared, since the material of the protective layer 17 is also a metal oxide, the protection of the metal oxide semiconductor layer 14 can be significantly enhanced, the influence of external water and oxygen on the oxide material can be reduced, and the stability of the thin film transistor can be improved And the conductivity of thin film transistors, and also improve the display effect.
  • the manufacturing method of the display panel of the present invention includes the following steps:
  • the base substrate 11 is a glass substrate.
  • the light shielding layer 12 covers the metal oxide semiconductor layer 14.
  • a plasma enhanced chemical vapor deposition method PECVD Pulsma Enhanced Chemical Vapor Deposition
  • PECVD Plasma enhanced chemical vapor deposition
  • the buffer layer 13 can be a single-layer film or a double-layer film, and the material of the buffer layer 13 can be At least one of Si 3 N 4 , SiO 2 and SiON is included, and the thickness of the buffer layer 13 may range from 1000 to 5000 ⁇ .
  • the material of the metal oxide semiconductor layer 14 may be an amorphous oxide semiconductor.
  • it includes at least one of IGZO, ITZO, and IGZTO.
  • the metal oxide semiconductor layer 14 may adopt physical vapor deposition (Physical Vapor Deposition). Deposition, PVD) process.
  • the thickness of the metal oxide semiconductor layer 14 may be in the range of 100-1000 ⁇ .
  • the gate insulating layer (Gate insulator, GI) can be deposited by a chemical vapor deposition process (such as PECVD), the material of the gate insulating layer 15 is SiOx, and the oxygen content can be determined by a chemical vapor deposition process (such as PECVD) for regulation, and the thickness of the gate insulating layer 15 is in the range of 500-2000 ⁇ .
  • the oxygen content in the chemical vapor deposition process PECVD
  • the conductive parameters include resistivity or each in the metal oxide semiconductor layer 14. The number of atoms of the element.
  • a metal layer is deposited on the gate insulating layer 15 through a PVD process to obtain the first metal layer.
  • the first metal layer 16 includes a first sublayer 161 and a second sublayer 162, and the first sublayer 161 is used to enhance the adhesion between the second sublayer 162 and the gate insulating layer 15
  • the material of the first sub-layer 161 includes at least one of Mo, Ti, and Ni; in one embodiment, the thickness of the first sub-layer 161 is smaller than the thickness of the second sub-layer 162, and the thickness of the first sub-layer 161
  • the thickness of the second sub-layer 162 may be in the range of 50-500 ⁇ , and the material of the second sub-layer 162 may be Cu or Cu alloy.
  • the thickness of the second sub-layer 162 may be in the range of 2000-10000 ⁇ .
  • the first sub-layer 161 and the second sub-layer 162 can be patterned at the same time.
  • the steps of the patterning treatment include exposure, development and etching.
  • the etching can use a wet etching process to define the gate.
  • the first metal layer 16 may also be a single layer of metal.
  • the gate can be used as an etched pattern of the gate insulating layer to etch the gate insulating layer to expose the channel region of the metal oxide semiconductor layer 14 to the outside.
  • an oxide material such as an amorphous metal oxide (amorphous metal oxide) is first deposited on the gate, the gate insulating layer 15 and the metal oxide semiconductor layer 14.
  • metal Oxide, AMO metal Oxide
  • the preparation process of this layer can be made by direct deposition, or it can be made by first depositing the corresponding metal material and then annealing and oxidizing to form the corresponding amorphous metal oxide.
  • the material of the protective layer 17 includes at least one of Al, Ca, Mg, Ti, Mo, and Ni, and the thickness of the protective layer 17 may range from 30 to 500 ⁇ .
  • a chemical vapor deposition process (such as PECVD) is used to deposit an insulating material on the protective layer 17.
  • the insulating material may include SiO 2
  • the oxygen content can be adjusted by the PECVD process, in order to further improve the thin film transistor
  • the conductivity can be set according to the conductivity parameters of the metal oxide semiconductor layer 14 in the oxygen content in the chemical vapor deposition process, where the conductivity parameters include resistivity or the number of atoms of each element in the metal oxide semiconductor layer 14.
  • the oxygen content may be set according to the conductivity parameters of the metal oxide semiconductor layer 14.
  • the thickness of the first insulating layer 18 is in the range of 3000-10000 ⁇ . After that, the protective layer 17 and the first insulating layer 18 may be patterned at the same time to form via holes.
  • a second metal layer 19 is fabricated on the first insulating layer 18.
  • the second metal layer 19 also includes a first sublayer and a second sublayer.
  • the first sublayer is For enhancing the adhesion between the second sub-layer and the first insulating layer 18, the material of the first sub-layer includes at least one of Mo, Ti, and Ni; in one embodiment, the first sub-layer The thickness is smaller than the thickness of the second sub-layer, the thickness of the first sub-layer may be in the range of 50-500 ⁇ , the material of the second sub-layer may be Cu or Cu alloy, and the thickness of the second sub-layer may be in the range of 2000-10000 ⁇ .
  • the first sub-layer and the second sub-layer can be patterned at the same time.
  • the steps of the patterning treatment include exposure, development and etching. Among them, the etching can adopt a wet etching process to define the source and drain. pole. It can be understood that, in other embodiments, the second metal layer 19 may also be a single layer of metal.
  • the PECVD process is used to deposit an insulating material on the second metal layer 19, and the thickness of the second insulating layer 20 is in the range of 1000-5000 ⁇ .
  • the resistance of the gate or the source and drain can be reduced, and the resistance can be significantly reduced compared with a single-layer metal (such as AL), thereby achieving better Drive requirements for high-resolution and larger AMOLED panels.
  • only one of the first metal layer 16 or the second metal layer 19 has a double-layer structure.
  • the present invention also provides an electronic device, which includes any of the above-mentioned display panels, and the electronic device can be a mobile phone, a tablet computer, or other equipment.
  • the display panel and the electronic device of the present invention include a base substrate; a metal oxide semiconductor layer provided on the base substrate; a gate insulating layer partially provided on the metal oxide semiconductor layer; a first metal layer, Is partially disposed on the gate insulating layer, the first metal layer includes a gate; a protective layer is disposed on the gate, the gate insulating layer, and the metal oxide semiconductor layer; the protective layer is The material is metal oxide; the first insulating layer is provided on the protective layer; the second metal layer is provided on the first insulating layer, and the second metal layer includes a source electrode and a drain electrode; due to the protective layer
  • the material is also a metal oxide, so it can significantly enhance the protection of the metal oxide semiconductor layer, reduce the influence of external water and oxygen on the oxide material, and improve the stability of the thin film transistor and the conductivity of the thin film transistor.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Thin Film Transistor (AREA)

Abstract

本发明提供一种显示面板以及电子装置，该显示面板包括：金属氧化物半导体层设于衬底基板上；栅绝缘层，部分设于所述金属氧化物半导体层上；第一金属层，部分设于所述栅绝缘层上，所述第一金属层包括栅极；保护层，设于所述栅极、所述栅绝缘层以及所述金属氧化物半导体层上；所述保护层的材料为金属氧化物。

Description

一种显示面板以及电子装置 技术领域
本发明涉及显示技术领域，特别是涉及一种显示面板以及电子装置。
 背景技术
为驱动显示面板（比如有机发光二极管（OLED）器件），需要薄膜晶体管（Thin Film Transistor，TFT）具备高的迁移率以产生足够高的驱动电流，并且薄膜晶体管的稳定性也直接影响到OLED的显示特性。
 技术问题
为了提高薄膜晶体管的迁移率，目前薄膜晶体管多采用氧化物半导体作为半导体层，然而氧化物半导体材料容易受到水氧的影响，使得TFT器件的稳定性降低，进而降低了薄膜晶体管的导电性能。
因此，有必要提供一种显示面板以及电子装置，以解决现有技术所存在的问题。
 技术解决方案
本发明的目的在于提供一种显示面板以及电子装置，能够提高薄膜晶体管的稳定性和薄膜晶体管的导电性能。
为解决上述技术问题，本发明提供一种显示面板，包括：
衬底基板；
金属氧化物半导体层，设于所述衬底基板上；
栅绝缘层，部分设于所述金属氧化物半导体层上；
第一金属层，部分设于所述栅绝缘层上，所述第一金属层包括栅极；
保护层，设于所述栅极、所述栅绝缘层以及所述金属氧化物半导体层上；所述保护层的材料为金属氧化物；
第一绝缘层，设于所述保护层上；以及
第二金属层，设于所述第一绝缘层上，所述第二金属层包括源极和漏极。
本发明还提供一种电子装置，其包括上述显示面板。
 有益效果
本发明的显示面板以及电子装置，包括衬底基板；金属氧化物半导体层，设于所述衬底基板上；栅绝缘层，部分设于所述金属氧化物半导体层上；第一金属层，部分设于所述栅绝缘层上，所述第一金属层包括栅极；保护层，设于所述栅极、所述栅绝缘层以及所述金属氧化物半导体层上；所述保护层的材料为金属氧化物；第一绝缘层，设于所述保护层上；第二金属层，设于所述第一绝缘层上，所述第二金属层包括源极和漏极；由于保护层的材料也为金属氧化物，因此可以显著增强对金属氧化物半导体层的保护，降低外界水氧对氧化物材料的影响，提高薄膜晶体管的稳定性和薄膜晶体管的导电性能。
 附图说明
图1为本发明一实施例的显示面板的结构示意图；
图2为本发明另一实施例的显示面板的结构示意图；
图3为本发明图2中的显示面板制作方法的第一步至第四步的结构示意图；
图4为本发明图2中的显示面板制作方法的第五步至第六步的结构示意图；
图5为本发明图2中的显示面板制作方法的第七步的结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是以相同标号表示。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别不同对象，而不是用于描述特定顺序。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。
请参照图1，图1为本发明一实施例的显示面板的结构示意图。
如图1所示，本实施例的显示面板包括：衬底基板11、金属氧化物半导体层14、栅绝缘层15、第一金属层16、保护层17、第一绝缘层18以及第二金属层19。
金属氧化物半导体层14设于所述衬底基板11上；
栅绝缘层15部分设于所述金属氧化物半导体层14上；
第一金属层16部分设于所述栅绝缘层15上，所述第一金属层16包括栅极（图中未标出）；该第一金属层16可为单层膜层。在一实施方式中，结合图2，为了减小栅极的电阻，该第一金属层包括第一子层161和第二子层162，该第一子层161用于增强第二子层162与栅绝缘层15之间的粘附力，第一子层161的材料包括Mo、Ti、Ni中的至少一种；其中在一实施方式中，第一子层161的厚度小于第二子层162的厚度，第一子层161的厚度范围可为50-500Å，第二子层162的材料可为Cu或者Cu合金，第二子层162的厚度范围2000-10000Å。当然可以理解的，此时第一金属层16的材料可为铜或者铜的合金。
保护层17设于所述栅极、所述栅绝缘层15以及所述金属氧化物半导体层14上；所述保护层17的材料为金属氧化物；在一实施方式中，所述保护层17的材料为非晶态金属氧化物。所述保护层17的材料包括Al、Ca、Mg、Ti、Mo以及Ni中的至少一种元素。
第一绝缘层18设于所述保护层17上；在一实施方式中所述保护层17的厚度可小于所述第一绝缘层18的厚度。所述保护层17的厚度范围为30Å-500Å，所述第一绝缘层18的厚度范围为3000Å-10000Å。其中保护层17和第一绝缘层18上均设置有过孔。
第二金属层19设于所述第一绝缘层18上，所述第二金属层19包括源极和漏极。在一实施方式中，该第二金属层19也包括第一子层和第二子层，该第一子层用于增强第二子层与第一绝缘层18之间的粘附力，第一子层的材料包括Mo、Ti、Ni中的至少一种；其中在一实施方式中，第一子层的厚度小于第二子层的厚度，第一子层的厚度范围可为50-500Å，第二子层的材料可为Cu或者Cu合金，第二子层的厚度范围2000-10000Å。当然可以理解的，该第二金属层19也可为单层膜层，此时第二金属层19的材料可为铜或者铜的合金。其中源极和漏极通过过孔与金属氧化物半导体层连接。
此外，上述显示面板还可包括遮光层12，所述遮光层12设于所述衬底基板11和所述金属氧化物半导体层14之间，所述遮光层12覆盖所述金属氧化物半导体层14，在一实施方式中，所述漏极可与所述遮光层12连接。
上述显示面板还可包括缓冲层13以及第二绝缘层20，所述缓冲层13设于所述遮光层12和所述金属氧化物半导体层14之间。
第二绝缘层20设于所述第二金属层19上。
由于通过制备保护层17，由于保护层17的材料也为金属氧化物，因此可以显著增强对金属氧化物半导体层14的保护，降低外界水氧对氧化物材料的影响，提高薄膜晶体管的稳定性和薄膜晶体管的导电性能，此外还提高显示效果。
本发明的显示面板的制作方法包括以下步骤：
S101、在衬底基板上制作遮光层12；
例如，如图3所示，在一实施方式中，衬底基板11为玻璃基板。
将玻璃基板（Array Glass）清洗干净，沉积金属层（可以为单层或者两层金属），采用湿法蚀刻（Wet）图形化该金属层，形成具备遮光层12，该遮光层12还可以用作走线，遮光层12覆盖金属氧化物半导体层14。
S102、在遮光层12上制作金属氧化物半导体层14；
例如，采用等离子体增强化学的气相沉积法PECVD（Plasma Enhanced Chemical Vapor Deposition）工艺在上述遮光层12上沉积缓冲层13，缓冲层13可以为单层膜或者双层膜，缓冲层13的材料可以包括Si 3N 4、SiO 2以及SiON中的至少一种，缓冲层13的厚度范围可1000-5000Å。
之后在缓冲层13上沉积氧化物半导体材料，并进行图形化处理，形成金属氧化物半导体层14，也即形成出主动区，该金属氧化物半导体层14的材料可以为非晶氧化物半导体，比如包括IGZO、ITZO以及IGZTO中的至少一种。
该金属氧化物半导体层14可以采用物理气相沉积（Physical Vapor Deposition，PVD）工艺进行制作。该金属氧化物半导体层14的厚度范围可为100-1000Å。
S103、在金属氧化物半导体层14上制作栅绝缘层；
例如，如图3所示，可以通过化学气相沉积工艺（比如PECVD）沉积栅绝缘层（Gate insulator，GI），栅绝缘层15的材料为SiOx，其中氧的含量可通过化学气相沉积工艺（比如PECVD）进行调控，栅绝缘层15的厚度范围为500-2000Å。为了进一步提高薄膜晶体管的导电性能，可以根据所述金属氧化物半导体层14的导电参数设置化学气相沉积工艺（PECVD）中氧的含量，其中导电参数包括电阻率或者金属氧化物半导体层14中各元素的原子个数。
S104、在栅绝缘层上制作第一金属层；
例如，结合图2和图3，通过PVD工艺在栅绝缘层15上沉积金属层，得到第一金属层。在一实施方式中，该第一金属层16包括第一子层161和第二子层162，该第一子层161为用于增强第二子层162与栅绝缘层15之间的粘附力，第一子层161的材料包括Mo、Ti、Ni中的至少一种；其中在一实施方式中，第一子层161的厚度小于第二子层162的厚度，第一子层161的厚度范围可为50-500Å，第二子层162的材料可为Cu或者Cu合金，第二子层162的厚度范围2000-10000Å。
在制作过程中可以同时对第一子层161和第二子层162进行图形化处理，图案化处理的步骤包括曝光、显影蚀刻等步骤，其中蚀刻可以采用湿法蚀刻工艺，从而限定出栅极。可以理解的，在其他实施方式中，该第一金属层16也可为单层金属。
之后，可利用上述栅极作为栅绝缘层的蚀刻的图形，对栅绝缘层进行蚀刻，以将金属氧化物半导体层14的沟道区域裸露在外。
S105、在栅极、栅绝缘层以及金属氧化物半导体层上制作保护层17；
例如，如图4所示，首先在栅极、栅绝缘层15以及金属氧化物半导体层14上沉积氧化物材料，比如非晶态金属氧化物（amorphous metal Oxide，AMO）；该层的制备工艺可以采用直接沉积的方式制作，也可以采用先沉积对应金属材料之后，采用退火氧化的方式形成对应非晶态金属氧化物。
该保护层17的材料包含Al、Ca、Mg、Ti、Mo以及Ni中的至少一种，该保护层17的厚度范围可为30-500Å。
S106、在保护层17上制作第一绝缘层18；
例如，如图4所示，采用化学气相沉积工艺（比如PECVD）在保护层17上沉积绝缘材料，绝缘材料可以包括SiO 2，其中氧含量可通过PECVD制程工艺进行调控，为了进一步提高薄膜晶体管的导电性能，可以根据所述金属氧化物半导体层14的导电参数设置化学气相沉积工艺中氧的含量，其中导电参数包括电阻率或者金属氧化物半导体层14中各元素的原子个数。在一实施方式中，为了进一步提高薄膜晶体管的导电性能，可以根据所述金属氧化物半导体层14的导电参数设置所述氧的含量。
第一绝缘层18的厚度范围为3000-10000Å。之后，可对上述保护层17和第一绝缘层18同时进行图案化处理，以形成过孔。
S107、在第一绝缘层18上制作第二金属层19；
如图5所示，在第一绝缘层18上制作第二金属层19，在一实施方式中，该第二金属层19也包括第一子层和第二子层，该第一子层为用于增强第二子层与第一绝缘层18之间的粘附力，第一子层的材料包括Mo、Ti、Ni中的至少一种；其中在一实施方式中，第一子层的厚度小于第二子层的厚度，第一子层的厚度范围可为50-500Å，第二子层的材料可为Cu或者Cu合金，第二子层的厚度范围2000-10000Å。
在制作过程中可以同时对第一子层和第二子层进行图形化处理，图案化处理的步骤包括曝光、显影蚀刻等步骤，其中蚀刻可以采用湿法蚀刻工艺，从而限定出源极和漏极。可以理解的，在其他实施方式中，该第二金属层19也可为单层金属。
S108、在第二金属层19上制作第二绝缘层20；
例如，返回图2，采用PECVD工艺在第二金属层19上沉积绝缘材料，该第二绝缘层20的厚度范围为1000-5000Å。
由于第一金属层16和第二金属层19采用双层结构，因此可以减小栅极或者源漏极的电阻，相比于单层金属（比如AL）而言可显著降低电阻，从而实现更高分辨率及更大尺寸的AMOLED面板的驱动需求。
可以理解的，在其他实施方式中，仅有第一金属层16或者第二金属层19中的一个为双层结构。
本发明还提供一种电子装置，其包括上述任意一种显示面板，该电子装置可以为手机、平板电脑等设备。
本发明的显示面板以及电子装置，包括衬底基板；金属氧化物半导体层，设于所述衬底基板上；栅绝缘层，部分设于所述金属氧化物半导体层上；第一金属层，部分设于所述栅绝缘层上，所述第一金属层包括栅极；保护层，设于所述栅极、所述栅绝缘层以及所述金属氧化物半导体层上；所述保护层的材料为金属氧化物；第一绝缘层，设于所述保护层上；第二金属层，设于所述第一绝缘层上，所述第二金属层包括源极和漏极；由于保护层的材料也为金属氧化物，因此可以显著增强对金属氧化物半导体层的保护，降低外界水氧对氧化物材料的影响，提高薄膜晶体管的稳定性和薄膜晶体管的导电性能。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种显示面板，其包括：
    衬底基板；
    金属氧化物半导体层，设于所述衬底基板上；
    栅绝缘层，部分设于所述金属氧化物半导体层上；
    第一金属层，部分设于所述栅绝缘层上，所述第一金属层包括栅极；
    保护层，设于所述栅极、所述栅绝缘层以及所述金属氧化物半导体层上；所述保护层的材料为金属氧化物；
    第一绝缘层，设于所述保护层上；以及
    第二金属层，设于所述第一绝缘层上，所述第二金属层包括源极和漏极。
  2. 根据权利要求1所述的显示面板，其中
    所述保护层的材料为非晶态金属氧化物。
  3. 根据权利要求2所述的显示面板，其中
    所述保护层的材料包括Al、Ca、Mg、Ti、Mo以及Ni中的至少一种元素。
  4. 根据权利要求1所述的显示面板，其中
    所述保护层的厚度小于所述第一绝缘层的厚度。
  5. 根据权利要求4所述的显示面板，其中
    所述保护层的厚度范围为30Å-500Å，所述第一绝缘层的厚度范围为3000Å-10000Å。
  6. 根据权利要求1所述的显示面板，其中
    所述第一金属层和/或所述第二金属层均包括第一子层和第二子层。
  7. 根据权利要求6所述的显示面板，其中
    所述第一子层的材料包括Mo、Ti、Ni中的至少一种；所述第二子层的材料为铜。
  8. 根据权利要求6所述的显示面板，其中
    所述第一子层的厚度小于所述第二子层的厚度。
  9. 根据权利要求8所述的显示面板，其中所述第一子层的厚度范围为50Å-500Å，所述第二子层的厚度范围为2000Å-10000Å。
  10. 根据权利要求1所述的显示面板，其中所述栅绝缘层和所述第一绝缘层均可通过化学气相沉积工艺制备得到，其中所述化学气相沉积工艺中氧的含量根据所述金属氧化物半导体层的导电参数设置的。
  11. 根据权利要求1所述的显示面板，其中所述显示面板还包括遮光层，所述遮光层设于所述衬底基板和所述氧化物半导体层之间，所述遮光层覆盖所述氧化物半导体层。
  12. 一种电子装置，其包括显示面板，其包括：
    衬底基板；
    金属氧化物半导体层，设于所述衬底基板上；
    栅绝缘层，部分设于所述金属氧化物半导体层上；
    第一金属层，部分设于所述栅绝缘层上，所述第一金属层包括栅极；
    保护层，设于所述栅极、所述栅绝缘层以及所述金属氧化物半导体层上；所述保护层的材料为金属氧化物；
    第一绝缘层，设于所述保护层上；以及
    第二金属层，设于所述第一绝缘层上，所述第二金属层包括源极和漏极。
  13. 根据权利要求12所述的电子装置，其中
    所述保护层的材料为非晶态金属氧化物。
  14. 根据权利要求13所述的电子装置，其中
    所述保护层的材料包括Al、Ca、Mg、Ti、Mo以及Ni中的至少一种元素。
  15. 根据权利要求12所述的电子装置，其中
    所述保护层的厚度小于所述第一绝缘层的厚度。
  16. 根据权利要求15所述的电子装置，其中
    所述保护层的厚度范围为30Å-500Å，所述第一绝缘层的厚度范围为3000Å-10000Å。
  17. 根据权利要求12所述的电子装置，其中
    所述第一金属层和/或所述第二金属层均包括第一子层和第二子层。
  18. 根据权利要求17所述的电子装置，其中
    所述第一子层的材料包括Mo、Ti、Ni中的至少一种；所述第二子层的材料为铜。
  19. 根据权利要求17所述的电子装置，其中
    所述第一子层的厚度小于所述第二子层的厚度。
  20. 根据权利要求12所述的电子装置，其中所述栅绝缘层和所述第一绝缘层均可通过化学气相沉积工艺制备得到，其中所述化学气相沉积工艺中氧的含量根据所述金属氧化物半导体层的导电参数设置的。
PCT/CN2020/074985 2020-01-19 2020-02-13 一种显示面板以及电子装置 WO2021142868A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/651,874 US20220005956A1 (en) 2020-01-19 2020-02-13 Display panel and electronic device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010062240.X 2020-01-19
CN202010062240.XA CN111244110B (zh) 2020-01-19 2020-01-19 一种显示面板以及电子装置

Publications (1)

Publication Number Publication Date
WO2021142868A1 true WO2021142868A1 (zh) 2021-07-22

Family

ID=70876524

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/074985 WO2021142868A1 (zh) 2020-01-19 2020-02-13 一种显示面板以及电子装置

Country Status (3)

Country Link
US (1) US20220005956A1 (zh)
CN (1) CN111244110B (zh)
WO (1) WO2021142868A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW202243178A (zh) * 2021-04-23 2022-11-01 元太科技工業股份有限公司 電子裝置及其線路結構
CN114141881A (zh) * 2021-11-24 2022-03-04 深圳市华星光电半导体显示技术有限公司 一种驱动基板和显示面板
CN114203730B (zh) * 2021-12-09 2023-05-30 深圳市华星光电半导体显示技术有限公司 显示面板及其制作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101556968A (zh) * 2008-04-11 2009-10-14 三星移动显示器株式会社 薄膜晶体管和其制造方法以及有机发光二极管显示装置
CN101577283A (zh) * 2008-05-06 2009-11-11 三星移动显示器株式会社 薄膜晶体管阵列构件和有机发光显示装置及其制造方法
CN103646966A (zh) * 2013-12-02 2014-03-19 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板及其制备方法、显示装置
CN109728003A (zh) * 2019-01-03 2019-05-07 合肥鑫晟光电科技有限公司 显示基板、显示装置和显示基板的制造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9412623B2 (en) * 2011-06-08 2016-08-09 Cbrite Inc. Metal oxide TFT with improved source/drain contacts and reliability
KR102169014B1 (ko) * 2013-10-14 2020-10-23 삼성디스플레이 주식회사 박막트랜지스터 어레이 기판 및 그 제조방법
US9082664B2 (en) * 2013-11-12 2015-07-14 Shenzhen China Star Optoelectronics Technology Co., Ltd Method for manufacturing thin-film transistor substrate and thin-film transistor substrate manufactured with same
KR102408021B1 (ko) * 2014-11-11 2022-06-13 삼성디스플레이 주식회사 금속배선 및 이를 포함하는 표시 장치
CN110521003B (zh) * 2017-03-27 2023-06-09 夏普株式会社 有源矩阵基板及其制造方法
CN107293493A (zh) * 2017-06-06 2017-10-24 武汉华星光电技术有限公司 铟镓锌氧化物薄膜晶体管的制作方法
CN107799570A (zh) * 2017-10-09 2018-03-13 深圳市华星光电半导体显示技术有限公司 顶栅自对准金属氧化物半导体tft及其制作方法
KR102550633B1 (ko) * 2018-05-04 2023-07-04 삼성디스플레이 주식회사 박막 트랜지스터 기판 및 그 제조방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101556968A (zh) * 2008-04-11 2009-10-14 三星移动显示器株式会社 薄膜晶体管和其制造方法以及有机发光二极管显示装置
CN101577283A (zh) * 2008-05-06 2009-11-11 三星移动显示器株式会社 薄膜晶体管阵列构件和有机发光显示装置及其制造方法
CN103646966A (zh) * 2013-12-02 2014-03-19 京东方科技集团股份有限公司 一种薄膜晶体管、阵列基板及其制备方法、显示装置
CN109728003A (zh) * 2019-01-03 2019-05-07 合肥鑫晟光电科技有限公司 显示基板、显示装置和显示基板的制造方法

Also Published As

Publication number Publication date
CN111244110A (zh) 2020-06-05
US20220005956A1 (en) 2022-01-06
CN111244110B (zh) 2023-04-18

Similar Documents

Publication Publication Date Title
WO2016041304A1 (zh) 薄膜晶体管及制备方法、阵列基板及制备方法、显示装置
US10236388B2 (en) Dual gate oxide thin-film transistor and manufacturing method for the same
CN105097948B (zh) 薄膜晶体管、阵列基板及其制作方法、显示面板和装置
WO2013013599A1 (zh) 阵列基板及其制作方法、液晶面板、显示装置
WO2018188146A1 (zh) 一种阵列基板、显示装置及其制作方法
WO2021142868A1 (zh) 一种显示面板以及电子装置
JP2007157916A (ja) Ｔｆｔ基板及びｔｆｔ基板の製造方法
WO2021022594A1 (zh) 阵列基板、显示面板及阵列基板的制作方法
CN106847837B (zh) 一种互补型薄膜晶体管及其制作方法和阵列基板
US20160343739A1 (en) Thin film transistor, method of manufacturing thin film transistor, array substrate and display device
WO2015043220A1 (zh) 薄膜晶体管及其制备方法、阵列基板和显示装置
WO2013104226A1 (zh) 薄膜晶体管及其制造方法、阵列基板和显示器件
WO2015096342A1 (zh) 氧化物薄膜晶体管及其制备方法、阵列基板及显示装置
WO2015067054A1 (zh) 互补式薄膜晶体管及其制备方法、阵列基板和显示装置
CN105097548A (zh) 氧化物薄膜晶体管、阵列基板及各自制备方法、显示装置
WO2021204100A1 (zh) 显示基板及其制作方法、显示装置
WO2022116313A1 (zh) 一种阵列基板、显示面板及其制备方法
WO2014169544A1 (zh) 薄膜晶体管及其制备方法、阵列基板、显示装置
US10361261B2 (en) Manufacturing method of TFT substrate, TFT substrate, and OLED display panel
TWI567871B (zh) 薄膜電晶體及其製造方法
WO2019095408A1 (zh) 阵列基板及其制作方法、显示面板
US20190371827A1 (en) Flexible thin film transistor and manufacturing method therefor
WO2020232946A1 (zh) 改善金属氧化物tft特性的结构与其制作方法
WO2014172957A1 (zh) 电路板、其制作方法以及显示装置
WO2020172918A1 (zh) 一种显示面板及其制作方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20914158

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20914158

Country of ref document: EP

Kind code of ref document: A1