WO2015089963A1 - 阵列基板及其制备方法、显示装置 - Google Patents

阵列基板及其制备方法、显示装置 Download PDF

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Publication number
WO2015089963A1
WO2015089963A1 PCT/CN2014/075393 CN2014075393W WO2015089963A1 WO 2015089963 A1 WO2015089963 A1 WO 2015089963A1 CN 2014075393 W CN2014075393 W CN 2014075393W WO 2015089963 A1 WO2015089963 A1 WO 2015089963A1
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Prior art keywords
layer
electrode
array substrate
filter
thin film
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PCT/CN2014/075393
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English (en)
French (fr)
Inventor
王强涛
崔贤植
方正
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US14/415,638 priority Critical patent/US9612487B2/en
Priority to EP14861105.6A priority patent/EP2919266B1/en
Publication of WO2015089963A1 publication Critical patent/WO2015089963A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133357—Planarisation layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio

Definitions

  • the invention belongs to the technical field of liquid crystal display, and particularly relates to an array substrate, a preparation method thereof and a display device. Background technique
  • liquid crystal panels are increasingly moving toward high resolution and high image quality.
  • 1 is a structure (COA; Color filter on Array) of a filter layer (including a color filter 107 and a black matrix 106), which is a COA array substrate, and can effectively reduce the problem of light leakage of the cartridge.
  • the width of the black matrix 106 increases the pixel aperture ratio and thus the panel transmittance.
  • the combination of COA technology and super multi-dimensional field-switching liquid crystal display technology which mainly relies on the in-plane rotation of liquid crystal molecules, can effectively prevent light leakage in the oblique direction and avoid color mixing. Therefore, this technology has become one of the most competitive technologies in high-resolution products.
  • a basic structure of a COA array substrate is a pattern including a thin film transistor formed on a substrate 101.
  • the thin film transistor may be a top gate type or a bottom gate type.
  • a bottom gate type thin film transistor is taken as an example for description.
  • the thin film transistor specifically includes: a gate electrode 102, a gate insulating layer 103 covering the gate electrode 102, an active region 104 disposed on the gate insulating layer 103, and a source and a drain 105, and the source and drain electrodes 105 and The source area 104 is connected.
  • a filter layer 107 is disposed on the substrate 101 on which the thin film transistor is formed; a planarization layer 108 is disposed on the filter layer to eliminate the step; and the first electrode layer (common electrode) 110 and the passivation layer 111 are sequentially disposed.
  • PVX a second electrode layer
  • pixel electrode a second electrode layer
  • the contact via 109 is connected to the drain 105 of the thin film transistor. Among them, due to the contact with the via 109, the liquid crystal alignment may be irregular and cause light leakage.
  • the technical problem to be solved by the present invention includes providing an array substrate with improved aperture ratio, a method for fabricating the same, and a display device in view of the above-mentioned deficiencies of the existing array substrate.
  • the present invention provides an array substrate comprising: a filter layer disposed on a substrate provided with a thin film transistor, a planarization layer covering the filter layer, and the planarization layer a pixel electrode on the layer, the array substrate further includes a third electrode layer connected to the drain of the thin film transistor and extending to the filter layer; and a planarization layer is disposed above the third electrode layer on the filter layer The via hole is contacted, and the pixel electrode is connected to the third electrode layer through the contact via.
  • the drain of the array substrate of the present invention is electrically connected to the pixel electrode through a third electrode layer connected thereto and extending to the filter layer, wherein a contact via penetrating the planarization layer is disposed above the third electrode layer on the filter layer.
  • the pixel electrode is connected to the third electrode layer through the contact via, and the contact via is obviously smaller than the opening of the contact via for connecting the drain and the pixel electrode in the prior art, and the drain is not required to be opened. The rate has increased significantly.
  • the filter layer comprises a color filter and a black matrix
  • the pixel electrode is located above the color filter
  • the black matrix is located at least above the thin film transistor
  • the color filter and the color filter Black matrixes are spaced apart on the substrate
  • the third electrode layer extends onto the color filter or the third electrode layer extends onto the black matrix.
  • the array substrate further includes a passivation layer and a common electrode disposed in sequence on the pixel electrode.
  • the array substrate further includes a passivation layer and a common electrode disposed between the pixel electrode and the planarization layer, wherein the common electrode and the passivation layer are sequentially disposed on the planarization layer And the contact via penetrates through the planarization layer and the passivation layer.
  • the material of the pixel electrode and the common electrode is indium tin oxide.
  • the present invention also provides a method for fabricating the above array substrate, comprising the steps of: forming a pattern including a filter layer by a patterning process on a substrate on which a thin film transistor is formed;
  • a pattern including a pixel electrode is formed by a patterning process, and the pixel electrode is connected to the third electrode layer through a contact via penetrating through the planarization layer.
  • the filter layer includes a color filter and a black matrix
  • the pixel electrode is formed above the color filter
  • the black matrix is formed at least above the thin film transistor
  • the color filter a sheet and the black matrix are spaced apart on the substrate
  • the third electrode layer extends onto the color filter or the third electrode layer extends onto the black matrix.
  • the preparation method further comprises the steps of:
  • a pattern including a common electrode is formed on the passivation layer by a patterning process.
  • the step of forming a contact via through the planarization layer after forming the planarization layer on the third electrode layer on the filter layer further comprises the steps of:
  • a contact via penetrating through the planarization layer formed over the third electrode layer on the filter layer also penetrates the passivation layer.
  • the preparation method of the array substrate of the present invention is simple and easy to implement.
  • the technical solution adopted to solve the technical problem of the present invention is a display device including the above array substrate.
  • the display device of the present invention includes the above array substrate, the aperture ratio thereof is improved.
  • 1 is a structural view of a conventional array substrate
  • FIG. 2 is a structural view of an array substrate according to an embodiment of the present invention
  • FIG. 3 is a structural view of another array substrate according to an embodiment of the present invention
  • FIG. 4 is another array according to an embodiment of the present invention.
  • the present embodiment provides an array substrate including a thin film transistor disposed on a substrate 101.
  • the thin film transistor may be either a top gate type or a bottom gate type.
  • a bottom gate type thin film transistor will be described as an example.
  • the thin film transistor specifically includes a gate electrode 102, a gate insulating layer 103 covering the gate electrode 102, an active region 104 disposed on the gate insulating layer 103, and a source and drain electrode 105 connected to the active region 104.
  • the array substrate further includes a filter layer (including a color filter and a black matrix) disposed on the substrate 101 provided with the thin film transistor, covering the filter layer
  • a filter layer including a color filter and a black matrix
  • the planarization layer 108, the pixel electrode provided on the planarization layer 108, and the third electrode layer 113 connected to the drain 105 of the thin film transistor and extending to the filter layer (covering a portion of the filter layer).
  • one end of the third electrode layer 113 is connected to the drain 105 of the thin film transistor, and the other end extends to the upper surface of the filter layer.
  • a contact via 109 penetrating the planarization layer 108 is disposed above the third electrode layer 113 on the filter layer, and the pixel electrode is connected to the third electrode layer 113 through the contact via 109, thereby further leaking with the thin film transistor.
  • the pole 105 is connected.
  • the drain 105 of the thin film transistor on the array substrate of the present embodiment is connected to the pixel electrode through a third electrode layer 113 extending to the filter without extending the length of the drain 105, so that the opening of the array substrate is not affected. rate.
  • the third electrode layer 113 extends over the partial filter layer, it is only necessary to form a contact via 109 of the planarization layer 108 penetrating the third electrode layer 113 on the filter, the contact via The depth of the 109 is shallower than that of the prior art, and the opening width is narrower than that of the prior art. Therefore, the aperture ratio of the array substrate provided in this embodiment is significantly higher than that of the existing array substrate.
  • the second electrode layer 112 is disposed above the first electrode layer 110 and separated by the passivation layer 111.
  • the electrode connected to the thin film transistor drain 105 through the third electrode layer 113 is a pixel electrode, and the other electrode is a common electrode. The details are described below.
  • the third electrode layer 113 extends to the color filter 107 (for example, a red filter, a green filter, and a blue filter). (covering a portion of the color filter 107), the first electrode layer 110 of the array substrate is positioned above the color filter 107. That is, a contact via 109 penetrating the planarization layer 108 is formed over the third electrode layer 113 on the color filter 107 such that the third electrode layer 113 is connected to the first electrode layer 110.
  • the color filter 107 for example, a red filter, a green filter, and a blue filter.
  • the drain electrode 105 of the thin film transistor is not extended, and the depth of the contact via 109 passing through the planarization layer 108 and the width of the opening are as large as the depth of the contact via and the width of the opening of the conventional array substrate shown in FIG. Small, so the aperture ratio of the array substrate of the present embodiment can be significantly improved.
  • the third electrode layer 113 is extended. Extending to the black matrix 106 (covering a portion of the black matrix 106), the black matrix 106 overlies the thin film transistor (the black matrix 106 is used to avoid light leakage in the region where the thin film transistor is located). That is, the contact via 109 penetrating the planarization layer 108 is formed over the third electrode layer 113 on the black matrix 106 such that the third electrode layer 113 is connected to the first electrode layer 110. Since the black matrix 106 is disposed above the thin film transistor, the contact via 109 is above the black matrix 106, and the depth of the contact via 109 and the width of the opening are significantly similar to those of the existing array substrate shown in FIG. The depth of the hole and the width of the opening are small, and the aperture ratio of the array substrate of the present embodiment is remarkably improved.
  • the first electrode layer 110 is a pixel electrode, and the pixel electrode is disposed on the planarization layer 108, and a passivation layer is sequentially disposed thereon.
  • the second electrode layer 112 is a common electrode, and the pixel electrode (the first electrode layer 110) is connected to the third electrode layer 113 through the contact via 109, thereby being connected to the drain of the thin film transistor. 105 connected.
  • the first electrode layer 110 is a common electrode
  • the second electrode layer 112 is a pixel electrode
  • the common electrode is disposed on the planarization layer 108, and is also sequentially disposed thereon.
  • the contact via 109 penetrates the planarization layer 108 and the passivation layer 111.
  • the third electrode layer 113 may also extend over the color filter 107, and other configurations are similar to those of FIG. 4, that is, the pixel electrode passes through the planarization layer 108 and the passivation layer 111.
  • the contact via 109 is connected to the third electrode layer 113 to be connected to the drain 105 of the thin film transistor.
  • the first electrode layer 110 is a plate electrode, and may also be a strip electrode; the second electrode layer 112 located above the first electrode layer 110 is a strip electrode. According to the direction of the electric field, this is the ADS mode. Of course, other modes are also possible. Further preferably, the material of the pixel electrode and the common electrode is indium tin oxide, and of course, other transparent conductive materials may be used. Example 2
  • This embodiment provides a method for preparing an array substrate, which includes the following steps: Step 1. Form a pattern including a thin film transistor by a patterning process on the substrate 101, wherein the thin film transistor may be a top gate type or a bottom gate type.
  • Step 1. Form a pattern including a thin film transistor by a patterning process on the substrate 101, wherein the thin film transistor may be a top gate type or a bottom gate type.
  • a description will be given of a case where a bottom gate type thin film transistor is prepared.
  • a gate electrode is formed on the substrate 101 by sputtering, exposure, development, etching, stripping, etc., and plasma enhanced chemical vapor deposition (PECVD; Plasma Enhanced) is performed on the gate 102.
  • PECVD plasma enhanced chemical vapor deposition
  • a process such as a chemical Vapor Deposition forms a gate insulating layer 103, and an active region 104 is formed on the gate insulating layer 103 by sputtering, exposure, development, etching, lift-off, etc., and sputtering is performed over the active region 104.
  • the source, drain, source and drain electrodes 105 are connected to the active region 104 by processes such as exposure, development, etching, and lift-off.
  • the gate 102 may be one or more materials selected from the group consisting of molybdenum (Mo), molybdenum-niobium alloy (MoNb), aluminum (A1), aluminum-niobium alloy (AlNd), titanium (Ti), and copper (Cu).
  • Mo molybdenum
  • MoNb molybdenum-niobium alloy
  • AlNd aluminum-niobium alloy
  • Ti titanium
  • Cu copper
  • the formed single-layer or multi-layer composite film is preferably a single layer or a multilayer composite film composed of Mo, A1 or an alloy containing Mo and A1; and has a thickness of 100 nm to 500 nm.
  • the gate insulating layer 103 may be silicon oxide (SiOx), silicon nitride (SiNx), germanium oxide (HfOx), silicon oxynitride (SiON), aluminum.
  • SiOx silicon oxide
  • SiNx silicon nitride
  • HfOx germanium oxide
  • SiON silicon oxynitride
  • a multilayer composite film composed of one or two materials of an oxide (AlOx) or the like. The thickness is controlled within 100 ⁇ 600nm and can be adjusted according to the actual situation.
  • the active region 104 may be formed by sputtering using a thin film containing an element of In (indium), Ga (gallium), Zn (zinc), 0 (oxygen), Sn (tin), etc., wherein the film must contain oxygen and Two or more other elements, such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), and the like.
  • the material of the oxide semiconductor active layer is preferably IGZO and IZO, and the thickness is preferably controlled within 10 to 100 nm.
  • the source and drain electrodes 105 may be molybdenum (Mo), molybdenum-niobium alloy (MoNb), aluminum.
  • A1 a single-layer or multi-layer composite laminate formed of one or more materials of aluminum-niobium alloy (AlNd), titanium (Ti) and copper (Cu), preferably Mo, A1 or containing Mo, A1 A single or multi-layer composite film composed of an alloy.
  • Step 2 On the substrate 101 on which the above steps are completed, a pattern including a filter layer is formed by a patterning process.
  • the filter layer comprises a color filter 107 and a black matrix 106.
  • a black matrix (BM; BLACK MATRIX) 106 is formed on the substrate 101 on which the thin film transistor is formed by coating, exposure, development, baking, or the like, and is coated on the substrate 101 on which the black matrix 106 is formed.
  • the process of exposure, development, baking, etc. forms a color filter 107, that is, a color filter 107 such as red, green, and blue (RGB) sub-pixels.
  • the black matrix 106 and the color filter 107 are spaced apart.
  • a third electrode layer 113 which is connected to the drain electrode 105 of the thin film transistor and extends to the filter layer is formed by a process of sputtering, exposure, development, etching, lift-off or the like.
  • the third electrode layer 113 preferably extends onto the color filter 107, and may preferably extend to the black matrix 106.
  • one end of the third electrode layer 113 is connected to the drain 105 of the thin film transistor, and the other end extends to the color filter 107 or the black matrix 106, preferably to the upper surface of the color filter 107 or the black matrix 106. on.
  • the material of the third electrode layer 113 is made of a conductive material, typically a metal material such as copper, aluminum, silver or the like.
  • a metal material such as copper, aluminum, silver or the like.
  • the projection of the third electrode layer 113 on the substrate 101 can be as small as possible, preferably not exceeding the projection of the drain 105 of the thin film transistor on the substrate 101, to reduce the effect on the aperture ratio.
  • Step 4 On the substrate 101 which has completed the above steps, a planarization layer 108 is formed for eliminating the difference between the color filters 107 of different colors and the black matrix 106.
  • the material of the planarization layer 108 is generally silicon dioxide, silicon nitride, aluminum oxide or the like.
  • Step 5 On the substrate 101 which has completed the above steps, a contact via 109 penetrating the planarization layer 108 is formed over the third electrode layer 113 on the filter layer.
  • a contact via 109 penetrating the planarization layer 108 is formed over the third electrode layer 113 on the color filter 107; if the third electrode The layer 113 extends over the black matrix 106 to form a contact via 109 through the planarization layer 108 over the third electrode layer 113 on the black matrix 106, respectively.
  • Step 6 On the substrate 101 that completes the above steps, formed by a patterning process A pattern of pixel electrodes is included, and the pixel electrodes are connected to the third electrode layer 113 through the contact vias 109.
  • the material of the pixel electrode is preferably indium tin oxide. Of course, other transparent conductive materials are also possible.
  • Step 7 On the substrate 101 which has completed the above steps, a passivation layer 111 is formed.
  • the material of the passivation layer 111 is generally silicon dioxide, silicon nitride, aluminum oxide or the like.
  • Step 8 On the substrate 101 which has completed the above steps, a pattern including a common electrode is formed by a patterning process.
  • the material of the common electrode is preferably indium tin oxide.
  • other transparent conductive materials are also possible, and an array substrate as shown in Fig. 2 or Fig. 3 is obtained.
  • the pixel electrode is the first electrode layer 110 shown in Figs. 2 and 3, and the common electrode is the second electrode layer 112.
  • the drain 105 of the thin film transistor on the array substrate prepared by the method provided by the embodiment is electrically connected to the pixel electrode 110 through a third electrode layer 113 extending to the filter without extending the length of the drain 105. Does not affect the aperture ratio of the array substrate. In particular, since the third electrode layer 113 extends onto the filter, it is only necessary to form a contact via 109 penetrating the planarization layer 108 on the third electrode layer 113 on the filter, the contact via 109 being distinct The aperture is shallower than the prior art, and the aperture width is narrower than that of the prior art. Therefore, the aperture ratio of the array substrate provided in this embodiment is significantly improved relative to the existing array substrate.
  • the embodiment provides a method for preparing an array substrate, which is similar to the second embodiment.
  • the common electrode is formed by a patterning process. Graphics.
  • the common electrode After forming the common electrode, it also includes: A passivation layer 111 is formed on the common electrode, and a contact via 109 penetrating the passivation layer 111 and the planarization layer 108 is formed over the third electrode layer 113 on the filter layer.
  • the third electrode layer 113 extends onto the color filter 107, a contact via 109 penetrating through the passivation layer 111 and the planarization layer 108 is formed over the third electrode layer 113 on the color filter 107;
  • the third electrode layer 113 extends onto the black matrix 106, and a contact via 109 penetrating the passivation layer 111 and the planarization layer 108 is formed over the third electrode layer 113 on the black matrix 106, respectively.
  • a pattern including a pixel electrode is formed by a patterning process, in which a portion of the third electrode layer 113 is exposed through the contact via 109 formed in the above step, that is, as shown in Fig. 4.
  • the pixel electrode is the second electrode layer 112
  • the common electrode is the first electrode layer 110.
  • the embodiment provides a display device comprising the array substrate described in Embodiment 1.
  • the display device can be: a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigation device, and the like, or any display product or component.
  • the display device of this embodiment has the array substrate of the first embodiment, so that it has a better aperture ratio and a better visual effect.

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Abstract

一种阵列基板及其制备方法、显示装置，属于液晶显示技术领域，阵列基板包括：设置在设有薄膜晶体管的基底（101）上的滤光层、覆盖滤光层的平坦化层（108）、设于平坦化层上的像素电极、以及与薄膜晶体管漏极（105）连接并延伸至滤光层上方的第三电极层（113）；在滤光层上方的第三电极层（113）的上方设有贯穿平坦化层（108）的接触过孔（109），且像素电极通过接触过孔（109）与第三电极层（113）连接，可解决现有的阵列基板的开口率低的问题。

Description

阵列基板及其制备方法、 显示装置 技术领域
本发明属于液晶显示技术领域， 具体涉及一种阵列基板及其 制备方法、 显示装置。 背景技术
随着平板显示器件薄膜工艺（thin film transistor )技术和工艺 的进步， 液晶面板日益向高分辨高画质方面发展。 图 1是滤光层 (包括彩色滤光片 107和黑矩阵 106 )位于阵列基板的结构（COA; Color filter on Array ) , 即 COA阵列基板， 由于没有对盒产生漏 光的问题， 从而可以有效减少黑矩阵 106宽度， 从而提高了像素 开口率， 进而提高面板透过率。 COA技术与主要靠液晶分子面内 旋转的超级多维场开关液晶显示技术相结合， 可以有效防止倾斜 方向漏光， 避免混色现象发生。 因此， 该技术成为高分辨率产品 中有竟争力的技术之一。
如图 1 所示， 通常 COA阵列基板的基本结构是在基底 101 上形成包括薄膜晶体管的图形， 其中薄膜晶体管为顶栅型或底栅 型均可， 这里以底栅型薄膜晶体管为例进行说明。 该薄膜晶体管 具体包括： 栅极 102, 覆盖栅极 102的栅极绝缘层 103 , 设于栅极 绝缘层 103上的有源区 104, 以及源、 漏极 105, 且源、 漏极 105 与有源区 104连接。 在形成有薄膜晶体管的基底 101上设有滤光 层 107; 在滤光层上设有平坦化层 108, 用来消除段差； 再依次设 置第一电极层 （公共电极） 110、 钝化层 111 ( PVX ) 、 第二电极 层 （像素电极） 112, 其中第二电极层 （像素电极） 112通过贯穿 钝化层 111、 第一电极层 （公共电极） 110、 平坦化层 108以及滤 光层的接触过孔 109与薄膜晶体管的漏极 105连接。 其中， 由于 接触过孔 109处， 液晶排列会出现不规则现象并导致漏光现象发 生， 故需要增加漏极 105部分的长度， 以避免漏光现象的发生。 但是漏极 105 的长度增加将导致开口率减小， 增加产品功耗。 而 且， 由于接触过孔 109 比较深， 其顶端开口较大， 所以会进一步 地影响 COA阵列基板的开口率。 再言之接触过孔 109比较深， 也 很可能引起断线现象， 导致像素电极与漏极断路， 无法进行像素 充电。 发明内容
本发明所要解决的技术问题包括， 针对现有的阵列基板存在 的上述不足， 提供一种开口率提高的阵列基板及其制备方法、 显 示装置。
为了解决上述技术问题， 本发明提供了一种阵列基板， 其包 括： 设置在设有薄膜晶体管的基底上的滤光层、 覆盖所述滤光层 的平坦化层、 和设于所述平坦化层上的像素电极， 所述阵列基板 还包括与薄膜晶体管的漏极连接并延伸至滤光层上的第三电极 层； 在滤光层上的第三电极层上方设有贯穿平坦化层的接触过孔， 且像素电极通过该接触过孔与第三电极层连接。
本发明的阵列基板的漏极通过与其连接并延伸至滤光层上的 第三电极层与像素电极电连接， 其中滤光层上的第三电极层上方 设有贯穿平坦化层的接触过孔， 像素电极通过该接触过孔与第三 电极层连接， 该接触过孔明显比现有技术中用于连接漏极与像素 电极的接触过孔的开口小， 且无需延长漏极， 故其开口率明显提 高。
优选的是， 所述滤光层包括彩色滤光片和黑矩阵， 所述像素 电极位于彩色滤光片上方， 所述黑矩阵至少位于所述薄膜晶体管 上方， 所述彩色滤光片和所述黑矩阵在所述基底上间隔设置， 并 且， 所述第三电极层延伸至所述彩色滤光片上， 或者所述第三电 极层延伸至所述黑矩阵上。
优选的是， 所述阵列基板还包括在所述像素电极上依次设置 的钝化层和公共电极， 可选择地， 所述阵列基板还包括在所述像素电极和所述平坦 化层之间设置的钝化层和公共电极， 所述公共电极和所述钝化层 依次设置在所述平坦化层上， 并且所述接触过孔贯穿所述平坦化 层和所述钝化层。
进一步优选的是， 所述像素电极与公共电极的材料均为氧化 铟锡。
为了解决本发明的技术问题， 本发明还提供了一种上述阵列 基板的制备方法， 其包括如下步骤： 在形成有薄膜晶体管的基底 上， 通过构图工艺形成包括滤光层的图形；
在完成上述的步骤的基底上， 通过构图工艺形成与薄膜晶体 管漏极连接并延伸至滤光层上的第三电极层；
在完成上述步骤的基底上， 形成平坦化层， 并在滤光层上的 第三电极层上方形成贯穿平坦化层的接触过孔；
在完成上述步骤的基底上， 通过构图工艺形成包括像素电极 的图形， 且所述像素电极通过贯穿平坦化层的接触过孔与第三电 极层连接。
优选的是， 所述滤光层包括彩色滤光片和黑矩阵， 所述像素 电极形成在所述彩色滤光片上方， 所述黑矩阵至少形成在所述薄 膜晶体管上方， 所述彩色滤光片和所述黑矩阵在所述基底上间隔 设置， 并且
所述第三电极层延伸至彩色滤光片上， 或者所述第三电极层 延伸至黑矩阵上。
优选的是， 所述制备方法还包括步骤：
在像素电极上形成钝化层； 和
在所述钝化层上通过构图工艺形成包括公共电极的图形。 可选择地， 在形成平坦化层之后、 在所述滤光层上的第三电 极层上形成贯穿平坦化层的接触过孔之前还包括步骤：
在所述平坦化层上通过构图工艺形成包括公共电极的图形； 以及
在所述公共电极上形成钝化层， 其中在所述滤光层上的第三电极层上方形成的贯穿平坦化层 的接触过孔还贯穿所述钝化层。
本发明的阵列基板的制备方法简单、 容易实现。
解决本发明技术问题所采用的技术方案是一种显示装置， 其 包括上述阵列基板。
由于本发明的显示装置包括上述阵列基板，故其开口率提高。 附图说明
图 1为现有阵列基板的结构图；
图 2为根据本发明实施例的一种阵列基板的结构图； 图 3为根据本发明实施例的另一种阵列基板的结构图； 以及， 图 4为根据本发明实施例的又一种阵列基板的结构图。 其中附图标记为： 101、 基底； 102、 栅极； 103、 栅极绝缘层； 104、 有源区； 105、 源极 /漏极； 106、 黑矩阵； 107、 彩色滤光片
108、 平坦化层； 109、 接触过孔； 110、 第一电极层； 111、 钝化 层； 112、 第二电极层； 113、 第三电极层。 具体实施方式
为使本领域技术人员更好地理解本发明的技术方案， 下面结 合附图和具体实施方式对本发明作进一步详细描述。 实施例 1 :
结合图 2、 3、 4所示， 本实施例提供了一种阵列基板， 其包 括， 设置在基底 101 上的薄膜晶体管。 需要说明的是， 该薄膜晶 体管为顶栅型或底栅型均可， 这里以底栅型薄膜晶体管为例进行 说明。 该薄膜晶体管具体包括， 栅极 102, 覆盖栅极 102的栅极绝 缘层 103,设于栅极绝缘层 103上的有源区 104,以及与有源区 104 连接的源漏极 105。该阵列基板还包括设于设有薄膜晶体管的基底 101上的滤光层（其包括彩色滤光片和黑矩阵）、覆盖所述滤光层 的平坦化层 108、设于所述平坦化层 108上的像素电极、 以及与薄 膜晶体管的漏极 105连接并延伸至滤光层上 （覆盖滤光层的一部 分）的第三电极层 113。 优选地， 第三电极层 113的一端连接至薄 膜晶体管的漏极 105, 另一端延伸至滤光层的上表面上。 其中， 在 滤光层上的第三电极层 113上方设有贯穿平坦化层 108的接触过 孔 109, 且像素电极通过该接触过孔 109与第三电极层 113连接， 进而与薄膜晶体管的漏极 105连接。
本实施例的阵列基板上的薄膜晶体管的漏极 105通过一延伸 至滤光片上的第三电极层 113 与像素电极连接， 而不用延长漏极 105的长度， 所以不会影响阵列基板的开口率。 特别是， 由于该第 三电极层 113延伸至部分滤光层上， 所以只需形成贯穿在滤光片 上的第三电极层 113上的平坦化层 108的接触过孔 109,该接触过 孔 109的深度比现有技术中的接触过孔的深度浅， 开口宽度比现 有技术中的窄， 所以本实施例提供的阵列基板相对于现有的阵列 基板的开口率明显提高。
如图 2~4所示， 第二电极层 112设于第一电极层 110上方且 通过钝化层 111隔开。 第一电极层 110和第二电极层 112之中通 过第三电极层 113与薄膜晶体管漏极 105连接的电极为像素电极， 另一电极为公共电极。 下面具体说明。
如图 2所示， 作为本实施例的一种情况， 优选地， 上述第三 电极层 113延伸至彩色滤光片 107(例如红色滤光片、绿色滤光片、 蓝色滤光片）上 （覆盖彩色滤光片 107 的一部分） ， 阵列基板的 第一电极层 110位于彩色滤光片 107上方。 也就是说在彩色滤光 片 107上的第三电极层 113上方形成贯穿平坦化层 108的接触过 孔 109, 使得第三电极层 113与第一电极层 110连接。 此时， 薄膜 晶体管的漏极 105不用延长， 而且贯穿平坦化层 108的接触过孔 109 的深度和开口的宽度要比如图 1 所示现有的阵列基板的接触 过孔的深度和开口的宽度小， 所以本实施例的阵列基板的开口率 可以得到明显的提高。
当然也可以如图 3所示， 优选地， 将上述第三电极层 113延 伸至黑矩阵 106上 （覆盖黑矩阵 106的一部分） ， 黑矩阵 106覆 盖在薄膜晶体管上方 （该黑矩阵 106用于避免薄膜晶体管所在区 域漏光） 。 也就是说在黑矩阵 106上的第三电极层 113上方形成 贯穿平坦化层 108的接触过孔 109,使得第三电极层 113与第一电 极层 110连接。 由于黑矩阵 106设于薄膜晶体管上方， 此时接触 过孔 109在黑矩阵 106的上方， 而且该接触过孔 109的深度和开 口的宽度明显比如图 1 所示的现有的阵列基板的接触过孔的深度 和开口的宽度小， 所示本实施例的阵列基板的开口率明显提高。
需要说明的是， 在上述如图 2、 3所示的阵列基板中， 第一电 极层 110为像素电极， 所述像素电极设在平坦化层 108上， 在其 上还依次设有钝化层 111和第二电极层 112, 所述第二电极层 112 为公共电极， 所述像素电极 (第一电极层 110 )通过接触过孔 109 与第三电极层 113相连， 从而与薄膜晶体管的漏极 105相连。
当然， 也可以如图 4所示， 所述第一电极层 110为公共电极， 所述第二电极层 112为像素电极，所述公共电极设在平坦化层 108 上， 在其上还依次设有钝化层 111 和像素电极， 所述像素电极通 过接触过孔 109与第三电极层 113相连， 从而与薄膜晶体管的漏 极 105相连。此时，接触过孔 109贯穿平坦化层 108和钝化层 111。
此外， 在图 4的情况下， 第三电极层 113也可以延伸至彩色 滤光片 107上方， 而其他构造与图 4相似， 即， 所述像素电极通 过贯穿平坦化层 108和钝化层 111的接触过孔 109与第三电极层 113相连， 从而与薄膜晶体管的漏极 105相连。
在本实施例中， 所述第一电极层 110为板状电极， 也可以为 条状电极； 位于第一电极层 110上方的第二电极层 112为条状电 极。根据电场方向，此时为 ADS模式。 当然其他模式也是可以的。 进一步优选像素电极与公共电极的材料均为氧化铟锡， 当然也可 以采用其他透明导电材料。 实施例 2
本实施例提供了一种阵列基板的制备方法，其包括如下步骤： 步骤一、 在基底 101上通过构图工艺形成包括薄膜晶体管的 图形， 其中， 薄膜晶体管为顶栅型或底栅型均可。 这里， 以制备 底栅型薄膜晶体管为例进行说明。 具体地， 在基底 101 上通过溅 射， 曝光， 显影， 刻蚀， 剥离等工艺形成栅电极， 在栅极 102上 通过等离子体增强化学气相沉积法 （PECVD; Plasma Enhanced
Chemical Vapor Deposition )等工艺形成栅极绝缘层 103 , 在栅极 绝缘层 103上通过溅射， 曝光， 显影， 刻蚀， 剥离等工艺形成有 源区 104, 在有源区 104之上通过溅射、 曝光、 显影、 刻蚀、 剥离 等工艺形成源、 漏极， 源、 漏极 105与有源区 104连接。
其中， 所述栅极 102可以为钼 （Mo ) 、 钼铌合金 ( MoNb ) 、 铝 （A1 ) 、 铝钕合金 ( AlNd ) 、 钛（Ti )和铜 （Cu ) 中的一种或 多种材料形成的单层或多层复合膜， 优选为 Mo、 A1或含 Mo、 A1 的合金组成的单层或多层复合膜； 厚度为 100nm~500nm。
在本实施例中， 所述栅极绝缘层 103 可以为硅的氧化物 ( SiOx ) 、 硅的氮化物 （SiNx ) 、 铪的氧化物 （ HfOx ) 、 硅的氮 氧化物 （SiON ) 、 铝的氧化物 （AlOx )等中的一种或两种材料组 成的多层复合膜。 其厚度控制在 100~600nm之内， 可依照实际情 况进行调整。
所述有源区 104可以由包含 In (铟）、 Ga (镓）、 Zn (锌）、 0 (氧）、 Sn (锡）等元素的薄膜通过溅射形成， 其中薄膜中必须 包含氧元素和其他两种或两种以上的元素， 如氧化铟镓锌 ( IGZO ) 、 氧化铟锌（ IZO ) 、 氧化铟锡（ InSnO ) 、 氧化铟镓锡 ( InGaSnO )等。 氧化物半导体有源层的材料优选 IGZO和 IZO, 厚度优选控制在 10~100nm之内。
所述源漏极 105可以是钼 （Mo ) 、 钼铌合金 ( MoNb ) 、 铝
( A1 ) 、 铝钕合金 ( AlNd ) 、 钛（Ti )和铜 （Cu ) 中的一种或多 种材料形成的单层或多层复合叠层， 优先为 Mo、 A1或含 Mo、 A1 的合金组成的单层或多层复合膜。
步骤二、 在完成上述步骤的基底 101上， 通过构图工艺形成 包括滤光层的图形。 其中， 滤光层包括彩色滤光片 107和黑矩阵 106。 具体地说， 在形成有薄膜晶体管的基底 101上通过涂覆， 曝 光，显影，烘烤等工艺形成黑矩阵 （BM; BLACK MATRIX) 106, 在形成有黑矩阵 106的基底 101上通过涂覆， 曝光， 显影， 烘烤 等工艺形成彩色滤光片 107, 也就是例如红、 绿、 蓝（RGB )子像 素的彩色滤光片 107。其中黑矩阵 106和彩色滤光片 107是间隔设 置的。
步骤三、 在完成上述步骤的基底 101上， 通过溅射， 曝光， 显影， 刻蚀， 剥离等工艺形成与薄膜晶体管的漏极 105连接并延 伸至滤光层上的第三电极层 113。此时， 该第三电极层 113优选延 伸至彩色滤光片 107上， 也可以优选延伸至黑矩阵 106上。 具体 地， 第三电极层 113的一端与薄膜晶体管的漏极 105连接， 另一 端延伸至彩色滤光片 107或者黑矩阵 106上， 优选地延伸至彩色 滤光片 107或者黑矩阵 106的上表面上。 第三电极层 113的材料 采用导电材料， 一般为金属材料， 例如铜、 铝、 银等。 在第三电 极层 113 的材料为金属材料并且其另一端延伸至彩色滤光片 107 的上表面上时， 在能够保证第三电极层 113 与像素电极之间的良 好的电连接的前提下， 第三电极层 113在基底 101上的投影可以 尽可能小， 优选地不超过薄膜晶体管的漏极 105在基底 101上的 投影， 以减少对开口率的影响。 步骤四、 在完成上述步骤的基底 101上， 形成平坦化层 108, 用于消除不同颜色的彩色滤光片 107 以及黑矩阵 106之间存在的段差。 其中， 平坦化层 108的材料一 般为二氧化硅、 氮化硅、 氧化铝材料等。
步骤五、 在完成上述步骤的基底 101上， 在滤光层上的第三 电极层 113上方形成贯穿平坦化层 108的接触过孔 109。这里， 如 果第三电极层 113延伸至彩色滤光片 107上， 就相应地在彩色滤 光片 107上的第三电极层 113上方形成贯穿平坦化层 108的接触 过孔 109; 如果第三电极层 113延伸至黑矩阵 106上， 就相应地在 黑矩阵 106上的第三电极层 113上方形成贯穿平坦化层 108的接 触过孔 109。
步骤六、 在完成上述步骤的基底 101上， 通过构图工艺形成 包括像素电极的图形， 且像素电极通过接触过孔 109与第三电极 层 113连接。 其中像素电极的材料优选为氧化铟锡， 当然其他透 明导电材料也是可以的。
步骤七、 在完成上述步骤的基底 101 上， 形成钝化层 111。 其中， 钝化层 111 的材料一般为二氧化硅、 氮化硅、 氧化铝材料 等。
步骤八、 在完成上述步骤的基底 101上， 通过构图工艺形成 包括公共电极的图形。 其中公共电极的材料优选为氧化铟锡， 当 然其他透明导电材料也是可以的， 得到如图 2或图 3所示的阵列 基板。
需要说明的是， 上述像素电极为图 2、 3中所示的第一电极层 110, 公共电极为第二电极层 112。
采用本实施例提供的方法制备的阵列基板上的薄膜晶体管的 漏极 105通过一延伸至滤光片上的第三电极层 113与像素电极 110 电连接， 而不用延长漏极 105 的长度， 所以不会影响阵列基板的 开口率。 特别是， 由于该第三电极层 113延伸至滤光片上， 所以 只需形成贯穿滤光片上的第三电极层 113上的平坦化层 108的接 触过孔 109, 该接触过孔 109明显深度比现有的浅， 开口宽度比现 有的窄， 所以本实施例提供的阵列基板相对于现有的阵列基板的 开口率明显提高。
本领域技术人员可以理解的是， 在制备完成阵列基板之后， 还要通过液晶灌注 （滴下）装置形成液晶层， 再将该阵列基板与 对盒基板（彩膜基板）对盒。 此处将省略了对这些已知操作的详 细说明。 实施例 3
本实施例提供了一种阵列基板的制备方法， 该方法与实施例 2相似， 区别在于， 在基底上依次制备完成薄膜晶体管、 滤光层、 平坦化层 108后， 通过构图工艺形成包括公共电极的图形。 在形 成公共电极后还包括： 在公共电极上形成钝化层 111 , 并在滤光层上的第三电极层 113上方形成贯穿钝化层 111和平坦化层 108的接触过孔 109。 如 果第三电极层 113延伸至彩色滤光片 107上， 就相应地在彩色滤 光片 107上的第三电极层 113上方形成贯穿钝化层 111和平坦化 层 108的接触过孔 109; 如果第三电极层 113延伸至黑矩阵 106 上， 就相应地在黑矩阵 106上的第三电极层 113上方形成贯穿钝 化层 111和平坦化层 108的接触过孔 109。
在完成上述步骤的基底上， 通过构图工艺形成包括像素电极 的图形， 其中通过上述步骤中形成的接触过孔 109暴露出第三电 极层 113的一部分， 也就是如图 4所示。 此时像素电极为第二电 极层 112, 公共电极为第一电极层 110。 实施例 4
本实施例提供了一种显示装置， 其包括实施例 1所述的阵列 基板。
该显示装置可以为： 手机、 平板电脑、 电视机、 显示器、 笔 记本电脑、 数码相框、 导航仪等任何具有显示功能的产品或部件。
本实施例的显示装置中具有实施例 1 中的阵列基板， 故其具 有更好的开口率， 视觉效果更好。
当然， 本实施例的显示装置中还可以包括其他常规结构， 如 背光源、 电源单元、 显示驱动单元等， 在此不予赘述。 可以理解的是， 以上实施方式仅仅是为了说明本发明的原理 而采用的示例性实施方式， 然而本发明并不局限于此。 对于本领 域内的普通技术人员而言， 在不脱离本发明的精神和实质的情况 下， 可以做出各种变型和改进， 这些变型和改进也视为本发明的 保护范围。

Claims

权 利 要 求 书
1. 一种阵列基板， 包括： 设置在设有薄膜晶体管的基底上的 滤光层、 覆盖所述滤光层的平坦化层、 设于所述平坦化层上方的 像素电极， 其特征在于， 所述阵列基板还包括与所述薄膜晶体管 的漏极连接并延伸至所述滤光层上方的第三电极层；
在所述第三电极层上方设有贯穿所述平坦化层的接触过孔， 且所述像素电极通过所述接触过孔与所述第三电极层连接。
2. 根据权利要求 1所述的阵列基板， 其特征在于， 所述滤光 层包括彩色滤光片和黑矩阵， 所述像素电极位于所述彩色滤光片 上方， 所述黑矩阵至少位于所述薄膜晶体管上方， 所述彩色滤光 片和所述黑矩阵在所述基底上间隔设置， 并且
所述第三电极层延伸至所述彩色滤光片上， 或者
所述第三电极层延伸至所述黑矩阵上。
3. 根据权利要求 2所述的阵列基板， 其特征在于， 还包括： 在所述像素电极上依次设置的钝化层和公共电极。
4. 根据权利要求 2所述的阵列基板， 其特征在于， 还包括： 在所述像素电极和所述平坦化层之间设置的钝化层和公共电极， 所述公共电极和所述钝化层依次设置在所述平坦化层上， 并且所 述接触过孔贯穿所述平坦化层和所述钝化层。
5. 根据权利要求 3或 4所述的阵列基板， 其特征在于， 所述 像素电极与所述公共电极的材料均为氧化铟锡。
6. 一种阵列基板的制备方法， 其特征在于， 包括如下步骤： 在形成有薄膜晶体管的基底上， 通过构图工艺形成包括滤光 层的图形； 在完成上述步骤的基底上， 通过构图工艺形成与所述薄膜晶 体管的漏极连接并延伸至所述滤光层上的第三电极层；
在完成上述步骤的基底上， 形成平坦化层， 并在所述滤光层 上的第三电极层上方形成贯穿平坦化层的接触过孔；
在完成上述步骤的基底上， 通过构图工艺形成包括像素电极 的图形， 且所述像素电极通过贯穿所述平坦化层的所述接触过孔 与所述第三电极层连接。
7. 根据权利要求 6所述的阵列基板的制备方法，其特征在于， 所述滤光层包括彩色滤光片和黑矩阵， 所述像素电极形成在所述 彩色滤光片上方， 所述黑矩阵至少形成在所述薄膜晶体管上方， 所述彩色滤光片和所述黑矩阵在所述基底上间隔设置， 并且
所述第三电极层延伸至所述彩色滤光片上， 或者
所述第三电极层延伸至所述黑矩阵上。
8. 根据权利要求 7所述的阵列基板的制备方法，其特征在于， 所述制备方法还包括步骤：
在所述像素电极上形成钝化层； 以及
在所述钝化层上， 通过构图工艺形成包括公共电极的图形。
9.根据权利要求 7所述的阵列基板的制备方法，其特征在于， 所述制备方法在所述形成平坦化层之后、 在所述滤光层上的第三 电极层上方形成贯穿平坦化层的接触过孔之前还包括步骤：
在所述平坦化层上通过构图工艺形成包括公共电极的图形； 以及
在所述公共电极上形成钝化层，
其中在所述滤光层上的第三电极层上方形成的贯穿平坦化层 的接触过孔还贯穿所述钝化层。
10. 一种显示装置， 其特征在于， 包括权利要求 1~5 中任意 一项所述的阵列基板。
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