WO2015089951A1 - 制备准soi源漏场效应晶体管器件的方法 - Google Patents

制备准soi源漏场效应晶体管器件的方法 Download PDF

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WO2015089951A1
WO2015089951A1 PCT/CN2014/074360 CN2014074360W WO2015089951A1 WO 2015089951 A1 WO2015089951 A1 WO 2015089951A1 CN 2014074360 W CN2014074360 W CN 2014074360W WO 2015089951 A1 WO2015089951 A1 WO 2015089951A1
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source
drain
layer
gate
quasi
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PCT/CN2014/074360
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English (en)
French (fr)
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黄如
樊捷闻
黎明
杨远程
宣浩然
吴汉明
卜伟海
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北京大学
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Priority to US14/787,261 priority Critical patent/US9349588B2/en
Publication of WO2015089951A1 publication Critical patent/WO2015089951A1/zh

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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/0843—Source or drain regions of field-effect devices
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Definitions

  • the present invention relates to a method of fabricating a quasi-SOI source drain field effect transistor device, and is a field of ultra-large scale integrated circuit fabrication technology. Background technique
  • the quasi-SOI source-drain device can reduce the leakage current and reduce the power consumption of the device, which has gradually attracted widespread attention.
  • the existing preparatory processes for quasi-SOI source and drain devices are mostly limited to silicon substrate materials, and cannot be well extended to high mobility semiconductor substrates such as germanium and tri-five materials; moreover, existing fabrication processes pass heat. Oxidation forms a quasi-SOI isolation layer with a high thermal budget, and the preparation process is relatively complicated and cannot be well applied to large-scale integrated manufacturing. Summary of the invention
  • the present invention provides a method for fabricating a quasi-SOI source drain field effect transistor device for a high performance, low power ultra-short trench device.
  • the solution can be easily integrated into the process flow with a small thermal budget that can be applied to semiconductor materials including germanium, germanium, silicon, and tri-five.
  • CVD chemical vapor deposition
  • CMP chemical mechanical polishing
  • step II uses the front gate process, directly enter the step ring; if the back gate process is used, it will serve as the gate of the dummy gate sacrificial layer
  • the stacked structure is removed, and the deposition of the high-k metal gate is performed again, firstly, the dummy gate sacrificial layer is removed by wet etching, and then the gate dielectric layer having a high dielectric constant is newly formed by atomic layer deposition (ALD), and then Re-forming the gate material layer by atomic layer deposition or physical vapor deposition physical vapor deposition (PVD), and finally planarizing the gate material layer by chemical mechanical polishing; VIII.
  • ALD atomic layer deposition
  • PVD physical vapor deposition physical vapor deposition
  • the first semiconductor material is a group IV semiconductor material or a tri-five semiconductor material, wherein: the group of semiconductor materials is silicon, germanium or germanium silicon.
  • the three or five semiconductor materials are gallium arsenide or indium arsenide.
  • the isolation technique in the above step I of the method for preparing a quasi-SOI source drain field effect transistor device is field oxide oxidation isolation (LOCOS isolation), the material is an oxide of a substrate formed by field oxide oxidation; or the isolation technique is shallow trench isolation.
  • LOC isolation field oxide oxidation isolation
  • the material is a shallow trench backfill spacer material, specifically silicon oxide or silicon nitride deposited by chemical vapor deposition.
  • the gate stack structure in the step II of the method for preparing a quasi-SOI source drain field effect transistor device is left to the last true gate; the gate stack structure is a dummy gate and finally removed as a sacrificial layer, and the redeposition is high.
  • the material of the gate dielectric layer is an oxide or oxynitride of a substrate material formed by oxidation and subsequent annealing, or a high dielectric constant dielectric material deposited by atomic layer deposition techniques Or a mixture of an oxide or oxynitride of the substrate material and a high dielectric constant dielectric material;
  • the gate material layer is polysilicon formed by chemical vapor deposition, or by atomic layer deposition or physical vapor deposition
  • the implantation technique for forming the doping structure of the source/drain extension region is a beam line ion implantation technique, a plasma doping technique, or a monolayer deposition.
  • Doping technique; the material of the first sidewall of the two sides of the gate stack may be silicon nitride, formed by CVD and anisotropic dry etching.
  • the recessed source/drain structure is silicon nitride, formed by CVD and anisotropic dry etching.
  • U-shaped recess source/drain structure U-shaped recess source/drain structure, ⁇ -shaped recess source/drain structure or S-type recess source/drain structure, wherein: U-shaped recess source/drain structure is formed by anisotropic dry etching of the first semiconductor substrate material, etching depth The HI; ⁇ -type recessed source-drain structure is based on the U-shaped recess source-drain structure, and the first semiconductor substrate is anisotropically wet-etched using TMAH etching solution, and the etching depth is H2, and H2 is larger than HI.
  • the S-shaped recessed source-drain structure is based on the source-drain structure of the U-shaped recess.
  • a second layer of sidewalls having a width L2 is formed by CVD and anisotropic dry etching, and the material of the second layer of sidewall spacers Different from the material of the first side wall and having an anisotropic dry etching selectivity ratio of 1:5 or more to the first semiconductor material, secondly etching the first semiconductor substrate by isotropic dry etching, longitudinal etching
  • the depth is H3, the lateral etching width is L3, L3 is formed larger than L2, and the second layer side wall is removed by isotropic wet etching.
  • the etch depth of the source-drain structure of the U-shaped recess is ⁇ 1, and the etch depth of the source-drain structure of the ⁇ -shaped recess is
  • the etch depth of the source-drain structure of the H1+H2, S-type recess is H1+H3, and the height H4 of the quasi-SOI source-drain isolation layer is smaller than the etch depth of the recessed source-drain structure, so that the recessed source/drain extension has a window reserved.
  • the subsequent epitaxial process can be performed to form source-drain contacts.
  • the source-drain extension region in the source-drain structure of the sag-shaped recess can be better wrapped by the subsequently formed quasi-SOI source-drain isolation material with less leakage current; if the source is formed by subsequent epitaxy
  • the drain is made of a second semiconductor material, and the germanium-shaped recessed source/drain structure can better conduct the stress generated by the epitaxial second semiconductor material source and drain to the first semiconductor material channel, and has higher mobility.
  • the source-drain extension region in the S-shaped recessed source-drain structure can be better wrapped by the subsequently formed quasi-SOI source-drain isolation material with less leakage current.
  • the material of the quasi-SOI source/drain isolation layer is different from the material of the first layer sidewall spacer, and silicon oxide or alumina having better thermal conductivity may be selected.
  • the material of the in situ doped epitaxial semiconductor is the same as or different from the material of the first semiconductor, and the epitaxial second semiconductor material is doped in situ to form a CMOS. Source and drain, P-type doping of PMOS or N-type doping of MOS.
  • the annealing is activated in a variety of ways, including furnace annealing, rapid thermal annealing, blaze annealing, laser annealing, or a variety of methods.
  • the combination If the material of the epitaxially doped second semiconductor is different from the material of the first semiconductor, the difference in lattice size between different semiconductors may be utilized to generate stress and improve the mobility of the channel of the first semiconductor material, such as a PMOS for silicon.
  • SiGe source and drain are used, and SiC source and drain are used for the NMOS of silicon.
  • the technical solution for preparing a quasi-SOI source drain silicon field effect transistor device comprises the following steps:
  • HDPCVD high density plasma chemical vapor deposition
  • source-drain extension regions are doped by implantation techniques;
  • LPCVD low pressure chemical vapor deposition
  • the first layer of alumina is etched by isotropic wet etching to form a quasi-SOI source-drain isolation layer, the thickness of the isolation layer is H4, and the source-drain structure of the depression is a U-shaped source-drain structure, H4 ⁇ H1; Leakage structure is ⁇ Source-drain structure of type depression, H4 ⁇ H1+H2; For the source-drain structure of the depression, the source-drain structure of S-shaped depression, H4 ⁇ H1 +
  • H3 The purpose is to leave the active drain extension window, and then the epitaxial process can be used to form the source-drain contact.
  • the present invention provides a method for fabricating a quasi-SOI source drain field effect transistor device for a high performance, low power ultra-short trench device.
  • the solution is compatible with traditional CMOS processes, can be easily integrated into the process flow, and has a small thermal budget. It can be applied to semiconductor materials including germanium, germanium silicon and tri-five families other than silicon. There is a large-scale integrated circuit manufacturing.
  • FIG. 1 is a process of depositing a first layer of silicon nitride as a CMP during formation of an active region of the device.
  • FIG. 1 is a process of depositing a first layer of silicon nitride as a CMP during formation of an active region of the device.
  • FIG. 2 is a schematic view showing the structure of a device after etching a first layer of nitride, a first layer of silicon oxide, and a silicon substrate to form an STI trench during formation of an active region of the device.
  • Figure 3 is a schematic view showing the structure of the device after wet etching to remove the first layer of silicon nitride and the first layer of silicon oxide during the formation of the active region of the device.
  • 4 is a schematic view showing the structure of the device after depositing the gate stack material and the gate hard mask material.
  • Fig. 5 is a schematic view showing the structure of a device after forming a gate stacked structure.
  • Fig. 6 is a schematic view showing the structure of a device after forming a doping of source-drain extension regions and forming a first layer spacer on both sides of the gate stack structure.
  • FIG. 7 is a schematic view showing the structure of a device after forming a U-shaped recessed source/drain structure.
  • FIG. 8 is a schematic view showing the structure of a device after forming a germanium-type recessed source/drain structure.
  • FIG. 9 is a schematic view showing the structure of a device after forming a second layer sidewall in the process of forming an S-type recess source/drain structure.
  • FIG. 10 is a schematic view showing the structure of a device after forming an S-type recessed source/drain structure.
  • FIG. 11 is a schematic view showing the structure of the device after removing the second layer sidewall in the process of forming the S-type recess source/drain structure.
  • FIG. 12 is a schematic view showing the structure of a device after forming a quasi-SOI source/drain isolation layer on a U-shaped recess source/drain structure.
  • FIG. 13 is a schematic view showing the structure of a device after a quasi-SOI source/drain isolation layer is formed on a germanium-type recess source/drain structure.
  • 14 is a schematic view showing the structure of a device after forming a quasi-SOI source/drain isolation layer on an S-type recess source/drain structure.
  • FIG. 15 is a schematic view showing the structure of the device after in-situ doping of the epitaxial source and drain and annealing.
  • Figure 16 is a schematic view showing the structure of a device for planarizing a sixth layer of silicon oxide, a second layer of silicon nitride, and a third layer of silicon nitride by CMP during the process of redepositing a high-k metal gate.
  • Figure 17 is a schematic view showing the structure of the device after the dummy gate is removed in the process of re-depositing the high-k metal gate.
  • Figure 18 is a schematic view showing the structure of the device after reforming the high-k metal gate.
  • Figure 19 is a schematic view showing the structure of a device after forming a contact and a metal interconnection.
  • FIG. 1 to Figure 19 1 - silicon substrate; 2 first layer of silicon oxide (silicon nitride buffer layer); 3 first layer of silicon nitride (CMP stop layer); 4 STI slot; 5 - Two-layer silicon oxide (STI trench backfill buffer layer) and third layer silicon oxide (STI Slot backfill material); 6—fourth layer silicon oxide (pseudo gate dielectric layer); 7—first layer polysilicon (pseudo gate material layer); 8- second layer silicon nitride (gate hard mask layer); Three layers of silicon nitride (first layer side wall); 10 U-shaped recess source/drain structure; 11 ⁇ -shaped recess source-drain structure; 12 fifth layer silicon oxide (second layer side wall); 13-S-type recess source and drain Structure; 14 first layer of alumina (quasi-SOI source and drain isolation layer); 15 - P type silicon germanium source and drain; 16 - sixth layer of silicon oxide; 17 - silicon oxide interface layer; 18 - yttrium
  • FIG. 20 is an illustration of the materials used. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • the present invention will be described in detail below by way of specific embodiments with reference to the accompanying drawings, in which a process scheme for preparing a quasi-S0I source-drain silicon field effect transistor device proposed by the present invention is specifically provided, but the scope of the present invention is not limited in any way.
  • the specific implementation steps of preparing a quasi-S0I source-drain silicon field effect transistor device using a back gate process using silicon as a substrate are as follows:
  • Forming an active region of the device by using STI isolation technology 1. Forming a first layer of silicon oxide 2 of 200 A on the silicon substrate 1 by thermal oxidation as a buffer layer of silicon nitride;
  • the third layer of silicon oxide 6 is planarized by CMP, and stopped on the first layer of silicon nitride 3. 7.
  • the first layer of silicon nitride 3 of 600A is removed by isotropic wet etching at 170 ° C by concentrated phosphoric acid solution.
  • the first layer of silicon oxide 2 of 200 A was removed by a room temperature isotropic wet etching of a hydrofluoric acid solution, as shown in FIG. Second, depositing a gate dielectric layer and a gate material layer, and forming a gate stack structure of the device by photolithography etching technology: 8. Forming a 50A fourth layer of silicon oxide 6 on the silicon substrate 1 by thermal oxidation as a dummy gate dielectric layer;
  • the source-drain extension region is implanted with a conventional beam-line ion implantation technique, with a dose of lel5cm-2, an energy of 5keV, and an angle of 0°.
  • the recessed source-drain structure may be formed as a U-shaped recess source/drain structure, a germanium-type recess source/drain structure or an S-type recess source/drain structure: 15.
  • the thickness of the isolation layer is H4, for the source-drain structure of the U-shaped depression, H4 ⁇ H1, as shown in Figure 12; for the source-drain structure of the sag-type depression, H4 ⁇ H1 + H2, as shown 13; For the S-type recess source-drain structure, H4 ⁇ H1 + H3, as shown in FIG.
  • the temperature is 1200 ° C, the time is lms;
  • the initial temperature and the termination temperature are both 400 ° C, the peak temperature is 900 ° C, the rising temperature is 200 ° C / s, and the falling temperature is 150 ° C / s, as shown in Figure 15; 7. If a back gate process is used (instead of the gate process), the previous dummy gate is removed and the deposition of the high-k metal gate is repeated:
  • the sixth layer of silicon oxide 16, the second layer of silicon nitride 8 and the third layer of silicon nitride 9 are planarized by CMP, and stopped on the first layer of polysilicon 7, that is, the dummy gate material layer, as shown in FIG. 27.
  • the first layer of polysilicon 7 of 1000A, that is, the dummy gate material layer, is removed by isotropic wet etching of TMAH solution;
  • the first metal gate 20 is planarized by CMP and stopped on the sixth layer of silicon oxide 16, as shown in FIG. 8. Forming contacts and metal interconnections:

Abstract

提供一种制备准绝缘体上硅（SOI）源漏场效应晶体管器件的方法，包括如下步骤：形成器件的有源区；形成器件的栅叠层结构；形成源漏延伸区的掺杂，并在栅叠层两侧形成第一层侧墙（9）；形成凹陷的源漏结构；形成准SOI源漏隔离层（14）；原位掺杂外延第二半导体材料源漏（15），并进行退火激活；若采用后栅工艺则去掉之前的假栅，重新进行高k金属栅的淀积；形成接触和金属互联（21）。所述方法能很好地与现有互补金属氧化物半导体（CMOS）工艺兼容，具有工艺简单、热预算较小的特点，相比传统的场效应晶体管，依据所述方法制备的准SOI源漏场效应晶体管器件能有效降低泄漏电流，减小器件的功耗。

Description

制备准 SOI源漏场效应晶体管器件的方法 相关申请的交叉引用
本申请要求于 2013年 12月 18日提交的中国专利申请 （201310697719.0) 的优 先权， 其全部内容通过引用合并于此。 技术领域 本发明涉及一种制备准 SOI源漏场效应晶体管器件的方法， 属于超大规模集成 电路制造技术领域。 背景技术
当今半导体制造业在摩尔定律的指导下迅速发展， 在不断提高集成电路的性能 和集成密度的同时， 需要尽可能的减小功耗。制备高性能， 低功耗的超短沟器件是未 来半导体制造业的焦点。当进入到 22纳米技术节点以后，为了克服上述问题，准 SOI 源漏器件能够很好地减小泄漏电流，降低器件功耗，因而逐渐引起广泛的关注。但是， 现有的准 SOI源漏器件制备工艺大多限制在硅衬底材料上，不能很好地拓展到锗、三 五族材料等高迁移率半导体衬底上；而且，现有制备工艺通过热氧化形成准 SOI隔离 层，具有较高的热预算，且制备工艺比较复杂，不能很好的应用到大规模集成制造中。 发明内容
本发明针对高性能， 低功耗的超短沟器件， 提供了一种制备准 SOI源漏场效应 晶体管器件的方法。 该方案可以与传统 CMOS工艺兼容， 能够很容易地整合到工艺 流程中， 同时具有较小的热预算， 能够应用到除硅以外的包括锗、锗硅及三五族等半 导体材料。
所述制备准 SOI源漏场效应晶体管器件的方法依次包括如下步骤：
I. 通过隔离技术， 以第一半导体材料为衬底， 在其上形成器件的有源区；
II. 在衬底上依次淀积栅介质层和栅材料层， 采用前栅工艺或后栅工艺形成器件 的栅叠层结构，其中采用前栅工艺形成的栅叠层结构为真栅，采用后栅工艺形成的栅 叠层结构为假栅； III. 通过注入技术形成源漏延伸区的掺杂， 并在栅叠层两侧形成宽度为 L1 的第 一层侧墙；
IV. 形成 U型、 ∑型或 S型凹陷源漏结构；
V. 通过化学气相淀积技术 （CVD) 淀积准 SOI源漏隔离层， 再通过化学机械抛 光技术 （CMP) 平坦化所述准 SOI源漏隔离层， 停止在栅材料层上， 然后通过各向 异性干法刻蚀回刻或者各向同性湿法腐蚀回漂所述准 SOI源漏隔离层，在凹陷源漏结 构的上面形成厚度为 H4的准 SOI源漏隔离层，其中所述准 SOI源漏隔离层的材料与 第一层侧墙的材料不同；
VI. 原位掺杂外延第二半导体材料， 形成源漏， 进行退火激活； VII. 若步骤 II采用前栅工艺， 直接进入步骤環； 若采用后栅工艺， 则将作为假 栅牺牲层的栅叠层结构去掉， 重新进行高 k金属栅的淀积， 具体为首先通过湿法腐蚀 去掉假栅牺牲层，其次通过原子层淀积（ALD)重新形成具有高介电常数的栅介质层， 然后通过原子层淀积或者物理气相淀积物理气相淀积（PVD)重新形成栅材料层， 最 后通过化学机械抛光技术平坦化栅材料层； VIII. 形成接触和金属互联， 完成准 SOI源漏硅场效应晶体管器件的制备。 上述制备准 SOI源漏场效应晶体管器件的方法的步骤 I中， 所述第一半导体材 料为四族半导体材料或者三五族半导体材料， 其中： 所述四族半导体材料为硅、锗或 锗硅， 所述三五族半导体材料为砷化镓或者砷化铟。 上述制备准 SOI源漏场效应晶体管器件的方法的步骤 I中的隔离技术为场氧氧 化隔离（LOCOS隔离）， 材料为场氧氧化形成的衬底的氧化物； 或者隔离技术为浅沟 槽隔离技术 （STI 隔离）， 材料为浅沟槽回填的隔离材料， 具体是通过化学气相淀积 技术淀积形成的氧化硅或者氮化硅。 在所述制备准 SOI源漏场效应晶体管器件的方法中的步骤 II中的栅叠层结构为 真栅则保留到最后； 栅叠层结构为假栅则最后作为牺牲层去掉， 重新淀积高 k金属栅 叠层；所述栅介质层的材料是通过氧化和后续退火形成的衬底材料的氧化物或氮氧化 合物， 或者是通过原子层淀积技术淀积形成的高介电常数介质材料， 或者是衬底材料 的氧化物或氮氧化合物与高介电常数介质材料的混合物；所述栅材料层是通过化学气 相淀积技术形成的多晶硅， 或者是通过原子层淀积或物理气相淀积形成的导电材料， 所述导电材料为氮化钛、 氮化钽、 钛或铝。 所述制备准 SOI源漏场效应晶体管器件的方法中的步骤 III中， 形成源漏延伸区 的掺杂结构采用的注入技术为束线离子注入技术、等离子体掺杂技术或者单分子层淀 积掺杂技术； 所述栅叠层两侧的第一层侧墙的材料可为氮化硅， 通过 CVD和各向异 性干法刻蚀而形成。 所述制备准 SOI源漏场效应晶体管器件的方法中的步骤 IV中， 凹陷源漏结构为
U型凹陷源漏结构、 ∑型凹陷源漏结构或者 S型凹陷源漏结构， 其中： U型凹陷源漏 结构是通过各向异性干法刻蚀第一半导体衬底材料而形成， 刻蚀深度为 HI ; ∑型凹 陷源漏结构是在所述 U型凹陷源漏结构的基础上继续使用 TMAH腐蚀液采用各向异 性湿法腐蚀第一半导体衬底， 腐蚀深度为 H2， H2 大于 HI而形成； S型凹陷源漏结 构是在所述 U型凹陷源漏结构的基础上， 首先通过 CVD和各向异性干法刻蚀形成宽 度为 L2的第二层侧墙， 第二层侧墙的材料与第一层侧墙的材料不同且其对第一半导 体材料具有 1 :5以上的各向异性干法刻蚀选择比， 其次通过各向同性干法刻蚀第一半 导体衬底， 纵向刻蚀深度为 H3， 横向刻蚀宽度为 L3， L3大于 L2而形成， 同时通过 各向同性湿法腐蚀去掉第二层侧墙。 所述 U 型凹陷源漏结构的刻蚀深度为 Η1， ∑ 型凹陷源漏结构的刻蚀深度为
H1+H2, S型凹陷源漏结构的刻蚀深度为 H1+H3 , 所述准 SOI源漏隔离层高度 H4均 小于凹陷源漏结构的刻蚀深度， 使得凹陷源漏延伸区预留有窗口，后续能够进行外延 工艺形成源漏接触。 相比 U型凹陷源漏结构， ∑形凹陷源漏结构中的源漏延伸区能够更好地被后续 形成的准 SOI源漏隔离材料包裹，具有更小的泄漏电流；如果后续外延形成的源漏采 用第二半导体材料，∑形凹陷源漏结构能够更好地将外延第二半导体材料源漏产生的 应力传导到第一半导体材料沟道， 具有更高的迁移率。 相比 U 型凹陷源漏结构， S 形凹陷源漏结构中的源漏延伸区能够更好地被后续形成的准 SOI源漏隔离材料包裹， 具有更小的泄漏电流。 所述制备准 SOI源漏场效应晶体管器件的方法中的步骤 V中， 准 SOI源漏隔离 层的材料与第一层侧墙的材料不同， 可选氧化硅或具有更好导热性的氧化铝。 所述制备准 SOI源漏场效应晶体管器件的方法中的步骤 VI中， 原位掺杂外延第 二半导体的材料与第一半导体的材料相同或者不同，原位掺杂外延第二半导体材料形 成 CMOS源漏， 可对 PMOS进行 P型掺杂或者对 MOS进行 N型掺杂。 所述退火 激活方式为多种， 包括炉退火、 快速热退火、 闪耀退火、 激光退火或者其中多种方式 的组合。 如果原位掺杂外延第二半导体的材料与第一半导体的材料不同， 可利用不同半 导体之间晶格大小的不同， 产生应力， 提高第一半导体材料沟道的迁移率， 如对硅的 PMOS采用 SiGe源漏， 对硅的 NMOS采用 SiC源漏。 以硅衬底为例， 本发明制备准 SOI源漏硅场效应晶体管器件的技术方案包括如 下步骤：
A. 利用 STI隔离技术形成器件的有源区：
( a) 通过热氧化在硅衬底上形成第一层氧化硅， 作为氮化硅的缓冲层；
(b) 通过低压化学气相淀积 （LPCVD) 在第一层氧化硅上淀积第一层氮化硅， 作为 CMP的停止层；
( c) 通过光刻和各向异性干法刻蚀第一层氮化硅、 第一层氧化硅和硅衬底， 形 成 STI槽；
( d)通过热氧化在 STI槽里面形成第二层氧化硅（Oxide Liner), 作为 STI回填 缓冲层；
( e) 通过高密度等离子体化学气相淀积 （HDPCVD) 形成第三层氧化硅， 作为
STI槽回填材料；
( 0 通过 CMP平坦化第三层氧化硅， 停止在第一层氮化硅上；
(g) 通过各向同性湿法腐蚀去掉第一层氮化硅和第一层氧化硅。
B. 淀积栅介质层和栅材料层， 并通过光刻刻蚀技术形成器件的栅叠层结构： ( a) 通过热氧化在硅衬底上形成第四层氧化硅， 作为假栅介质层；
(b) 通过低压化学气相淀积 （LPCVD) 第一层多晶硅， 作为假栅材料层；
( c) 通过低压化学气相淀积 （LPCVD) 第二层氮化硅， 作为栅硬掩膜层；
( d) 通过光刻和各向异性干法刻蚀第二层氮化硅、 第一层多晶硅和第四层氧化 硅， 形成栅叠层结构。 C. 形成源漏延伸区的掺杂， 并在栅叠层两侧形成侧墙：
( a) 源漏延伸区通过注入技术， 形成掺杂； (b)通过低压化学气相淀积 （LPCVD) 形成第三层氮化硅， 作为第一层侧墙材 料， 淀积厚度为 L1 ;
(c)通过各向异性干法刻蚀第三层氮化硅， 形成栅叠层结构两侧的第一层侧墙， 第一层侧墙的宽度为 Ll。 D. 形成 U型凹陷源漏结构、 ∑型凹陷源漏结构或者 S型凹陷源漏结构， 其中， 形成 U型凹陷源漏结构：
(a) 各向异性干法刻蚀硅衬底， 刻蚀深度为 Hl， 形成 U型凹陷源漏结构。 形成∑型凹陷源漏结构：
(a) 通过各向异性干法刻蚀硅衬底， 刻蚀深度为 HI ; (b) 通过各向异性湿法腐蚀硅衬底， 腐蚀深度为 H2， H2 > H1 , 形成∑型凹陷 源漏结构。
形成 S型凹陷源漏结构：
(a) 通过各向异性干法刻蚀硅衬底， 刻蚀深度为 HI ;
(b) 通过 LPCVD淀积第五层氧化硅， 作为第二层侧墙材料， 淀积厚度为 L2; (c) 通过各向异性干法刻蚀第五层氧化硅， 形成保护源漏延伸区不被后续各向 同性干法刻蚀工艺去除的第二层侧墙， 第二层侧墙的宽度为 L2;
(d)通过各向同性干法刻蚀硅衬底， 纵向刻蚀深度为 H3， 横向刻蚀宽度为 L3， L3 > L2, 形成 S型凹陷源漏结构；
(e) 通过各向同性湿法腐蚀去除第五层氧化硅 （第二层侧墙）。 E. 在凹陷源漏结构的上面形成准 SOI源漏隔离层：
(a) 通过 LPCVD形成第一层氧化铝， 作为准 SOI源漏隔离层材料；
(b) 通过 CMP平坦化第一层氧化铝， 停止在第二层氮化硅上 （栅硬掩膜层）；
(c) 通过各向异性干法刻蚀第一层氧化铝， 停止在第三层氧化硅 （STI氧化硅） 上；
(d) 通过各向同性湿法腐蚀第一层氧化铝， 形成准 SOI源漏隔离层， 隔离层厚 度为 H4， 对于凹陷源漏结构为 U型凹陷源漏结构， H4 < H1 ; 对于凹陷源漏结构为∑ 型凹陷源漏结构， H4<H1+H2; 对于凹陷源漏结构为 S型凹陷源漏结构， H4<H1 +
H3; 目的是留有源漏延伸区窗口， 后续能够进行外延工艺形成源漏接触。
F. 原位掺杂外延源漏， 退火激活
(a) 通过之前预留的源漏延伸区外延窗口， 原位掺杂外延 P型锗硅源漏； (b) 通过激光退火和快速热退火， 激活杂质。
G. 去掉之前作为假栅的栅叠层结构， 重新进行高 k金属栅的淀积：
(a) 通过 LPCVD淀积第六层氧化硅， 作为第零隔离介质层；
(b)通过 CMP平坦化第六层氧化硅、第二层氮化硅和第三层氮化硅， 停止在第 一层多晶硅 （栅材料层） 上； (c) 通过各向同性湿法腐蚀去除第一层多晶硅 （假栅材料层）；
(d)通过各向同性湿法腐蚀去除第四层氧化硅 （假栅介质层）；
(e)通过原位蒸汽氧化形成界面层；
(f)通过 ALD形成第一层高介电常数介质 （真栅介质层）；
(g)通过 ALD形成第一层金属功函数 （真栅功函数调节层）； (h)通过 PVD形成第一层金属栅 （真栅材料层）；
(i)通过 CMP平坦化第一层金属栅， 停止在第六层氧化硅上；
H. 形成接触和金属互联， 完成准 SOI源漏硅场效应晶体管器件的制备。 本发明具有以下技术效果： 本发明针对高性能、 低功耗的超短沟器件， 提供了一种制备准 SOI源漏场效应 晶体管器件的方法。 该方案可以与传统 CMOS工艺兼容， 能够很容易地整合到工艺 流程中， 同时具有较小的热预算， 能够应用到除硅以外的包括锗、锗硅及三五族等半 导体材料； 有利于应有到大规模集成电路制造中。 附图说明
图 1~19为本发明制备 SOI源漏硅场效应晶体管器件的具体实施流程中形成的器 件结构示意图， 其中： 图 1为形成器件的有源区过程中淀积第一层氮化硅作为 CMP停止层的器件示意 图。
图 2为形成器件的有源区过程中刻蚀第一层氮化、 第一层氧化硅和硅衬底形成 STI槽之后的器件结构示意图。 图 3为形成器件的有源区过程中湿法腐蚀去掉第一层氮化硅和第一层氧化硅之 后的器件结构示意图。 图 4为淀积栅叠层材料和栅硬掩膜材料之后的器件结构示意图。 图 5为形成栅叠层结构之后的器件结构示意图。 图 6为形成源漏延伸区的掺杂并在栅叠层结构两侧形成第一层侧墙之后的器件 结构示意图。
图 7为形成 U型凹陷源漏结构之后的器件结构示意图。 图 8为形成∑型凹陷源漏结构之后的器件结构示意图。 图 9为形成 S型凹陷源漏结构过程中形成第二层侧墙之后的器件结构示意图。 图 10为形成 S型凹陷源漏结构之后的器件结构示意图。 图 11为形成 S型凹陷源漏结构过程中去除第二层侧墙之后的器件结构示意图。 图 12为在 U型凹陷源漏结构上形成准 SOI源漏隔离层之后的器件结构示意图。 图 13为在∑型凹陷源漏结构上形成准 SOI源漏隔离层之后的器件结构示意图。 图 14为在 S型凹陷源漏结构上形成准 SOI源漏隔离层之后的器件结构示意图。 图 15为原位掺杂外延源漏并退火激活后的器件结构示意图。 图 16为重新淀积高 k金属栅的过程中通过 CMP平坦化第六层氧化硅、 第二层 氮化硅和第三层氮化硅， 停止在第一层多晶硅上的器件结构示意图。 图 17为重新淀积高 k金属栅的过程中去除假栅之后的器件结构示意图。 图 18为重新形成高 k金属栅之后的器件结构示意图。 图 19为形成接触和金属互联之后的器件结构示意图。 在图 1〜图 19中： 1一硅衬底； 2 第一层氧化硅 （氮化硅的缓冲层）； 3 第一层氮化硅 （CMP 的 停止层）； 4 STI槽； 5—第二层氧化硅 （STI槽回填缓冲层） 和第三层氧化硅 （STI 槽回填材料）； 6—第四层氧化硅（假栅介质层）； 7—第一层多晶硅（假栅材料层）； 8- 第二层氮化硅 （栅硬掩膜层）； 9 第三层氮化硅 （第一层侧墙）； 10 U型凹陷源漏 结构； 11 ∑型凹陷源漏结构； 12 第五层氧化硅（第二层侧墙）； 13— S型凹陷源漏 结构； 14 第一层氧化铝 （准 SOI源漏隔离层）； 15— P型锗硅源漏； 16—第六层氧 化硅； 17—氧化硅界面层； 18—氧化铪层 （真栅介质层）； 19一氮化钛层 （真栅功函 数调节层）； 20—铝层 （真栅材料层）； 21 铝材料 （形成接触和金属互联）。 图 20为所用材料的说明。 具体实施方式 下面结合附图， 通过具体实施例详细说明本发明， 具体给出实现本发明提出的 制备准 S0I源漏硅场效应晶体管器件的一个工艺方案，但不以任何方式限制本发明的 范围。 以硅为衬底采用后栅工艺制备准 S0I源漏硅场效应晶体管器件的具体实施步骤 如下：
一、 利用 STI隔离技术形成器件的有源区： 1. 通过热氧化在硅衬底 1上形成 200A的第一层氧化硅 2，作为氮化硅的缓冲层；
2. 在第一层氧化硅 2上通过 LPCVD形成 600A的第一层氮化硅 3， 作为 CMP 停止层， 如图 1所示；
3. 通过光刻和各向异性干法刻蚀 600A的第一层氮化硅 3、 200A的第一层氧化 硅 2和 5000A的硅衬底 1， 形成 STI槽 4， 如图 2所示； 4. 通过热氧化在 STI槽 4里面形成 100A的第二层氧化硅 5， 作为 STI回填缓冲 层；
5. 通过高密度等离子体化学气相淀积（HDPCVD)形成 8000 A的第三层氧化硅 6， 作为 STI槽回填材料；
6. 通过 CMP平坦化第三层氧化硅 6， 停止在第一层氮化硅 3上； 7. 通过浓磷酸溶液 170°C各向同性湿法腐蚀去掉 600A的第一层氮化硅 3和通过 氢氟酸溶液室温各向同性湿法腐蚀去掉 200A的第一层氧化硅 2， 如图 3所示。 二、 淀积栅介质层和栅材料层， 并通过光刻刻蚀技术形成器件的栅叠层结构： 8. 通过热氧化在硅衬底 1上形成 50A的第四层氧化硅 6， 作为假栅介质层；
9. 通过 LPCVD形成 1000A的第一层多晶硅 7， 作为假栅材料层；
10. 通过 LPCVD形成 500A的第二层氮化硅 8， 作为栅硬掩膜层， 如图 4所示；
11. 通过光刻和各向异性干法刻蚀 500 A的第二层氮化硅 8、 1000A的第一层多 晶硅 7和 50A的第四层氧化硅 6， 形成栅叠层结构， 栅长为 30nm， 如图 5所示。 三、 形成源漏延伸区的掺杂， 并在栅叠层两侧形成侧墙：
12. 源漏延伸区通过传统束线离子注入技术， 注 As, 剂量为 lel5cm-2， 能量为 5keV, 角度为 0°， 形成掺杂；
13. 通过 LPCVD 形成第三层氮化硅 9， 作为第一层侧墙材料， 淀积厚度为 L1=300A;
14. 通过各向异性干法刻蚀 300A的第三层氮化硅 9， 形成栅叠层结构两侧的第 一层侧墙， 侧墙宽度 L1=300A， 如图 6所示； 四、形成凹陷源漏结构， 可以形成为 U型凹陷源漏结构、∑型凹陷源漏结构或者 S型凹陷源漏结构： 15. 通过各向异性干法刻蚀硅衬底 1， 刻蚀深度为 H1=300A， 形成 U型凹陷源漏 结构 10， 如图 7所示；
16. 也可形成∑型凹陷源漏结构：
(a) 通过各向异性干法刻蚀硅衬底 1， 刻蚀深度为 H1=300A;
(b) 通过各向异性湿法腐蚀硅衬底 1， 腐蚀深度为 H2=500A， 满足 H2 > H1， 形成∑型凹陷源漏结构 11， 如图 8所示；
17. 或者形成 S型凹陷源漏结构：
(a) 通过各向异性干法刻蚀硅衬底 1， 刻蚀深度为 H1=300A;
(b) 通过 LPCVD形成 300A的第五层氧化硅 12， 作为第二层侧墙材料；
(c) 通过各向异性干法刻蚀 300A的第五层氧化硅 12， 形成保护源漏延伸区不 被后续各向同性干法刻蚀工艺去除的第二层侧墙， 侧墙宽度为 L2=300A， 如图 9所 示；
(d) 通过各向同性干法刻蚀硅衬底 1， 纵向刻蚀深度为 Η3=50θΑ， 横向刻蚀宽 度为 L3=600A， 满足 L3 > L2， 形成 S型凹陷源漏结构 13， 如图 10所示；
(e) 通过氢氟酸溶液各向同性湿法腐蚀去除 300A的第五层氧化硅 12， 也即第 二层侧墙， 如图 11所示； 五、 在凹陷源漏的上面形成准 SOI源漏隔离层： 18. 通过 LPCVD形成 5000A的第一层氧化铝 14， 作为准 SOI源漏隔离层材料；
19. 通过 CMP平坦化第一层氧化铝 14， 停止在第二层氮化硅 8上， 也即栅硬掩 膜层；
20. 通过各向异性干法刻蚀 1550A的第一层氧化铝 14， 停止在第三层氧化硅 5 上， 也即 STI氧化硅上； 21. 通过盐酸溶液各向同性湿法腐蚀 200A 的第一层氧化铝 14， 腐蚀深度小于
HI , 形成准 SOI源漏隔离层， 隔离层厚度为 H4， 对于 U型凹陷源漏结构， H4 < H1， 如图 12所示； 对于∑型凹陷源漏结构， H4 < H1 + H2， 如图 13所示； 对于 S型凹陷 源漏结构， H4 < H1 + H3， 如图 14所示。 六、 原位掺杂外延源漏， 退火激活： 22. 通过之前预留的源漏延伸区外延窗口， 原位掺杂外延 600A的 P型锗硅源漏
15；
23. 通过激光退火， 温度为 1200°C， 时间为 lms;
24. 通过快速热退火， 起始温度和终止温度均为 400°C， 峰值温度为 900°C， 上 升温度为 200°C/s， 下降温度为 150°C/s， 如图 15所示； 七、 如采用的是后栅工艺 （代替栅工艺）， 去掉之前的假栅， 重新进行高 k金属 栅的淀积：
25. 通过 LPCVD形成 5000A的第六层氧化硅 16， 作为第零隔离介质层；
26. 通过 CMP平坦化第六层氧化硅 16， 第二层氮化硅 8和第三层氮化硅 9， 停 止在第一层多晶硅 7上， 也即假栅材料层， 如图 16所示； 27. 通过 TMAH溶液各向同性湿法腐蚀去除 1000A的第一层多晶硅 7， 也即假 栅材料层；
28. 通过氢氟酸溶液各向同性湿法腐蚀去除 50A的第四层氧化硅 6， 也即假栅介 质层， 如图 17所示；
29. 通过原位蒸汽氧化形成 10A的氧化硅界面层 17;
30. 通过 ALD第一层高介电常数介质， 形成 20A的氧化铪层 18， 也即真栅介质 层；
31. 通过 ALD第一层金属功函数， 形成 50A的氮化钛层 19， 也即真栅功函数调 节层；
32. 通过 PVD第一层金属栅 20， 形成 2000A的铝层 20; 也即真栅材料层；
33. 通过 CMP平坦化第一层金属栅 20， 停止在第六层氧化硅 16上， 如图 18所 示。 八、 形成接触和金属互联：
34. 形成接触和金属互联 21，完成准 SOI源漏硅场效应晶体管器件的制备，如图 19所示。 上面描述的实施例并非用于限定本发明， 任何本领域的技术人员， 在不脱离本 发明的精神和范围内，可做各种的更动和润饰， 因此本发明的保护范围视权利要求范 围所界定。

Claims

权 利 要 求
1. 一种制备准 S0I源漏场效应晶体管器件的方法， 其特征在于， 包括如下 步骤：
1 ) 通过隔离技术， 以第一半导体材料为衬底， 在其上形成器件的有源区； 2) 在衬底上依次淀积栅介质层和栅材料层， 采用前栅工艺或后栅工艺形成 器件的栅叠层结构， 其中采用前栅工艺形成的栅叠层结构为真栅， 采用后栅工艺 形成的栅叠层结构为假栅；
3 ) 通过注入技术形成源漏延伸区的掺杂， 并在栅叠层两侧形成宽度为 L1 的第一层侧墙；
4) 形成 U型、 ∑型或 S型凹陷源漏结构；
5 ) 通过化学气相淀积技术淀积准 SOI源漏隔离层， 再通过化学机械抛光技 术平坦化所述准 SOI源漏隔离层，停止在栅材料层上，然后通过各向异性干法刻 蚀回刻或者各向同性湿法腐蚀回漂所述准 SOI源漏隔离层，在凹陷源漏结构的上 面形成厚度为 H4的准 SOI源漏隔离层，其中所述准 SOI源漏隔离层的材料与第 一层侧墙的材料不同；
6) 原位掺杂外延第二半导体材料， 形成源漏， 进行退火激活；
7) 若步骤 2) 采用前栅工艺， 直接进入步骤 8); 若采用后栅工艺， 则将作 为假栅牺牲层的栅叠层结构去掉， 重新进行高 k金属栅的淀积， 具体为首先通过 湿法腐蚀去掉假栅牺牲层，其次通过原子层淀积重新形成具有高介电常数的栅介 质层， 然后通过原子层淀积或者物理气相淀积物理气相淀积重新形成栅材料层， 最后通过化学机械抛光技术平坦化栅材料层；
8) 形成接触和金属互联， 完成准 SOI源漏硅场效应晶体管器件的制备。
2. 如权利要求 1所述制备准 SOI源漏场效应晶体管器件的方法， 其特征在 于， 所述第一半导体材料为四族半导体材料或者三五族半导体材料， 其中： 所述 四族半导体材料为硅、 锗或锗硅， 所述三五族半导体材料为砷化镓或者砷化铟。
3. 如权利要求 1所述制备准 SOI源漏场效应晶体管器件的方法， 其特征在 于， 所述步骤 1 ) 中的隔离技术为场氧氧化隔离， 材料为场氧氧化形成的衬底的 氧化物； 或者隔离技术为 STI隔离， 材料为浅沟槽回填的隔离材料， 具体是通过 化学气相淀积技术淀积形成的氧化硅或者氮化硅。
4. 如权利要求 1所述制备准 SOI源漏场效应晶体管器件的方法， 其特征在 于， 在所述步骤 2) 中的栅叠层结构为真栅则保留到最后； 栅叠层结构为假栅则 最后作为牺牲层去掉， 重新淀积高 k金属栅叠层； 所述栅介质层的材料是通过氧 化和后续退火形成的衬底材料的氧化物或氮氧化合物，或者是通过原子层淀积技 术淀积形成的高介电常数介质材料，或者是衬底材料的氧化物或氮氧化合物与高 介电常数介质材料的混合物；所述栅材料层是通过化学气相淀积技术形成的多晶 硅， 或者是通过原子层淀积或物理气相淀积形成的导电材料， 所述导电材料为氮 化钛、 氮化钽、 钛或铝。
5. 如权利要求 1所述的制备准 SOI源漏场效应晶体管器件的方法， 其特征 在于， 所述步骤 3 )形成源漏延伸区的掺杂结构采用的注入技术为束线离子注入 技术、等离子体掺杂技术或者单分子层淀积掺杂技术； 所述栅叠层两侧的第一层 侧墙的材料为氮化硅， 通过化学气相淀积技术和各向异性干法刻蚀而形成。
6. 如权利要求 1所述的制备准 SOI源漏场效应晶体管器件的方法， 其特征 在于， 所述步骤 4)中的凹陷源漏结构为 U型、∑型或 S型凹陷源漏结构， 其中： U型凹陷源漏结构是通过各向异性干法刻蚀衬底材料而形成，刻蚀深度为 HI ;∑ 型凹陷源漏结构是在所述 U型凹陷源漏结构的基础上继续使用 TMAH腐蚀液采 用各向异性湿法腐蚀衬底， 腐蚀深度为 H2， H2 大于 HI而形成； S型凹陷源漏 结构是在所述 U型凹陷源漏结构的基础上， 首先通过化学气相淀积技术和各向 异性干法刻蚀形成宽度为 L2的第二层侧墙， 第二层侧墙的材料与第一层侧墙的 材料不同且其对第一半导体材料具有 1 :5以上的各向异性干法刻蚀选择比， 其次 通过各向同性干法刻蚀衬底， 纵向刻蚀深度为 H3， 横向刻蚀宽度为 L3， L3大 于 L2而形成， 同时通过各向同性湿法腐蚀去掉第二层侧墙。
7. 如权利要求 1或权利要求 6所述的制备准 SOI源漏场效应晶体管器件的 方法， 其特征在于， 所述 U型凹陷源漏结构的刻蚀深度为 Η1， ∑型凹陷源漏结 构的刻蚀深度为 H1+H2, S型凹陷源漏结构的刻蚀深度为 H1+H3 , 所述准 SOI 源漏隔离层高度 H4均小于凹陷源漏结构的刻蚀深度， 使得凹陷源漏延伸区预留 有窗口。
8. 如权利要求 1所述的制备准 SOI源漏场效应晶体管器件的方法， 其特征 在于， 所述步骤 5 ) 中准 SOI源漏隔离层的材料是氧化硅或氧化铝。
9. 如权利要求 1所述的制备准 SOI源漏场效应晶体管器件的方法， 其特征 在于， 步骤 6) 中所述的第二半导体材料与步骤 1 ) 中所述的第一半导体材料相 同或者不同； 所述原位掺杂外延第二半导体材料形成 CMOS源漏对 PMOS进行 P型掺杂或者对 MOS进行 N型掺杂； 当第一半导体材料为硅时， 对 PMOS采 用锗硅源漏， 对 MOS采用碳硅源漏。
10. 如权利要求 1所述的制备准 SOI源漏场效应晶体管器件的方法， 其特征 在于， 所述步骤 6) 中的退火激活方式选自下列方式中的一种或多种： 炉退火、 快速热退火、 闪耀退火和激光退火。
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