WO2014153942A1 - 制备源漏准soi多栅结构器件的方法 - Google Patents

制备源漏准soi多栅结构器件的方法 Download PDF

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Publication number
WO2014153942A1
WO2014153942A1 PCT/CN2013/084743 CN2013084743W WO2014153942A1 WO 2014153942 A1 WO2014153942 A1 WO 2014153942A1 CN 2013084743 W CN2013084743 W CN 2013084743W WO 2014153942 A1 WO2014153942 A1 WO 2014153942A1
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Prior art keywords
silicon oxide
source
layer
silicon
drain
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PCT/CN2013/084743
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English (en)
French (fr)
Inventor
黎明
樊捷闻
李佳
许晓燕
黄如
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北京大学
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Priority to US14/764,155 priority Critical patent/US9356124B2/en
Publication of WO2014153942A1 publication Critical patent/WO2014153942A1/zh

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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2

Definitions

  • the invention relates to a method for preparing a source-drained quasi-multi-gate structure device, and belongs to the technical field of ultra-large scale integrated circuit manufacturing. Background technique
  • the object of the present invention is to provide a method for preparing a source-drained quasi-SOI multi-gate structure device in view of the difficulty of a multi-gate structure device still having a large leakage current at a short trench length.
  • This solution can be implemented in a process compatible with traditional bulk silicon CMOS, can be easily integrated into the process flow, and can still maintain a small leakage current under a short channel length condition, thereby reducing the power consumption of the device. .
  • the technical solution for preparing a source-drain quasi-SOI multi-gate structure device includes the following steps:
  • a) Forming an active region in the shape of a Fin strip The main purpose of this step is to form a thin stripe (Fin strip shape) pattern structure on the hard mask by photolithography. i. depositing a layer of silicon oxide (200 A in thickness) and a layer of silicon nitride (50 ⁇ ⁇ ) on the surface of the silicon wafer. As a hard mask material.
  • Ii. Define a thin strip of Fin strip structure by lithography. Iii. Transfer the pattern to the hard mask by dry etching.
  • STI material i. Deposit a thick layer of silicon oxide (more than 1000 A above the height of the Fin strip) as the STI material.
  • CMP Chemical Mechanical Polishing
  • Iv. By dry etching, the silicon oxide in the STI region is etched back to form an STI. v. Perform well implant and well anneal. Vi. Perform substrate parasitic transistor suppression implant and annealing.
  • Ii. Deposit a thicker polysilicon (more than 1000 A above the height of the Fin strip) as a gate material layer. Iii. Plan the polysilicon by CMP chemistry and stop at a certain height on top of the Fin strip. Iv. Deposit a layer of silicon oxide (thickness 30 ⁇ ) as a hard mask layer for the gate lines. v. Photolithographic etching to form hard mask lines and gate lines.
  • Ii Perform the implantation of the source and drain extension regions and anneal.
  • Iii. A further layer of ( ⁇ ) silicon oxide is deposited and dry etched back to form a silicon oxide sidewall.
  • Ii Deposit a layer of (150A) silicon nitride and dry etch it back to form a silicon nitride sidewall.
  • the sidewalls are only outside the sidewalls of the silicon oxide, and the silicon nitride in the recesses of the source and drain regions between the STIs must be completely removed.
  • the anisotropic dry etching etches the silicon in the groove of the source and drain regions to a certain depth (20-30 nm).
  • Wet oxidation forms silicon oxide in the grooves of the source and drain regions as a quasi-S0I isolation layer.
  • High k means high dielectric constant material
  • Metal gate structure The main purpose of this step is to form a high-k metal gate structure by dummy gate and dummy gate dielectric removal and backfilling of the corresponding high-k metal gate material.
  • i. Deposit a layer of (4000A) silicon oxide as the dielectric layer.
  • Ii. CMP silicon oxide and stop on the polysilicon surface to planarize the silicon oxide and polysilicon surfaces.
  • Iii. Wet etching removes the polysilicon dummy gate material.
  • Atomic layer deposition forms a silicon oxide transition layer and a high-k gate dielectric Hf0 2 .
  • Vi. Atomic layer deposition forms a metal work function adjustment layer TiN.
  • the invention has the following technical effects:
  • the solution can be implemented in a process compatible with traditional bulk silicon CMOS, can be easily integrated into the process flow, and can still maintain a small leakage current under a short channel length condition, thereby reducing the power consumption of the device. . DRAWINGS
  • Figure 1 is a schematic view showing the structure of a device after forming a Fin strip.
  • Fig. 2 is a schematic view showing the structure of a device after isolation of silicon oxide by CMP.
  • FIG. 3 is a schematic view showing the structure of the device after forming the isolation region and the active region.
  • FIG. 4 is a schematic view showing the structure of a device after forming a dummy gate.
  • Figure 5 is a schematic diagram of the structure of the device after forming the Offset and the sidewall spacers.
  • Fig. 6 is a schematic view showing the structure of the device after the grooves are formed between the source and drain regions STI.
  • Figure 7 is a schematic view showing the structure of the device after forming a silicon nitride sidewall.
  • Figure 8 is a cross-sectional view in the AA direction of Figure 7.
  • Figure 9 is a cross-sectional view taken along the line BB in Figure 7.
  • Figure 10 is a schematic view showing the structure of the device after another anisotropic dry etching.
  • Figure 11 is a cross-sectional view in the AA direction of Figure 10.
  • Figure 12 is a cross-sectional view taken along line BB of Figure 1.
  • Figure 13 is a schematic view showing the structure of the device after wet oxidation has formed a quasi-SOI in the source and drain regions.
  • Figure 14 is a cross-sectional view taken along line AA of Figure 13;
  • Figure 15 is a cross-sectional view taken along the line BB in Figure 13 .
  • Figure 16 is a schematic view showing the structure of the device after wet etching to remove the silicon nitride sidewall.
  • Figure 17 is a cross-sectional view taken along line AA of Figure 16.
  • FIG. 18 is a cross-sectional view taken along line BB of Figure 16.
  • FIG. 19 is a schematic view showing the structure of a device after epitaxial single crystal silicon forms an elevated source and drain.
  • FIG. 20 is a schematic view showing the structure of a device after the dielectric layer silicon oxide is subjected to CMP.
  • 21 is a schematic view showing the structure of a device after forming a high-k metal gate.
  • Figure 22 is a description of the materials used. detailed description
  • An n-type tri-gate field effect transistor having a Fin strip width of about 10 nm, a height of 30 nm, and a channel length of about 25 nm was prepared according to the following procedure:
  • Optical lithography defines a Fin strip with a Fin strip width of 20 nm
  • CMP chemical mechanical polishing planarizes the polysilicon and stops on the silicon nitride hard mask layer, as shown in Figure 2;
  • RTP rapid thermal annealing
  • Substrate parasitic transistor suppression injection Note B, implantation energy is 8keV, injection inclination is 0 degree, injection dose is lel3cm- 2
  • Parasitic transistor suppression injection activation laser annealing, 1100 degrees, 1 nanosecond; 18. HF solution for silicon surface treatment;
  • Optical lithography defines a gate line having a gate line width of 25 nm, that is, a physical gate length of 25 nm;
  • Source-drain extension region injection Note As, injection energy is 5keV, injection inclination angle is 20 degrees, injection dose is lel5cm" 2 , divided into two injections;
  • FIG. 7 Anisotropic dry etching 250A silicon nitride, forming sidewalls, and exposing silicon in the source and drain regions, as shown in FIG. 7, the cross-sectional view in the AA direction in FIG. 7 is as shown in FIG. The cross-sectional view in the BB direction of 7 is shown in Fig. 9;
  • the anisotropic dry etching 100 A silicon as shown in FIG. 10, the cross-sectional view in the AA direction in FIG. 10 is as shown in FIG. 11, and the cross-sectional view in the BB direction in FIG. 10 is as shown in FIG. ;
  • FIG. 35 Wet oxidation forms 200 A of silicon oxide inside the groove of the source and drain regions, as shown in Fig. 13, a cross-sectional view in the direction of AA in Fig. 13 is shown in Fig. 14, and a cross-sectional view in the direction of BB in Fig. 13 As shown in FIG. 15; 36. Isotropic wet etching of 150A silicon nitride by hot phosphoric acid solution, as shown in FIG. 16, a cross-sectional view in the AA direction of FIG. 16 is shown in FIG. 17, and FIG. 16 is in the BB direction. The cross-sectional view is shown in Figure 18; 37.
  • the in-situ doped epitaxial single-crystal silicon forming a highly doped source and drain lifting, epitaxial thickness 50 ⁇ , doping concentration le20cm_ 3.
  • the shape of the epitaxial single crystal silicon lifted source and drain is related to the crystal plane of the silicon wafer and the crystal orientation of the channel.
  • Source and drain region injection Note As, the implantation energy is 10keV, the injection inclination angle is 0 degree, and the implantation dose is 2el5cm" 2 ;
  • the doping dose is lel5cm_ 2 ;
  • Atomic layer deposition 100 A silicon oxide
  • Atomic layer deposition 20 A yttrium oxide
  • the source and drain forms a contact hole and a metal contact

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Abstract

提供了一种制备源漏准SOI多栅结构器件的方法，包括：形成Fin条形状的有源区；形成STI氧化隔离层；形成多晶硅假栅结构；形成源漏延伸区结构；形成源漏准SOI结构；形成高k金属栅结构。所述方法可以通过与传统体硅CMOS兼容的工艺方法实现，能够很容易地整合到工艺流程中，并且在较短沟道长度条件下，仍然能够保持较小的泄漏电流，从而降低器件的功耗。

Description

制备源漏准 SOI多栅结构器件的方法 技术领域
本发明涉及一种制备源漏准 soi多栅结构器件的方法， 属于超大规模集成电路 制造技术领域。 背景技术
当今半导体制造业在摩尔定律的指导下迅速发展， 不断提高集成电路的性能和 集成密度， 同时需要尽可能的减小功耗。 制备高性能， 低功耗的超短沟器件是未来半 导体制造业的焦点。 当进入到 22纳米技术节点以后， 传统平面场效应晶体管由于日 益严重的短沟道效应导致泄漏电流不断增加， 不能满足半导体制造的发展。为了克服 上述问题， 多栅结构器件由于其优秀的栅控性能和输运特性，在克服短沟道效应的同 时提高单位面积的驱动电流密度， 因而逐渐引起广泛的关注。
虽然由于多栅结构器件本身的特殊几何结构， 使得其拥有出色的栅控性能， 然 而， 当沟道尺寸缩小到一定程度之后， 仍然会有较大的泄漏电流， 这会严重影响到器 件的功耗。使用 SOI衬底可以减小泄漏电流，但是由于较高的成本和与原来体硅工艺 的差异， 因此， 很少应用到大规模集成电路制造中。 发明内容
本发明的目的在于针对多栅结构器件在短沟长时仍然有较大泄漏电流的困难， 提供了一种制备源漏准 SOI多栅结构器件的方法。该方案可以通过与传统体硅 CMOS 兼容的工艺方法实现，能够很容易地整合到工艺流程中，并且在较短沟道长度条件下， 仍然能够保持较小的泄漏电流， 从而降低器件的功耗。 以三栅结构 （本发明所述方法可以适用于双栅器件和三栅器件） 器件为例， 本 发明制备源漏准 SOI多栅结构器件的技术方案包括如下步骤：
a) 形成 Fin条形状的有源区 该步骤主要目的是利用光刻在硬掩膜上形成细条状 （Fin条形状） 的图形结构。 i. 在硅片表面淀积一层氧化硅 （厚度为 200 A) 和一层氮化硅 （厚度为 50θ Α)， 作为硬掩膜材料。
ii. 通过光刻定义细条状的 Fin条图形结构。 iii. 通过干法刻蚀， 将图形转移到硬掩膜上。
iv. 利用硬掩膜， 将图形转移到硅片上， 并去掉光刻胶。
b) 形成 STI ( Shallow Trench Isolation， 浅沟道隔离） 氧化隔离层 该步骤主要目的是在有源区四周形成 STI氧化隔离层。
i. 淀积一层较厚 （超过 Fin条高度 1000 A以上的） 的氧化硅， 作为 STI材料。 ii. CMP (化学机械抛光） 氧化硅， 并停止在氮化硅表面， 并且使得氮化硅、 氧 化硅表面平坦化。
iii. 通过湿法腐蚀， 去掉氮化硅硬掩膜。
iv. 通过干法刻蚀， 回刻 STI区域的氧化硅， 形成 STI。 v. 进行阱注入和阱退火。 vi. 进行衬底寄生晶体管抑制注入和退火。
C) 形成多晶硅假栅结构 该步骤主要目的是利用牺牲侧墙来减小凹槽的宽度， 然后通过回填多晶硅， 形成 超窄线宽的多晶硅假栅线条。 i. 干氧氧化形成氧化硅， 作为假栅介质层。
ii. 淀积较厚的 （超过 Fin条高度 1000 A以上的） 多晶硅， 作为栅材料层。 iii. 通过 CMP化学将多晶硅平坦化， 停止在 Fin条顶部一定高度处。 iv. 淀积一层氧化硅 （厚度为 30θΑ)， 作为栅线条的硬掩膜层。 v. 光刻刻蚀， 形成硬掩膜线条和栅线条。
d) 形成源漏延伸区结构 该步骤主要目的是形成多栅结构器件的源漏。
i. 淀积一层很薄 （50A) 的氧化硅， 作为 Offset材料。
ii. 进行源漏延伸区的注入， 并退火。 iii. 再淀积一层 （ΙΟθΑ) 氧化硅， 并进行干法刻蚀回刻， 形成氧化硅侧墙。 e) 形成源漏准 SOI结构 i. 刻蚀源漏区域的硅， 停止在 STI表面以下。
ii. 淀积一层 （150A) 氮化硅， 并进行干法刻蚀回刻， 形成氮化硅侧墙。 该侧墙 只是在氧化硅侧墙外面， 而必须将 STI之间源漏区域凹槽内的氮化硅完全去除。 iii. 再一次各项异性干法刻蚀源漏区域凹槽内的硅， 至一定深度 （20-30nm)。 iv. 湿法氧化在源漏区域凹槽内形成氧化硅， 作为准 S0I隔离层。
v. 湿法腐蚀去掉氮化硅侧墙。 vi. 原位掺杂外延单晶硅， 形成高掺杂的抬升源漏。
vii.进行源漏区的注入， 并退火。
f) 形成高 k (高 k表示高介电常数的材料） 金属栅结构 该步骤主要目的是通过假栅和假栅介质去除以及相应高 k金属栅材料的回填，形 成高 k金属栅结构。 i. 淀积一层 （4000A) 氧化硅作为介质层。 ii. CMP氧化硅， 并停止在多晶硅表面， 使得氧化硅和多晶硅表面平坦化。 iii.湿法腐蚀去掉多晶硅假栅材料。
iv. 湿法腐蚀去掉氧化硅假栅介质。
v. 原子层淀积形成氧化硅过渡层和高 k栅介质 Hf02。 vi. 原子层淀积形成金属功函数调节层 TiN。
vii.物理汽相淀积形成金属栅材料 Al。
viii. CMP金属栅材料 Al， 并停止在氧化硅表面， 使得氧化硅和 A1表面平坦 化。 ix. 光刻刻蚀形成接触孔。
X. 形成金属接触并合金。
本发明具有如下技术效果： 该方案可以通过与传统体硅 CMOS兼容的工艺方法实现， 能够很容易的整合到 工艺流程中， 并且在较短沟道长度条件下， 仍然能够保持较小的泄漏电流， 从而降低 器件的功耗。 附图说明
图 1为形成 Fin条之后的器件结构示意图。 图 2为用来隔离的氧化硅经过 CMP之后的器件结构示意图。 图 3为形成隔离区和有源区之后的器件结构示意图。
图 4为形成假栅之后的器件结构示意图。
图 5为形成 Offset和侧墙之后的器件结构示意图。
图 6为源漏区域 STI之间形成凹槽之后的器件结构示意图。 图 7为形成氮化硅侧墙之后的器件结构示意图。
图 8为图 7中 AA方向上的截面图。 图 9为图 7中 BB方向上的截面图。 图 10为再一次各向异性干法刻蚀之后的器件结构示意图。
图 11为图 10中 AA方向上的截面图。
图 12为图 1中 BB方向上的截面图。 图 13为湿法氧化在源漏区域形成准 SOI之后的器件结构示意图。
图 14为图 13中 AA方向上的截面图。 图 15为图 13中 BB方向上的截面图。 图 16为湿法腐蚀去掉氮化硅侧墙之后的器件结构示意图。
图 17为图 16中 AA方向上的截面图。
图 18为图 16中 BB方向上的截面图。 图 19为外延单晶硅形成抬升源漏之后的器件结构示意图。 图 20为介质层氧化硅经过 CMP之后的器件结构示意图。 图 21为形成高 k金属栅之后的器件结构示意图。 图 22为所用材料说明。 具体实施方式
下面结合具体实施例对本发明进行详细说明， 具体给出一实现本发明提出的制 备超短沟道多栅结构器件的工艺方案， 并以三栅结构器件为例，但不以任何方式限制 本发明的范围。
根据下列步骤制备 Fin条宽度约为 10纳米， 高度为 30纳米， 沟道长度约为 25 纳米的 n型三栅场效应晶体管：
1. 在硅衬底上低压化学气相沉积氧化硅 200 A;
2. 在氧化硅上低压化学气相沉积氮化硅 500 A;
3. 光学光刻定义 Fin条， Fin条宽度为 20nm;
4. 各项异性干法刻蚀 500A氮化硅；
5. 各向异性干法刻蚀 200A氧化硅；
6. 各向异性干法刻蚀 3000A硅衬底， 如图 1所示；
7. 去掉光刻胶；
8. 在硅衬底上低压化学气相淀积氧化硅 5000A;
9. CMP化学机械研磨将多晶硅平坦化，停止在氮化硅硬掩膜层上，如图 2所示；
10.热磷酸溶液各向同性湿法腐蚀 500A氮化硅；
11.各向异性干法刻蚀 1000A氧化硅， 露出 300A硅， 作为有源区， 如图 3所示；
12. P阱注入，注 B，注入能量为 100keV，注入倾角为 0度，注入剂量为 lel3cm— 2 13. P阱注入， 注 B， 注入能量为 60keV， 注入倾角为 0度， 注入剂量为 lel3cm— 2
14. P阱注入， 注 B， 注入能量为 20keV， 注入倾角为 0度， 注入剂量为 lel3cm— 2
15.阱驱进， 并激活， RTP (快速热退火） 退火， 1050度， 20秒；
16.衬底寄生晶体管抑制注入， 注 B， 注入能量为 8keV， 注入倾角为 0度， 注入 剂量为 lel3cm-2
17.寄生晶体管抑制注入激活， 激光退火， 1100度， 1纳秒； 18. HF溶液进行硅表面处理；
19.干氧氧化 2θΑ， 作为假栅介质；
20.低压化学气相沉积多晶硅 ιοοοΑ, 作为假栅材料；
21. CMP化学机械研磨将多晶硅平坦化至 Fin条顶端 300 A处； 22.低压化学气相沉积氧化硅 30θΑ， 作为栅线条的硬掩膜材料；
23.光学光刻定义栅线条， 栅线条宽度为 25nm， 即物理栅长为 25nm;
24.各项异性干法刻蚀 300A氧化硅， 形成硬掩膜线条；
25.各项异性干法刻蚀 3000A多晶硅和 20A氧化硅， 形成假栅， 如图 4所示；
26.低压化学气相沉积氧化硅 5θΑ， 作为 Offset材料；
27.源漏延伸区注入， 注 As， 注入能量为 5keV， 注入倾角为 20度， 注入剂量为 lel5cm"2, 分两次注入；
28.源漏延伸区杂质激活， 激光退火， 1100度， 1纳秒；
29.低压化学气相沉积氧化硅 10θΑ， 作为侧墙材料；
30.各向异性干法刻蚀 150A氧化硅， 形成侧墙， 并使得源漏区域的硅裸露出来， 如图 5所示；
31.各项异性干法刻蚀 400 Α硅， 在源漏区域 STI之间形成凹槽， 如图 6所示；
32.低压化学气相沉积氮化硅 15θΑ， 作为侧墙材料；
33.各向异性干法刻蚀 250A氮化硅， 形成侧墙， 并使得源漏区域的硅裸露出来， 如图 7所示， 图 7中 AA方向上的截面图如图 8所示， 图 7中 BB方向上的截面图如 图 9所示；
34.再一次各项异性干法刻蚀 100 A硅， 如图 10所示， 图 10中 AA方向上的截 面图如图 11所示， 图 10中 BB方向上的截面图如图 12所示；
35.湿法氧化在源漏区域的凹槽内部形成 200 A的氧化硅， 如图 13所示， 图 13 中 AA方向上的截面图如图 14所示， 图 13中 BB方向上的截面图如图 15所示； 36.热磷酸溶液各向同性湿法腐蚀 150A氮化硅， 如图 16所示， 图 16中 AA方向 上的截面图如图 17所示， 图 16中 BB方向上的截面图如图 18所示； 37.原位掺杂外延单晶硅， 形成高掺杂的抬升源漏， 外延厚度为 50θΑ， 掺杂浓度 为 le20cm_3。 外延单晶硅抬升源漏的形状与硅片的晶面和沟道的晶向有关， 这里取
( 100) 晶面上 <100>晶向的器件为例， 如图 19所示；
38.源漏区注入， 注 As， 注入能量为 10keV， 注入倾角为 0 度， 注入剂量为 2el5cm"2 ;
39.源漏区杂质激活， 激光退火， 1100度， 1纳秒；
40.低压化学气相淀积氧化硅 ΙΟΟθΑ, 作为介质层；
41. CMP化学机械研磨将氧化硅平坦化， 停止在多晶硅层上， 如图 20所示；
42. TMAH溶液各向同性湿法腐蚀 400A多晶硅；
43. HF溶液各项同性湿法腐蚀 20A氧化硅；
44.通过等离子体杂质掺杂技术， 硅外延原位掺杂技术或者单分子层掺杂技术实 现沟道表面高掺杂， 掺杂剂量为 lel5cm_2;
45.原子层淀积 100 A氧化硅；
46.沟道区杂质激活， 激光退火， 1100度， 1纳秒； 47. HF溶液各项同性湿法腐蚀 100A氧化硅；
48.原子层淀积 8 A氧化硅；
49.原子层淀积 20 A氧化铪；
50.原子层淀积 50A氮化钛；
51.物理溅射淀积 500A铝； CMP化学机械研磨将铝平坦化， 停止在氧化硅层上， 如图 21所示；
52.源漏形成接触孔和金属接触；
53.合金； 上面描述的实施例并非用于限定本发明， 任何本领域的技术人员， 在不脱离本 发明的精神和范围内，可做各种的更动和润饰， 因此本发明的保护范围视权利要求范 围所界定。

Claims

权 利 要 求
1. 一种制备源漏准 SOI多栅结构器件的方法， 其特征是， 包括如下步骤: 1) 形成 Fin条形状的有源区， 包括：
1.1 在硅片表面淀积一层氧化硅和一层氮化硅， 作为硬掩膜材料; 1.2 通过光刻定义细条状的 Fin条图形结构；
1.3 通过干法刻蚀， 将图形转移到硬掩膜上；
1.4 利用硬掩膜， 将图形转移到硅片上， 并去掉光刻胶；
2) 形成 STI氧化隔离层， 包括:
2.1 淀积一层氧化硅， 作为 STI材料；
2.2 CMP氧化硅， 并停止在氮化硅表面， 并且使得氮化硅、 氧化硅表面 平坦化
2.3 通过湿法腐蚀， 去掉氮化硅硬掩膜；
2.4 通过干法刻蚀， 回刻 STI区域的氧化硅， 形成 STI;
2.5 进行阱注入和阱退火；
2.6 进行衬底寄生晶体管抑制注入和退火；
3) 形成多晶硅假栅结构， 包括:
3.1 干氧氧化形成氧化硅， 作为假栅介质层；
3.2 淀积一层多晶硅， 作为栅材料层；
3.3 通过 CMP化学将多晶硅平坦化， 停止在 Fin条顶部一定高度处; 3.4 淀积一层氧化硅， 作为栅线条的硬掩膜层；
3.5 光刻刻蚀， 形成硬掩膜线条和栅线条；
4) 形成源漏延伸区结构， 包括:
4.1 淀积一层氧化硅， 作为 Offset材料；
4.2 进行源漏延伸区的注入， 并退火；
4.3 再淀积一层氧化硅， 并进行干法刻蚀回刻， 形成氧化硅侧墙; 5) 形成源漏准 SOI结构， 包括:
1 刻蚀源漏区域的硅， 停止在 STI表面以下；
5.2 淀积一层氮化硅， 并进行干法刻蚀回刻， 形成氮化硅侧墙； 该侧墙 只是在氧化硅侧墙外面， 而必须将 STI之间源漏区域凹槽内的氮化硅完全去 除；
.3) 再一次各项异性干法刻蚀源漏区域凹槽内的硅， 至一定深度； .4)湿法氧化在源漏区域凹槽内形成氧化硅， 作为准 S0I隔离层； 湿法腐蚀去掉氮化硅侧墙；
.6) 原位掺杂外延单晶硅， 形成高掺杂的抬升源漏； 进行源漏区的注入， 并退火；
6) 形成高 k金属栅结构， 包括：
6.1) 淀积一层氧化硅作为介质层；
6.2) CMP氧化硅， 并停止在多晶硅表面， 使得氧化硅和多晶硅表面平坦 化;
6.3 湿法腐蚀去掉多晶硅假栅材料；
6.4 湿法腐蚀去掉氧化硅假栅介质；
6.5 原子层淀积形成氧化硅过渡层和高 k栅介质 Hf02 ;
6.6 原子层淀积形成金属功函数调节层 TiN;
6.7 物理汽相淀积形成金属栅材料 A1;
6.8 CMP金属栅材料 Al， 并停止在氧化硅表面， 使得氧化硅和 A1表面 平坦化；
6.9) 光刻刻蚀形成接触孔；
6.10) 形成金属接触并合金。
2. 如权利要求 1所述的制备源漏准 SOI多栅结构器件的方法， 其特征是， 步骤 1.1)中， 氧化硅的厚度为 200 A， 氮化硅的厚度为 500 A。 步骤 3.2)中， 氧化硅的厚度超过 Fin条高度 1000 A以上。
4. 如权利要求 1所述的制备源漏准 SOI多栅结构器件的方法， 其特征是， 步骤 3.4)中， 氧化硅的厚度为 30θΑ。
5. 如权利要求 1所述的制备源漏准 SOI多栅结构器件的方法， 其特征是， 步骤 4.1)中， 氧化硅的厚度为 50A。
6. 如权利要求 1所述的制备源漏准 SOI多栅结构器件的方法， 其特征是， 步骤 4.3)中， 氧化硅的厚度为 10θΑ。
7. 如权利要求 1所述的制备源漏准 SOI多栅结构器件的方法， 其特征是， 步骤 5.2)中， 氮化硅的厚度为 150A。
8. 如权利要求 1所述的制备源漏准 SOI多栅结构器件的方法， 其特征是， 步骤 5.3)中所述深度为 20-30nm。
9. 如权利要求 1所述的制备源漏准 SOI多栅结构器件的方法， 其特征是， 步骤 4.3)中， 氧化硅的厚度为 4000A。
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