TW201434155A - 半導體裝置及其製造方法 - Google Patents
半導體裝置及其製造方法 Download PDFInfo
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- TW201434155A TW201434155A TW102147705A TW102147705A TW201434155A TW 201434155 A TW201434155 A TW 201434155A TW 102147705 A TW102147705 A TW 102147705A TW 102147705 A TW102147705 A TW 102147705A TW 201434155 A TW201434155 A TW 201434155A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
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- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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Abstract
一鰭式場效電晶體(fin field effect transistor、FinFET)的製造方法,包含:形成複數的第一鰭狀物以及複數的第二鰭狀物突出於該基板之上,其中任兩相鄰之第一鰭狀物係被一第一隔離區域所分隔,以及任兩相鄰之第二鰭狀物係被一第二隔離區域所分隔。上述方法更包含對該第一隔離區施以一第一離子植入製程,其中具有一第一極性的摻質被植入該第一隔離區,且對該第二隔離區施以一第二離子植入製程,其中具有一第一極性的摻質被植入該第二隔離區,以及進行一蝕刻製程使該第一隔離區域以及該第二隔離區域凹陷。
Description
本發明係關於半導體裝置,更特別關於具有鰭式場效電晶體結構的半導體裝置。
半導體產業如積體電路的快速成長,係奠基於不同電子元件如電晶體、二極體、電阻、電容、或類似物其積體密度的快速成長。積體密度的改善大部份歸功於最小結構尺寸的持續縮減,這使整合至固定面積的元件數目不斷增加。然而,較小的結構尺寸會傾向導致該較多的漏電流。隨著近來對於具有更小體積電子裝置需求日益增加,降低半導體裝置的漏電流逐漸成為一個重要的課題。
在一互補金氧半導體(complementary metal oxide semiconductor、CMOS)場效電晶體(field effect transistor、FET)中,主動區域包含一汲極、一源極、一通道區位於該汲極以及該源極間、以及一閘極位於該通道區之上(用來控制該通道區的開或關)。當該閘極電壓高於一臨界電壓,一導通的通道區係形成於該汲極以及該源極之間。如此一來,電子或電洞可被允許在該汲極以及源極間移動。換言之,當該閘極電壓小於該臨界電壓時,理論上,該通道區係被係不導通的,且沒有任何
電子或電洞被允許在該汲極以及源極間移動。然而,當半導體裝置在設計上其尺寸逐漸變小,由於短通道區的漏電效應,使得該閘極無法完全控制該通道區,特別是對於距離該閘極較遠的通道區部份。如此一來,當半導體裝置尺寸小於30奈米時,該相對較短長度的閘極(與傳統平面電晶體相比)易使得該閘極不易控制該通道區關閉。
隨著半導體技術的發展,鰭式場效電晶體(fin field
effect transistor、FinFET)已經成為一種有效替代傳統電晶體以進一步降低漏電流的半導體裝置。
在一鰭式場效電晶體(fin field effect transistor、
FinFET)中,一主動區域包含一汲極、一通道區以及一源極突出該半導體基板的表面。該鰭式場效電晶體(fin field effect transistor、FinFET)的主動區域,像是一鰭狀物,由一剖面方向來看係為一長方形。此外,該鰭式場效電晶體(fin field effect transistor、FinFET)的閘極包覆該主動區域的三個側面,其形狀例如像是一個倒置的U。如此一來,該閘極具有較強的通道區控制能力,因此可降低短通道區所造成的漏電流效應。當該鰭式場效電晶體(fin field effect transistor、FinFET)關閉時,該閘極仍可有效控制該通道區,以降低漏電流。
該鰭式場效電晶體(fin field effect transistor、
FinFET)之鰭狀物形成方式可包含對一基板施以一部份移除製程以形成凹槽;填入介電材料於該凹槽中;進行一化學機械研磨製程移除位於該鰭狀物之上的介電材料;以及,移除該介電材料的上表面,使得殘留的該介電材料在該凹槽中形成淺溝槽
隔離區(STI)。
本發明一實施例提供一種半導體裝置,包括:一第一鰭式場效電晶體、及一第二鰭式場效電晶體。該第一鰭式場效電晶體包含一第一鰭狀物,其中該第一鰭式場效電晶體(fin field effect transistor、FinFET)具有一第一極性,且該第一鰭狀物係具有一第一高度。該第二鰭式場效電晶體包含一第二鰭狀物,其中:該第二鰭式場效電晶體係具有一第二極性;以及,該第二鰭狀物係具有一第二高度,其中該第一鰭狀物以及該第二鰭狀物係在同一鰭狀物形成步驟中被形成,且該第一高度係與該第二高度不同。
本發明另一實施例提供一種半導體裝置的製造方法,包含:在一基板上形成複數的隔離區域,其中,一第一鰭狀物係被一第一隔離區所圍繞;以及一第二鰭狀物係被一第二隔離區所圍繞。對該第一隔離區施以一第一離子植入製程,其中具有一第一極性的摻質被植入該第一隔離區。對該第二隔離區施以一第二離子植入製程,其中具有一第一極性的摻質被植入該第二隔離區;以及,對該第一隔離區以及該第二隔離區施以一蝕刻製程,以形成該第一鰭狀物之一第一部份、該第一鰭狀物之一第二部份、該第二鰭狀物之一第一部份、以及該第二鰭狀物之一第二部份,其中該第一鰭狀物之該第一部份係在該第一隔離區之一上表面之上、該第二鰭狀物之該第一部份係在該第二隔離區之一上表面之上,且該第一鰭狀物之該第一部份係高於該第二鰭狀物之該第一部份。
本發明又一實施例提供一種半導體裝置的製造方
法,包含:形成複數的第一鰭狀物以及複數的第二鰭狀物突出於該基板之上,其中任兩相鄰之第一鰭狀物係被一第一隔離區域所分隔,且任兩相鄰之第二鰭狀物係被一第二隔離區域所分隔;對該第一隔離區施以一第一離子植入製程,其中具有一第一極性的摻質被植入該第一隔離區;對該第二隔離區施以一第二離子植入製程,其中具有一第一極性的摻質被植入該第二隔離區;以及,進行一蝕刻製程使該第一隔離區域以及該第二隔離區域凹陷。
100‧‧‧鰭式場效電晶體
102‧‧‧基板
104‧‧‧鰭狀物
106‧‧‧第一汲極/源極區
108‧‧‧第二汲極/源極區
110‧‧‧閘極介電層
112‧‧‧閘極
200‧‧‧半導體裝置
202‧‧‧基板
212、214、216、218‧‧‧鰭狀物部份
220‧‧‧開口
302‧‧‧光阻層
304‧‧‧P型摻質
402‧‧‧光阻層
404‧‧‧N型摻質
602‧‧‧虛置閘極介電層
702‧‧‧虛置閘極
802‧‧‧遮罩層
902、906‧‧‧遮罩層
904、908‧‧‧虛置閘極
1004‧‧‧封合間隙壁
1202‧‧‧虛置間隙壁
1302、1304、1306‧‧‧凹槽
1402、1404、1406‧‧‧汲極/源極區域
1602‧‧‧間隙壁
1702、1704、1706‧‧‧汲極/源極區域
1902‧‧‧接觸蝕刻停止層
2002‧‧‧層間介電層
2202、2204‧‧‧開口
2402‧‧‧閘極介電層
2502‧‧‧閘極層
2601、2602、2603、2604、2605、2607、2608、2609、2610、2611、2612、2613、2614、2615、2616、2617、2618、2619、2620、2621、2622、2623、2624‧‧‧步驟
H1、H2、H4、H5‧‧‧高度
H3、H6‧‧‧高度差
X‧‧‧切線
Y‧‧‧切線
第1圖係顯示根據本發明實施例所示之鰭式場效電晶體(fin field effect transistor、FinFET)之立體示意圖;第2A-25A、2B-25B圖係顯示一系列剖面結構示意圖,用以說明根據本發明實施例所示之鰭式場效電晶體(fin field effect transistor、FinFET)的製造流程;以及第26圖係一製造流程圖,用以說明第2A-25A、2B-25B圖所示之步驟。在不同的特徵中所對應之數字和符號,除非另有註記,一般而言視為對應部份。所繪示的特徵清楚地標明了具體實施方式的相關態樣,且其並不一定依比例繪製。
以下以各實施例詳細說明並伴隨著圖式說明之範例,做為本發明之參考依據。且在圖式中,實施例之形狀或是
厚度可擴大,並以簡化或是方便標示。再者,圖式中各元件之部分將以分別描述說明之,值得注意的是,圖中未繪示或描述之元件,為所屬技術領域中具有通常知識者所知的形式,此外,特定之實施例僅為揭示本發明使用之特定方式,其並非用以限定本發明。
本發明一實施例揭露一鰭式場效電晶體(fin field
effect transistor、FinFET)半導體裝置,其中該鰭式場效電晶體(fin field effect transistor、FinFET)半導體裝置具有複數的P型金氧半導體(PMOS)電晶體以及複數的N型金氧半導體(NMOS)電晶體,且該PMOS電晶體以及該NMOS電晶體具有不同的鰭狀物高度。值得注意的是,雖然本發明所述之方法係以一特定順序加以描述,然而該實施例所述之方法包含的步驟可依任何符合邏輯的順序來加以施行。此外,相同的元件符號係用以表示相同的元件。
第1圖係顯示根據本發明實施例所示之鰭式場效
電晶體(fin field effect transistor、FinFET)之立體示意圖。該鰭式場效電晶體(fin field effect transistor、FinFET)100包含一鰭狀物(fin)104,該鰭狀物(fin)104位於一基板102之上。一閘極介電層110包覆該鰭狀物(fin)104的三個側面,其形狀例如像是一個倒置的U。一閘極112形成於該閘極介電層110之上。
該鰭狀物(fin)104包含一第一汲極/源極區106,一
第二汲極/源極區108以及一通道區位於該第一汲極/源極區106以及該第二汲極/源極區108之間。如第1圖所示,該第一汲極/源極區106以及該第二汲極/源極區108係配置於該鰭狀物
(fin)104相對的兩側,即分別位於該閘極介電層110以及該閘極112的兩側。
該閘極介電層110之材質可為氧化物,其形成方式
可為氧化製程,例如濕式或乾式熱氧化法、濺鍍、或化學氣相沉積法(chemical vapor deposition、CVD,例如使用矽酸乙酯(tetra-ethyl-ortho-silicate、TEOS)以及氧氣作為前驅物)。此外,該閘極介電層110可為一高介電常數(high-K)的介電材料(K>10),像是氧化矽、氮氧化矽、氮化矽、氧化物、含氮的氧化物、氧化鋁、氧化鑭、氧化鉿、氧化鋯、氮氧化鉿、或其組合。
該閘極112可包含一導電材料,擇自於以下成份所組成之族群:多晶矽、多晶矽鍺、金屬材料、金屬矽化物材料、金屬氮化物材料、或金屬氧化物材料等。舉例來說,金屬材料可包含鉭、鈦、鉬、鎢、鉑、鋁、鉿、釕、或其組合。金屬矽化物材料包含矽化鈦、矽化鈷、矽化鎳、矽化鉭、或其組合。金屬氮化物材料包含氮化鈦、氮化鉭、氮化鎢、或其組合。金屬氧化物材料包含氧化釕、氧化錫、或其組合。
該閘極112之形成方式可例如為化學氣相沉積法、物理氣相蒸鍍(physical vapor deposition、PVD),電漿輔助化學氣相沉積法(PECVD)、常壓化學氣相沉積法(APCVD)、高密度電漿化學氣相沉積法(HDCVD)、低壓化學氣相沉積法(LPCVD)、原子層沉積法(atomic layer deposition、ALD)等。
第1圖進一步繪示兩不同方向且互相交錯的切線,延該兩不同方向切線的剖面係分別顯示於第2A至25A圖以
及第2B至25B圖。一第一剖面切線X-X係延著該鰭狀物(fin)104之一縱軸方向,舉例來說該方向係為該第一汲極/源極區106以及該第二汲極/源極區108之間的電流流動方向。一第二剖面切線Y-Y係垂直於該第一剖面切線X-X,並跨越該通道區、該閘極介電層110、以及該該鰭式場效電晶體(fin field effect transistor、FinFET)100之閘極112。
第2A-25A、2B-25B圖係一系列剖面結構示意圖,
用以說明本發明實施例所述鰭式場效電晶體(fin field effect transistor、FinFET)之製造方法的各階段。第2A至25B圖中,圖號中具有“A”的圖係為延第1圖所示之第一剖面切線X-X的剖面圖,而圖號中具有“B”的圖係為延第1圖所示之第二剖面切線Y-Y的剖面圖。
第2A以及2B圖係繪示根據本發明實施例所述包含
有四個鰭狀物之半導體裝置的剖面結構示意圖。該半導體裝置200包含四個鰭式場效電晶體(fin field effect transistor、FinFET),其各自由一第一鰭狀物212、一第二鰭狀物214、一第三鰭狀物216、以及一第四鰭狀物218所形成。鰭狀物212、214、216、以及218係形成於一基板202之上。在某些實施例中,由該第一鰭狀物21以及該第二鰭狀物214所形成之該鰭式場效電晶體(fin field effect transistor、FinFET)係為NMOS電晶體。
另一方面,由該第三鰭狀物216以及該第四鰭狀物218所形成之該鰭式場效電晶體(fin field effect transistor、FinFET)係為PMOS電晶體。綜觀本發明,該半導體裝置200包含鰭狀物212以及214的部份可被稱為該半導體裝置200的NMOS部份。同樣
的,該半導體裝置200包含鰭狀物216以及218的部份可被稱為該半導體裝置200的PMOS部份。值得注意的是第2B圖所示之包含四個鰭狀物(例如,鰭狀物212、214、216、以及218)的半導體裝置200,僅為本發明之一例。一本領域具有通常知識者可依據本發明之結構加以修改或變化。舉例來說,該半導體裝置200可依實際應用或設計上的需要改變其鰭狀物的數量。
該基板202之材質可為矽,該基板202亦可包含其
元素,例如碳,鍺、鎵、砷、氮、銦、及/或磷等。該基板202可為一塊狀基板或一絕緣層上覆半導體(semiconductor-on-insulator、SOI)基板。
如第2B圖所示,該鰭狀物212、214、216、以及218
係被該隔離區220所包圍。該隔離區220可為一淺溝槽隔離區(shallow trench isolation、STI)結構。該淺溝槽隔離區(shallow trench isolation、STI)結構(例如,隔離區220)的形成方式可例如為微影蝕刻製程技術。詳細地說,該微影蝕刻製程可包含沉積一普遍使用的光遮材料(像是光阻)於該基板202之上,且該光遮材料露出一預定設計的圖案。接著,依據該圖案對該基板202進行一蝕刻製程,以將光遮材料的圖案轉移到該基板202上,如此一來可形成複數的開口。
該開口接著被填入介電材料以形成該淺溝槽隔離區(shallow trench isolation、STI)結構(例如,隔離區域220)。根據一實施例,該介電材料可例如一氧化物材料、或一高密度電漿(high-density plasma、HDP)氧化物。此外,該介電材料可擇自於以下成份所組成的族群:氧化矽、氮化矽、氮碳化矽、
及碳氮氧化矽。該介電材料的形成方式可為化學氣相沉積法(chemical vapor deposition、CVD)、次常壓化學氣相沈積(sub-atmospheric chemical vapor deposition、SACVD)、或高密度電漿化學氣相沉積法(high-density plasma chemical vapor deposition、HDPCVD)等。接著,對鰭狀物上的介電材料施以一化學機械研磨(chemical mechanical polishing、CMP)製程。
如此一來,該介電材料多餘的部分可以被移除,如第2B圖所示。而餘留的該介電材料部份則構成該隔離區220。
如第2B圖所示,該隔離區220可為一連續的結構,
根據一實施例該隔離區220可形成一隔離環狀結構。此外,該隔離區220可具有兩個互相分離的隔離區域,其中該兩個互相分離的隔離區域具有互相面對的側壁。
第3A及3B圖係為剖面結構示意圖,用以說明形成
一光阻層於第2A以及2B圖所述之該半導體裝置的該PMOS部份上,並對該半導體裝置的該NMOS部份施以一P型植入製程。
該光阻層302係配置於該半導體裝置200的鰭狀物
216以及218之上。換言之,該半導體裝置的該PMOS部份200係被該光阻層302所覆蓋。該光阻層302之材質可例如為聚苯并噁唑(polybenzoxazole、PBO)、SU-8光敏性環氧樹脂(photo-sensitive epoxy)、或膜狀高分子材料等。該光阻層302的形成方式可為旋轉塗佈法。
如第3B圖所示,P型摻質304係植入該半導體裝置
的NMOS部份200之隔離區域220中。該P型摻質304可包含硼、或BF2等。該P型摻質304的植入該隔離區220的劑量係大體上等
於1013cm-3。該硼離子佈植所使用的能量等級可為140KV。換言之,P型摻質的濃度可等於或小於1018cm-3。
在該P型摻質304植入該半導體裝置的該NMOS部
份200後,該光阻層302可被移除(例如以一灰化製程來移除該光阻層)。
第4A及4B圖係為剖面結構示意圖,用以說明形成
一光阻層於第3A及3B圖所示之該半導體裝置的該NMOS部份上,並對該半導體裝置的該PMOS部份施以一N型植入製程。
該光阻層402之材質係相似於第3B圖所述之光阻
層302。如第4B圖所示,N型摻質404係植入該半導體裝置的PMOS部份200之隔離區域220。該N型摻質404包含磷、或砷等。
該N型摻質404植入該隔離區域220之PMOS部份的劑量係大體上等於1013cm-2。該磷離子佈植所使用的等量等級可為10KV。換言之,N型摻質的濃度係等於或小於1018cm-3。
將摻質植入該半導體裝置的NMOS部份及PMOS部
份的隔離區域220(如第3B及4B圖所示步驟)的好處之一在於藉由摻質種類及植入濃度的不同來改變隔離區域220被蝕刻速度。在某些實施例中,被植入P型摻質的隔離區域之被蝕刻速度係大於被植入N型摻質的隔離區域。
在某些實施例中,當對隔離區域(包含被植入P型摻
質的NMOS部份隔離區域(如第3B圖所示)以及被植入N型摻質的PMOS部份隔離區域(如第4B所示)施以一濕蝕刻製程時,蝕刻該被植入N型摻質的隔離區域之速率係約為每分鐘34.7。另一方面,蝕刻該被植入P型摻質的隔離區域之速率係則約為每
分鐘52.8。該蝕刻速率的差異可促進在絕緣凹陷製程中形成具有不同高度的鰭狀物,請參照第5B圖。
在完成第3B及4B圖所示的植入步驟後,可進行一
退火製程來增加N型摻質以及P型摻質的摻雜深度。該退火製程可為一快速熱退火(rapid thermal annealing、RTA)製程、一毫秒退火(millisecond annealing、MSA)製程、或一雷射退火製程等。
在某些實施例中,該退火製程的溫度可介於600到
1300℃之間。舉例來說,可對該隔離區域220施以一快速熱退火製程,該退火製程的溫度可約為1000℃,該退火製程的時間約為10秒。
值得注意的是雖然本發明之第3B及4B圖係顯示對
該半導體裝置200施行一N型植入製程之順序係優先於對該半導體裝置200施行一P型植入製程,但此領域具有通常之知識者可了解該順序僅為本發明之一例,並且可對該等步驟進行調整或改變。舉例來說,對該半導體裝置200施行一N型植入製程的順序可優先於對該半導體裝置200施行一P型植入製程。
第5A及5B圖係為剖面結構示意圖,用以說明對第
4A及4B圖所述之該半導體裝置進行一蝕刻製程。
該隔離區域220係被凹陷化,以致於使得該鰭狀物
212、214、216、以及218突出該隔離區域220的上表面。對該隔離區域220進行凹陷化的步驟可例如為對該隔離區域220進行一選擇性蝕刻製程。舉例來說,該選擇性蝕刻製程可為化學氧化物除去處理(chemical oxide removal、COR,使用Tokyo
Electronic Limited所製的Certas、或Applied Material所製的工具SICONI)。此外,亦可使用濕蝕刻製程,像是使用稀釋後的氫氟酸(dHF)溶液。
在某些實施例中,該化學氧化物除去處理
(chemical oxide removal、COR)的壓力可為160毫托。該製程配方包含HF氣體、氨氣、以及氬氣。在其他實施例中,可使用濕蝕刻製程對該隔離區域220進行凹陷化。所使用的稀釋後的氫氟酸(dHF)溶液包含水及氫氟酸,且水及氫氟酸的重量比為100:1。該濕蝕刻製程的時間可約為30秒。在對隔離區域220進行凹陷化後,該NMOS電晶體(例如,鰭狀物212)所露出的鰭狀物高度、以及該PMOS電晶體(例如,鰭狀物216)所露出的鰭狀物高度可依據實際的需求及應用加以調整及改變。
在某些實施例中,如第5B圖所示,該NMOS電晶
體其露出的鰭狀物(例如,鰭狀物212)係高於該PMOS電晶體其露出的鰭狀物(例如鰭狀物216)。換言之,如第5B圖所示,該鰭狀物212的高度H1係大於該鰭狀物216的高度H2,而該高度H1與該高度H2的高度差係定義為H3。在某些實施例中,高度差H3係等於或大於2nm。
本發明所述具有不同鰭狀物高度差的NMOS電晶
體及PMOS電晶體其好處之一係在於可藉由調整該NMOS電晶體及該PMOS電晶體的鰭狀物高度來控制該該NMOS電晶體及該PMOS電晶體的臨界電壓。
此外,由於本發明所述之具有不同鰭狀物高度差
H3的結構(如第5B圖所示)可藉由一單一蝕刻製程來達成,如此
一來可簡化該鰭式場效電晶體(fin field effect transistor、FinFET)的製造步驟,並降低製造成本。
第6A及6B圖係為剖面結構示意圖,係用以說明形
成一虛置閘極(dummy gate)介電層於第5A及5B圖所述之該半導體裝置中。該虛置閘極(dummy gate)介電層602係形成於該鰭狀物212、214、216、以及218之上。該虛置閘極(dummy gate)介電層602之材質可例如為氧化矽、氮化矽、或其結合。該虛置閘極(dummy gate)介電層602之形成方式可例如為沉積法、或是熱氧化法。
第7A及7B圖係為剖面結構示意圖,用以說明形成
一虛置閘極(dummy gate)於第6A及6B圖所述之該半導體裝置的虛置閘極(dummy gate)介電層之上。該虛置閘極(dummy gate)702之材質可例如為多晶矽。此外,該虛置閘極(dummy gate)702之材質亦可選用與該隔離區域220相比具有高蝕刻選擇性的材料。此外,在形成該虛置閘極(dummy gate)702的過程中,可對後續作為虛置閘極(dummy gate)702的膜層進行一化學機械研磨(chemical mechanical polishing)製程,以獲得第7A及7B圖所示的平坦閘極。
第8A及8B圖係為剖面結構示意圖,用以說明形成
一遮罩層於第7A及7B圖所述該半導體裝置之虛置閘極(dummy gate)之上。該遮罩層802之材質可例如為氮化矽。該遮罩層802可配置於該虛置閘極(dummy gate)之上,且其形成方式可為任何合適之形成方法。
第9A及9B圖係為剖面結構示意圖,用以說明對第
8A及8B圖所述半導體裝置之虛置閘極(dummy gate)施以一蝕刻製程。該虛置閘極(dummy gate)702可藉由一黃光微影蝕刻製程來進行圖案化(配合遮罩層902及906),以形成虛置閘極(dummy gate)904以及908,如第9A圖所示。
第10A及10B圖係為剖面結構示意圖,用以說明形
成複數個封合間隙壁(seal spacer)於第9A及9B圖所示半導體裝置之虛置閘極(dummy gate)的側壁上。
該封合間隙壁(seal spacer)1004之材質可為介電材
料,像是氧化矽、氮化矽、氮氧化矽、或其結合。該封合間隙壁(seal spacer)1004之形成方式可例如為熱氧化法。
第11A及11B圖係為剖面結構示意圖,用以說明形
成淺摻雜汲極/源極(LDD)區域(未繪示)於第10A及10B圖所示之半導體裝置的鰭狀物上。與第3B及4B圖相似,當以N型摻質植入N型鰭狀物(例如,鰭狀物212)時,可形成遮罩層於該半導體裝置200的PMOS部份。在完成N型摻質植入製程後,可將該遮罩層移除。接著,形成遮罩層於該半導體裝置200的NMOS部份,以將P型摻質植入P型鰭狀物(例如,鰭狀物216)中。在完成P型摻質植入製程後,可將該遮罩層移除。接著,可進行一退火製程以增加P型摻質以及該N型摻質的摻雜深度。第12A及12B圖係為剖面結構示意圖,用以說明形成複數的虛置間隙壁(dummy spacer)於第11A及11B圖所述半導體裝置之封合間隙壁(seal spacer)上。
該虛置間隙壁(dummy spacer)1202的形成方式可
例如以原子層沉積法(ALD),低壓化學氣相沉積法(LPCVD)、
或分子層沉積法(molecular layer deposition、MLD)形成一膜層後,在以一合適的蝕刻製程(例如一非等向性蝕刻(anisotropic etching)製程)圖形化,形成該虛置間隙壁(dummy spacer)1202,如第12A圖所示。該虛置間隙壁(dummy spacer)1202之材質可例如為介電材料,像是氮化矽、氮氧化物、碳化矽、或氧化物等。
第13A及13B圖係為剖面結構示意圖,用以說明對
第12A及12B圖所示半導體裝置之鰭狀物施以一蝕刻製程。如第圖所示13A,該鰭狀物(例如,鰭狀物212)之汲極/源極區域預定區域係被蝕刻以形成凹槽1302、1304、以及1306。形成該凹槽1302、1304、以及1306的蝕刻方式可為乾蝕刻、或濕蝕刻。
第14A及14B圖係為剖面結構示意圖,用以說明對
第13A及13B圖所示半導體裝置之鰭狀物施以一磊晶成長製程。在某些實施例中,該汲極/源極區域可為應變(strained)汲極/源極。該應變(strained)汲極/源極區域1402、1404、以及1406可例用磊晶成長形成於該凹槽1302、1304、以及1306中。如第14A圖所示,該應變(strained)汲極/源極區域1402、1404、以及1406之上表面可高該鰭狀物212之上表面。
第15A及15B圖係為剖面結構示意圖,用以說明對
第14A及14B圖所示半導體裝置之虛置間隙壁(dummy spacer)施以一虛置間隙壁(dummy spacer)移除製程。如第15A圖所示,移除該虛置閘極(dummy gate)間隙壁的方式可為一蝕刻製程,例如一乾蝕刻、或濕蝕刻製程。
第16A及16B圖係為剖面結構示意圖,用以說明形
成複數的間隙壁於第15A及15B圖所示半導體裝置之封合間隙壁(seal spacer)上。該間隙壁1602之形成方式可為坦覆性(blanket)沉積一或更多的膜層,之後在進行一圖行化蝕刻製程(例如非等向性蝕刻(anisotropic etching)製程),以形成該間隙壁1602(如第16A圖所示)。該間隙壁1602之材質可為介電材料,像是氮化矽,氮氧化物,碳化矽、或氧化物等。該間隙壁1602的形成方式可為原子層沉積法(ALD)、低壓化學氣相沉積法(LPCVD)、或分子層沉積法(MLD)等。
第17A及17B圖係為剖面結構示意圖,用以說明對
第16A及16B圖所示半導體裝置之鰭狀物施以一汲極/源極植入製程。對於該半導體裝置200的PMOS部份,該汲極/源極區域(像是汲極/源極區域1706)之形成方式可為植入適當的P型摻質,像是硼、鎵、銦等。此外,於該半導體裝置200的NMOS部份,該半導體裝置200,該汲極/源極區域(像是汲極/源極區域1704)之形成方式可為植入適當的N型摻質,像是磷、砷等。在某些實施例中,第14A圖所示之磊晶成長源極/汲極區域可在形成時進行原位摻雜。
第18A及18B圖係為剖面結構示意圖,用以說明對
第17A及17B圖所述該半導體裝置之遮罩層施以一蝕刻製程以移除該遮罩層。移除第17A以及17B圖所示之該遮罩層802的蝕刻方式可為任何合適的蝕刻製程,例如乾蝕刻或濕蝕刻製程。
第19A及19B圖係為剖面結構示意圖,用以說明配
置接觸蝕刻停止層於第18A及18B圖所述半導體裝置上。該接觸蝕刻停止層1902係用來提供後續蝕刻製程一控制點(control
point)。該接觸蝕刻停止層1902之材質可為一介電材料,像是氮化矽、或是氧化物。在某些實施例中,該接觸蝕刻停止層1902的形成方式可為化學氣相沉積法(CVD)、電漿輔助化學氣相沉積法(PECVD)、或原子層沉積法(ALD)等。
第20A以及20B圖係為剖面結構示意圖,用以說明
配置一層間介電層(inter-layer dielectric(ILD)layer)於第19A及19B圖所述半導體裝置之接觸蝕刻停止層上。該層間介電層2002之形成方式可例如為化學氣相沉積法、濺鍍法、或是習知可用來形成層間介電層的任何合適的方法。
該層間介電層2002之厚度可介於4,000至
13,000,亦可為其他合適的厚度。該層間介電層2002之材質可為摻雜或未摻雜氧化矽、氮化矽、具有摻質的矽酸鹽玻璃、高介電常數材料、或其組合。
第21A以及21B圖係為剖面結構示意圖,用以說明
對第20A以及20B圖所述半導體裝置進行一化學機械研磨(chemical mechanical polish、CMP)製程。一移除製程可用來移除用來形成層間介電層2002後多餘的介電材料,其中該移除製程可例如為研磨、拋光、化學蝕刻、或其結合。
根據本發明某些實施例,該移除製程可為一化學
機械研磨(chemical mechanical polish、CMP)製程。在該化學機械研磨(chemical mechanical polish、CMP)製程中,蝕刻材料以及研磨材料係放置在該層間介電層2002的上表面,並與其接觸。一研磨墊(未繪示)可用來移除多餘的介電材料直到露出該閘極的上表面。
第22A以及22B圖係為剖面結構示意圖,用以說明
對第21A以及21B圖所述半導體裝置施以一虛置閘極(dummy gate)移除製程。第21A圖所示之虛置閘極(dummy gate)係藉由一蝕刻製程來移除。如此一來,可形成開口2202以及2204。值得注意的是在進行該虛置閘極(dummy gate)移除製程時,形成於該虛置閘極(dummy gate)以及該鰭狀物間的虛置閘極(dummy gate)介電層可用來作為蝕刻停止層。
第23A以及23B圖係為剖面結構示意圖,用以說明
對第22A以及22B圖所述半導體裝置之施以另一蝕刻製程。移除該虛置閘極(dummy gate)介電層的方式可為任何適合的蝕刻製程、例如乾蝕刻製程、濕蝕刻製程、或其結合。
請參照第第23A及23B圖所示,該虛置閘極(dummy
gate)介電層可被移除,因此該露出的鰭狀物部份212、214、216、以及218的高度與第5圖所示的高度相比可為不相同。而該高度係由於在第5B圖之後的蝕刻製程所造成的。
如第23B圖所示,該NMOS電晶體的鰭狀物(例
如,鰭狀物212)具有一高度H4;該PMOS電晶體的鰭狀物(例如,鰭狀物216)具有一高度H5;而NMOS電晶體的鰭狀物(例如,鰭狀物212)之高度H4及PMOS電晶體的鰭狀物(例如,鰭狀物216)之高度H5間具有一高度差H6。在某些實施例中,高度差H6係大於第5B圖所述之高度差H3。
第24A以及24B圖係為剖面結構示意圖,用以說明
配置一閘極介電層於第23A以及23B圖所述半導體裝置的開口內。該閘極介電層2402係順應性填入於該開口2202以及2204
內。該閘極介電層2402可為一介電材料像是氧化矽、氮氧化矽、氮化矽、氧化物、含氮氧化物、或其組合。
該閘極介電層2402可具有一相對介電常數值約大
於4。根據本發明其他實施例,該閘極介電層2402可為氧化鋁、氧化鑭、氧化鉿、氧化鋯、氮氧化鉿、或其組合。根據本發明一實施例,該閘極介電層2402可包含一氧化層,而其形成方式可例如為一熱製程(利用蒸氣作為前驅物)、或為一濕製程(利用臭氧(O3)作為前驅物。
第25A以及25B圖係為剖面結構示意圖,用以說明
形成一閘極層於第24A以及24B圖所述半導體裝置之閘極介電層上。該閘極層2502可包含一導電材料,像是一金屬(例如鉭、鈦、鉬、鎢、鉑、鋁、鉿、釕)、一金屬矽化物(例如矽化鈦、矽化鈷、矽化鎳、矽化鉭)、一金屬氮化物(例如氮化鈦、氮化鉭)、摻雜的多晶矽、或其組合。在將該閘極層2502填入第24A圖所述的開口後,可對該閘極層2502施以一化學機械研磨(CMP)製程,以移除多餘的閘極層材料。
第26圖係一製造流程圖,用以說明第2A至25B圖所
述的步驟。在步驟2601中,隔離區域像是淺溝槽隔離區(STI)區域係形成於鰭式場效電晶體(fin field effect transistor、FinFET)半導體裝置。關於該淺溝槽隔離區(STI)區域的形成方式係詳述於第2B圖。在步驟2602中,一P型摻質植入製程係施以該鰭式場效電晶體(fin field effect transistor、FinFET)半導體裝置的NMOS部份。該P型摻質植入製程係詳述於第3B圖。
在步驟2603中,一N型摻質植入製程係施該鰭式場效電晶體(fin
field effect transistor、FinFET)半導體裝置的PMOS部份。該N型植入製程係詳述於第4B圖。
在步驟2604中,施以一退火製程以增加被植入的P
型摻質以及N型摻質的摻雜深度。在步驟2605中,該鰭式場效電晶體(fin field effect transistor、FinFET)半導體裝置的鰭狀物係形成並通過該凹陷的隔離區域。該隔離區凹陷製程係繪示於第5B圖。在步驟2606中,一虛置閘極(dummy gate)介電層係如第6A以及6B圖所繪示的方示配置。在步驟2607中,一虛置閘極(dummy gate)層係配置於該虛置閘極(dummy gate)介電層之上,如第7A以及7B圖所示。
在步驟2608中,施行一閘極黃光微影製程以形成
第9A圖所示該虛置閘極(dummy gate)結構。在步驟2609中,複數的封合間隙壁(seal spacer)係如第10A圖所示方式形成。在步驟2610中,藉由植入製程、擴散及/或退火製程形成輕摻雜的汲極/源極(LDD)區域,如第11A圖所示。在步驟2611中,虛置間隙壁(dummy spacer)係配置於第12A圖所示的封合間隙壁(seal spacer)上。在步驟2612中,一蝕刻製程係用以形成的複數的凹槽於應變(strained)汲極/源極上,如第13A圖所示。
在步驟2613中,該應變(strained)源極/汲極(SSD)
之製程如第14A圖所示。在步驟2614中,虛置間隙壁(dummy spacer)係被移除,如第示15A圖所示。在步驟2615中,閘極間隙壁係配置於該虛置閘極(dummy gate)的側壁上,如第16A圖所示。在步驟2616中,汲極/源極區域藉由植入製程、擴散及/或退火製程形成,如第17A圖所示。
在步驟2617中,形成於該虛置閘極(dummy gate)
的遮罩層係被移除,如第18A以及18B圖所示。在步驟2618中,一接觸蝕刻停止層(CESL)形成於該半導體裝置之上,如第19A以及19B圖所示。在步驟2619中,一層間介電層(inter-layer dielectric(ILD)layer)形成於該接觸蝕刻停止層(CESL)之上,如第20A以及20B所示。在步驟2620中,一化學機械研磨(chemical mechanical polishing、CMP)製程用以移除該層間介電層(inter-layer dielectric(ILD)layer)多餘的部份,如第21A以及21B圖所示。
在步驟2621中,移除該虛置閘極(dummy gate),如
第22A以及22B圖所示。在步驟2622中,藉由一蝕刻製程移除該虛置閘極(dummy gate)介電層,如第23A以及23B圖所示。在步驟2623中,沉積一閘極介電層,如第24A以及24B圖。在步驟2624中,配置一閘極層係該閘極介電層之上,如第25A以及25B圖。
根據一實施例,本發明提供一半導體裝置的製造
方法,包含形成複數的隔離區域於一基板上,其中一第一鰭狀物係由一第一隔離區所圍繞,以及一第二鰭狀物係由一第二隔離區所圍繞;對該第一隔離區施以一第一離子植入製程,其中具有一第一極性的摻質被植入該第一隔離區;以及,對該第二隔離區施以一第二離子植入製程,其中具有一第一極性的摻質被植入該第二隔離區。
該半導體裝置的製造方法更包含對該第一隔離區
以及該第二隔離區施以一蝕刻製程,以形成該第一鰭狀物之一
第一部份、該第一鰭狀物之一第二部份、該第二鰭狀物之一第一部份、以及該第二鰭狀物之一第二部份,其中該第一鰭狀物之該第一部份係在該第一隔離區之一上表面之上,以及該第二鰭狀物之該第一部份係在該第二隔離區之一上表面之上,其中該第一鰭狀物之該第一部份係高於該第二鰭狀物之該第一部份。
根據一實施例,本發明提供一半導體裝置,包含
一第一鰭式場效電晶體(fin field effect transistor、FinFET),其中該第一鰭式場效電晶體包含一第一鰭狀物,且該第一鰭式場效電晶體(fin field effect transistor、FinFET)具有一第一極性以及該第一鰭狀物係具有一第一高度;一第二鰭式場效電晶體(fin field effect transistor、FinFET)包含一第二鰭狀物,其中該第二鰭式場效電晶體(fin field effect transistor、FinFET)具有一第二極性,且該第二鰭狀物係具有一第二高度,其中該第一鰭狀物以及該第二鰭狀物係在同一鰭狀物形成步驟中被形成,且該第一高度係與該第二高度不同。
根據一實施例,本發明提供一半導體裝置的製造
方法,包含形成複數的第一鰭狀物,以及複數的第二鰭狀物突出於該基板之上,其中任兩相鄰之第一鰭狀物係被一第一隔離區域所分隔,以及任兩相鄰之第二鰭狀物係被一第二隔離區域所分隔。
本發明所述半導體裝置的製造方法,更包含對該
第一隔離區施以一第一離子植入製程,其中具有一第一極性的摻質被植入該第一隔離區;對該第二隔離區施以一第二離子植
入製程,其中具有一第一極性的摻質被植入該第二隔離區;以及,進行一蝕刻製程使該第一隔離區域以及該第二隔離區域凹陷。
前述已揭露了本發明數個具體實施方式的特徵,
使此領域中具有通常技藝者得更加瞭解本發明細節的描述。此領域中具有通常技藝者應能完全明白且能使用所揭露之技術特徵,做為設計或改良其他製程和結構的基礎,以實現和達成在此所介紹實施態樣之相同的目的和優點。此領域中具有通常技藝者應也能瞭解這些對應的說明,並沒有偏離本發明所揭露之精神和範圍,且可在不偏離本發明所揭露之精神和範圍下進行各種改變、替換及修改。
100‧‧‧鰭式場效電晶體
102‧‧‧基板
104‧‧‧鰭狀物
106‧‧‧第一汲極/源極區
108‧‧‧第二汲極/源極區
110‧‧‧閘極介電層
112‧‧‧閘極
X‧‧‧切線
Y‧‧‧切線
Claims (9)
- 一種半導體裝置,包含:一第一鰭式場效電晶體(fin field effect transistor、FinFET)包含一第一鰭狀物,其中該第一鰭式場效電晶體(fin field effect transistor、FinFET)具有一第一極性,且該第一鰭狀物係具有一第一高度;一第二鰭式場效電晶體包含一第二鰭狀物,其中該第二鰭式場效電晶體係具有一第二極性,且該第二鰭狀物係具有一第二高度,其中該第一鰭狀物以及該第二鰭狀物係在同一鰭狀物形成步驟中被形成,且該第一高度係與該第二高度不同。
- 如申請專利範圍第1項所述之半導體裝置,其中該第二鰭狀物係高於該第一鰭狀物。
- 如申請專利範圍第1項所述之半導體裝置,其中該第二鰭狀物以及該第一鰭狀物之間的高度差係等於或大於2nm。
- 如申請專利範圍第1項所述之半導體裝置,其中該第二鰭式場效電晶體與該第一鰭式場效電晶體係藉由一隔離區所分隔。
- 如申請專利範圍第1項所述之半導體裝置,更包含:一第三鰭式場效電晶體包含一第三鰭狀物,其中該第三鰭式場效電晶體係為第一極性,且該第三鰭狀物係具有一第三高度,其中該第三高度係大體上等於該第一高度;以及 一第四鰭式場效電晶體包含一第四鰭狀物,其中該第四鰭式場效電晶體具有該第二極性,且該第四鰭狀物具有一第四高度,其中該第四高度係大體上等於該第二高度。
- 一種半導體裝置的製造方法,包含:在一基板上形成複數的隔離區域,其中一第一鰭狀物係被一第一隔離區所圍繞,且一第二鰭狀物係被一第二隔離區所圍繞;對該第一隔離區施以一第一離子植入製程,其中具有一第一極性的摻質被植入該第一隔離區;對該第二隔離區施以一第二離子植入製程,其中具有一第一極性的摻質被植入該第二隔離區;以及對該第一隔離區以及該第二隔離區施以一蝕刻製程,以形成該第一鰭狀物之一第一部份、該第一鰭狀物之一第二部份、該第二鰭狀物之一第一部份、以及該第二鰭狀物之一第二部份,其中該第一鰭狀物之該第一部份係在該第一隔離區之一上表面之上、該第二鰭狀物之該第一部份係在該第二隔離區之一上表面之上、且該第一鰭狀物之該第一部份係高於該第二鰭狀物之該第一部份。
- 如申請專利範圍第6項所述之半導體裝置的製造方法,更包含:對該第一隔離區以及該第二隔離區施以一乾蝕刻製程以形成該第一鰭狀物之該第一部份以及該第二鰭狀物之該第一部份,其中該第一鰭狀物之該第一部份係高於該第二鰭狀物之該第一部份。
- 如申請專利範圍第6項所述之半導體裝置的製造方法,更包含:對該第一隔離區以及該第二隔離區施以一化學氧化移除製程以形成該第一鰭狀物之該第一部份以及該第二鰭狀物之該第一部份,其中該第一鰭狀物之該第一部份係高於該第二鰭狀物之該第一部份。
- 一種半導體裝置的製造方法,包含:形成複數的第一鰭狀物以及複數的第二鰭狀物突出於該基板之上,其中任兩相鄰之第一鰭狀物係被一第一隔離區域所分隔,且任兩相鄰之第二鰭狀物係被一第二隔離區域所分隔;對該第一隔離區施以一第一離子植入製程,其中具有一第一極性的摻質被植入該第一隔離區;對該第二隔離區施以一第二離子植入製程,其中具有一第一極性的摻質被植入該第二隔離區;以及進行一蝕刻製程使該第一隔離區域以及該第二隔離區域凹陷。
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US9478634B2 (en) | 2014-11-07 | 2016-10-25 | Globalfoundries Inc. | Methods of forming replacement gate structures on finFET devices and the resulting devices |
TWI557777B (zh) * | 2014-01-24 | 2016-11-11 | 台灣積體電路製造股份有限公司 | 半導體裝置及其形成方法 |
TWI613713B (zh) * | 2015-07-21 | 2018-02-01 | 台灣積體電路製造股份有限公司 | 半導體裝置與其形成方法 |
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2013
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- 2013-05-14 KR KR1020130054210A patent/KR20140107073A/ko not_active Application Discontinuation
- 2013-12-23 TW TW102147705A patent/TWI584478B/zh active
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2016
- 2016-03-30 US US15/085,750 patent/US10002765B2/en active Active
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- 2019-11-19 US US16/688,099 patent/US10840126B2/en active Active
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CN108122981B (zh) * | 2016-11-29 | 2023-01-06 | 台湾积体电路制造股份有限公司 | 半导体装置的制造方法 |
CN114530417A (zh) * | 2022-04-24 | 2022-05-24 | 合肥晶合集成电路股份有限公司 | 一种半导体结构的制作方法 |
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KR20140107073A (ko) | 2014-09-04 |
US20210050247A1 (en) | 2021-02-18 |
US20180301339A1 (en) | 2018-10-18 |
US10840126B2 (en) | 2020-11-17 |
US10504770B2 (en) | 2019-12-10 |
US10002765B2 (en) | 2018-06-19 |
US20160211138A1 (en) | 2016-07-21 |
US9318367B2 (en) | 2016-04-19 |
US20200083091A1 (en) | 2020-03-12 |
TWI584478B (zh) | 2017-05-21 |
US20140239404A1 (en) | 2014-08-28 |
US11532500B2 (en) | 2022-12-20 |
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