WO2015076372A1 - 埋設回路を備えるプリント配線板の製造方法及びその製造方法で得られるプリント配線板 - Google Patents

埋設回路を備えるプリント配線板の製造方法及びその製造方法で得られるプリント配線板 Download PDF

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Publication number
WO2015076372A1
WO2015076372A1 PCT/JP2014/080917 JP2014080917W WO2015076372A1 WO 2015076372 A1 WO2015076372 A1 WO 2015076372A1 JP 2014080917 W JP2014080917 W JP 2014080917W WO 2015076372 A1 WO2015076372 A1 WO 2015076372A1
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WO
WIPO (PCT)
Prior art keywords
copper foil
layer
printed wiring
carrier
wiring board
Prior art date
Application number
PCT/JP2014/080917
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English (en)
French (fr)
Japanese (ja)
Inventor
歩 立岡
Original Assignee
三井金属鉱業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三井金属鉱業株式会社 filed Critical 三井金属鉱業株式会社
Priority to KR1020167013101A priority Critical patent/KR20160089364A/ko
Priority to JP2015515311A priority patent/JP6753669B2/ja
Priority to KR1020177024807A priority patent/KR20170104648A/ko
Priority to CN201480062866.3A priority patent/CN105746003B/zh
Publication of WO2015076372A1 publication Critical patent/WO2015076372A1/ja

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0014—Shaping of the substrate, e.g. by moulding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/022—Processes for manufacturing precursors of printed circuits, i.e. copper-clad substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0376—Flush conductors, i.e. flush with the surface of the printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09118—Moulded substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0376—Etching temporary metallic carrier substrate

Definitions

  • the present invention relates to a method for manufacturing a printed wiring board having an embedded circuit and a printed wiring board obtained by the manufacturing method.
  • the present invention relates to the manufacture of a printed wiring board suitable for forming a circuit having a wiring width of 30 ⁇ m or less.
  • Patent Document 1 discloses the production of a multilayer printed wiring board that does not require removal of the refractory metal layer even when the multilayer printed wiring board is manufactured by a coreless buildup method using a copper foil with a carrier foil provided with a refractory metal layer.
  • insulation is performed on the surface of the carrier foil of the copper foil with carrier foil using a copper foil with carrier foil comprising four layers of “at least copper foil layer / peeling layer / heat-resistant metal layer / carrier foil”
  • a copper foil with carrier foil comprising four layers of “at least copper foil layer / peeling layer / heat-resistant metal layer / carrier foil”
  • a method for manufacturing a printed wiring board and a printed wiring board according to the present invention are shown below.
  • a manufacturing method of printed wiring board is a manufacturing method of a printed wiring board using a support substrate composed of an ultrathin copper foil with a carrier and an insulating layer constituent material for supporting substrate configuration. It is characterized by including the following steps, and is for obtaining a printed wiring board in which at least one outer layer circuit is embedded in an insulating layer constituting material.
  • Preparation of ultrathin copper foil with carrier The carrier can be peeled off at the release layer, and the outer surface of the ultrathin copper foil satisfies 0.2 ⁇ m ⁇ Wmax ⁇ 1.3 ⁇ m and 0.08 ⁇ m ⁇ Ia ⁇ An ultrathin copper foil with a carrier of 0.43 ⁇ m is prepared.
  • Preparation step of supporting substrate Using the ultrathin copper foil with carrier, an insulating layer constituent material for supporting substrate is laminated on the surface of the carrier, and the ultrathin copper foil with carrier and insulating layer for supporting substrate configuration A support substrate made up of components is prepared.
  • Plating resist pattern forming step A plating resist pattern having an opening is formed on the surface of the ultrathin copper foil layer of the ultrathin copper foil with carrier of the support substrate. Copper plating process: A copper plating layer is formed in the plating resist opening part of the said support substrate with a plating resist pattern, and a circuit pattern is formed. Plating resist removal step: The plating resist is removed from the plating resist pattern and the support substrate with a circuit pattern.
  • Lamination process of printed wiring board constituent member The printed wiring board constituent member is laminated on the circuit pattern forming surface of the circuit pattern supporting substrate.
  • Separation process of support substrate The carrier is peeled off and separated in the release layer of the ultrathin copper foil with carrier of the laminate with the printed wiring board component, and only the ultrathin copper foil layer of the ultrathin copper foil with carrier is printed. Let it be the laminated body with the ultra-thin copper foil layer left on the laminated body side with a wiring board structural member.
  • Etching process of ultra-thin copper foil layer The outer layer embedded in the insulating layer constituent material is removed by etching the ultra-thin copper foil layer in the outer layer of the laminate with the ultra-thin copper foil layer for a short time. A printed wiring board provided with a circuit is obtained.
  • the printed wiring board according to the present application is obtained by any of the above-described methods for manufacturing a printed wiring board.
  • the printed wiring board manufacturing method is a circuit-forming layer of a coreless build-up support substrate having an ultra-thin copper foil with a carrier having an ultra-thin copper foil layer excellent in resist adhesion and circuit linearity of pattern copper plating. Therefore, a fine circuit having excellent dimensional accuracy and linearity can be formed on the surface of the coreless buildup support substrate even if the fine circuit has a wiring width of 30 ⁇ m or less. Furthermore, by forming this fine circuit into a circuit embedded in the insulating layer structure material, a coreless build-up wiring board having an outer layer circuit having good adhesion to the insulating layer structure material and excellent impedance control can be obtained.
  • a manufacturing method of printed wiring board is a manufacturing method of a printed wiring board using a support substrate composed of an ultrathin copper foil with a carrier and an insulating layer constituent material for supporting substrate configuration. And includes the following steps.
  • the printed wiring board obtained by this manufacturing method is such that at least one outer layer circuit is embedded in an insulating layer constituent material.
  • it demonstrates for every process.
  • the carrier can be peeled off in the release layer, and the outer surface of the ultrathin copper foil satisfies 0.2 ⁇ m ⁇ Wmax ⁇ 1.3 ⁇ m and 0.08 ⁇ m.
  • An ultrathin copper foil with a carrier satisfying ⁇ Ia ⁇ 0.43 ⁇ m is prepared.
  • What was shown as a schematic cross-sectional view in FIG. 1 (A) is an ultrathin copper foil 1 with a carrier.
  • the outer surface 25 of the ultrathin copper foil is a surface exposed on the surface.
  • This Wmax is preferably 1.3 ⁇ m or less from the viewpoint of linearity of a circuit formed by plating on the surface of the ultrathin copper foil layer.
  • Wmax is preferably 0.2 ⁇ m or more from the viewpoint of improving the adhesion of the plating resist.
  • Wmax is the maximum height difference of the waviness, and was extracted by using a filter from information related to the unevenness of the ultrathin copper foil surface of the ultrathin copper foil with carrier obtained using a three-dimensional surface structure analysis microscope. This is the maximum value of the height difference of the waveform data related to the swell (the sum of the maximum peak height of the waveform and the maximum valley depth).
  • the unevenness Ia on the outer surface of the ultrathin copper foil is preferably 0.08 ⁇ m ⁇ Ia ⁇ 0.43 ⁇ m from the viewpoint of adhesion of the plating resist and the viewpoint of resist circuit linearity.
  • Ia is the average surface height.
  • Zygo New View 5032 (manufactured by Zygo) is used as a measuring instrument, and Metro Pro Ver. 8.0.2 was used, the low frequency filter was set to 11 ⁇ m, and the measurement was performed according to the following procedures a) to c).
  • a) The outer surface of the ultrathin copper foil with a carrier is fixed to the sample table by using the outer surface of the ultrathin copper foil as a measurement surface.
  • 6 points of view of 108 ⁇ m ⁇ 144 ⁇ m are selected and measured within the range of 1 cm square of the outer surface of the ultrathin copper foil with carrier.
  • the average value of the values obtained from the six measurement points was adopted as the Wmax value and Ia value of the outer surface of the ultrathin copper foil.
  • the ultrathin copper foil with a carrier to be used has a layer structure of “carrier 2 / peeling layer 3 / ultra thin copper foil layer 4”, or “carrier 2 / peeling layer 3 / heat resistant metal layer / It is preferable to use one having a layer configuration of “ultra-thin copper foil layer 4”. This is because by providing such a layer structure, it becomes easy to peel off the carrier afterwards.
  • the ultrathin copper foil layer 4 is preferably thinner than the carrier 2.
  • the thickness of the ultrathin copper foil layer 4 is preferably a copper foil layer having a thickness of 0.5 ⁇ m to 5 ⁇ m, from the viewpoint of generation of pinholes and reduction in etching amount variation during etching removal.
  • the ultrathin copper foil layer 4 is formed by any of a liquid phase method such as an electrolysis method or an electroless method, a chemical vapor reaction method such as CVD, or a physical method such as sputtering or vapor deposition. It doesn't matter.
  • the thickness of the carrier is preferably 12 ⁇ m to 70 ⁇ m, more preferably 12 ⁇ m to 35 ⁇ m, from the viewpoint of ensuring rigidity during handling and ensuring parallelism during press lamination.
  • the release layer includes an organic release layer and an inorganic release layer.
  • an inorganic release layer it is preferred to employ one containing at least one compound selected from the group consisting of nitrogen-containing compounds, sulfur-containing compounds and carboxylic acids.
  • the nitrogen-containing organic compound here includes a nitrogen-containing organic compound having a substituent.
  • examples of the nitrogen-containing organic compound include 1,2,3-benzotriazole, carboxybenzotriazole, N ′, N′-bis (benzotriazolylmethyl) urea, which are triazole compounds having a substituent, and 1H. It is preferable to use -1,2,4-triazole, 3-amino-1H-1,2,4-triazole and the like.
  • the sulfur-containing organic compound it is preferable to use mercaptobenzothiazole, thiocyanuric acid, 2-benzimidazolethiol, or the like.
  • the carboxylic acid it is particularly preferable to use a monocarboxylic acid, and it is particularly preferable to use oleic acid, linoleic acid, linolenic acid, or the like.
  • At least 1 type selected from the group which consists of an alloy or a compound which has Ni, Mo, Co, Cr, Fe, Ti, W, P, carbon, or these as a main component as an inorganic component It is preferable to form using the above.
  • these inorganic bonding interface layers it is possible to form with an arbitrary thickness using a known method such as an electrodeposition method, an electroless method, or a physical vapor deposition method.
  • the heat-resistant metal layer (not shown) having a layer structure of “carrier 2 / peeling layer 3 / heat-resistant metal layer / ultra-thin copper foil layer 4” is formed by “carrier 2 and ultra-thin copper” that occurs when hot press molding is performed.
  • the “interdiffusion between the foil layers 4” is suppressed to prevent seizure between the carrier 2 and the ultrathin copper foil layer 4 so that the carrier 2 can be easily peeled thereafter.
  • This refractory metal layer is preferably selected from the group of molybdenum, tantalum, tungsten, cobalt, nickel and various alloys containing these metal components. However, it is most preferable to form the refractory metal layer using nickel or a nickel alloy.
  • the nickel or nickel alloy film has excellent film forming accuracy and stable heat resistance.
  • physical vapor deposition techniques such as an electroless method, an electrolysis method, sputtering vapor deposition, a chemical vapor reaction method, for formation of a heat-resistant metal layer.
  • an insulating layer constituting material for supporting substrate construction is bonded to the surface of this carrier. That is, “insulating layer constituting material 5 for supporting substrate / carrier 2 / peeling layer 3 / ultra-thin copper foil layer 4” or “insulating layer constituting material 5 for supporting substrate / carrier 2 / peeling layer 3 / heat resistance”
  • a supporting substrate having a layer configuration of any one of “metal layer / ultra thin copper foil layer 4” is prepared.
  • the insulating layer constituting material 5 for constituting the support substrate used at this time use of a prepreg, a resin film, a resin film with an adhesive, or the like can be assumed.
  • the bonding method a hot press molding method, a bonding method using an adhesive, and the like can be arbitrarily selected.
  • Plating resist pattern forming step In this step, a plating resist pattern 10 having an opening is formed on the surface of the ultrathin copper foil layer of the above-mentioned support substrate with an ultrathin copper foil with a carrier, and the pattern shown in FIG. A “supporting substrate S2 with a plating resist pattern” as shown in the sectional view is obtained.
  • the plating resist used at this time it is preferable to use a dry film or a liquid resist. This is because the exposure resolution is excellent and it meets the purpose of forming a fine circuit. Using these, the surface of the ultrathin copper foil layer of the ultrathin copper foil with carrier of the support substrate is coated.
  • the desired plating resist pattern is exposed and developed to obtain “supporting substrate S2 with plating resist pattern” of FIG.
  • an extra oxide film on the surface of the ultra-thin copper foil layer is removed.
  • Copper plating step In this step, the copper plating 20 is applied to the plating resist opening of the above-mentioned “supporting substrate S2 with a plating resist pattern”. That is, a copper plating layer serving as a circuit pattern is formed at a portion where no plating resist is present, and a circuit pattern is formed where a copper plating layer is not formed at a portion where the plating resist is present. What is obtained in this step is the “supporting substrate S3 with plating resist pattern and circuit pattern” shown in FIG. At this time, the surface of the circuit pattern on the ultrathin copper foil layer side is a replica of the surface shape of the ultrathin copper foil layer.
  • Plating resist removal step In this step, the plating resist 10 is removed from the “supporting substrate S3 with plating resist pattern and circuit pattern” to obtain the “supporting substrate S4 with circuit pattern” shown in FIG. At this time, the plating resist 10 is usually removed using an alkaline solution.
  • Lamination process of printed wiring board constituent members In this process, a desired printed wiring board necessary to obtain a target printed wiring board on the circuit pattern forming surface using the above-mentioned “supporting substrate with circuit pattern S4”. The constituent members are bonded together as shown in FIG. 3E to obtain a “laminated body S5 with a printed wiring board constituent member” shown in FIG. With regard to the “desired printed wiring board constituent member necessary for obtaining the target printed wiring board” here, there is no particular limitation as long as the printed wiring board is finally obtained. However, it is preferable to adopt the following method.
  • the insulating layer constituting material 6 is used as the printed wiring board constituting member. That is, as shown in FIG. 3E, the insulating layer constituting material 6 is bonded to the circuit pattern forming surface of the “circuit pattern supporting substrate S4”, and the “laminated printed wiring board constituting member laminated member” shown in FIG. The body S5 "can be obtained.
  • a multilayered printed wiring board by using a build-up wiring layer as the printed wiring board constituent member.
  • a build-up wiring layer There is no particular limitation on the multilayering method of the build-up wiring layer here.
  • a “printed wiring board configuration” in which a normal printed wiring board type is multilayered by a method of sequentially pasting the circuit pattern forming surface of the “supporting substrate S4 with circuit pattern” via the insulating layer constituting material 6
  • the method of using the member-attached laminate S5 can be employed.
  • a new copper foil layer is provided on the circuit pattern forming surface of the “support substrate with circuit pattern S4” via an insulating layer constituting material, and via hole processing, plating processing, etching processing, etc. are performed, and the same operation is performed.
  • Etching process of ultra-thin copper foil layer In this process, the ultra-thin copper foil layer 4 in the outer layer of the laminate S6 with the ultra-thin copper foil layer is dissolved and removed by etching for a short time to form an insulating layer constituent material A printed wiring board having a circuit pattern which is an outer layer circuit embedded in 6 is obtained. That is, a printed wiring board P as shown in FIG. At this time, the surface of the circuit pattern which is the outer layer circuit is formed with a replica surface 30 in which the surface shape of the ultrathin copper foil layer 4 is inverted unless a special etching process, roughening process, or the like is performed.
  • the circuit surface having such surface characteristics is excellent in wettability with solder, it can be suitably used as a component terminal. Even if the surface of the circuit pattern which is the outer layer circuit is subjected to chemical treatment, etching treatment, roughening treatment, etc., the same surface property can be maintained as long as the surface property does not vary greatly. . Further, by etching the ultrathin copper foil layer 4, a replica surface in which the shape of the surface of the ultrathin copper foil layer 4 is reversed is also formed on the surface of the insulating layer constituting material 6.
  • the surface of the insulating layer constituting material 6 also takes values of 0.2 ⁇ m ⁇ Wmax ⁇ 1.3 ⁇ m and 0.08 ⁇ m ⁇ Ia ⁇ 0.43 ⁇ m.
  • the surface of the insulating layer constituting material 6 has good adhesion to a resin material such as a solder resist formed on the surface layer or a sealing resin.
  • the circuit pattern side of the “support substrate S4 with a circuit pattern” shown in FIG. 2D is placed on the outer layer of the printed wiring board constituent member via the insulating layer constituent material 6.
  • the carrier is peeled off in the peeling layer of the ultrathin copper foil with a carrier and separated and removed, and the ultrathin copper foil layer is formed on both sides. It is also possible to obtain a printed wiring board in which a laminated body with an exposed ultrathin copper foil layer is formed, and outer layer circuits on both sides are embedded in an insulating layer constituent material.
  • the printed wiring board manufacturing method according to the present application described above apparently has one surface of the insulating layer constituting material 5 for constituting the supporting substrate shown in FIG. 1A so that the process can be easily understood. It has been described as the form used. However, the same operation can be performed on both surfaces of the insulating layer constituting material 5 for constituting the support substrate in FIG.
  • a printed wiring board according to the present application is obtained by the method for manufacturing a printed wiring board described above.
  • the printed wiring board according to the present application may be a single-sided printed wiring board, a double-sided printed wiring board, or a multilayer printed wiring board having three or more layers.
  • This ultrathin copper foil 1 with a carrier comprises a carrier 2 having a thickness of 18 ⁇ m, an ultrathin copper foil layer 4 having a thickness of 3.0 ⁇ m, and a release layer 3 formed of carboxybenzotriazole.
  • Support substrate preparation step In this step, using the above-mentioned ultrathin copper foil 1 with a carrier, an insulating layer constituent material 5 for supporting substrate configuration is laminated on the surface of the carrier 2, and "insulating layer for supporting substrate configuration" A support substrate S1 shown in FIG. 1A having a layer configuration of “component 5 / carrier 2 / peeling layer 3 / ultra thin copper foil layer 4” was obtained. As the insulating layer constituting material 5 for constituting the support substrate, FR-4 prepreg was used.
  • Plating resist pattern forming step In this step, a plating resist (dry film) is provided on the surface of the ultrathin copper foil layer with a carrier of the support substrate S1 described above, and exposure and development are performed. A plating resist pattern 10 having an opening with a width of 20 ⁇ m was formed to obtain “supporting substrate S2 with a plating resist pattern” as shown in the schematic cross-sectional view of FIG.
  • Copper plating step In this step, a copper plating layer 20 serving as a circuit pattern is formed in the plating resist opening of the above-mentioned “supporting substrate S2 with plating resist pattern”, and a “plating resist pattern and a pattern as shown in FIG. A support substrate S3 with a circuit pattern "was obtained.
  • Plating resist removal step In this step, the plating resist 10 is removed from the “supporting substrate S3 with plating resist pattern and circuit pattern” using an alkaline solution, and a “support with circuit pattern” as shown in FIG. Substrate S4 "was obtained.
  • Lamination process of printed wiring board constituent members In this process, the insulating layer constituting material 6 is obtained on the circuit pattern forming surface using the above-mentioned “support substrate with circuit pattern S4” in order to obtain a target printed wiring board. By pasting as shown in FIG. 3E, a “laminated body S5 with printed wiring board constituting member” as shown in FIG. 3F was obtained.
  • Plating resist adhesion test method The plating resist evaluation samples were as follows. In the above-described plating resist pattern forming step, a plating resist (dry film) was provided on the surface of the ultrathin copper foil layer of the ultrathin copper foil with carrier of the support substrate S1, and the entire surface was exposed. After that, after the plating resist on the support substrate S1 is attached to a phenol resin plate having a thickness of 0.8 mm with an adhesive, the carrier is separated from the release layer to expose the ultrathin copper foil layer. A laminate having a layer structure of / adhesive layer / phenol resin plate was obtained.
  • the peel strength (angle 90 °, speed 50 mm / min) of the electrolytic copper plating layer cut to 1 cm width is obtained.
  • the adhesion of the plating resist was evaluated. The criteria for determining the adhesion strength were as follows. (Criteria for plating resist adhesion) ⁇ : 0.01 kgf / cm or more ⁇ : less than 0.01 kgf / cm
  • Circuit linearity evaluation method As the above-mentioned outer layer circuit pattern, the wiring width of a printed wiring board P having an embedded circuit with a wiring width of 20 ⁇ m is measured at 15 points in increments of 4 ⁇ m, and the standard deviation ⁇ w of the line width is determined. Obtained as an index of circuit linearity.
  • the standard for the standard deviation value was as follows. (Criteria for circuit linearity) ⁇ : ⁇ w ⁇ 2.2 ⁇ m ⁇ : ⁇ w > 2.2 ⁇ m
  • the outer surface of the ultrathin copper foil satisfies 0.2 ⁇ m ⁇ Wmax ⁇ 1.3 ⁇ m and 0.08 ⁇ m ⁇ Ia ⁇ . It is a requirement to use 0.43 ⁇ m.
  • the ultra-thin copper foil with carrier used in each example satisfies the requirements for the ultra-thin copper foil with carrier according to the present application, and the plating resist adhesion test and circuit Good results have been obtained in both linearity tests.
  • a coreless build-up wiring board having an embedded circuit with excellent linearity as an outer layer even for a fine circuit with a wiring width of 30 ⁇ m or less. it can.
  • This advantage can be used in various applications as a thin coreless build-up substrate with excellent impedance control.
  • it can be used as a semiconductor package or module substrate for high-frequency digital signal circuits in the 1 to 10 GHz band, such as application processors and memories installed in smartphones, tablets, computers, servers, routers, workstations, etc. is there.
  • the mounting form is excellent in impedance matching, it is possible to reduce the number of mounting electronic components such as additional resistors and inductors.
  • this excellent characteristic it can be used not only for the above-mentioned digital signal processing but also for an antenna element substrate for a transmission / reception circuit used for multi-band analog wireless communication, a CSP, and the like.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)
PCT/JP2014/080917 2013-11-22 2014-11-21 埋設回路を備えるプリント配線板の製造方法及びその製造方法で得られるプリント配線板 WO2015076372A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020167013101A KR20160089364A (ko) 2013-11-22 2014-11-21 매설 회로를 구비하는 프린트 배선판의 제조 방법 및 그 제조 방법으로 얻어지는 프린트 배선판
JP2015515311A JP6753669B2 (ja) 2013-11-22 2014-11-21 埋設回路を備えるプリント配線板の製造方法及びその製造方法で得られるプリント配線板
KR1020177024807A KR20170104648A (ko) 2013-11-22 2014-11-21 코어리스 빌드업 지지 기판 및 당해 코어리스 빌드업 지지 기판을 사용하여 제조된 프린트 배선판
CN201480062866.3A CN105746003B (zh) 2013-11-22 2014-11-21 具有包埋电路的印刷线路板的制造方法及用该制造方法得到的印刷线路板

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JP2013-241584 2013-11-22
JP2013241584 2013-11-22

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WO2015076372A1 true WO2015076372A1 (ja) 2015-05-28

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JP (2) JP6753669B2 (zh)
KR (2) KR20160089364A (zh)
CN (2) CN107708314B (zh)
TW (2) TWI589201B (zh)
WO (1) WO2015076372A1 (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017114070A (ja) * 2015-12-25 2017-06-29 三井金属鉱業株式会社 キャリア付銅箔及びコアレス支持体用積層板、並びに配線層付コアレス支持体及びプリント配線板の製造方法
WO2017149810A1 (ja) * 2016-02-29 2017-09-08 三井金属鉱業株式会社 キャリア付銅箔及びその製造方法、並びに配線層付コアレス支持体及びプリント配線板の製造方法
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