WO2014175343A1 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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Definitions
- the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.
- the front electrode and circuit layer of a semiconductor element are electrically connected by wire bonding such as aluminum (Al) wire.
- wire bonding such as aluminum (Al) wire.
- the front surface electrode is, for example, an aluminum-silicon (Si) electrode or an Al-Si-copper (Cu) electrode
- the circuit layer is made of a conductor such as Cu.
- wire bonding of Cu wires has been studied in place of Al wires. A structure of a conventional semiconductor device having a module structure will be described.
- FIG. 10 is a sectional view showing the structure of a conventional semiconductor device having a module structure.
- FIG. 11 is a cross-sectional view schematically showing the structure of the semiconductor element of FIG.
- a conventional semiconductor device having a module structure includes a semiconductor element 101, an insulating substrate 102 such as a ceramic insulating substrate (DCB (Direct Copper Bonding) substrate), a Cu base 106, and an Al wire 107. ing.
- the insulating substrate 102 is provided with a circuit layer 104 made of Cu on the front surface side of the insulating layer 103 and a back copper foil 105 on the back surface side.
- the semiconductor element 101 has a front electrode 112 on the front surface of the semiconductor substrate 111 and a back electrode 113 on the back surface.
- the back electrode 113 of the semiconductor element 101 is bonded to the circuit layer 104 via the solder bonding layer 101a.
- the front surface electrode 112 of the semiconductor element 101 is electrically connected to the circuit layer 104 by wire bonding such as an Al wire 107.
- the Al wire 107 is joined using ultrasonic vibration, and the connection failure is reduced by optimizing conditions such as heat, ultrasonic vibration, and applied pressure with respect to the diameter (diameter) of the Al wire 107. A good bond is formed without causing it.
- the front surface of the Cu base 106 is bonded to the back copper foil 105 via a solder bonding layer (not shown).
- the recrystallization temperature is set to 150 ° C. or more so as to have an average crystal grain size of 50 ⁇ m or more in connection between the element and the external electrode and not to cause recrystallization when energized.
- An apparatus composed of an aluminum wire containing 0.02 wt% to 1 wt% of Fe for increasing has been proposed (see, for example, Patent Document 1 below).
- the film is formed on the top surface of the surface electrode.
- a device including a metal protective film, and a wire wiring electrically bonded to the surface electrode via the metal protective film by thermocompression bonding or ultrasonic vibration (see, for example, Patent Document 4 below). ).
- Factors that determine the power cycle tolerance are the maximum value Tjmax of the junction temperature of the semiconductor element and the temperature change ⁇ Tj of the junction temperature of the semiconductor element caused by the intermittent flow of current.
- the constituent members of the semiconductor device have different linear expansion coefficients, and each constituent member is subjected to a stress corresponding to the difference in the linear expansion coefficients.
- Tjmax of the junction temperature of the semiconductor element increases, the stress corresponding to the difference in the linear expansion coefficient of each constituent member increases, which may lead to element destruction. For this reason, it is necessary to improve the power cycle tolerance in high temperature operation, and to achieve high temperature operation and high reliability at the same time.
- the crystal grains near the bonding interface of the Al wire become fine particles due to wire bonding, and the bonding strength of the Al wire is improved.
- the high-temperature operation for example, about 175 ° C.
- the vicinity of the bonding interface of the Al wire and the crystal grains of the front electrode are coarsened and softened.
- cracks are likely to occur in the vicinity of the bonding interface between the Al wire and the front electrode.
- a crack was generated in the Al wire, and this crack progressed to the inside of the wire with an increase in the number of repeated power cycles. It was found that the device was destroyed.
- An object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device that can improve power cycle tolerance in large current conduction and high-temperature operation in order to eliminate the above-described problems caused by the prior art.
- a semiconductor device has the following characteristics in a semiconductor device in which electrodes of a semiconductor element and wires are electrically connected by wire bonding.
- a metal film having a hardness higher than that of the wire is provided on the surface of the electrode.
- the wire is bonded to the metal film by wire bonding.
- the recrystallization temperature of the joint interface with the said metal film of the said wire is 175 degreeC or more.
- the crystal grain size of the bonding interface of the wire is 15 ⁇ m or less, and a portion apart from the bonding interface of the wire is a crystal having a particle size of greater than 15 ⁇ m. It is characterized by containing grains.
- the hardness of the wire is higher than the hardness of the electrode.
- the semiconductor device according to the present invention is characterized in that, in the above-described invention, the metal film is a nickel plating film.
- the semiconductor device according to the present invention is characterized in that, in the above-described invention, the thickness of the nickel plating film is 3 ⁇ m to 7 ⁇ m.
- the semiconductor device according to the present invention is characterized in that, in the above-described invention, the metal film is a copper plating film.
- the semiconductor device according to the present invention is characterized in that, in the above-described invention, the thickness of the copper plating film is 4.5 ⁇ m to 10.5 ⁇ m.
- a semiconductor device manufacturing method includes a semiconductor device manufacturing method in which an electrode of a semiconductor element and a wire are electrically connected. It has the characteristics of. First, a step of providing a metal film having a higher hardness than the wire on the surface of the electrode is performed. Next, the step of bonding the wire to the metal film is performed by setting the crystal grain size of the bonding interface between the wire and the metal film to 15 ⁇ m or less by ultrasonic vibration of wire bonding.
- the recrystallization temperature of the wire higher than the recrystallization temperature of the conventional aluminum wire, it is possible to suppress the occurrence of cracks in the wire even under use conditions at a higher temperature than in the past. . Thereby, the period until a crack arises in a wire can be made longer than before.
- the electrode can be strengthened by providing a metal film having a hardness higher than that of the wire on the surface of the electrode of the semiconductor element (semiconductor chip), so that the electrode is prevented from being cracked. can do.
- the metal film functions as a barrier. Therefore, even when a crack occurs in the wire, the crack can be prevented from progressing to the electrode. .
- FIG. 1 is a cross-sectional view illustrating the structure of the semiconductor device according to the embodiment.
- FIG. 2 is a cross-sectional view schematically showing the structure of the semiconductor element of FIG.
- FIG. 3 is a cross-sectional view schematically showing a state of crystal grains in the vicinity of the wire bonding interface of the semiconductor device according to the embodiment.
- FIG. 4 is a cross-sectional view schematically showing the state of crystal grains in the vicinity of the wire bonding interface of the semiconductor device of the reference example.
- FIG. 5 is a cross-sectional view schematically showing the state of crystal grains in the vicinity of the wire bonding interface of a conventional semiconductor device.
- FIG. 6 is a characteristic diagram illustrating the bonding strength of the wires of the semiconductor device according to the embodiment.
- FIG. 7 is a characteristic diagram showing the bonding strength of wires of a conventional semiconductor device.
- FIG. 8 is a characteristic diagram showing the power cycle capability of the semiconductor device according to the embodiment.
- FIG. 9 is a cross-sectional view schematically showing a state in the vicinity of the bonding interface of the wire after the wire bonding of the semiconductor device according to the embodiment.
- FIG. 10 is a cross-sectional view showing the structure of a conventional semiconductor device having a module structure.
- FIG. 11 is a cross-sectional view schematically showing the structure of the semiconductor element of FIG.
- FIG. 12 is a characteristic diagram illustrating the bonding strength of the wires of the semiconductor device according to the embodiment.
- FIG. 13 is a characteristic diagram illustrating the bonding strength of another example of the semiconductor device according to the embodiment.
- FIG. 14 is a characteristic diagram showing the bonding strength of another example of a conventional semiconductor device.
- FIG. 1 is a cross-sectional view illustrating the structure of the semiconductor device according to the embodiment.
- FIG. 2 is a cross-sectional view schematically showing the structure of the semiconductor element of FIG.
- the semiconductor device according to the embodiment includes a semiconductor element (semiconductor chip) 1, an insulating substrate 2 such as a ceramics insulating substrate (DCB substrate), a copper (Cu) base 6, and wires.
- 7 is a module-structured semiconductor device.
- the insulating substrate 2 is provided with a circuit layer 4 made of, for example, Cu on the front surface side of the insulating layer 3 and a back copper foil 5 on the back surface side.
- the semiconductor element 1 has a front electrode 12 on the front surface of a semiconductor substrate (for example, a silicon (Si) substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, etc.) 11, and the rear surface.
- a back electrode 13 is provided.
- the back electrode 13 of the semiconductor element 1 is bonded to the circuit layer 4 via the solder bonding layer 1a.
- the front surface of the Cu base 6 is bonded to the back copper foil 5 via a solder bonding layer (not shown).
- a resin case provided with external terminals is bonded to the periphery of the Cu base 6.
- the semiconductor device is used with the back surface of the Cu base 6 fixed to a cooling body via a thermal compound.
- the front surface electrode (hereinafter simply referred to as front surface electrode) 12 of the semiconductor element 1 is, for example, an aluminum (Al) -silicon (Si) electrode.
- the crystal grain size of the front electrode 12 may be, for example, 1 ⁇ m to 5 ⁇ m.
- a front surface metal film 14 such as a nickel (Ni) film or a copper (Cu) film is formed on the surface of the front surface electrode 12 by electroless plating, electrolytic plating, sputtering, vapor deposition, or the like. Yes.
- the hardness of the front surface metal film 14 is higher than the hardness of the front surface electrode 12 and the wire 7.
- the front metal film 14 has a function of improving the strength of the front electrode 12 and preventing the front electrode 12 from cracking.
- the hardness of the front metal film 14 is preferably Hv100 to Hv900, for example.
- the thickness of the front metal film 14 is preferably 3 ⁇ m to 30 ⁇ m, for example.
- the thickness of the front surface metal film 14 is 3 ⁇ m to 7 ⁇ m, preferably 3 ⁇ m to 5 ⁇ m.
- the reason for setting the film thickness to 3 ⁇ m or more is that when a Ni plating film is formed as the front metal film 14, if the plating film thickness is less than 3 ⁇ m, frictional heat generated when wire 7 is wire bonded, This is because the plating film is destroyed by the solid phase flow.
- the breaking strength of the front metal film 14 can be increased, but in consideration of throughput and economy, it is 30 ⁇ m or less, preferably 5 ⁇ m or less. It is good.
- the thickness of the front surface metal film 14 is 4.5 ⁇ m to 10.5 ⁇ m, preferably 4.5 ⁇ m to 7.5 ⁇ m. Since the hardness of the Cu plating film is in the range of Hv100 to Hv300, the fracture strength equivalent to that of the Ni plating film can be obtained by making the film thickness about 1.5 times that of the Ni plating film. Also, when the front metal film 14 is formed by sputtering or vapor deposition, the above-mentioned hardness and film thickness are preferably set for the same reason.
- the front surface electrode 12 and the circuit layer 4 are electrically connected via a wire 7.
- one end of the wire 7 is bonded to the front surface metal film 14 on the surface of the front electrode 12 by wire bonding using heat, ultrasonic vibration and pressure (bonding load). Is connected to the circuit layer 4 at the other end.
- the bonding load for bonding the wire 7 and the member to be bonded is, for example, a wire bonder BJ935 (ultrasonic frequency 60 kHz) manufactured by H & K (Hess & Knipps GmbH).
- the wire bonding ultrasonic output is 11 V or more, for example, 800 gf to 1400 gf, and when the wire bonding ultrasonic output is 13 V or more, 1000 gf to 1400 gf.
- the wire 7 is made of, for example, iron (Fe) of 0.2 mass% to 2.0 mass% and the balance of aluminum (Al) having a purity of 99.99% or more. It is a high heat resistant aluminum wire.
- the crystal grain size of the wire 7 is controlled to be smaller than the crystal grain size of the conventional aluminum wire by containing a predetermined amount of Fe.
- the recrystallization temperature of the wire 7 is increased to at least 175 ° C. or more, and the hardness of the wire 7 is higher than the hardness of the front electrode 12.
- the hardness of the wire 7 is higher than the hardness Hv20 of the AlSi electrode which is the front electrode 12, for example, immediately after the wire bonding.
- the recrystallization temperature of the wire 7 By setting the recrystallization temperature of the wire 7 within the above range, the heat history due to the manufacturing process after wire bonding and the high temperature operation (for example, about 175 ° C.) due to energization / heating of the semiconductor element 1 (hereinafter, the heat history and energization / heating are reduced Since the wire 7 is not recrystallized, the crystal grains of the wire 7 can be prevented from becoming coarse. As a result, during energization heat generation, the crystal grains of the wire 7 are not substantially changed, and the hardness of the wire 7 is maintained in a state immediately after the wire bonding. Therefore, the wire 7 is not easily softened by the power cycle, and the wire 7 is less likely to be cracked than before.
- the crystal grain size of the wire 7 before wire bonding is preferably the maximum, for example, in the range of 1 ⁇ m to 20 ⁇ m.
- the crystal grains in the vicinity of the bonding interface between the wire 7 and the member to be bonded (hereinafter referred to as the bonding interface of the wire 7) can be made into fine particles by controlling the conditions during wire bonding.
- the crystal grain size of the wire 7 extends from the bonding interface of the wire 7 to the axial direction of the wire 7 up to a portion where cracks are likely to occur due to heat history in the manufacturing process after wire bonding or high-temperature operation heat due to energization heat generation of the semiconductor element. It is preferably finely grained by wire bonding.
- the crystal grain size of the wire 7 immediately after the wire bonding is, for example, in the range of 1 ⁇ m to 15 ⁇ m at the maximum (average is 3 ⁇ m or less) in the crystal grains near the bonding interface with the bonded member.
- the crystal grain size before wire bonding is maintained in a portion away from the bonding interface (other than the vicinity of the bonding interface of the wire 7).
- the crystal grain size is evaluated by an electron beam backscatter diffraction method (EBSD: Electron Backscatter Diffraction).
- EBSD Electron Backscatter Diffraction
- the wire diameter of the wire 7 may be, for example, 100 ⁇ m to 500 ⁇ m.
- the wire diameter of the wire 7 is thickened to about 500 ⁇ m, for example. The reason is that the wire heating temperature during energization can be reduced by thickening.
- Ni is plated as the front surface metal film 14 on the surface of the AlSi electrode that is the front surface electrode 12 by using an electroless nickel plating method.
- a zincate treatment is generally performed as a pretreatment for the electroless plating treatment to improve the adhesion of the nickel plating film to the AlSi electrode.
- the surface of the front electrode 12 is degreased to remove oily dirt and foreign matter adhering to the surface and clean it.
- the wettability of the front electrode 12 such as an etching solution in the subsequent process is improved.
- an etching process is performed using an acid solution.
- acid cleaning is performed using a nitric acid (HNO 3 ) solution to remove deposits (smut) generated by the etching treatment.
- a first zincate treatment is performed to replace Al on the surface of the front electrode 12 with zinc (Zn), and a Zn film having a desired crystal grain size is generated on the surface of the front electrode 12. .
- the Zn film formed on the surface of the front electrode 12 is removed using a nitric acid solution.
- a Zn film is formed again on the surface of the front electrode 12 by performing a second zincate process.
- an electroless Ni plating process is performed to replace the Zn film with Ni, and Ni is continuously deposited on the surface of the front electrode 12 to form a Ni plating film.
- a Ni plating film is formed as the front metal film 14 on the surface of the front electrode 12.
- a Ni plating film may be formed as a protective film for the front electrode 12 by a palladium process.
- FIG. 3 is a cross-sectional view schematically showing a state of crystal grains in the vicinity of the wire bonding interface of the semiconductor device according to the embodiment.
- FIG. 4 is a cross-sectional view schematically showing the state of crystal grains in the vicinity of the wire bonding interface of the semiconductor device of the reference example.
- FIG. 5 is a cross-sectional view schematically showing the state of crystal grains in the vicinity of the wire bonding interface of a conventional semiconductor device. 3 to 5, (a) shows a state before wire bonding, (b) shows a state immediately after wire bonding, and (c) shows a state after a power cycle test.
- the semiconductor device according to the above-described embodiment hereinafter referred to as an example
- the state of the crystal grains in the vicinity of the bonding interface 20 of the wire 7 observed with a microscope after the power cycle test is schematically shown in FIG.
- the wire diameter of the wire 7 was set to 400 ⁇ m, and the crystal grain size of the wire 7 before wire bonding was set within a range of 1 ⁇ m to 20 ⁇ m.
- the crystal grain size in the vicinity of the bonding interface 20 of the wire 7 after wire bonding is in the range of 1 ⁇ m to 15 ⁇ m, and the crystal grain size of the part away from the bonding interface 20 of the wire 7 after wire bonding indicates the state before the wire bonding. It was maintained within a range of 1 ⁇ m to 20 ⁇ m.
- the hardness of the wire 7 after wire bonding is Hv25 to Hv40.
- a 0.3 ⁇ m thick Ni plating film (Example 1) and a 5 ⁇ m thick Ni plating film (Example 2) were formed.
- the hardness of the Ni plating film is Hv900.
- An AlSi electrode was formed as the front electrode 12, and the crystal grain size was in the range of 1 ⁇ m to 5 ⁇ m.
- a semiconductor device (hereinafter referred to as a reference example) in which the front surface metal film 14 is not provided, that is, the wire 37 is bonded to the front surface electrode 32 of the front surface of the semiconductor substrate 31 is implemented.
- the result of conducting the same power cycle test with the same number of repeated cycles as in the example is schematically shown in FIG.
- the configuration of the reference example is the same as that of the example except that the front metal film 14 is not provided.
- a conventional semiconductor device (hereinafter referred to as Conventional Example 1) in which a conventional aluminum wire 107 is bonded to the front surface electrode 112 of the semiconductor substrate 111 is the same in the same number of cycles as in the example.
- the results of the power cycle test are schematically shown in FIG.
- the crystal grain size (maximum) of the Al wire 107 before wire bonding was 40 ⁇ m or more.
- the crystal grain size in the vicinity of the bonding interface 120 of the Al wire 107 after wire bonding is in the range of 1 ⁇ m to 20 ⁇ m, the maximum grain size is larger than 15 ⁇ m, and the crystal in the part away from the bonding interface 120 of the Al wire 107 after wire bonding
- the particle size was 40 ⁇ m or more while maintaining the state before wire bonding.
- the configuration of Conventional Example 1 is the same as that of the example except that the Al wire 107 is used and the front metal film 14 is not provided.
- the bonding load, ultrasonic amplitude, and bonding time between the wire and the member to be bonded are the same in all of the examples, the reference example, and the conventional example 1.
- the crystal grains of the front electrode 12 were coarsened and softened, but no cracks were generated in the front electrode 12. This is presumably because the front electrode 12 is reinforced by the front metal film 14 having a hardness higher than that of the wire 7. Further, although the crack 21 is generated in the wire 7, it is provided between the wire 7 and the front surface electrode 12 even when the crack 21 progresses inside the wire 7 as the number of repeated power cycles is increased. It was confirmed that the formed front metal film 14 functions as a barrier, and the crack 21 generated in the wire 7 does not progress to the front electrode 12.
- the state of the crystal grains of the wire 37 and the front surface electrode 32 in the period from immediately after the wire bonding to the occurrence of the crack is the same as in the example. Although it was the same, it was confirmed that no crack was generated in the wire 37 and the crack 23 was generated in the front electrode 32. This is because the hardness of the front electrode 32 is lower than the hardness of the wire 37. Thereby, the front surface electrode 32 can be strengthened by providing the front surface metal film 14 on the surface of the front surface electrode 32 as in the embodiment. It was confirmed that the wire 7 having high hardness can be used.
- reference numeral 22 denotes a bonding interface between the wire 37 and the front electrode 32.
- FIG. 7 is a characteristic diagram showing the bonding strength of wires of a conventional semiconductor device.
- FIG. 6 shows the result of producing a plurality of the above-described Example 1 under different wire bonding conditions and measuring the bonding strength of the wire 7.
- FIG. 12 shows the result of producing a plurality of the above-described Example 2 under different wire bonding conditions and measuring the bonding quality of the wire 7. As a comparison, FIG.
- Example 2 From the results shown in FIG. 6, in Example 1, when the ultrasonic output of wire bonding is 11 V or more, the bonding load for bonding the wire 7 and the member to be bonded is set to 800 gf to 1400 gf, and the wire bonding super It was confirmed that when the sound wave output is 13 V or more, the bonding strength of the wire 7 can be sufficiently secured by setting the bonding load to 1000 gf to 1400 gf. From the results shown in FIG. 12, in Example 2, the bonding load range in which the bonding strength between the wire 7 and the member to be bonded can be sufficiently secured by setting the ultrasonic output of the wire bonding to 11 V or more.
- FIG. 8 is a characteristic diagram showing the power cycle capability of the semiconductor device according to the embodiment.
- FIG. 8 shows the relationship between the number of cycles of the power cycle and the temperature change ⁇ Tj of the junction temperature of the semiconductor element in Examples 1 and 2 and Conventional Example 1 described above.
- the maximum junction temperature Tjmax of the semiconductor element was 175 ° C. From the results shown in FIG. 8, it was confirmed that Examples 1 and 2 can perform more power cycle cycles than Conventional Example 1 under the use conditions at high temperatures. That is, Examples 1 and 2 were able to increase the power cycle tolerance twice or more than Conventional Example 1.
- FIG. 9 is a cross-sectional view schematically showing a state near the bonding interface of the wire after wire bonding of the semiconductor device according to the embodiment.
- 9A to 9F show wires of a semiconductor device in which Ni plating films having thicknesses of 0.1 ⁇ m, 0.3 ⁇ m, 0.5 ⁇ m, 1 ⁇ m, 3 ⁇ m, and 5 ⁇ m are formed as the front surface metal film 14. 47 shows the vicinity of the bonding interface.
- the Ni plating film 43 is shown by a line segment, and the thickness of the Ni plating film 43 is shown by the thickness of this line segment.
- 9 (e) and 9 (f) the Ni plating film 44 is illustrated by a black solid line, and the thickness of the horizontal line (the width in the depth direction of the semiconductor substrate 41) of the Ni plating film 44 is shown. The film thickness is shown.
- FIG. 9B showing the Ni plating film 43 having a thickness of 0.3 ⁇ m corresponds to the semiconductor device of the first embodiment
- FIG. 9F showing the Ni plating film 44 having a thickness of 5 ⁇ m is the semiconductor device of the second embodiment.
- the Ni plating film 43 was broken by wire bonding, and the AlSi electrode 42 as the front electrode 12 was formed. It was confirmed that it was dispersed at the bonding interface between the wire 47 and the wire 47.
- Example 1 the state in the vicinity of the bonding interface of the wire 47 is that the Ni plating film 43 is broken immediately after the wire bonding, and the wire 47 and the AlSi electrode 42 are directly bonded, and the reference shown in FIG. It became an embodiment of the example, and it was confirmed that it was as shown in FIG. 4C after the power cycle test.
- the Ni plating films 43 having thicknesses of 0.1 ⁇ m, 0.5 ⁇ m, and 1 ⁇ m shown in FIGS. 9A, 9C, and 9D, respectively, are formed immediately after wire bonding, as in the first embodiment.
- the Ni plating film 43 was broken.
- the thickness of the front metal film 14 is 3 ⁇ m or more, preferably 3 ⁇ m to 5 ⁇ m.
- FIG. 13 is a characteristic diagram showing the bonding quality of another example of the semiconductor device according to the embodiment.
- FIG. 14 is a characteristic diagram showing the bonding quality of another example of a conventional semiconductor device. ⁇ indicates the case where the bonding strength of the wire is sufficiently secured to withstand as a product, ⁇ indicates the case where the bonding strength of the wire is low, and ⁇ indicates the case where the wire peels and causes element destruction Yes.
- Example 3 The result of measuring the bonding strength of the wire 7 in the semiconductor device according to the embodiment (hereinafter referred to as Example 3) in which the wire 7 having a wire diameter of 500 ⁇ m was bonded to the front metal film 14 under different wire bonding conditions.
- a Ni plating film having a thickness of 5 ⁇ m was formed as the front metal film 14.
- the configuration of the third embodiment is the same as that of the second embodiment except that the wire 7 has a different wire diameter.
- the bonding strength of the wire 37 was measured in a conventional semiconductor device (hereinafter referred to as Conventional Example 2) in which a wire 37 having a wire diameter of 500 ⁇ m was bonded to the front electrode 112 under different wire bonding conditions.
- Conventional Example 2 The results are shown in FIG.
- the configuration of Conventional Example 2 is the same as that of the reference example except that the wire 37 has a different wire diameter.
- the thickness of the Ni plating film (front metal film 14) is set to 5.0 ⁇ m, and the wire diameter of the wire 7 is set to 500 ⁇ m. Even if the sound wave output is increased (18 V to 22 V) and the bonding load for bonding the wire 7 and the member to be bonded is increased (1300 gf to 1500 gf), the bonding between the front metal film 14 and the wire 7 is performed. It was confirmed that no bonding failure occurred in the portion and the bonding strength of the wire 7 could be sufficiently secured. On the other hand, from the result shown in FIG.
- the crystal grain size of the wire is controlled so that the recrystallization temperature of the wire is higher than the recrystallization temperature of the conventional aluminum wire, and the hardness of the wire is increased.
- the front electrode can be strengthened by providing the front metal film having a hardness higher than that of the wire on the surface of the front electrode. It can prevent that a crack arises in a surface electrode.
- the front surface metal film functions as a barrier, so even if a crack occurs in the wire, It is possible to prevent the crack from progressing to the front electrode.
- the power cycle resistance can be improved by preventing the surface electrode from cracking and suppressing the cracking from occurring in the wire. Therefore, a highly reliable semiconductor device can be provided.
- the stress applied to the front electrode due to thermal deformation of the wire is increased, but the hardness of the surface of the front electrode is higher than that of the wire. Since the front electrode is strengthened by providing the front metal film, it is possible to prevent the front electrode from being damaged.
- the present invention can be variously changed.
- the dimensions of each part are variously set according to required specifications.
- the semiconductor device and the method for manufacturing the semiconductor device according to the present invention are useful for a semiconductor device having a module structure used for a general-purpose inverter, wind power generation, solar power generation, electric railway, and the like.
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Abstract
Description
実施の形態にかかる半導体装置の構造について説明する。図1は、実施の形態にかかる半導体装置の構造を示す断面図である。図2は、図1の半導体素子の構造を模式的に示す断面図である。図1,2に示すように、実施の形態にかかる半導体装置は、半導体素子(半導体チップ)1と、セラミクス絶縁基板(DCB基板)などの絶縁基板2と、銅(Cu)ベース6と、ワイヤ7とを備えたモジュール構造の半導体装置である。絶縁基板2は、絶縁層3のおもて面側に例えばCuなどからなる回路層4が設けられ、裏面側に裏銅箔5が設けられている。
1a はんだ接合層
2 絶縁基板
3 絶縁層
4 回路層
5 裏銅箔
6 Cuベース
7 ワイヤ
11 半導体基板
12 おもて面電極
13 裏面電極
14 おもて面金属膜
20 ワイヤの接合界面
21 クラック
Claims (8)
- ワイヤボンディングによって半導体素子の電極とワイヤとを電気的に接続してなる半導体装置において、
前記電極の表面に、前記ワイヤよりも硬度が高い金属膜が設けられており、
前記ワイヤは、ワイヤボンディングによって前記金属膜に接合されており、
前記ワイヤの前記金属膜との接合界面の再結晶温度が175℃以上であることを特徴とする半導体装置。 - 前記ワイヤの前記接合界面の結晶粒の粒径は15μm以下であり、
前記ワイヤの前記接合界面から離れた部分は粒径が15μmより大きい結晶粒を含むことを特徴とする請求項1に記載の半導体装置。 - 前記ワイヤの硬度は、前記電極の硬度よりも高いことを特徴とする請求項1に記載の半導体装置。
- 前記金属膜はニッケルめっき膜であることを特徴とする請求項1~3のいずれか一つに記載の半導体装置。
- 前記ニッケルめっき膜の膜厚は3μm~7μmであることを特徴とする請求項4に記載の半導体装置。
- 前記金属膜は銅めっき膜であることを特徴とする請求項1~3のいずれか一つに記載の半導体装置。
- 前記銅めっき膜の膜厚は4.5μm~10.5μmであることを特徴とする請求項6に記載の半導体装置。
- 半導体素子の電極とワイヤとを電気的に接続する半導体装置の製造方法において、
前記ワイヤよりも硬度が高い金属膜を前記電極の表面に設ける工程と、
ワイヤボンディングの超音波振動により前記ワイヤの前記金属膜との接合界面の結晶粒の粒径を15μm以下にして前記ワイヤを前記金属膜に接合する工程と、
を含むことを特徴とする半導体装置の製造方法。
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| CN201480012154.0A CN105190858B (zh) | 2013-04-25 | 2014-04-23 | 半导体装置及半导体装置的制造方法 |
| JP2015513808A JP6132014B2 (ja) | 2013-04-25 | 2014-04-23 | 半導体装置および半導体装置の製造方法 |
| US14/845,256 US9748186B2 (en) | 2013-04-25 | 2015-09-03 | Semiconductor device and method for manufacturing the semiconductor device |
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| JP2017199813A (ja) * | 2016-04-27 | 2017-11-02 | 富士電機株式会社 | 半導体装置及びその製造方法 |
| WO2022163695A1 (ja) * | 2021-01-28 | 2022-08-04 | 三菱電機株式会社 | 半導体装置、電力変換装置および半導体装置の製造方法 |
| JP2023033668A (ja) * | 2021-08-30 | 2023-03-13 | 株式会社 日立パワーデバイス | 半導体装置及びその製造方法 |
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| JPWO2014175343A1 (ja) | 2017-02-23 |
| DE112014002135T5 (de) | 2016-01-14 |
| CN105190858B (zh) | 2018-11-06 |
| JP6132014B2 (ja) | 2017-05-24 |
| US9748186B2 (en) | 2017-08-29 |
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| CN105190858A (zh) | 2015-12-23 |
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