WO2014162854A1 - セラミック電子部品 - Google Patents
セラミック電子部品 Download PDFInfo
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- WO2014162854A1 WO2014162854A1 PCT/JP2014/057053 JP2014057053W WO2014162854A1 WO 2014162854 A1 WO2014162854 A1 WO 2014162854A1 JP 2014057053 W JP2014057053 W JP 2014057053W WO 2014162854 A1 WO2014162854 A1 WO 2014162854A1
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- metal film
- ceramic chip
- ceramic
- adhesion
- film
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/30—Stacked capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/005—Electrodes
- H01G4/012—Form of non-self-supporting electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/018—Dielectrics
- H01G4/06—Solid dielectrics
- H01G4/08—Inorganic dielectrics
- H01G4/12—Ceramic dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/228—Terminals
- H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/228—Terminals
- H01G4/248—Terminals the terminals embracing or surrounding the capacitive element, e.g. caps
Definitions
- the present invention relates to a ceramic electronic component using a ceramic chip as a component body.
- Ceramic electronic components using a ceramic chip as a component body are generally provided with two or more external electrodes on the outer surface of a substantially rectangular parallelepiped ceramic chip.
- Each external electrode is located on a surface that defines at least a height dimension of the ceramic chip, and a first planar portion that is positioned on a surface that defines a length dimension or a width dimension of the ceramic chip. It has at least one second planar portion that is continuous with the planar portion, and the cross-sectional shape along the height direction is substantially U-shaped or substantially L-shaped.
- Such a ceramic electronic component is mounted on a substrate by electrically connecting mainly the second planar portion of each external electrode to a conductor pad of the substrate via a bonding material such as solder.
- a bonding material such as solder.
- the stress based on this bending is transmitted to the ceramic chip through the conductor pad, the bonding material and the external electrode, and this stress causes the ceramic portion of the ceramic chip and the ceramic chip. Cracks and deformations may occur in the conductor portions provided inside and outside of the ceramic, and as a result, the performance of the ceramic electronic component may be degraded.
- the ceramic element body 1 in order to prevent the ceramic element body 1 from being cracked by a stress corresponding to the stress, the ceramic element body 1 is provided in the wraparound portions 15a and 15b of the external terminal electrodes 5a and 5b. Are provided with tip separation portions 15a2 and 15b2 spaced from the main surfaces 11 and 12.
- the wraparound portions 15a and 15b of the external terminal electrodes 5a and 5b have the base end side joint portions 15a1 and 15b1 joined to the main surfaces 11 and 12 of the ceramic body 1, a stress corresponding to the stress is generated. Propagation to the ceramic body 1 through the external terminal electrodes 5a and 5b is difficult to suppress.
- An object of the present invention is to provide a ceramic electronic component capable of suppressing the stress based on the bending from being transmitted to the ceramic chip even when the substrate is bent due to thermal shock or the like when the ceramic electronic component is mounted on the substrate. There is to do.
- the present invention provides at least a height dimension of a first planar portion located on a surface defining a length dimension or a width dimension of a substantially rectangular parallelepiped ceramic chip, and at least a height dimension of the ceramic chip.
- a ceramic electronic component comprising two or more external electrodes having at least one second planar portion located on a defining surface and continuing from the first planar portion, wherein the second planar portion Includes at least a plating metal film and an adhesion reducing film for reducing the adhesion of the plating metal film to the surface on which the plating metal film is formed.
- a ceramic electronic component capable of suppressing stress based on the deflection from being transmitted to the ceramic chip even when the substrate is bent due to thermal shock or the like when the ceramic electronic component is mounted on the substrate. can do.
- FIG. 1 is a sectional view along the height direction showing an embodiment in which the present invention is applied to a multilayer ceramic capacitor.
- FIG. 2 is an enlarged view of a main part of FIG.
- FIG. 3 is an explanatory diagram of the operation and effect of the embodiment shown in FIGS. 1 and 2.
- 4 is a view corresponding to FIG. 2 showing a first modification of the embodiment shown in FIGS.
- FIG. 7 is a diagram corresponding to FIG. 2 showing a fourth modification of the embodiment shown in FIGS. 1 and 2.
- FIG. 8 is a diagram corresponding to FIG.
- FIG. 9 is a view corresponding to FIG. 2 showing a sixth modification of the embodiment shown in FIGS.
- FIG. 10 is a diagram corresponding to FIG. 2 showing a seventh modification of the embodiment shown in FIGS.
- FIG. 11 is a view corresponding to FIG. 2 showing an eighth modification of the embodiment shown in FIGS.
- the multilayer ceramic capacitor 10 (hereinafter simply referred to as the capacitor 10) is provided with two external electrodes 12 on the outer surface of a substantially rectangular parallelepiped ceramic chip 11. *
- the ceramic chip 11 is provided so as to cover each of the plurality (16 in FIG. 1) of internal electrode layers 11b stacked in the height direction via the capacitance forming layer 11a and the internal electrode layers 11b on both sides in the height direction.
- a protective layer 11c is provided.
- One end (odd number from the top in FIG. 1) of the plurality of internal electrode layers 11b is connected to one of the external electrodes 12 (left side in FIG. 1) and the other part (even number from the top in FIG. 1). The end is connected to the other external electrode 12 (the right side in FIG. 1).
- the total number of internal electrode layers 11b is 16 for convenience of illustration, but the actual total number is larger than this. *
- each capacitance forming layer 11a and each protective layer 11c is made of dielectric ceramics, preferably a dielectric of ⁇ > 1000 or class 2 (high dielectric constant). Ceramics are used, and the thickness dimension of each capacitance forming layer 11a is substantially the same, and the thickness dimension of each protective dielectric layer 11c is also substantially the same. Specific examples of dielectric ceramics used for each capacitance forming layer 11a and each protective layer 11c include barium titanate, strontium titanate, calcium titanate, magnesium titanate, calcium zirconate, calcium zirconate titanate, zirconate Barium or titanium oxide is mentioned.
- each internal electrode layer 11b of the dielectric chip 11 metal is used as the material of each internal electrode layer 11b of the dielectric chip 11, and the thickness dimension and the top view shape (substantially rectangular) of each internal electrode layer 11a are substantially the same.
- Specific examples of the metal used for each internal electrode layer 11b include nickel, copper, palladium, platinum, silver, gold, or alloys thereof. *
- each external electrode 12 has one first surface portion SEa having a substantially rectangular outline located on the surface defining the length dimension of the ceramic chip 11 and the surface defining the height dimension of the ceramic chip 11.
- the cross-sectional shape is substantially U-shaped.
- the rounded annular portion SEc (hereinafter referred to as the boundary) is formed at the boundary between the first planar portion SEa and each second planar portion SEb. (Referred to as part SEc). *
- boundary portion SEc is a shared portion of the first planar portion SEa and each second planar portion SEb and is not captured as a part of the external electrode 12 in the present specification and claims.
- the boundary part SEc is treated as a term indicating a partial area of the external electrode 12 in the following description.
- the first planar portion SEa and the boundary portion SEc are composed of a baked metal film 12a formed on the outer surface of the ceramic chip 11 and a plated metal film 12b formed on the outer surface of the baked metal film 12a. It is constituted by.
- the second planar portion SEb is formed by a baked metal film 12a formed on the outer surface of the ceramic chip 11 and a plated metal film 12b formed on the outer surface of the baked metal film 12a via the adhesion reducing film 12c. It is configured.
- the baking metal film 12a constituting the first planar portion SEa and the baking metal film 12a constituting the second planar portion SEb are one continuous baking metal film, and the plating constituting the first planar portion SEa.
- the plated metal film 12b constituting the metal film 12b and the second planar portion SEb is one continuous plated metal film. *
- the baked metal film 12a is a metal film formed by applying a paste containing metal powder and performing a baking process.
- metals used for the baked metal film 12a include nickel, copper, palladium, platinum, Silver, gold
- the plated metal film 12b is a metal film formed using a plating method such as electrolytic plating or electroless plating. Examples of the metal used for the plated metal film 12b include tin, silver, palladium, Gold or copper is mentioned.
- the adhesion relaxation film 12c is a metal film formed by physical vapor deposition (PVD) such as sputtering or vacuum deposition, and specific examples of metals used for the adhesion relaxation film 12c include tin, Silver, palladium, gold, or copper may be mentioned.
- PVD physical vapor deposition
- specific examples of metals used for the adhesion relaxation film 12c include tin, Silver, palladium, gold, or copper may be mentioned.
- the important point is to use a metal film whose adhesion force to the outer surface of the baked metal film 12a is lower than the adhesion force to the inner surface of the plated metal film 12b as the adhesion force relaxation film 12c. *
- the capacitor 10 is mounted on the substrate 20 by electrically connecting mainly the second planar portion SEb of each external electrode 12 to the conductor pad 21 of the substrate 20 through a bonding material 30 such as solder. As shown in FIG. 3, when the end portion of the conductor pad 21 protrudes outward from each external electrode 12, the bonding material 30 gets wet on the outer surface of the first planar portion SEa of each external electrode 12. Thus, the fillet 30a is formed.
- the second planar portion SEb of each external electrode 12 has a baked metal film 12 a formed on the outer surface of the ceramic chip 11 and a baked metal film via the adhesion relaxation film 12 c.
- the plating metal film 12b is formed on the outer surface of 12a, and the adhesion force of the plating metal film 12b to the outer surface of the baked metal film 12a is alleviated by the adhesion reducing film 12c.
- the stress based on the bending BE of the substrate 20 is transmitted to the ceramic chip 11 through the conductor pad 21, the bonding material 30, and the external electrode 12.
- the adhesive force relaxation film 12c constituting the second planar portion SEb is baked.
- the action of releasing the adhesion with the metal film 12a (not shown), in addition, (2) the action of the adhesion relaxation film 12c constituting the second planar portion SEb being peeled from the baking metal film 12a together with the plated metal film 12b ( 3) (see peeling EX in FIG. 3).
- Capacitor 10 has a capability of lowering capacitance by preventing cracks and deformations from occurring in each capacitor forming layer 11a and each protective layer 11c of chip 11 and each internal electrode layer 11b provided in ceramic chip 11 as much as possible. It is possible to avoid the reduction as much as possible.
- the sample was soldered to one side of a glass epoxy substrate in accordance with JIS-C-6484, and then the sample soldered part on one side of the glass epoxy substrate was supported at 45 mm on both sides by a piece.
- a portion corresponding to the sample soldering portion is deformed by pressing downward at a constant speed of 0.5 mm / sec with a jig (the pressing portion is formed of a curved surface having a curvature radius of 230 mm).
- FIG. 4 This first modification is different from the embodiment (capacitor 10) shown in FIGS. 1 and 2 in that the first planar portion SEa of the external electrode 12-1 is a ceramic chip. 11 is composed of a baked metal film 12a-1 formed on the outer surface of 11 and a plated metal film 12b-2 formed on the outer surface of the baked metal film 12a-1. The planar portion SEb and the boundary portion SEc are formed on the outer surface of the baked metal film 12a-1 via the baked metal film 12a-1 formed on the outer surface of the ceramic chip 11 and the adhesion relaxation film 12c-1.
- the structure is different in that it is constituted by the plated metal film 12b-1, that is, the adhesion relaxation film 12c-1 is provided so as to extend not only to the second planar portion SEb but also to the boundary portion SEc.
- This second modification includes the embodiment (capacitor 10) shown in FIGS. 1 and 2, and the first surface portion SEa and the second surface of the external electrode 12-2.
- the part SEb and the boundary part SEc are formed on the outer surface of the baked metal film 12a-2 via the baked metal film 12a-2 formed on the outer surface of the ceramic chip 11 and the adhesion relaxation film 12c-2.
- the adhesion reducing film 12c-2 is provided so as to extend not only to the second planar portion SEb but also to the boundary portion SEc and the first planar portion SEa.
- the structure is different in respect. *
- the baked metal film 12a-2 and the plated metal film 12b-2 are in direct contact with each other at the first surface portion SEa, the second surface portion SEb, and the boundary portion SEc of the external electrode 12-2. Since there is no portion, if the peeled portion is extremely widened with the action (2), the internal conductivity of the external electrode 12-2 may be lowered.
- the adhesion strengthening film 12d is a metal film formed by physical vapor deposition (PVD) such as sputtering or vacuum deposition or chemical vapor deposition (CVD), and is used as the adhesion strengthening film 12d.
- PVD physical vapor deposition
- the metal used include titanium, chromium, molybdenum, tungsten, or iron.
- the adhesion reinforcing film 12d is formed on the outer surface of the baked metal film 12a-2. It is preferable to perform a cleaning process such as reverse sputtering on the outer surface of the metal film 12a-2 before. *
- This third modification includes the embodiment (capacitor 10) shown in FIGS. 1 and 2, and a baked metal film on the second planar portion SEb of the external electrode 12-3.
- 12a-3 is shorter than the length of the plated metal film 12b-3 and the adhesion reducing film 12c-3, that is, the end of the plated metal film 12b-3 is the adhesion reducing film 12c.
- the structure is different in that the film is formed on the outer surface of the ceramic chip 11 through ⁇ 3. *
- the adhesion force of the adhesion force relaxation film 12c-3 to the outer surface of the ceramic chip 11 is as low as the adhesion force to the outer surface of the baked metal film 12a-3.
- FIG. 7 This fourth modification is different from the embodiment (capacitor 10) shown in FIGS. 1 and 2 in that the second planar portion SEb of the external electrode 12-4 has an adhesive force.
- the structure is different in that it is provided only in SEc. *
- FIG. 8 This fifth modification is different from the embodiment (capacitor 10) shown in FIGS. 1 and 2, and the second planar portion SEb and the boundary portion SEc of the external electrode 12-4. Is composed of the plated metal film 12b-5 formed on the outer surface of the ceramic chip 11 through the adhesion relaxation film 12c-5, that is, the baked metal film 12a-5 is formed into the first planar portion. The structure is different in that it is provided only in SEa. *
- FIG. 9 This sixth modification is different from the embodiment (capacitor 10) shown in FIGS. 1 and 2 in that the second planar portion SEa of the external electrode 12-6 is a ceramic chip.
- a point / external electrode 12-6 provided only on one side (lower side in FIG. 9) defining a height dimension of 11 is a first rectangular portion SEa having a substantially rectangular outline and a substantially rectangular outline.
- the second planar portion SEb has a continuous shape, and the structure is different in that the cross-sectional shape along the height direction is substantially L-shaped.
- the first surface portion SEa and the boundary portion SEc of the external electrode 12-6 are constituted by the baked metal film 12a-6 and the plated metal film 12b-6, and the second surface portion SEb is baked metal film 12a-. 6. It is constituted by a plated metal film 12b-6 and an adhesion reducing film 12c-6.
- This seventh modification is different from the embodiment (capacitor 10) shown in FIGS. 1 and 2 in that the second planar portion SEb of the external electrode 12-7 is a ceramic chip. 11 is provided on only one side (the lower side in FIG. 10) on the surface defining the height dimension of 11 and the external electrode 12-7 has one first planar portion SEa having a substantially rectangular outline and a substantially rectangular outline. The second surface portion SEb of the external electrode 12-7 is in close contact with the second surface portion SEb of the outer electrode 12-7.
- the structure is different in that it is constituted by a plated metal film 12b-7 formed on the outer surface of the ceramic chip 11 via the force relaxation film 12c-7.
- the first planar portion SEa and the boundary portion SEc of the external electrode 12-7 are constituted by a baked metal film 12a-7 and a plated metal film 12b-7. *
- This eighth modification includes the embodiment (capacitor 10) shown in FIGS. 1 and 2, and the second planar portion SEb and boundary portion SEc of the external electrode 12-8.
- the point that the external electrode 12-8 is provided on only one side (the lower side in FIG. 11) defining the height dimension of the ceramic chip 11 is one first surface portion SEa having a substantially rectangular outline.
- a second surface portion of the external electrode 12-8, in which the first surface portion SEb having a substantially rectangular outline is a continuous shape and the cross-sectional shape along the height direction is substantially L-shaped.
- the SEb and the boundary part SEc are different in structure in that they are constituted by a plated metal film 12b-8 formed on the outer surface of the ceramic chip 11 via the adhesion relaxation film 12c-8.
- the first planar portion SEa of the external electrode 12-8 is composed of a baked metal film 12a-8 and a plated metal film 12b-8.
- One first planar portion SEa of the external electrodes 12 and 12-1 to 12-5 is positioned on a surface that defines the width dimension of the ceramic chip 11, and four second planar portions SEb are continuous with the first planar portion SEa. Two of them are located on both sides of the surface defining the height dimension of the ceramic chip 11, and the other two are located both on the surface defining the length dimension of the ceramic chip 11. good.
- the external electrode in this case also has a shape in which one first surface portion SEa having a substantially rectangular outline and four second surface portions SEb having a substantially quadrangular cylindrical shape are continuous. Therefore, the external electrodes 12 and 12 ⁇ Similar to 1 to 12-5, the cross-sectional shape along the height direction is substantially U-shaped.
- the external electrode in this case also has a shape in which one first surface portion SEa having a substantially rectangular contour and one second surface portion SEb having a substantially rectangular contour are continuous, and therefore, the external electrodes 12-6 to 12-8. Similarly, the cross-sectional shape along the height direction is substantially L-shaped.
- the second surface portions SEb of the external electrodes 12 and 12-1 to 12-5 may be two positioned only on the surface defining the height dimension of the ceramic chip 11.
- the external electrode in this case has a shape in which one first surface portion SEa having a substantially rectangular contour and two second surface portions SEb having a substantially rectangular contour are continuous, and the cross-sectional shape along the height direction is substantially It becomes a letter shape.
- the plated metal films 12b and 12b-1 to 12b-8 may be formed with another plated metal film formed on the outer surface as external electrodes.
- the number of the other plated metal films is not limited to one, but may be two or more. It is preferable that the material of the outermost plated metal film and the material of the inner plated metal film are different.
- specific examples of the metal used for the outermost plated metal film include tin, silver, palladium, gold, or copper
- specific examples of the metal used for the inner plated metal film include platinum, Silver, palladium, chromium, gold, copper, or nickel can be used. *
- the adhesion relaxation films 12c and 12c-1 to 12c-8 metal film formed by physical vapor deposition (PVD) is shown as the adhesion relaxation films 12c and 12c-1 to 12c-8, the plated metal films 12b and 12b-1 Any material other than the above metal film can be used as long as it can relieve the adhesion of the plated metal film to the surface on which 12b-8 is formed (the outer surface of the baked metal film or the outer surface of the ceramic chip). For example, even when a non-metallic material such as silica or polyimide formed in a film shape is used as the adhesion reducing film, the same effect as described above can be obtained. *
- the external electrodes 12-6 to 12-8 and the external electrode described in the second modification item are substantially L-shaped in cross section
- the external electrode described in the third modification item In the case of such an external electrode having a substantially U-shaped cross section, three or more external electrodes may be provided on the outer surface of the substantially rectangular parallelepiped ceramic chip according to the state of the conductor portion provided inside and outside the ceramic chip. Although it is possible, even in such a case, it can suppress that the stress based on the bending of a board
- SYMBOLS 10 Multilayer ceramic capacitor, 11 ... Ceramic chip, 11a ... Capacitor formation layer, 11b ... Internal electrode layer, 11c ... Protective layer, 12, 12-1 to 12-8 ... External electrode, SEa ... 1st planar part, SEb ... second planar portion, SEc ... boundary portion, 12a, 12a-1 to 12a-8 ... baked metal film, 12b, 12b-1 to 12b-8 ... plated metal film, 12c, 12c-1 to 12c-8 ... Adhesion relaxation film.
Abstract
Description
極層11bに亀裂や変形等が発生することを極力防止して、コンデンサ10にキャパシタンス低下等の性能低下が生じることを極力回避することができる。
連続した形状となるため、外部電極12及び12-1~12-5と同様に、その高さ方向に沿う断面形は略コ字形となる。
Claims (8)
- 略直方体状のセラミックチップの長さ寸法又は幅寸法を規定する面上に位置する1つの第1面状部分と、前記セラミックチップの少なくとも高さ寸法を規定する面上に位置し前記第1面状部分と連続する少なくとも1つの第2面状部分と、を有する2個以上の外部電極を備えたセラミック電子部品であって、 前記第2面状部分は、メッキ金属膜と、前記メッキ金属膜が成膜される面に対する該メッキ金属膜の密着力を緩和するための密着力緩和膜と、を少なくとも含んでいる、 ことを特徴とするセラミック電子部品。
- 前記第2面状部分は、前記セラミックチップの外面に成膜された焼付け金属膜と、前記密着力緩和膜を介して前記焼付け金属膜の外面に成膜された前記メッキ金属膜によって構成されている、 ことを特徴とする請求項1に記載のセラミック電子部品。
- 前記第2面状部分は、前記密着力緩和膜を介して前記セラミックチップの外面に成膜された前記メッキ金属膜によって構成されている、 ことを特徴とする請求項1に記載のセラミック電子部品。
- 前記密着力緩和膜は、前記メッキ金属膜の内面に対する密着力よりも前記焼付け金属膜の外面又は前記セラミックチップの外面に対する密着力が低い金属膜である、 ことを特徴とする請求項2又は3に記載のセラミック電子部品。
- 前記第1面状部分は、前記セラミックチップの外面に成膜された焼付け金属膜と、前記焼付け金属膜の外面に成膜された前記メッキ金属膜によって構成されている、 ことを特徴とする請求項1~4の何れか1項に記載のセラミック電子部品。
- 前記メッキ金属膜の外面に、別のメッキ金属膜が成膜されている、 ことを特徴とする請求項1~5の何れか1項に記載のセラミック電子部品。
- 前記第2面状部分は4つ又は2つであり、前記2個以上の外部電極の高さ方向に沿う断面形は略コ字形である、 ことを特徴とする請求項1~6の何れか1項に記載のセラミック電子部品。
- 前記第2面状部分は1つであり、前記2個以上の外部電極の高さ方向に沿う断面形は略L字形である、 ことを特徴とする請求項1~6の何れか1項に記載のセラミック電子部品。
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US14/781,017 US9837213B2 (en) | 2013-04-03 | 2014-03-17 | Ceramic electronic component |
CN201480019334.1A CN105103250B (zh) | 2013-04-03 | 2014-03-17 | 陶瓷电子部件 |
KR1020157023427A KR101768862B1 (ko) | 2013-04-03 | 2014-03-17 | 세라믹 전자 부품 |
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JP2013077490A JP6106009B2 (ja) | 2013-04-03 | 2013-04-03 | セラミック電子部品 |
JP2013-077490 | 2013-04-03 |
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JP (1) | JP6106009B2 (ja) |
KR (1) | KR101768862B1 (ja) |
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US9442408B2 (en) | 2014-11-28 | 2016-09-13 | Canon Kabushiki Kaisha | Member for electrophotography, method for producing the same, and image forming apparatus |
JP2018032788A (ja) | 2016-08-25 | 2018-03-01 | 太陽誘電株式会社 | 積層セラミックコンデンサおよびその製造方法 |
IL250305B (en) * | 2017-01-26 | 2021-02-28 | Vishay Israel Ltd | Electronic component with flexible terminal |
JP6791068B2 (ja) * | 2017-08-29 | 2020-11-25 | 株式会社村田製作所 | コイル部品およびコイル部品付き実装基板 |
JP7089402B2 (ja) | 2018-05-18 | 2022-06-22 | 太陽誘電株式会社 | 積層セラミックコンデンサおよびその製造方法 |
JP7145652B2 (ja) * | 2018-06-01 | 2022-10-03 | 太陽誘電株式会社 | 積層セラミックコンデンサおよびその製造方法 |
JP7446705B2 (ja) * | 2018-06-12 | 2024-03-11 | 太陽誘電株式会社 | 積層セラミックコンデンサおよびその製造方法 |
JP7221616B2 (ja) * | 2018-08-27 | 2023-02-14 | 太陽誘電株式会社 | セラミック電子部品、セラミック電子部品の製造方法および電子部品実装回路基板 |
JP7065735B2 (ja) * | 2018-09-07 | 2022-05-12 | 太陽誘電株式会社 | 積層セラミック電子部品 |
JP2019009463A (ja) * | 2018-09-14 | 2019-01-17 | 太陽誘電株式会社 | 積層セラミックコンデンサ |
JP6939762B2 (ja) * | 2018-12-25 | 2021-09-22 | 株式会社村田製作所 | 積層セラミック電子部品およびその実装構造 |
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JP4310585B2 (ja) * | 2003-02-21 | 2009-08-12 | 株式会社村田製作所 | 積層型セラミック電子部品およびその製造方法 |
JP2007234800A (ja) * | 2006-02-28 | 2007-09-13 | Tdk Corp | 電子部品及びその製造方法 |
JP5082919B2 (ja) * | 2008-02-25 | 2012-11-28 | Tdk株式会社 | 電子部品の実装構造 |
JP5532581B2 (ja) | 2008-10-31 | 2014-06-25 | 株式会社村田製作所 | セラミック電子部品 |
JP2010129621A (ja) * | 2008-11-26 | 2010-06-10 | Murata Mfg Co Ltd | 積層セラミック電子部品およびその製造方法 |
JP2011134875A (ja) * | 2009-12-24 | 2011-07-07 | Tdk Corp | 電子部品の製造方法 |
JP6439551B2 (ja) * | 2014-05-21 | 2018-12-19 | 株式会社村田製作所 | 積層セラミックコンデンサ |
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JPH0888138A (ja) * | 1994-09-16 | 1996-04-02 | Murata Mfg Co Ltd | セラミック電子部品 |
JPH11162771A (ja) * | 1997-11-25 | 1999-06-18 | Kyocera Corp | 積層セラミックコンデンサ |
JP2012094585A (ja) * | 2010-10-25 | 2012-05-17 | Tdk Corp | 電子部品及び電子部品の製造方法 |
JP2014027085A (ja) * | 2012-07-26 | 2014-02-06 | Tdk Corp | 電子部品 |
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US9837213B2 (en) | 2017-12-05 |
JP2014203910A (ja) | 2014-10-27 |
CN105103250B (zh) | 2018-07-17 |
KR101768862B1 (ko) | 2017-08-17 |
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